modularkbd.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000a914 080001c4 080001c4 000011c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000005c 0800aad8 0800aad8 0000bad8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800ab34 0800ab34 0000c1a0 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800ab34 0800ab34 0000bb34 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800ab3c 0800ab3c 0000c1a0 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800ab3c 0800ab3c 0000bb3c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800ab40 0800ab40 0000bb40 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 000001a0 20000000 0800ab44 0000c000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000f6c 200001a0 0800ace4 0000c1a0 2**2 ALLOC 10 ._user_heap_stack 00000604 2000110c 0800ace4 0000d10c 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000c1a0 2**0 CONTENTS, READONLY 12 .debug_info 0001afd8 00000000 00000000 0000c1d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004037 00000000 00000000 000271a8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001788 00000000 00000000 0002b1e0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001246 00000000 00000000 0002c968 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026060 00000000 00000000 0002dbae 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001e6f9 00000000 00000000 00053c0e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d7edb 00000000 00000000 00072307 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014a1e2 2**0 CONTENTS, READONLY 20 .debug_frame 000062c0 00000000 00000000 0014a228 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000062 00000000 00000000 001504e8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 200001a0 .word 0x200001a0 80001e0: 00000000 .word 0x00000000 80001e4: 0800aac0 .word 0x0800aac0 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 200001a4 .word 0x200001a4 8000200: 0800aac0 .word 0x0800aac0 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 468e mov lr, r1 800023c: 4604 mov r4, r0 800023e: 4688 mov r8, r1 8000240: 2b00 cmp r3, #0 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> 800024a: fab2 f682 clz r6, r2 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> 8000250: f1c6 0320 rsb r3, r6, #32 8000254: fa01 f806 lsl.w r8, r1, r6 8000258: fa20 f303 lsr.w r3, r0, r3 800025c: 40b7 lsls r7, r6 800025e: ea43 0808 orr.w r8, r3, r8 8000262: 40b4 lsls r4, r6 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 8000268: fa1f fc87 uxth.w ip, r7 800026c: fbb8 f1fe udiv r1, r8, lr 8000270: 0c23 lsrs r3, r4, #16 8000272: fb0e 8811 mls r8, lr, r1, r8 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 800027a: fb01 f20c mul.w r2, r1, ip 800027e: 429a cmp r2, r3 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> 8000282: 18fb adds r3, r7, r3 8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> 800028c: 429a cmp r2, r3 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> 8000292: 3902 subs r1, #2 8000294: 443b add r3, r7 8000296: 1a9a subs r2, r3, r2 8000298: b2a3 uxth r3, r4 800029a: fbb2 f0fe udiv r0, r2, lr 800029e: fb0e 2210 mls r2, lr, r0, r2 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 80002a6: fb00 fc0c mul.w ip, r0, ip 80002aa: 459c cmp ip, r3 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> 80002ae: 18fb adds r3, r7, r3 80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> 80002b8: 459c cmp ip, r3 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> 80002be: 443b add r3, r7 80002c0: 3802 subs r0, #2 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 80002c6: eba3 030c sub.w r3, r3, ip 80002ca: 2100 movs r1, #0 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> 80002ce: 40f3 lsrs r3, r6 80002d0: 2200 movs r2, #0 80002d2: e9c5 3200 strd r3, r2, [r5] 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: 428b cmp r3, r1 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> 80002e0: e9c5 0100 strd r0, r1, [r5] 80002e4: 2100 movs r1, #0 80002e6: 4608 mov r0, r1 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> 80002ea: fab3 f183 clz r1, r3 80002ee: 2900 cmp r1, #0 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> 80002f2: 4573 cmp r3, lr 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> 80002f6: 4282 cmp r2, r0 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> 80002fc: 1a84 subs r4, r0, r2 80002fe: eb6e 0203 sbc.w r2, lr, r3 8000302: 2001 movs r0, #1 8000304: 4690 mov r8, r2 8000306: 2d00 cmp r5, #0 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> 800030a: e9c5 4800 strd r4, r8, [r5] 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> 8000310: 2a00 cmp r2, #0 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> 8000316: fab2 f682 clz r6, r2 800031a: 2e00 cmp r6, #0 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> 8000320: 1a8a subs r2, r1, r2 8000322: 0c03 lsrs r3, r0, #16 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 8000328: b280 uxth r0, r0 800032a: b2bc uxth r4, r7 800032c: 2101 movs r1, #1 800032e: fbb2 fcfe udiv ip, r2, lr 8000332: fb0e 221c mls r2, lr, ip, r2 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 800033a: fb04 f20c mul.w r2, r4, ip 800033e: 429a cmp r2, r3 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> 8000342: 18fb adds r3, r7, r3 8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> 800034a: 429a cmp r2, r3 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> 8000350: 46c4 mov ip, r8 8000352: 1a9b subs r3, r3, r2 8000354: fbb3 f2fe udiv r2, r3, lr 8000358: fb0e 3312 mls r3, lr, r2, r3 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 8000360: fb02 f404 mul.w r4, r2, r4 8000364: 429c cmp r4, r3 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> 8000368: 18fb adds r3, r7, r3 800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> 8000370: 429c cmp r4, r3 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> 8000376: 4602 mov r2, r0 8000378: 1b1b subs r3, r3, r4 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> 8000380: f1c1 0620 rsb r6, r1, #32 8000384: 408b lsls r3, r1 8000386: fa22 f706 lsr.w r7, r2, r6 800038a: 431f orrs r7, r3 800038c: fa0e f401 lsl.w r4, lr, r1 8000390: fa20 f306 lsr.w r3, r0, r6 8000394: fa2e fe06 lsr.w lr, lr, r6 8000398: ea4f 4917 mov.w r9, r7, lsr #16 800039c: 4323 orrs r3, r4 800039e: fa00 f801 lsl.w r8, r0, r1 80003a2: fa1f fc87 uxth.w ip, r7 80003a6: fbbe f0f9 udiv r0, lr, r9 80003aa: 0c1c lsrs r4, r3, #16 80003ac: fb09 ee10 mls lr, r9, r0, lr 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 80003b4: fb00 fe0c mul.w lr, r0, ip 80003b8: 45a6 cmp lr, r4 80003ba: fa02 f201 lsl.w r2, r2, r1 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> 80003c0: 193c adds r4, r7, r4 80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> 80003ca: 45a6 cmp lr, r4 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> 80003d0: 3802 subs r0, #2 80003d2: 443c add r4, r7 80003d4: eba4 040e sub.w r4, r4, lr 80003d8: fa1f fe83 uxth.w lr, r3 80003dc: fbb4 f3f9 udiv r3, r4, r9 80003e0: fb09 4413 mls r4, r9, r3, r4 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003e8: fb03 fc0c mul.w ip, r3, ip 80003ec: 45a4 cmp ip, r4 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> 80003f0: 193c adds r4, r7, r4 80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> 80003fa: 45a4 cmp ip, r4 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> 80003fe: 3b02 subs r3, #2 8000400: 443c add r4, r7 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 8000406: eba4 040c sub.w r4, r4, ip 800040a: fba0 ec02 umull lr, ip, r0, r2 800040e: 4564 cmp r4, ip 8000410: 4673 mov r3, lr 8000412: 46e1 mov r9, ip 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> 800041a: ebb8 0203 subs.w r2, r8, r3 800041e: eb64 0409 sbc.w r4, r4, r9 8000422: fa04 f606 lsl.w r6, r4, r6 8000426: fa22 f301 lsr.w r3, r2, r1 800042a: 431e orrs r6, r3 800042c: 40cc lsrs r4, r1 800042e: e9c5 6400 strd r6, r4, [r5] 8000432: 2100 movs r1, #0 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> 8000436: fbb1 fcf2 udiv ip, r1, r2 800043a: 0c01 lsrs r1, r0, #16 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 8000440: b280 uxth r0, r0 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 8000446: 463b mov r3, r7 8000448: 4638 mov r0, r7 800044a: 463c mov r4, r7 800044c: 46b8 mov r8, r7 800044e: 46be mov lr, r7 8000450: 2620 movs r6, #32 8000452: fbb1 f1f7 udiv r1, r1, r7 8000456: eba2 0208 sub.w r2, r2, r8 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> 8000460: 4601 mov r1, r0 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> 8000464: 4610 mov r0, r2 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> 8000468: f1c6 0220 rsb r2, r6, #32 800046c: fa2e f302 lsr.w r3, lr, r2 8000470: 40b7 lsls r7, r6 8000472: 40b1 lsls r1, r6 8000474: fa20 f202 lsr.w r2, r0, r2 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 800047c: 430a orrs r2, r1 800047e: fbb3 f8fe udiv r8, r3, lr 8000482: b2bc uxth r4, r7 8000484: fb0e 3318 mls r3, lr, r8, r3 8000488: 0c11 lsrs r1, r2, #16 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 800048e: fb08 f904 mul.w r9, r8, r4 8000492: 40b0 lsls r0, r6 8000494: 4589 cmp r9, r1 8000496: ea4f 4310 mov.w r3, r0, lsr #16 800049a: b280 uxth r0, r0 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> 800049e: 1879 adds r1, r7, r1 80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> 80004a6: 4589 cmp r9, r1 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> 80004aa: eba1 0109 sub.w r1, r1, r9 80004ae: fbb1 f9fe udiv r9, r1, lr 80004b2: fb09 f804 mul.w r8, r9, r4 80004b6: fb0e 1119 mls r1, lr, r9, r1 80004ba: b292 uxth r2, r2 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 80004c0: 4542 cmp r2, r8 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> 80004c4: 18ba adds r2, r7, r2 80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> 80004cc: 4542 cmp r2, r8 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> 80004d0: f1a9 0102 sub.w r1, r9, #2 80004d4: 443a add r2, r7 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> 80004d8: 45f0 cmp r8, lr 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> 80004dc: ebbe 0302 subs.w r3, lr, r2 80004e0: eb6c 0c07 sbc.w ip, ip, r7 80004e4: 3801 subs r0, #1 80004e6: 46e1 mov r9, ip 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> 80004ea: eba7 0909 sub.w r9, r7, r9 80004ee: 4449 add r1, r9 80004f0: f1a8 0c02 sub.w ip, r8, #2 80004f4: fbb1 f9fe udiv r9, r1, lr 80004f8: fb09 f804 mul.w r8, r9, r4 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> 80004fe: 4673 mov r3, lr 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> 8000502: 4650 mov r0, sl 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> 8000506: 4608 mov r0, r1 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> 800050a: 443b add r3, r7 800050c: 3a02 subs r2, #2 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> 8000510: f1ac 0c02 sub.w ip, ip, #2 8000514: 443b add r3, r7 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> 8000518: 4649 mov r1, r9 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> 800051c: eba1 0109 sub.w r1, r1, r9 8000520: 46c4 mov ip, r8 8000522: fbb1 f9fe udiv r9, r1, lr 8000526: fb09 f804 mul.w r8, r9, r4 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> 0800052c <__aeabi_idiv0>: 800052c: 4770 bx lr 800052e: bf00 nop 08000530 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000530: b580 push {r7, lr} 8000532: b082 sub sp, #8 8000534: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000536: 2300 movs r3, #0 8000538: 607b str r3, [r7, #4] 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000544: 6313 str r3, [r2, #48] @ 0x30 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 8000552: 2300 movs r3, #0 8000554: 603b str r3, [r7, #0] 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000560: 6313 str r3, [r2, #48] @ 0x30 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800056a: 603b str r3, [r7, #0] 800056c: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 800056e: 2200 movs r2, #0 8000570: 2100 movs r1, #0 8000572: 200b movs r0, #11 8000574: f001 fc05 bl 8001d82 HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000578: 200b movs r0, #11 800057a: f001 fc1e bl 8001dba /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 800057e: 2200 movs r2, #0 8000580: 2100 movs r1, #0 8000582: 200d movs r0, #13 8000584: f001 fbfd bl 8001d82 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000588: 200d movs r0, #13 800058a: f001 fc16 bl 8001dba /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); 800058e: 2200 movs r2, #0 8000590: 2100 movs r1, #0 8000592: 200f movs r0, #15 8000594: f001 fbf5 bl 8001d82 HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 8000598: 200f movs r0, #15 800059a: f001 fc0e bl 8001dba /* DMA1_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); 800059e: 2200 movs r2, #0 80005a0: 2100 movs r1, #0 80005a2: 2010 movs r0, #16 80005a4: f001 fbed bl 8001d82 HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); 80005a8: 2010 movs r0, #16 80005aa: f001 fc06 bl 8001dba /* DMA1_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); 80005ae: 2200 movs r2, #0 80005b0: 2100 movs r1, #0 80005b2: 2011 movs r0, #17 80005b4: f001 fbe5 bl 8001d82 HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); 80005b8: 2011 movs r0, #17 80005ba: f001 fbfe bl 8001dba /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); 80005be: 2200 movs r2, #0 80005c0: 2100 movs r1, #0 80005c2: 202f movs r0, #47 @ 0x2f 80005c4: f001 fbdd bl 8001d82 HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); 80005c8: 202f movs r0, #47 @ 0x2f 80005ca: f001 fbf6 bl 8001dba /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); 80005ce: 2200 movs r2, #0 80005d0: 2100 movs r1, #0 80005d2: 203a movs r0, #58 @ 0x3a 80005d4: f001 fbd5 bl 8001d82 HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); 80005d8: 203a movs r0, #58 @ 0x3a 80005da: f001 fbee bl 8001dba /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 80005de: 2200 movs r2, #0 80005e0: 2100 movs r1, #0 80005e2: 2046 movs r0, #70 @ 0x46 80005e4: f001 fbcd bl 8001d82 HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 80005e8: 2046 movs r0, #70 @ 0x46 80005ea: f001 fbe6 bl 8001dba } 80005ee: bf00 nop 80005f0: 3708 adds r7, #8 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 80005f6: bf00 nop 80005f8: 40023800 .word 0x40023800 080005fc : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000602: f107 0314 add.w r3, r7, #20 8000606: 2200 movs r2, #0 8000608: 601a str r2, [r3, #0] 800060a: 605a str r2, [r3, #4] 800060c: 609a str r2, [r3, #8] 800060e: 60da str r2, [r3, #12] 8000610: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000612: 2300 movs r3, #0 8000614: 613b str r3, [r7, #16] 8000616: 4b45 ldr r3, [pc, #276] @ (800072c ) 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 800061a: 4a44 ldr r2, [pc, #272] @ (800072c ) 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000620: 6313 str r3, [r2, #48] @ 0x30 8000622: 4b42 ldr r3, [pc, #264] @ (800072c ) 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 800062a: 613b str r3, [r7, #16] 800062c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800062e: 2300 movs r3, #0 8000630: 60fb str r3, [r7, #12] 8000632: 4b3e ldr r3, [pc, #248] @ (800072c ) 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 8000636: 4a3d ldr r2, [pc, #244] @ (800072c ) 8000638: f043 0301 orr.w r3, r3, #1 800063c: 6313 str r3, [r2, #48] @ 0x30 800063e: 4b3b ldr r3, [pc, #236] @ (800072c ) 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 8000642: f003 0301 and.w r3, r3, #1 8000646: 60fb str r3, [r7, #12] 8000648: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800064a: 2300 movs r3, #0 800064c: 60bb str r3, [r7, #8] 800064e: 4b37 ldr r3, [pc, #220] @ (800072c ) 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 8000652: 4a36 ldr r2, [pc, #216] @ (800072c ) 8000654: f043 0304 orr.w r3, r3, #4 8000658: 6313 str r3, [r2, #48] @ 0x30 800065a: 4b34 ldr r3, [pc, #208] @ (800072c ) 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 800065e: f003 0304 and.w r3, r3, #4 8000662: 60bb str r3, [r7, #8] 8000664: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000666: 2300 movs r3, #0 8000668: 607b str r3, [r7, #4] 800066a: 4b30 ldr r3, [pc, #192] @ (800072c ) 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 800066e: 4a2f ldr r2, [pc, #188] @ (800072c ) 8000670: f043 0302 orr.w r3, r3, #2 8000674: 6313 str r3, [r2, #48] @ 0x30 8000676: 4b2d ldr r3, [pc, #180] @ (800072c ) 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 800067a: f003 0302 and.w r3, r3, #2 800067e: 607b str r3, [r7, #4] 8000680: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000682: 2300 movs r3, #0 8000684: 603b str r3, [r7, #0] 8000686: 4b29 ldr r3, [pc, #164] @ (800072c ) 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 800068a: 4a28 ldr r2, [pc, #160] @ (800072c ) 800068c: f043 0308 orr.w r3, r3, #8 8000690: 6313 str r3, [r2, #48] @ 0x30 8000692: 4b26 ldr r3, [pc, #152] @ (800072c ) 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 8000696: f003 0308 and.w r3, r3, #8 800069a: 603b str r3, [r7, #0] 800069c: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); 800069e: 2200 movs r2, #0 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 80006a4: 4822 ldr r0, [pc, #136] @ (8000730 ) 80006a6: f002 f951 bl 800294c /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); 80006aa: 2200 movs r2, #0 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 80006b0: 4820 ldr r0, [pc, #128] @ (8000734 ) 80006b2: f002 f94b bl 800294c /*Configure GPIO pins : PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80006b6: 2330 movs r3, #48 @ 0x30 80006b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ba: 2300 movs r3, #0 80006bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006be: 2302 movs r3, #2 80006c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006c2: f107 0314 add.w r3, r7, #20 80006c6: 4619 mov r1, r3 80006c8: 4819 ldr r0, [pc, #100] @ (8000730 ) 80006ca: f001 ff93 bl 80025f4 /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; 80006ce: f240 4307 movw r3, #1031 @ 0x407 80006d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 2300 movs r3, #0 80006d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006d8: 2302 movs r3, #2 80006da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006dc: f107 0314 add.w r3, r7, #20 80006e0: 4619 mov r1, r3 80006e2: 4815 ldr r0, [pc, #84] @ (8000738 ) 80006e4: f001 ff86 bl 80025f4 /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 80006ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006ee: 2301 movs r3, #1 80006f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006f2: 2300 movs r3, #0 80006f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006f6: 2300 movs r3, #0 80006f8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006fa: f107 0314 add.w r3, r7, #20 80006fe: 4619 mov r1, r3 8000700: 480b ldr r0, [pc, #44] @ (8000730 ) 8000702: f001 ff77 bl 80025f4 /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000706: f44f 7380 mov.w r3, #256 @ 0x100 800070a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 2301 movs r3, #1 800070e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 2300 movs r3, #0 8000712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000714: 2300 movs r3, #0 8000716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000718: f107 0314 add.w r3, r7, #20 800071c: 4619 mov r1, r3 800071e: 4805 ldr r0, [pc, #20] @ (8000734 ) 8000720: f001 ff68 bl 80025f4 } 8000724: bf00 nop 8000726: 3728 adds r7, #40 @ 0x28 8000728: 46bd mov sp, r7 800072a: bd80 pop {r7, pc} 800072c: 40023800 .word 0x40023800 8000730: 40020800 .word 0x40020800 8000734: 40020000 .word 0x40020000 8000738: 40020400 .word 0x40020400 0800073c : I2C_HandleTypeDef hi2c1; /* I2C1 init function */ void MX_I2C1_Init(void) { 800073c: b580 push {r7, lr} 800073e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000740: 4b12 ldr r3, [pc, #72] @ (800078c ) 8000742: 4a13 ldr r2, [pc, #76] @ (8000790 ) 8000744: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8000746: 4b11 ldr r3, [pc, #68] @ (800078c ) 8000748: 4a12 ldr r2, [pc, #72] @ (8000794 ) 800074a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800074c: 4b0f ldr r3, [pc, #60] @ (800078c ) 800074e: 2200 movs r2, #0 8000750: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8000752: 4b0e ldr r3, [pc, #56] @ (800078c ) 8000754: 2200 movs r2, #0 8000756: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000758: 4b0c ldr r3, [pc, #48] @ (800078c ) 800075a: f44f 4280 mov.w r2, #16384 @ 0x4000 800075e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000760: 4b0a ldr r3, [pc, #40] @ (800078c ) 8000762: 2200 movs r2, #0 8000764: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8000766: 4b09 ldr r3, [pc, #36] @ (800078c ) 8000768: 2200 movs r2, #0 800076a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800076c: 4b07 ldr r3, [pc, #28] @ (800078c ) 800076e: 2200 movs r2, #0 8000770: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000772: 4b06 ldr r3, [pc, #24] @ (800078c ) 8000774: 2200 movs r2, #0 8000776: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000778: 4804 ldr r0, [pc, #16] @ (800078c ) 800077a: f002 f901 bl 8002980 800077e: 4603 mov r3, r0 8000780: 2b00 cmp r3, #0 8000782: d001 beq.n 8000788 { Error_Handler(); 8000784: f000 fbba bl 8000efc } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000788: bf00 nop 800078a: bd80 pop {r7, pc} 800078c: 200001bc .word 0x200001bc 8000790: 40005400 .word 0x40005400 8000794: 000186a0 .word 0x000186a0 08000798 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 8000798: b580 push {r7, lr} 800079a: b08a sub sp, #40 @ 0x28 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007a0: f107 0314 add.w r3, r7, #20 80007a4: 2200 movs r2, #0 80007a6: 601a str r2, [r3, #0] 80007a8: 605a str r2, [r3, #4] 80007aa: 609a str r2, [r3, #8] 80007ac: 60da str r2, [r3, #12] 80007ae: 611a str r2, [r3, #16] if(i2cHandle->Instance==I2C1) 80007b0: 687b ldr r3, [r7, #4] 80007b2: 681b ldr r3, [r3, #0] 80007b4: 4a19 ldr r2, [pc, #100] @ (800081c ) 80007b6: 4293 cmp r3, r2 80007b8: d12b bne.n 8000812 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007ba: 2300 movs r3, #0 80007bc: 613b str r3, [r7, #16] 80007be: 4b18 ldr r3, [pc, #96] @ (8000820 ) 80007c0: 6b1b ldr r3, [r3, #48] @ 0x30 80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 ) 80007c4: f043 0302 orr.w r3, r3, #2 80007c8: 6313 str r3, [r2, #48] @ 0x30 80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 ) 80007cc: 6b1b ldr r3, [r3, #48] @ 0x30 80007ce: f003 0302 and.w r3, r3, #2 80007d2: 613b str r3, [r7, #16] 80007d4: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80007d6: 23c0 movs r3, #192 @ 0xc0 80007d8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80007da: 2312 movs r3, #18 80007dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80007de: 2300 movs r3, #0 80007e0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80007e2: 2303 movs r3, #3 80007e4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 80007e6: 2304 movs r3, #4 80007e8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80007ea: f107 0314 add.w r3, r7, #20 80007ee: 4619 mov r1, r3 80007f0: 480c ldr r0, [pc, #48] @ (8000824 ) 80007f2: f001 feff bl 80025f4 /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 80007f6: 2300 movs r3, #0 80007f8: 60fb str r3, [r7, #12] 80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 ) 80007fc: 6c1b ldr r3, [r3, #64] @ 0x40 80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 ) 8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000804: 6413 str r3, [r2, #64] @ 0x40 8000806: 4b06 ldr r3, [pc, #24] @ (8000820 ) 8000808: 6c1b ldr r3, [r3, #64] @ 0x40 800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800080e: 60fb str r3, [r7, #12] 8000810: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000812: bf00 nop 8000814: 3728 adds r7, #40 @ 0x28 8000816: 46bd mov sp, r7 8000818: bd80 pop {r7, pc} 800081a: bf00 nop 800081c: 40005400 .word 0x40005400 8000820: 40023800 .word 0x40023800 8000824: 40020400 .word 0x40020400 08000828
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000828: b580 push {r7, lr} 800082a: b08a sub sp, #40 @ 0x28 800082c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800082e: f001 f937 bl 8001aa0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000832: f000 f8dd bl 80009f0 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000836: f7ff fee1 bl 80005fc MX_DMA_Init(); 800083a: f7ff fe79 bl 8000530 MX_TIM2_Init(); 800083e: f000 fc4f bl 80010e0 MX_TIM3_Init(); 8000842: f000 fca5 bl 8001190 MX_UART4_Init(); 8000846: f000 fd97 bl 8001378 MX_UART5_Init(); 800084a: f000 fdbf bl 80013cc MX_USART1_UART_Init(); 800084e: f000 fde7 bl 8001420 MX_USART2_UART_Init(); 8000852: f000 fe0f bl 8001474 MX_I2C1_Init(); 8000856: f7ff ff71 bl 800073c MX_USB_DEVICE_Init(); 800085a: f009 fc57 bl 800a10c /* USER CODE BEGIN 2 */ //Enable UART RX DMA for all ports HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 800085e: 2210 movs r2, #16 8000860: 4953 ldr r1, [pc, #332] @ (80009b0 ) 8000862: 4854 ldr r0, [pc, #336] @ (80009b4 ) 8000864: f005 fa58 bl 8005d18 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000868: 2210 movs r2, #16 800086a: 4953 ldr r1, [pc, #332] @ (80009b8 ) 800086c: 4853 ldr r0, [pc, #332] @ (80009bc ) 800086e: f005 fa53 bl 8005d18 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000872: 2210 movs r2, #16 8000874: 4952 ldr r1, [pc, #328] @ (80009c0 ) 8000876: 4853 ldr r0, [pc, #332] @ (80009c4 ) 8000878: f005 fa4e bl 8005d18 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 800087c: 2210 movs r2, #16 800087e: 4952 ldr r1, [pc, #328] @ (80009c8 ) 8000880: 4852 ldr r0, [pc, #328] @ (80009cc ) 8000882: f005 fa49 bl 8005d18 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { switch (MODE){ 8000886: 4b52 ldr r3, [pc, #328] @ (80009d0 ) 8000888: 781b ldrb r3, [r3, #0] 800088a: b2db uxtb r3, r3 800088c: 2b02 cmp r3, #2 800088e: d007 beq.n 80008a0 8000890: 2b02 cmp r3, #2 8000892: f300 8087 bgt.w 80009a4 8000896: 2b00 cmp r3, #0 8000898: d01c beq.n 80008d4 800089a: 2b01 cmp r3, #1 800089c: d051 beq.n 8000942 } USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); break; default: break; 800089e: e081 b.n 80009a4 resetReport(); 80008a0: f000 fb1c bl 8000edc matrixScan(); 80008a4: f000 fac0 bl 8000e28 UARTREPORT.DEPTH = DEPTH; 80008a8: 4b4a ldr r3, [pc, #296] @ (80009d4 ) 80008aa: 881b ldrh r3, [r3, #0] 80008ac: 82bb strh r3, [r7, #20] UARTREPORT.TYPE = 0xEE; 80008ae: 23ee movs r3, #238 @ 0xee 80008b0: 82fb strh r3, [r7, #22] memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS)); 80008b2: 4a49 ldr r2, [pc, #292] @ (80009d8 ) 80008b4: f107 0318 add.w r3, r7, #24 80008b8: 3202 adds r2, #2 80008ba: 6810 ldr r0, [r2, #0] 80008bc: 6851 ldr r1, [r2, #4] 80008be: 6892 ldr r2, [r2, #8] 80008c0: c307 stmia r3!, {r0, r1, r2} HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT)); 80008c2: 4b46 ldr r3, [pc, #280] @ (80009dc ) 80008c4: 681b ldr r3, [r3, #0] 80008c6: f107 0114 add.w r1, r7, #20 80008ca: 2210 movs r2, #16 80008cc: 4618 mov r0, r3 80008ce: f005 f9a7 bl 8005c20 break; 80008d2: e068 b.n 80009a6 if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ 80008d4: 4b42 ldr r3, [pc, #264] @ (80009e0 ) 80008d6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80008da: b2db uxtb r3, r3 80008dc: 2b03 cmp r3, #3 80008de: d106 bne.n 80008ee MODE = MODE_MAINBOARD; 80008e0: 4b3b ldr r3, [pc, #236] @ (80009d0 ) 80008e2: 2201 movs r2, #1 80008e4: 701a strb r2, [r3, #0] DEPTH = 0; 80008e6: 4b3b ldr r3, [pc, #236] @ (80009d4 ) 80008e8: 2200 movs r2, #0 80008ea: 801a strh r2, [r3, #0] break; 80008ec: e05b b.n 80009a6 REQ.DEPTH = 0; 80008ee: 2300 movs r3, #0 80008f0: 80bb strh r3, [r7, #4] REQ.TYPE = 0xFF; //Message code for request is 0xFF 80008f2: 23ff movs r3, #255 @ 0xff 80008f4: 80fb strh r3, [r7, #6] memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); 80008f6: 1d3b adds r3, r7, #4 80008f8: 3304 adds r3, #4 80008fa: 220c movs r2, #12 80008fc: 2100 movs r1, #0 80008fe: 4618 mov r0, r3 8000900: f00a f8b2 bl 800aa68 HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); 8000904: 1d3b adds r3, r7, #4 8000906: 2210 movs r2, #16 8000908: 4619 mov r1, r3 800090a: 482a ldr r0, [pc, #168] @ (80009b4 ) 800090c: f005 f988 bl 8005c20 HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); 8000910: 1d3b adds r3, r7, #4 8000912: 2210 movs r2, #16 8000914: 4619 mov r1, r3 8000916: 4829 ldr r0, [pc, #164] @ (80009bc ) 8000918: f005 f982 bl 8005c20 HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); 800091c: 1d3b adds r3, r7, #4 800091e: 2210 movs r2, #16 8000920: 4619 mov r1, r3 8000922: 4828 ldr r0, [pc, #160] @ (80009c4 ) 8000924: f005 f97c bl 8005c20 HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); 8000928: 1d3b adds r3, r7, #4 800092a: 2210 movs r2, #16 800092c: 4619 mov r1, r3 800092e: 4827 ldr r0, [pc, #156] @ (80009cc ) 8000930: f005 f976 bl 8005c20 HAL_Delay(500); 8000934: f44f 70fa mov.w r0, #500 @ 0x1f4 8000938: f001 f924 bl 8001b84 findBestParent(); //So true... 800093c: f000 f96c bl 8000c18 break; 8000940: e031 b.n 80009a6 resetReport(); 8000942: f000 facb bl 8000edc matrixScan();//Something related to this making the key stick. Likely due to race conditions 8000946: f000 fa6f bl 8000e28 if(uartUpdateFlag){ 800094a: 4b26 ldr r3, [pc, #152] @ (80009e4 ) 800094c: 681b ldr r3, [r3, #0] 800094e: 2b00 cmp r3, #0 8000950: d022 beq.n 8000998 for(int i = 0; i < 12; i++){ 8000952: 2300 movs r3, #0 8000954: 627b str r3, [r7, #36] @ 0x24 8000956: e014 b.n 8000982 REPORT.KEYPRESS[i] |= uartBuffer.KEYPRESS[i]; 8000958: 4a1f ldr r2, [pc, #124] @ (80009d8 ) 800095a: 6a7b ldr r3, [r7, #36] @ 0x24 800095c: 4413 add r3, r2 800095e: 3302 adds r3, #2 8000960: 781a ldrb r2, [r3, #0] 8000962: 4921 ldr r1, [pc, #132] @ (80009e8 ) 8000964: 6a7b ldr r3, [r7, #36] @ 0x24 8000966: 440b add r3, r1 8000968: 3304 adds r3, #4 800096a: 781b ldrb r3, [r3, #0] 800096c: 4313 orrs r3, r2 800096e: b2d9 uxtb r1, r3 8000970: 4a19 ldr r2, [pc, #100] @ (80009d8 ) 8000972: 6a7b ldr r3, [r7, #36] @ 0x24 8000974: 4413 add r3, r2 8000976: 3302 adds r3, #2 8000978: 460a mov r2, r1 800097a: 701a strb r2, [r3, #0] for(int i = 0; i < 12; i++){ 800097c: 6a7b ldr r3, [r7, #36] @ 0x24 800097e: 3301 adds r3, #1 8000980: 627b str r3, [r7, #36] @ 0x24 8000982: 6a7b ldr r3, [r7, #36] @ 0x24 8000984: 2b0b cmp r3, #11 8000986: dde7 ble.n 8000958 uartUpdateFlag = 0; 8000988: 4b16 ldr r3, [pc, #88] @ (80009e4 ) 800098a: 2200 movs r2, #0 800098c: 601a str r2, [r3, #0] memset(uartBuffer.KEYPRESS, 0, 12); 800098e: 220c movs r2, #12 8000990: 2100 movs r1, #0 8000992: 4816 ldr r0, [pc, #88] @ (80009ec ) 8000994: f00a f868 bl 800aa68 USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); 8000998: 220e movs r2, #14 800099a: 490f ldr r1, [pc, #60] @ (80009d8 ) 800099c: 4810 ldr r0, [pc, #64] @ (80009e0 ) 800099e: f007 ffe9 bl 8008974 break; 80009a2: e000 b.n 80009a6 break; 80009a4: bf00 nop } HAL_Delay(100); 80009a6: 2064 movs r0, #100 @ 0x64 80009a8: f001 f8ec bl 8001b84 switch (MODE){ 80009ac: e76b b.n 8000886 80009ae: bf00 nop 80009b0: 20000230 .word 0x20000230 80009b4: 200003a0 .word 0x200003a0 80009b8: 20000240 .word 0x20000240 80009bc: 200003e8 .word 0x200003e8 80009c0: 20000250 .word 0x20000250 80009c4: 20000310 .word 0x20000310 80009c8: 20000220 .word 0x20000220 80009cc: 20000358 .word 0x20000358 80009d0: 20000268 .word 0x20000268 80009d4: 20000260 .word 0x20000260 80009d8: 20000210 .word 0x20000210 80009dc: 20000264 .word 0x20000264 80009e0: 20000738 .word 0x20000738 80009e4: 2000027c .word 0x2000027c 80009e8: 2000026c .word 0x2000026c 80009ec: 20000270 .word 0x20000270 080009f0 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80009f0: b580 push {r7, lr} 80009f2: b094 sub sp, #80 @ 0x50 80009f4: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80009f6: f107 031c add.w r3, r7, #28 80009fa: 2234 movs r2, #52 @ 0x34 80009fc: 2100 movs r1, #0 80009fe: 4618 mov r0, r3 8000a00: f00a f832 bl 800aa68 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000a04: f107 0308 add.w r3, r7, #8 8000a08: 2200 movs r2, #0 8000a0a: 601a str r2, [r3, #0] 8000a0c: 605a str r2, [r3, #4] 8000a0e: 609a str r2, [r3, #8] 8000a10: 60da str r2, [r3, #12] 8000a12: 611a str r2, [r3, #16] /** Configure the main internal regulator out put voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000a14: 2300 movs r3, #0 8000a16: 607b str r3, [r7, #4] 8000a18: 4b29 ldr r3, [pc, #164] @ (8000ac0 ) 8000a1a: 6c1b ldr r3, [r3, #64] @ 0x40 8000a1c: 4a28 ldr r2, [pc, #160] @ (8000ac0 ) 8000a1e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000a22: 6413 str r3, [r2, #64] @ 0x40 8000a24: 4b26 ldr r3, [pc, #152] @ (8000ac0 ) 8000a26: 6c1b ldr r3, [r3, #64] @ 0x40 8000a28: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000a2c: 607b str r3, [r7, #4] 8000a2e: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 8000a30: 2300 movs r3, #0 8000a32: 603b str r3, [r7, #0] 8000a34: 4b23 ldr r3, [pc, #140] @ (8000ac4 ) 8000a36: 681b ldr r3, [r3, #0] 8000a38: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8000a3c: 4a21 ldr r2, [pc, #132] @ (8000ac4 ) 8000a3e: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000a42: 6013 str r3, [r2, #0] 8000a44: 4b1f ldr r3, [pc, #124] @ (8000ac4 ) 8000a46: 681b ldr r3, [r3, #0] 8000a48: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000a4c: 603b str r3, [r7, #0] 8000a4e: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000a50: 2301 movs r3, #1 8000a52: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000a54: f44f 3380 mov.w r3, #65536 @ 0x10000 8000a58: 623b str r3, [r7, #32] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000a5a: 2302 movs r3, #2 8000a5c: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000a5e: f44f 0380 mov.w r3, #4194304 @ 0x400000 8000a62: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 8000a64: 2304 movs r3, #4 8000a66: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 96; 8000a68: 2360 movs r3, #96 @ 0x60 8000a6a: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000a6c: 2302 movs r3, #2 8000a6e: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 8000a70: 2304 movs r3, #4 8000a72: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 8000a74: 2302 movs r3, #2 8000a76: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000a78: f107 031c add.w r3, r7, #28 8000a7c: 4618 mov r0, r3 8000a7e: f004 f9bd bl 8004dfc 8000a82: 4603 mov r3, r0 8000a84: 2b00 cmp r3, #0 8000a86: d001 beq.n 8000a8c { Error_Handler(); 8000a88: f000 fa38 bl 8000efc } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000a8c: 230f movs r3, #15 8000a8e: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000a90: 2302 movs r3, #2 8000a92: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; 8000a94: 2380 movs r3, #128 @ 0x80 8000a96: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000a98: f44f 5380 mov.w r3, #4096 @ 0x1000 8000a9c: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000a9e: 2300 movs r3, #0 8000aa0: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000aa2: f107 0308 add.w r3, r7, #8 8000aa6: 2101 movs r1, #1 8000aa8: 4618 mov r0, r3 8000aaa: f003 fb33 bl 8004114 8000aae: 4603 mov r3, r0 8000ab0: 2b00 cmp r3, #0 8000ab2: d001 beq.n 8000ab8 { Error_Handler(); 8000ab4: f000 fa22 bl 8000efc } } 8000ab8: bf00 nop 8000aba: 3750 adds r7, #80 @ 0x50 8000abc: 46bd mov sp, r7 8000abe: bd80 pop {r7, pc} 8000ac0: 40023800 .word 0x40023800 8000ac4: 40007000 .word 0x40007000 08000ac8 : /* USER CODE BEGIN 4 */ // UART Message Requests Goes Here void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000ac8: b580 push {r7, lr} 8000aca: b082 sub sp, #8 8000acc: af00 add r7, sp, #0 8000ace: 6078 str r0, [r7, #4] if (huart->Instance == USART1) { 8000ad0: 687b ldr r3, [r7, #4] 8000ad2: 681b ldr r3, [r3, #0] 8000ad4: 4a1e ldr r2, [pc, #120] @ (8000b50 ) 8000ad6: 4293 cmp r3, r2 8000ad8: d109 bne.n 8000aee handleUARTMessages((uint8_t*)&RX1Msg, &huart1); 8000ada: 491e ldr r1, [pc, #120] @ (8000b54 ) 8000adc: 481e ldr r0, [pc, #120] @ (8000b58 ) 8000ade: f000 f8dd bl 8000c9c HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000ae2: 2210 movs r2, #16 8000ae4: 491c ldr r1, [pc, #112] @ (8000b58 ) 8000ae6: 481b ldr r0, [pc, #108] @ (8000b54 ) 8000ae8: f005 f916 bl 8005d18 } else if (huart->Instance == UART5) { handleUARTMessages((uint8_t*)&RX5Msg, &huart5); HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000aec: e02b b.n 8000b46 else if (huart->Instance == USART2) { 8000aee: 687b ldr r3, [r7, #4] 8000af0: 681b ldr r3, [r3, #0] 8000af2: 4a1a ldr r2, [pc, #104] @ (8000b5c ) 8000af4: 4293 cmp r3, r2 8000af6: d109 bne.n 8000b0c handleUARTMessages((uint8_t*)&RX2Msg, &huart2); 8000af8: 4919 ldr r1, [pc, #100] @ (8000b60 ) 8000afa: 481a ldr r0, [pc, #104] @ (8000b64 ) 8000afc: f000 f8ce bl 8000c9c HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000b00: 2210 movs r2, #16 8000b02: 4918 ldr r1, [pc, #96] @ (8000b64 ) 8000b04: 4816 ldr r0, [pc, #88] @ (8000b60 ) 8000b06: f005 f907 bl 8005d18 } 8000b0a: e01c b.n 8000b46 else if (huart->Instance == UART4) { 8000b0c: 687b ldr r3, [r7, #4] 8000b0e: 681b ldr r3, [r3, #0] 8000b10: 4a15 ldr r2, [pc, #84] @ (8000b68 ) 8000b12: 4293 cmp r3, r2 8000b14: d109 bne.n 8000b2a handleUARTMessages((uint8_t*)&RX4Msg, &huart4); 8000b16: 4915 ldr r1, [pc, #84] @ (8000b6c ) 8000b18: 4815 ldr r0, [pc, #84] @ (8000b70 ) 8000b1a: f000 f8bf bl 8000c9c HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000b1e: 2210 movs r2, #16 8000b20: 4913 ldr r1, [pc, #76] @ (8000b70 ) 8000b22: 4812 ldr r0, [pc, #72] @ (8000b6c ) 8000b24: f005 f8f8 bl 8005d18 } 8000b28: e00d b.n 8000b46 else if (huart->Instance == UART5) { 8000b2a: 687b ldr r3, [r7, #4] 8000b2c: 681b ldr r3, [r3, #0] 8000b2e: 4a11 ldr r2, [pc, #68] @ (8000b74 ) 8000b30: 4293 cmp r3, r2 8000b32: d108 bne.n 8000b46 handleUARTMessages((uint8_t*)&RX5Msg, &huart5); 8000b34: 4910 ldr r1, [pc, #64] @ (8000b78 ) 8000b36: 4811 ldr r0, [pc, #68] @ (8000b7c ) 8000b38: f000 f8b0 bl 8000c9c HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000b3c: 2210 movs r2, #16 8000b3e: 490f ldr r1, [pc, #60] @ (8000b7c ) 8000b40: 480d ldr r0, [pc, #52] @ (8000b78 ) 8000b42: f005 f8e9 bl 8005d18 } 8000b46: bf00 nop 8000b48: 3708 adds r7, #8 8000b4a: 46bd mov sp, r7 8000b4c: bd80 pop {r7, pc} 8000b4e: bf00 nop 8000b50: 40011000 .word 0x40011000 8000b54: 200003a0 .word 0x200003a0 8000b58: 20000230 .word 0x20000230 8000b5c: 40004400 .word 0x40004400 8000b60: 200003e8 .word 0x200003e8 8000b64: 20000240 .word 0x20000240 8000b68: 40004c00 .word 0x40004c00 8000b6c: 20000310 .word 0x20000310 8000b70: 20000250 .word 0x20000250 8000b74: 40005000 .word 0x40005000 8000b78: 20000358 .word 0x20000358 8000b7c: 20000220 .word 0x20000220 08000b80 : void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8000b80: b580 push {r7, lr} 8000b82: b082 sub sp, #8 8000b84: af00 add r7, sp, #0 8000b86: 6078 str r0, [r7, #4] // Restart DMA on error if (huart->Instance == USART1) { 8000b88: 687b ldr r3, [r7, #4] 8000b8a: 681b ldr r3, [r3, #0] 8000b8c: 4a16 ldr r2, [pc, #88] @ (8000be8 ) 8000b8e: 4293 cmp r3, r2 8000b90: d105 bne.n 8000b9e HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000b92: 2210 movs r2, #16 8000b94: 4915 ldr r1, [pc, #84] @ (8000bec ) 8000b96: 4816 ldr r0, [pc, #88] @ (8000bf0 ) 8000b98: f005 f8be bl 8005d18 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); } else if (huart->Instance == UART5) { HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000b9c: e01f b.n 8000bde else if (huart->Instance == USART2) { 8000b9e: 687b ldr r3, [r7, #4] 8000ba0: 681b ldr r3, [r3, #0] 8000ba2: 4a14 ldr r2, [pc, #80] @ (8000bf4 ) 8000ba4: 4293 cmp r3, r2 8000ba6: d105 bne.n 8000bb4 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000ba8: 2210 movs r2, #16 8000baa: 4913 ldr r1, [pc, #76] @ (8000bf8 ) 8000bac: 4813 ldr r0, [pc, #76] @ (8000bfc ) 8000bae: f005 f8b3 bl 8005d18 } 8000bb2: e014 b.n 8000bde else if (huart->Instance == UART4) { 8000bb4: 687b ldr r3, [r7, #4] 8000bb6: 681b ldr r3, [r3, #0] 8000bb8: 4a11 ldr r2, [pc, #68] @ (8000c00 ) 8000bba: 4293 cmp r3, r2 8000bbc: d105 bne.n 8000bca HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000bbe: 2210 movs r2, #16 8000bc0: 4910 ldr r1, [pc, #64] @ (8000c04 ) 8000bc2: 4811 ldr r0, [pc, #68] @ (8000c08 ) 8000bc4: f005 f8a8 bl 8005d18 } 8000bc8: e009 b.n 8000bde else if (huart->Instance == UART5) { 8000bca: 687b ldr r3, [r7, #4] 8000bcc: 681b ldr r3, [r3, #0] 8000bce: 4a0f ldr r2, [pc, #60] @ (8000c0c ) 8000bd0: 4293 cmp r3, r2 8000bd2: d104 bne.n 8000bde HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000bd4: 2210 movs r2, #16 8000bd6: 490e ldr r1, [pc, #56] @ (8000c10 ) 8000bd8: 480e ldr r0, [pc, #56] @ (8000c14 ) 8000bda: f005 f89d bl 8005d18 } 8000bde: bf00 nop 8000be0: 3708 adds r7, #8 8000be2: 46bd mov sp, r7 8000be4: bd80 pop {r7, pc} 8000be6: bf00 nop 8000be8: 40011000 .word 0x40011000 8000bec: 20000230 .word 0x20000230 8000bf0: 200003a0 .word 0x200003a0 8000bf4: 40004400 .word 0x40004400 8000bf8: 20000240 .word 0x20000240 8000bfc: 200003e8 .word 0x200003e8 8000c00: 40004c00 .word 0x40004c00 8000c04: 20000250 .word 0x20000250 8000c08: 20000310 .word 0x20000310 8000c0c: 40005000 .word 0x40005000 8000c10: 20000220 .word 0x20000220 8000c14: 20000358 .word 0x20000358 08000c18 : void findBestParent(){ 8000c18: b580 push {r7, lr} 8000c1a: b084 sub sp, #16 8000c1c: af00 add r7, sp, #0 //Find least depth parent uint16_t least_val = 0xFF; 8000c1e: 23ff movs r3, #255 @ 0xff 8000c20: 81fb strh r3, [r7, #14] UART_HandleTypeDef* least_port = NULL; 8000c22: 2300 movs r3, #0 8000c24: 60bb str r3, [r7, #8] for(uint8_t i = 0; i < 4; i++){ 8000c26: 2300 movs r3, #0 8000c28: 71fb strb r3, [r7, #7] 8000c2a: e013 b.n 8000c54 if(PORT_DEPTH[i]) 8000c30: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000c34: 89fa ldrh r2, [r7, #14] 8000c36: 429a cmp r2, r3 8000c38: d909 bls.n 8000c4e least_port = PORTS[i]; 8000c3a: 79fb ldrb r3, [r7, #7] 8000c3c: 4a13 ldr r2, [pc, #76] @ (8000c8c ) 8000c3e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000c42: 60bb str r3, [r7, #8] least_val = PORT_DEPTH[i]; 8000c44: 79fb ldrb r3, [r7, #7] 8000c46: 4a10 ldr r2, [pc, #64] @ (8000c88 ) 8000c48: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000c4c: 81fb strh r3, [r7, #14] for(uint8_t i = 0; i < 4; i++){ 8000c4e: 79fb ldrb r3, [r7, #7] 8000c50: 3301 adds r3, #1 8000c52: 71fb strb r3, [r7, #7] 8000c54: 79fb ldrb r3, [r7, #7] 8000c56: 2b03 cmp r3, #3 8000c58: d9e8 bls.n 8000c2c } } //Assign if valid if(least_val < 0xFF){ 8000c5a: 89fb ldrh r3, [r7, #14] 8000c5c: 2bfe cmp r3, #254 @ 0xfe 8000c5e: d80e bhi.n 8000c7e PARENT = least_port; 8000c60: 4a0b ldr r2, [pc, #44] @ (8000c90 ) 8000c62: 68bb ldr r3, [r7, #8] 8000c64: 6013 str r3, [r2, #0] DEPTH = least_val + 1; 8000c66: 89fb ldrh r3, [r7, #14] 8000c68: 3301 adds r3, #1 8000c6a: b29a uxth r2, r3 8000c6c: 4b09 ldr r3, [pc, #36] @ (8000c94 ) 8000c6e: 801a strh r2, [r3, #0] MODE = MODE_ACTIVE; 8000c70: 4b09 ldr r3, [pc, #36] @ (8000c98 ) 8000c72: 2202 movs r2, #2 8000c74: 701a strb r2, [r3, #0] HAL_Delay(500); 8000c76: f44f 70fa mov.w r0, #500 @ 0x1f4 8000c7a: f000 ff83 bl 8001b84 } } 8000c7e: bf00 nop 8000c80: 3710 adds r7, #16 8000c82: 46bd mov sp, r7 8000c84: bd80 pop {r7, pc} 8000c86: bf00 nop 8000c88: 20000078 .word 0x20000078 8000c8c: 20000080 .word 0x20000080 8000c90: 20000264 .word 0x20000264 8000c94: 20000260 .word 0x20000260 8000c98: 20000268 .word 0x20000268 08000c9c : // Called when UART RX interrupt completes void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) { 8000c9c: b590 push {r4, r7, lr} 8000c9e: b08d sub sp, #52 @ 0x34 8000ca0: af00 add r7, sp, #0 8000ca2: 6078 str r0, [r7, #4] 8000ca4: 6039 str r1, [r7, #0] UARTMessage msg; UARTMessage reply; // Parse incoming message into struct memcpy(&msg, data, sizeof(UARTMessage)); 8000ca6: 687b ldr r3, [r7, #4] 8000ca8: f107 041c add.w r4, r7, #28 8000cac: 6818 ldr r0, [r3, #0] 8000cae: 6859 ldr r1, [r3, #4] 8000cb0: 689a ldr r2, [r3, #8] 8000cb2: 68db ldr r3, [r3, #12] 8000cb4: c40f stmia r4!, {r0, r1, r2, r3} switch(msg.TYPE) { 8000cb6: 8bfb ldrh r3, [r7, #30] 8000cb8: 2bff cmp r3, #255 @ 0xff 8000cba: d026 beq.n 8000d0a 8000cbc: 2bff cmp r3, #255 @ 0xff 8000cbe: dc62 bgt.n 8000d86 8000cc0: 2baa cmp r3, #170 @ 0xaa 8000cc2: d002 beq.n 8000cca 8000cc4: 2bee cmp r3, #238 @ 0xee 8000cc6: d03a beq.n 8000d3e uartUpdateFlag = 1; } break; default: break; 8000cc8: e05d b.n 8000d86 if(sender == &huart5) { 8000cca: 683b ldr r3, [r7, #0] 8000ccc: 4a33 ldr r2, [pc, #204] @ (8000d9c ) 8000cce: 4293 cmp r3, r2 8000cd0: d103 bne.n 8000cda PORT_DEPTH[0] = msg.DEPTH; 8000cd2: 8bba ldrh r2, [r7, #28] 8000cd4: 4b32 ldr r3, [pc, #200] @ (8000da0 ) 8000cd6: 801a strh r2, [r3, #0] break; 8000cd8: e057 b.n 8000d8a } else if(sender == &huart1) { 8000cda: 683b ldr r3, [r7, #0] 8000cdc: 4a31 ldr r2, [pc, #196] @ (8000da4 ) 8000cde: 4293 cmp r3, r2 8000ce0: d103 bne.n 8000cea PORT_DEPTH[1] = msg.DEPTH; 8000ce2: 8bba ldrh r2, [r7, #28] 8000ce4: 4b2e ldr r3, [pc, #184] @ (8000da0 ) 8000ce6: 805a strh r2, [r3, #2] break; 8000ce8: e04f b.n 8000d8a } else if(sender == &huart2) { 8000cea: 683b ldr r3, [r7, #0] 8000cec: 4a2e ldr r2, [pc, #184] @ (8000da8 ) 8000cee: 4293 cmp r3, r2 8000cf0: d103 bne.n 8000cfa PORT_DEPTH[2] = msg.DEPTH; 8000cf2: 8bba ldrh r2, [r7, #28] 8000cf4: 4b2a ldr r3, [pc, #168] @ (8000da0 ) 8000cf6: 809a strh r2, [r3, #4] break; 8000cf8: e047 b.n 8000d8a } else if(sender == &huart4) { 8000cfa: 683b ldr r3, [r7, #0] 8000cfc: 4a2b ldr r2, [pc, #172] @ (8000dac ) 8000cfe: 4293 cmp r3, r2 8000d00: d143 bne.n 8000d8a PORT_DEPTH[3] = msg.DEPTH; 8000d02: 8bba ldrh r2, [r7, #28] 8000d04: 4b26 ldr r3, [pc, #152] @ (8000da0 ) 8000d06: 80da strh r2, [r3, #6] break; 8000d08: e03f b.n 8000d8a if(MODE!=MODE_INACTIVE){ 8000d0a: 4b29 ldr r3, [pc, #164] @ (8000db0 ) 8000d0c: 781b ldrb r3, [r3, #0] 8000d0e: b2db uxtb r3, r3 8000d10: 2b00 cmp r3, #0 8000d12: d03c beq.n 8000d8e reply.TYPE = 0xAA; 8000d14: 23aa movs r3, #170 @ 0xaa 8000d16: 81fb strh r3, [r7, #14] reply.DEPTH = DEPTH; // use your local DEPTH 8000d18: 4b26 ldr r3, [pc, #152] @ (8000db4 ) 8000d1a: 881b ldrh r3, [r3, #0] 8000d1c: 81bb strh r3, [r7, #12] memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS)); 8000d1e: f107 030c add.w r3, r7, #12 8000d22: 3304 adds r3, #4 8000d24: 220c movs r2, #12 8000d26: 2100 movs r1, #0 8000d28: 4618 mov r0, r3 8000d2a: f009 fe9d bl 800aa68 HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply)); 8000d2e: f107 030c add.w r3, r7, #12 8000d32: 2210 movs r2, #16 8000d34: 4619 mov r1, r3 8000d36: 6838 ldr r0, [r7, #0] 8000d38: f004 ff72 bl 8005c20 break; 8000d3c: e027 b.n 8000d8e if (MODE != MODE_INACTIVE) { 8000d3e: 4b1c ldr r3, [pc, #112] @ (8000db0 ) 8000d40: 781b ldrb r3, [r3, #0] 8000d42: b2db uxtb r3, r3 8000d44: 2b00 cmp r3, #0 8000d46: d024 beq.n 8000d92 for (int i = 0; i < sizeof(REPORT.KEYPRESS); i++) { 8000d48: 2300 movs r3, #0 8000d4a: 62fb str r3, [r7, #44] @ 0x2c 8000d4c: e014 b.n 8000d78 uartBuffer.KEYPRESS[i] |= msg.KEYPRESS[i]; 8000d4e: 4a1a ldr r2, [pc, #104] @ (8000db8 ) 8000d50: 6afb ldr r3, [r7, #44] @ 0x2c 8000d52: 4413 add r3, r2 8000d54: 3304 adds r3, #4 8000d56: 781a ldrb r2, [r3, #0] 8000d58: f107 0120 add.w r1, r7, #32 8000d5c: 6afb ldr r3, [r7, #44] @ 0x2c 8000d5e: 440b add r3, r1 8000d60: 781b ldrb r3, [r3, #0] 8000d62: 4313 orrs r3, r2 8000d64: b2d9 uxtb r1, r3 8000d66: 4a14 ldr r2, [pc, #80] @ (8000db8 ) 8000d68: 6afb ldr r3, [r7, #44] @ 0x2c 8000d6a: 4413 add r3, r2 8000d6c: 3304 adds r3, #4 8000d6e: 460a mov r2, r1 8000d70: 701a strb r2, [r3, #0] for (int i = 0; i < sizeof(REPORT.KEYPRESS); i++) { 8000d72: 6afb ldr r3, [r7, #44] @ 0x2c 8000d74: 3301 adds r3, #1 8000d76: 62fb str r3, [r7, #44] @ 0x2c 8000d78: 6afb ldr r3, [r7, #44] @ 0x2c 8000d7a: 2b0b cmp r3, #11 8000d7c: d9e7 bls.n 8000d4e uartUpdateFlag = 1; 8000d7e: 4b0f ldr r3, [pc, #60] @ (8000dbc ) 8000d80: 2201 movs r2, #1 8000d82: 601a str r2, [r3, #0] break; 8000d84: e005 b.n 8000d92 break; 8000d86: bf00 nop 8000d88: e004 b.n 8000d94 break; 8000d8a: bf00 nop 8000d8c: e002 b.n 8000d94 break; 8000d8e: bf00 nop 8000d90: e000 b.n 8000d94 break; 8000d92: bf00 nop } } 8000d94: bf00 nop 8000d96: 3734 adds r7, #52 @ 0x34 8000d98: 46bd mov sp, r7 8000d9a: bd90 pop {r4, r7, pc} 8000d9c: 20000358 .word 0x20000358 8000da0: 20000078 .word 0x20000078 8000da4: 200003a0 .word 0x200003a0 8000da8: 200003e8 .word 0x200003e8 8000dac: 20000310 .word 0x20000310 8000db0: 20000268 .word 0x20000268 8000db4: 20000260 .word 0x20000260 8000db8: 2000026c .word 0x2000026c 8000dbc: 2000027c .word 0x2000027c 08000dc0 : void addUSBReport(uint8_t usageID){ 8000dc0: b480 push {r7} 8000dc2: b085 sub sp, #20 8000dc4: af00 add r7, sp, #0 8000dc6: 4603 mov r3, r0 8000dc8: 71fb strb r3, [r7, #7] if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000dca: 79fb ldrb r3, [r7, #7] 8000dcc: 2b03 cmp r3, #3 8000dce: d922 bls.n 8000e16 8000dd0: 79fb ldrb r3, [r7, #7] 8000dd2: 2b73 cmp r3, #115 @ 0x73 8000dd4: d81f bhi.n 8000e16 uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit 8000dd6: 79fb ldrb r3, [r7, #7] 8000dd8: b29b uxth r3, r3 8000dda: 3b04 subs r3, #4 8000ddc: 81fb strh r3, [r7, #14] uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array 8000dde: 89fb ldrh r3, [r7, #14] 8000de0: 08db lsrs r3, r3, #3 8000de2: b29b uxth r3, r3 8000de4: 737b strb r3, [r7, #13] uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset 8000de6: 89fb ldrh r3, [r7, #14] 8000de8: b2db uxtb r3, r3 8000dea: f003 0307 and.w r3, r3, #7 8000dee: 733b strb r3, [r7, #12] REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); 8000df0: 7b7b ldrb r3, [r7, #13] 8000df2: 4a0c ldr r2, [pc, #48] @ (8000e24 ) 8000df4: 4413 add r3, r2 8000df6: 789b ldrb r3, [r3, #2] 8000df8: b25a sxtb r2, r3 8000dfa: 7b3b ldrb r3, [r7, #12] 8000dfc: 2101 movs r1, #1 8000dfe: fa01 f303 lsl.w r3, r1, r3 8000e02: b25b sxtb r3, r3 8000e04: 4313 orrs r3, r2 8000e06: b25a sxtb r2, r3 8000e08: 7b7b ldrb r3, [r7, #13] 8000e0a: b2d1 uxtb r1, r2 8000e0c: 4a05 ldr r2, [pc, #20] @ (8000e24 ) 8000e0e: 4413 add r3, r2 8000e10: 460a mov r2, r1 8000e12: 709a strb r2, [r3, #2] 8000e14: e000 b.n 8000e18 if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000e16: bf00 nop } 8000e18: 3714 adds r7, #20 8000e1a: 46bd mov sp, r7 8000e1c: f85d 7b04 ldr.w r7, [sp], #4 8000e20: 4770 bx lr 8000e22: bf00 nop 8000e24: 20000210 .word 0x20000210 08000e28 : void matrixScan(void){ 8000e28: b580 push {r7, lr} 8000e2a: b082 sub sp, #8 8000e2c: af00 add r7, sp, #0 for (uint8_t col = 0; col < COL; col++){ 8000e2e: 2300 movs r3, #0 8000e30: 71fb strb r3, [r7, #7] 8000e32: e044 b.n 8000ebe HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); 8000e34: 79fb ldrb r3, [r7, #7] 8000e36: 4a26 ldr r2, [pc, #152] @ (8000ed0 ) 8000e38: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000e3c: 79fb ldrb r3, [r7, #7] 8000e3e: 4a24 ldr r2, [pc, #144] @ (8000ed0 ) 8000e40: 00db lsls r3, r3, #3 8000e42: 4413 add r3, r2 8000e44: 889b ldrh r3, [r3, #4] 8000e46: 2201 movs r2, #1 8000e48: 4619 mov r1, r3 8000e4a: f001 fd7f bl 800294c HAL_Delay(1); 8000e4e: 2001 movs r0, #1 8000e50: f000 fe98 bl 8001b84 for(uint8_t row = 0; row < ROW; row++){ 8000e54: 2300 movs r3, #0 8000e56: 71bb strb r3, [r7, #6] 8000e58: e01e b.n 8000e98 if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){ 8000e5a: 79bb ldrb r3, [r7, #6] 8000e5c: 4a1d ldr r2, [pc, #116] @ (8000ed4 ) 8000e5e: f852 2033 ldr.w r2, [r2, r3, lsl #3] 8000e62: 79bb ldrb r3, [r7, #6] 8000e64: 491b ldr r1, [pc, #108] @ (8000ed4 ) 8000e66: 00db lsls r3, r3, #3 8000e68: 440b add r3, r1 8000e6a: 889b ldrh r3, [r3, #4] 8000e6c: 4619 mov r1, r3 8000e6e: 4610 mov r0, r2 8000e70: f001 fd54 bl 800291c 8000e74: 4603 mov r3, r0 8000e76: 2b00 cmp r3, #0 8000e78: d00b beq.n 8000e92 addUSBReport(KEYCODES[row][col]); 8000e7a: 79ba ldrb r2, [r7, #6] 8000e7c: 79f9 ldrb r1, [r7, #7] 8000e7e: 4816 ldr r0, [pc, #88] @ (8000ed8 ) 8000e80: 4613 mov r3, r2 8000e82: 009b lsls r3, r3, #2 8000e84: 4413 add r3, r2 8000e86: 4403 add r3, r0 8000e88: 440b add r3, r1 8000e8a: 781b ldrb r3, [r3, #0] 8000e8c: 4618 mov r0, r3 8000e8e: f7ff ff97 bl 8000dc0 for(uint8_t row = 0; row < ROW; row++){ 8000e92: 79bb ldrb r3, [r7, #6] 8000e94: 3301 adds r3, #1 8000e96: 71bb strb r3, [r7, #6] 8000e98: 79bb ldrb r3, [r7, #6] 8000e9a: 2b05 cmp r3, #5 8000e9c: d9dd bls.n 8000e5a } } HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); 8000e9e: 79fb ldrb r3, [r7, #7] 8000ea0: 4a0b ldr r2, [pc, #44] @ (8000ed0 ) 8000ea2: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000ea6: 79fb ldrb r3, [r7, #7] 8000ea8: 4a09 ldr r2, [pc, #36] @ (8000ed0 ) 8000eaa: 00db lsls r3, r3, #3 8000eac: 4413 add r3, r2 8000eae: 889b ldrh r3, [r3, #4] 8000eb0: 2200 movs r2, #0 8000eb2: 4619 mov r1, r3 8000eb4: f001 fd4a bl 800294c for (uint8_t col = 0; col < COL; col++){ 8000eb8: 79fb ldrb r3, [r7, #7] 8000eba: 3301 adds r3, #1 8000ebc: 71fb strb r3, [r7, #7] 8000ebe: 79fb ldrb r3, [r7, #7] 8000ec0: 2b04 cmp r3, #4 8000ec2: d9b7 bls.n 8000e34 } } 8000ec4: bf00 nop 8000ec6: bf00 nop 8000ec8: 3708 adds r7, #8 8000eca: 46bd mov sp, r7 8000ecc: bd80 pop {r7, pc} 8000ece: bf00 nop 8000ed0: 20000030 .word 0x20000030 8000ed4: 20000000 .word 0x20000000 8000ed8: 20000058 .word 0x20000058 08000edc : void resetReport(void){ 8000edc: b580 push {r7, lr} 8000ede: af00 add r7, sp, #0 REPORT.MODIFIER = 0; 8000ee0: 4b04 ldr r3, [pc, #16] @ (8000ef4 ) 8000ee2: 2200 movs r2, #0 8000ee4: 701a strb r2, [r3, #0] memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); 8000ee6: 220c movs r2, #12 8000ee8: 2100 movs r1, #0 8000eea: 4803 ldr r0, [pc, #12] @ (8000ef8 ) 8000eec: f009 fdbc bl 800aa68 } 8000ef0: bf00 nop 8000ef2: bd80 pop {r7, pc} 8000ef4: 20000210 .word 0x20000210 8000ef8: 20000212 .word 0x20000212 08000efc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000efc: b480 push {r7} 8000efe: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000f00: b672 cpsid i } 8000f02: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000f04: bf00 nop 8000f06: e7fd b.n 8000f04 08000f08 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000f08: b480 push {r7} 8000f0a: b083 sub sp, #12 8000f0c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000f0e: 2300 movs r3, #0 8000f10: 607b str r3, [r7, #4] 8000f12: 4b10 ldr r3, [pc, #64] @ (8000f54 ) 8000f14: 6c5b ldr r3, [r3, #68] @ 0x44 8000f16: 4a0f ldr r2, [pc, #60] @ (8000f54 ) 8000f18: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000f1c: 6453 str r3, [r2, #68] @ 0x44 8000f1e: 4b0d ldr r3, [pc, #52] @ (8000f54 ) 8000f20: 6c5b ldr r3, [r3, #68] @ 0x44 8000f22: f403 4380 and.w r3, r3, #16384 @ 0x4000 8000f26: 607b str r3, [r7, #4] 8000f28: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000f2a: 2300 movs r3, #0 8000f2c: 603b str r3, [r7, #0] 8000f2e: 4b09 ldr r3, [pc, #36] @ (8000f54 ) 8000f30: 6c1b ldr r3, [r3, #64] @ 0x40 8000f32: 4a08 ldr r2, [pc, #32] @ (8000f54 ) 8000f34: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000f38: 6413 str r3, [r2, #64] @ 0x40 8000f3a: 4b06 ldr r3, [pc, #24] @ (8000f54 ) 8000f3c: 6c1b ldr r3, [r3, #64] @ 0x40 8000f3e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000f42: 603b str r3, [r7, #0] 8000f44: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000f46: bf00 nop 8000f48: 370c adds r7, #12 8000f4a: 46bd mov sp, r7 8000f4c: f85d 7b04 ldr.w r7, [sp], #4 8000f50: 4770 bx lr 8000f52: bf00 nop 8000f54: 40023800 .word 0x40023800 08000f58 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000f58: b480 push {r7} 8000f5a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000f5c: bf00 nop 8000f5e: e7fd b.n 8000f5c 08000f60 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000f60: b480 push {r7} 8000f62: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000f64: bf00 nop 8000f66: e7fd b.n 8000f64 08000f68 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000f68: b480 push {r7} 8000f6a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000f6c: bf00 nop 8000f6e: e7fd b.n 8000f6c 08000f70 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000f70: b480 push {r7} 8000f72: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000f74: bf00 nop 8000f76: e7fd b.n 8000f74 08000f78 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000f78: b480 push {r7} 8000f7a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000f7c: bf00 nop 8000f7e: e7fd b.n 8000f7c 08000f80 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000f80: b480 push {r7} 8000f82: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000f84: bf00 nop 8000f86: 46bd mov sp, r7 8000f88: f85d 7b04 ldr.w r7, [sp], #4 8000f8c: 4770 bx lr 08000f8e : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000f8e: b480 push {r7} 8000f90: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000f92: bf00 nop 8000f94: 46bd mov sp, r7 8000f96: f85d 7b04 ldr.w r7, [sp], #4 8000f9a: 4770 bx lr 08000f9c : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000f9c: b480 push {r7} 8000f9e: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000fa0: bf00 nop 8000fa2: 46bd mov sp, r7 8000fa4: f85d 7b04 ldr.w r7, [sp], #4 8000fa8: 4770 bx lr 08000faa : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000faa: b580 push {r7, lr} 8000fac: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000fae: f000 fdc9 bl 8001b44 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000fb2: bf00 nop 8000fb4: bd80 pop {r7, pc} ... 08000fb8 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8000fb8: b580 push {r7, lr} 8000fba: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_rx); 8000fbc: 4802 ldr r0, [pc, #8] @ (8000fc8 ) 8000fbe: f001 f8af bl 8002120 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8000fc2: bf00 nop 8000fc4: bd80 pop {r7, pc} 8000fc6: bf00 nop 8000fc8: 200004f0 .word 0x200004f0 08000fcc : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8000fcc: b580 push {r7, lr} 8000fce: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_rx); 8000fd0: 4802 ldr r0, [pc, #8] @ (8000fdc ) 8000fd2: f001 f8a5 bl 8002120 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8000fd6: bf00 nop 8000fd8: bd80 pop {r7, pc} 8000fda: bf00 nop 8000fdc: 20000430 .word 0x20000430 08000fe0 : /** * @brief This function handles DMA1 stream4 global interrupt. */ void DMA1_Stream4_IRQHandler(void) { 8000fe0: b580 push {r7, lr} 8000fe2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ /* USER CODE END DMA1_Stream4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_tx); 8000fe4: 4802 ldr r0, [pc, #8] @ (8000ff0 ) 8000fe6: f001 f89b bl 8002120 /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ /* USER CODE END DMA1_Stream4_IRQn 1 */ } 8000fea: bf00 nop 8000fec: bd80 pop {r7, pc} 8000fee: bf00 nop 8000ff0: 20000490 .word 0x20000490 08000ff4 : /** * @brief This function handles DMA1 stream5 global interrupt. */ void DMA1_Stream5_IRQHandler(void) { 8000ff4: b580 push {r7, lr} 8000ff6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ /* USER CODE END DMA1_Stream5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8000ff8: 4802 ldr r0, [pc, #8] @ (8001004 ) 8000ffa: f001 f891 bl 8002120 /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ /* USER CODE END DMA1_Stream5_IRQn 1 */ } 8000ffe: bf00 nop 8001000: bd80 pop {r7, pc} 8001002: bf00 nop 8001004: 20000670 .word 0x20000670 08001008 : /** * @brief This function handles DMA1 stream6 global interrupt. */ void DMA1_Stream6_IRQHandler(void) { 8001008: b580 push {r7, lr} 800100a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ /* USER CODE END DMA1_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 800100c: 4802 ldr r0, [pc, #8] @ (8001018 ) 800100e: f001 f887 bl 8002120 /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ /* USER CODE END DMA1_Stream6_IRQn 1 */ } 8001012: bf00 nop 8001014: bd80 pop {r7, pc} 8001016: bf00 nop 8001018: 200006d0 .word 0x200006d0 0800101c : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 800101c: b580 push {r7, lr} 800101e: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8001020: 4802 ldr r0, [pc, #8] @ (800102c ) 8001022: f004 fe9f bl 8005d64 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8001026: bf00 nop 8001028: bd80 pop {r7, pc} 800102a: bf00 nop 800102c: 200003a0 .word 0x200003a0 08001030 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 8001030: b580 push {r7, lr} 8001032: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8001034: 4802 ldr r0, [pc, #8] @ (8001040 ) 8001036: f004 fe95 bl 8005d64 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 800103a: bf00 nop 800103c: bd80 pop {r7, pc} 800103e: bf00 nop 8001040: 200003e8 .word 0x200003e8 08001044 : /** * @brief This function handles DMA1 stream7 global interrupt. */ void DMA1_Stream7_IRQHandler(void) { 8001044: b580 push {r7, lr} 8001046: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ /* USER CODE END DMA1_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_tx); 8001048: 4802 ldr r0, [pc, #8] @ (8001054 ) 800104a: f001 f869 bl 8002120 /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ /* USER CODE END DMA1_Stream7_IRQn 1 */ } 800104e: bf00 nop 8001050: bd80 pop {r7, pc} 8001052: bf00 nop 8001054: 20000550 .word 0x20000550 08001058 : /** * @brief This function handles UART4 global interrupt. */ void UART4_IRQHandler(void) { 8001058: b580 push {r7, lr} 800105a: af00 add r7, sp, #0 /* USER CODE BEGIN UART4_IRQn 0 */ /* USER CODE END UART4_IRQn 0 */ HAL_UART_IRQHandler(&huart4); 800105c: 4802 ldr r0, [pc, #8] @ (8001068 ) 800105e: f004 fe81 bl 8005d64 /* USER CODE BEGIN UART4_IRQn 1 */ /* USER CODE END UART4_IRQn 1 */ } 8001062: bf00 nop 8001064: bd80 pop {r7, pc} 8001066: bf00 nop 8001068: 20000310 .word 0x20000310 0800106c : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800106c: b580 push {r7, lr} 800106e: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 8001070: 4802 ldr r0, [pc, #8] @ (800107c ) 8001072: f004 fe77 bl 8005d64 /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 8001076: bf00 nop 8001078: bd80 pop {r7, pc} 800107a: bf00 nop 800107c: 20000358 .word 0x20000358 08001080 : /** * @brief This function handles DMA2 stream2 global interrupt. */ void DMA2_Stream2_IRQHandler(void) { 8001080: b580 push {r7, lr} 8001082: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 8001084: 4802 ldr r0, [pc, #8] @ (8001090 ) 8001086: f001 f84b bl 8002120 /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } 800108a: bf00 nop 800108c: bd80 pop {r7, pc} 800108e: bf00 nop 8001090: 200005b0 .word 0x200005b0 08001094 : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 8001094: b580 push {r7, lr} 8001096: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 8001098: 4802 ldr r0, [pc, #8] @ (80010a4 ) 800109a: f001 ff00 bl 8002e9e /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 800109e: bf00 nop 80010a0: bd80 pop {r7, pc} 80010a2: bf00 nop 80010a4: 20000c14 .word 0x20000c14 080010a8 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 80010a8: b580 push {r7, lr} 80010aa: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 80010ac: 4802 ldr r0, [pc, #8] @ (80010b8 ) 80010ae: f001 f837 bl 8002120 /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 80010b2: bf00 nop 80010b4: bd80 pop {r7, pc} 80010b6: bf00 nop 80010b8: 20000610 .word 0x20000610 080010bc : * configuration. * @param None * @retval None */ void SystemInit(void) { 80010bc: b480 push {r7} 80010be: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 80010c0: 4b06 ldr r3, [pc, #24] @ (80010dc ) 80010c2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80010c6: 4a05 ldr r2, [pc, #20] @ (80010dc ) 80010c8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80010cc: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 80010d0: bf00 nop 80010d2: 46bd mov sp, r7 80010d4: f85d 7b04 ldr.w r7, [sp], #4 80010d8: 4770 bx lr 80010da: bf00 nop 80010dc: e000ed00 .word 0xe000ed00 080010e0 : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { 80010e0: b580 push {r7, lr} 80010e2: b08a sub sp, #40 @ 0x28 80010e4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010e6: f107 0320 add.w r3, r7, #32 80010ea: 2200 movs r2, #0 80010ec: 601a str r2, [r3, #0] 80010ee: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 80010f0: 1d3b adds r3, r7, #4 80010f2: 2200 movs r2, #0 80010f4: 601a str r2, [r3, #0] 80010f6: 605a str r2, [r3, #4] 80010f8: 609a str r2, [r3, #8] 80010fa: 60da str r2, [r3, #12] 80010fc: 611a str r2, [r3, #16] 80010fe: 615a str r2, [r3, #20] 8001100: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8001102: 4b22 ldr r3, [pc, #136] @ (800118c ) 8001104: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8001108: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 800110a: 4b20 ldr r3, [pc, #128] @ (800118c ) 800110c: 2200 movs r2, #0 800110e: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8001110: 4b1e ldr r3, [pc, #120] @ (800118c ) 8001112: 2200 movs r2, #0 8001114: 609a str r2, [r3, #8] htim2.Init.Period = 4294967295; 8001116: 4b1d ldr r3, [pc, #116] @ (800118c ) 8001118: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800111c: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800111e: 4b1b ldr r3, [pc, #108] @ (800118c ) 8001120: 2200 movs r2, #0 8001122: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001124: 4b19 ldr r3, [pc, #100] @ (800118c ) 8001126: 2200 movs r2, #0 8001128: 619a str r2, [r3, #24] if (HAL_TIM_OC_Init(&htim2) != HAL_OK) 800112a: 4818 ldr r0, [pc, #96] @ (800118c ) 800112c: f004 f904 bl 8005338 8001130: 4603 mov r3, r0 8001132: 2b00 cmp r3, #0 8001134: d001 beq.n 800113a { Error_Handler(); 8001136: f7ff fee1 bl 8000efc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800113a: 2300 movs r3, #0 800113c: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800113e: 2300 movs r3, #0 8001140: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8001142: f107 0320 add.w r3, r7, #32 8001146: 4619 mov r1, r3 8001148: 4810 ldr r0, [pc, #64] @ (800118c ) 800114a: f004 fc9d bl 8005a88 800114e: 4603 mov r3, r0 8001150: 2b00 cmp r3, #0 8001152: d001 beq.n 8001158 { Error_Handler(); 8001154: f7ff fed2 bl 8000efc } sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; 8001158: 2350 movs r3, #80 @ 0x50 800115a: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800115c: 2300 movs r3, #0 800115e: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001160: 2300 movs r3, #0 8001162: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001164: 2300 movs r3, #0 8001166: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001168: 1d3b adds r3, r7, #4 800116a: 2200 movs r2, #0 800116c: 4619 mov r1, r3 800116e: 4807 ldr r0, [pc, #28] @ (800118c ) 8001170: f004 f9d8 bl 8005524 8001174: 4603 mov r3, r0 8001176: 2b00 cmp r3, #0 8001178: d001 beq.n 800117e { Error_Handler(); 800117a: f7ff febf bl 8000efc } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 800117e: 4803 ldr r0, [pc, #12] @ (800118c ) 8001180: f000 f8c2 bl 8001308 } 8001184: bf00 nop 8001186: 3728 adds r7, #40 @ 0x28 8001188: 46bd mov sp, r7 800118a: bd80 pop {r7, pc} 800118c: 20000280 .word 0x20000280 08001190 : /* TIM3 init function */ void MX_TIM3_Init(void) { 8001190: b580 push {r7, lr} 8001192: b08c sub sp, #48 @ 0x30 8001194: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 8001196: f107 030c add.w r3, r7, #12 800119a: 2224 movs r2, #36 @ 0x24 800119c: 2100 movs r1, #0 800119e: 4618 mov r0, r3 80011a0: f009 fc62 bl 800aa68 TIM_MasterConfigTypeDef sMasterConfig = {0}; 80011a4: 1d3b adds r3, r7, #4 80011a6: 2200 movs r2, #0 80011a8: 601a str r2, [r3, #0] 80011aa: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80011ac: 4b20 ldr r3, [pc, #128] @ (8001230 ) 80011ae: 4a21 ldr r2, [pc, #132] @ (8001234 ) 80011b0: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 80011b2: 4b1f ldr r3, [pc, #124] @ (8001230 ) 80011b4: 2200 movs r2, #0 80011b6: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80011b8: 4b1d ldr r3, [pc, #116] @ (8001230 ) 80011ba: 2200 movs r2, #0 80011bc: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 80011be: 4b1c ldr r3, [pc, #112] @ (8001230 ) 80011c0: f64f 72ff movw r2, #65535 @ 0xffff 80011c4: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80011c6: 4b1a ldr r3, [pc, #104] @ (8001230 ) 80011c8: 2200 movs r2, #0 80011ca: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80011cc: 4b18 ldr r3, [pc, #96] @ (8001230 ) 80011ce: 2200 movs r2, #0 80011d0: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI1; 80011d2: 2301 movs r3, #1 80011d4: 60fb str r3, [r7, #12] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 80011d6: 2300 movs r3, #0 80011d8: 613b str r3, [r7, #16] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 80011da: 2301 movs r3, #1 80011dc: 617b str r3, [r7, #20] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 80011de: 2300 movs r3, #0 80011e0: 61bb str r3, [r7, #24] sConfig.IC1Filter = 0; 80011e2: 2300 movs r3, #0 80011e4: 61fb str r3, [r7, #28] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 80011e6: 2300 movs r3, #0 80011e8: 623b str r3, [r7, #32] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 80011ea: 2301 movs r3, #1 80011ec: 627b str r3, [r7, #36] @ 0x24 sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 80011ee: 2300 movs r3, #0 80011f0: 62bb str r3, [r7, #40] @ 0x28 sConfig.IC2Filter = 0; 80011f2: 2300 movs r3, #0 80011f4: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 80011f6: f107 030c add.w r3, r7, #12 80011fa: 4619 mov r1, r3 80011fc: 480c ldr r0, [pc, #48] @ (8001230 ) 80011fe: f004 f8ea bl 80053d6 8001202: 4603 mov r3, r0 8001204: 2b00 cmp r3, #0 8001206: d001 beq.n 800120c { Error_Handler(); 8001208: f7ff fe78 bl 8000efc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800120c: 2300 movs r3, #0 800120e: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001210: 2300 movs r3, #0 8001212: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8001214: 1d3b adds r3, r7, #4 8001216: 4619 mov r1, r3 8001218: 4805 ldr r0, [pc, #20] @ (8001230 ) 800121a: f004 fc35 bl 8005a88 800121e: 4603 mov r3, r0 8001220: 2b00 cmp r3, #0 8001222: d001 beq.n 8001228 { Error_Handler(); 8001224: f7ff fe6a bl 8000efc } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8001228: bf00 nop 800122a: 3730 adds r7, #48 @ 0x30 800122c: 46bd mov sp, r7 800122e: bd80 pop {r7, pc} 8001230: 200002c8 .word 0x200002c8 8001234: 40000400 .word 0x40000400 08001238 : void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) { 8001238: b480 push {r7} 800123a: b085 sub sp, #20 800123c: af00 add r7, sp, #0 800123e: 6078 str r0, [r7, #4] if(tim_ocHandle->Instance==TIM2) 8001240: 687b ldr r3, [r7, #4] 8001242: 681b ldr r3, [r3, #0] 8001244: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001248: d10d bne.n 8001266 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 800124a: 2300 movs r3, #0 800124c: 60fb str r3, [r7, #12] 800124e: 4b09 ldr r3, [pc, #36] @ (8001274 ) 8001250: 6c1b ldr r3, [r3, #64] @ 0x40 8001252: 4a08 ldr r2, [pc, #32] @ (8001274 ) 8001254: f043 0301 orr.w r3, r3, #1 8001258: 6413 str r3, [r2, #64] @ 0x40 800125a: 4b06 ldr r3, [pc, #24] @ (8001274 ) 800125c: 6c1b ldr r3, [r3, #64] @ 0x40 800125e: f003 0301 and.w r3, r3, #1 8001262: 60fb str r3, [r7, #12] 8001264: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 8001266: bf00 nop 8001268: 3714 adds r7, #20 800126a: 46bd mov sp, r7 800126c: f85d 7b04 ldr.w r7, [sp], #4 8001270: 4770 bx lr 8001272: bf00 nop 8001274: 40023800 .word 0x40023800 08001278 : void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) { 8001278: b580 push {r7, lr} 800127a: b08a sub sp, #40 @ 0x28 800127c: af00 add r7, sp, #0 800127e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001280: f107 0314 add.w r3, r7, #20 8001284: 2200 movs r2, #0 8001286: 601a str r2, [r3, #0] 8001288: 605a str r2, [r3, #4] 800128a: 609a str r2, [r3, #8] 800128c: 60da str r2, [r3, #12] 800128e: 611a str r2, [r3, #16] if(tim_encoderHandle->Instance==TIM3) 8001290: 687b ldr r3, [r7, #4] 8001292: 681b ldr r3, [r3, #0] 8001294: 4a19 ldr r2, [pc, #100] @ (80012fc ) 8001296: 4293 cmp r3, r2 8001298: d12b bne.n 80012f2 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800129a: 2300 movs r3, #0 800129c: 613b str r3, [r7, #16] 800129e: 4b18 ldr r3, [pc, #96] @ (8001300 ) 80012a0: 6c1b ldr r3, [r3, #64] @ 0x40 80012a2: 4a17 ldr r2, [pc, #92] @ (8001300 ) 80012a4: f043 0302 orr.w r3, r3, #2 80012a8: 6413 str r3, [r2, #64] @ 0x40 80012aa: 4b15 ldr r3, [pc, #84] @ (8001300 ) 80012ac: 6c1b ldr r3, [r3, #64] @ 0x40 80012ae: f003 0302 and.w r3, r3, #2 80012b2: 613b str r3, [r7, #16] 80012b4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80012b6: 2300 movs r3, #0 80012b8: 60fb str r3, [r7, #12] 80012ba: 4b11 ldr r3, [pc, #68] @ (8001300 ) 80012bc: 6b1b ldr r3, [r3, #48] @ 0x30 80012be: 4a10 ldr r2, [pc, #64] @ (8001300 ) 80012c0: f043 0301 orr.w r3, r3, #1 80012c4: 6313 str r3, [r2, #48] @ 0x30 80012c6: 4b0e ldr r3, [pc, #56] @ (8001300 ) 80012c8: 6b1b ldr r3, [r3, #48] @ 0x30 80012ca: f003 0301 and.w r3, r3, #1 80012ce: 60fb str r3, [r7, #12] 80012d0: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80012d2: 23c0 movs r3, #192 @ 0xc0 80012d4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80012d6: 2302 movs r3, #2 80012d8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012da: 2300 movs r3, #0 80012dc: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80012de: 2300 movs r3, #0 80012e0: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 80012e2: 2302 movs r3, #2 80012e4: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80012e6: f107 0314 add.w r3, r7, #20 80012ea: 4619 mov r1, r3 80012ec: 4805 ldr r0, [pc, #20] @ (8001304 ) 80012ee: f001 f981 bl 80025f4 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 80012f2: bf00 nop 80012f4: 3728 adds r7, #40 @ 0x28 80012f6: 46bd mov sp, r7 80012f8: bd80 pop {r7, pc} 80012fa: bf00 nop 80012fc: 40000400 .word 0x40000400 8001300: 40023800 .word 0x40023800 8001304: 40020000 .word 0x40020000 08001308 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 8001308: b580 push {r7, lr} 800130a: b088 sub sp, #32 800130c: af00 add r7, sp, #0 800130e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001310: f107 030c add.w r3, r7, #12 8001314: 2200 movs r2, #0 8001316: 601a str r2, [r3, #0] 8001318: 605a str r2, [r3, #4] 800131a: 609a str r2, [r3, #8] 800131c: 60da str r2, [r3, #12] 800131e: 611a str r2, [r3, #16] if(timHandle->Instance==TIM2) 8001320: 687b ldr r3, [r7, #4] 8001322: 681b ldr r3, [r3, #0] 8001324: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001328: d11d bne.n 8001366 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800132a: 2300 movs r3, #0 800132c: 60bb str r3, [r7, #8] 800132e: 4b10 ldr r3, [pc, #64] @ (8001370 ) 8001330: 6b1b ldr r3, [r3, #48] @ 0x30 8001332: 4a0f ldr r2, [pc, #60] @ (8001370 ) 8001334: f043 0301 orr.w r3, r3, #1 8001338: 6313 str r3, [r2, #48] @ 0x30 800133a: 4b0d ldr r3, [pc, #52] @ (8001370 ) 800133c: 6b1b ldr r3, [r3, #48] @ 0x30 800133e: f003 0301 and.w r3, r3, #1 8001342: 60bb str r3, [r7, #8] 8001344: 68bb ldr r3, [r7, #8] /**TIM2 GPIO Configuration PA5 ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8001346: 2320 movs r3, #32 8001348: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800134a: 2302 movs r3, #2 800134c: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800134e: 2300 movs r3, #0 8001350: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001352: 2300 movs r3, #0 8001354: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8001356: 2301 movs r3, #1 8001358: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800135a: f107 030c add.w r3, r7, #12 800135e: 4619 mov r1, r3 8001360: 4804 ldr r0, [pc, #16] @ (8001374 ) 8001362: f001 f947 bl 80025f4 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8001366: bf00 nop 8001368: 3720 adds r7, #32 800136a: 46bd mov sp, r7 800136c: bd80 pop {r7, pc} 800136e: bf00 nop 8001370: 40023800 .word 0x40023800 8001374: 40020000 .word 0x40020000 08001378 : DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart2_tx; /* UART4 init function */ void MX_UART4_Init(void) { 8001378: b580 push {r7, lr} 800137a: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 800137c: 4b11 ldr r3, [pc, #68] @ (80013c4 ) 800137e: 4a12 ldr r2, [pc, #72] @ (80013c8 ) 8001380: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 8001382: 4b10 ldr r3, [pc, #64] @ (80013c4 ) 8001384: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001388: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 800138a: 4b0e ldr r3, [pc, #56] @ (80013c4 ) 800138c: 2200 movs r2, #0 800138e: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 8001390: 4b0c ldr r3, [pc, #48] @ (80013c4 ) 8001392: 2200 movs r2, #0 8001394: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 8001396: 4b0b ldr r3, [pc, #44] @ (80013c4 ) 8001398: 2200 movs r2, #0 800139a: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 800139c: 4b09 ldr r3, [pc, #36] @ (80013c4 ) 800139e: 220c movs r2, #12 80013a0: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80013a2: 4b08 ldr r3, [pc, #32] @ (80013c4 ) 80013a4: 2200 movs r2, #0 80013a6: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 80013a8: 4b06 ldr r3, [pc, #24] @ (80013c4 ) 80013aa: 2200 movs r2, #0 80013ac: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart4) != HAL_OK) 80013ae: 4805 ldr r0, [pc, #20] @ (80013c4 ) 80013b0: f004 fbe6 bl 8005b80 80013b4: 4603 mov r3, r0 80013b6: 2b00 cmp r3, #0 80013b8: d001 beq.n 80013be { Error_Handler(); 80013ba: f7ff fd9f bl 8000efc } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 80013be: bf00 nop 80013c0: bd80 pop {r7, pc} 80013c2: bf00 nop 80013c4: 20000310 .word 0x20000310 80013c8: 40004c00 .word 0x40004c00 080013cc : /* UART5 init function */ void MX_UART5_Init(void) { 80013cc: b580 push {r7, lr} 80013ce: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 80013d0: 4b11 ldr r3, [pc, #68] @ (8001418 ) 80013d2: 4a12 ldr r2, [pc, #72] @ (800141c ) 80013d4: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 80013d6: 4b10 ldr r3, [pc, #64] @ (8001418 ) 80013d8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80013dc: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 80013de: 4b0e ldr r3, [pc, #56] @ (8001418 ) 80013e0: 2200 movs r2, #0 80013e2: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 80013e4: 4b0c ldr r3, [pc, #48] @ (8001418 ) 80013e6: 2200 movs r2, #0 80013e8: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 80013ea: 4b0b ldr r3, [pc, #44] @ (8001418 ) 80013ec: 2200 movs r2, #0 80013ee: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 80013f0: 4b09 ldr r3, [pc, #36] @ (8001418 ) 80013f2: 220c movs r2, #12 80013f4: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80013f6: 4b08 ldr r3, [pc, #32] @ (8001418 ) 80013f8: 2200 movs r2, #0 80013fa: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 80013fc: 4b06 ldr r3, [pc, #24] @ (8001418 ) 80013fe: 2200 movs r2, #0 8001400: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 8001402: 4805 ldr r0, [pc, #20] @ (8001418 ) 8001404: f004 fbbc bl 8005b80 8001408: 4603 mov r3, r0 800140a: 2b00 cmp r3, #0 800140c: d001 beq.n 8001412 { Error_Handler(); 800140e: f7ff fd75 bl 8000efc } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 8001412: bf00 nop 8001414: bd80 pop {r7, pc} 8001416: bf00 nop 8001418: 20000358 .word 0x20000358 800141c: 40005000 .word 0x40005000 08001420 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 8001420: b580 push {r7, lr} 8001422: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001424: 4b11 ldr r3, [pc, #68] @ (800146c ) 8001426: 4a12 ldr r2, [pc, #72] @ (8001470 ) 8001428: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800142a: 4b10 ldr r3, [pc, #64] @ (800146c ) 800142c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001430: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8001432: 4b0e ldr r3, [pc, #56] @ (800146c ) 8001434: 2200 movs r2, #0 8001436: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001438: 4b0c ldr r3, [pc, #48] @ (800146c ) 800143a: 2200 movs r2, #0 800143c: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800143e: 4b0b ldr r3, [pc, #44] @ (800146c ) 8001440: 2200 movs r2, #0 8001442: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001444: 4b09 ldr r3, [pc, #36] @ (800146c ) 8001446: 220c movs r2, #12 8001448: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800144a: 4b08 ldr r3, [pc, #32] @ (800146c ) 800144c: 2200 movs r2, #0 800144e: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001450: 4b06 ldr r3, [pc, #24] @ (800146c ) 8001452: 2200 movs r2, #0 8001454: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8001456: 4805 ldr r0, [pc, #20] @ (800146c ) 8001458: f004 fb92 bl 8005b80 800145c: 4603 mov r3, r0 800145e: 2b00 cmp r3, #0 8001460: d001 beq.n 8001466 { Error_Handler(); 8001462: f7ff fd4b bl 8000efc } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001466: bf00 nop 8001468: bd80 pop {r7, pc} 800146a: bf00 nop 800146c: 200003a0 .word 0x200003a0 8001470: 40011000 .word 0x40011000 08001474 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 8001474: b580 push {r7, lr} 8001476: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8001478: 4b11 ldr r3, [pc, #68] @ (80014c0 ) 800147a: 4a12 ldr r2, [pc, #72] @ (80014c4 ) 800147c: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800147e: 4b10 ldr r3, [pc, #64] @ (80014c0 ) 8001480: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001484: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8001486: 4b0e ldr r3, [pc, #56] @ (80014c0 ) 8001488: 2200 movs r2, #0 800148a: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800148c: 4b0c ldr r3, [pc, #48] @ (80014c0 ) 800148e: 2200 movs r2, #0 8001490: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 8001492: 4b0b ldr r3, [pc, #44] @ (80014c0 ) 8001494: 2200 movs r2, #0 8001496: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8001498: 4b09 ldr r3, [pc, #36] @ (80014c0 ) 800149a: 220c movs r2, #12 800149c: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800149e: 4b08 ldr r3, [pc, #32] @ (80014c0 ) 80014a0: 2200 movs r2, #0 80014a2: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 80014a4: 4b06 ldr r3, [pc, #24] @ (80014c0 ) 80014a6: 2200 movs r2, #0 80014a8: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 80014aa: 4805 ldr r0, [pc, #20] @ (80014c0 ) 80014ac: f004 fb68 bl 8005b80 80014b0: 4603 mov r3, r0 80014b2: 2b00 cmp r3, #0 80014b4: d001 beq.n 80014ba { Error_Handler(); 80014b6: f7ff fd21 bl 8000efc } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80014ba: bf00 nop 80014bc: bd80 pop {r7, pc} 80014be: bf00 nop 80014c0: 200003e8 .word 0x200003e8 80014c4: 40004400 .word 0x40004400 080014c8 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 80014c8: b580 push {r7, lr} 80014ca: b090 sub sp, #64 @ 0x40 80014cc: af00 add r7, sp, #0 80014ce: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80014d0: f107 032c add.w r3, r7, #44 @ 0x2c 80014d4: 2200 movs r2, #0 80014d6: 601a str r2, [r3, #0] 80014d8: 605a str r2, [r3, #4] 80014da: 609a str r2, [r3, #8] 80014dc: 60da str r2, [r3, #12] 80014de: 611a str r2, [r3, #16] if(uartHandle->Instance==UART4) 80014e0: 687b ldr r3, [r7, #4] 80014e2: 681b ldr r3, [r3, #0] 80014e4: 4a4a ldr r2, [pc, #296] @ (8001610 ) 80014e6: 4293 cmp r3, r2 80014e8: f040 80a0 bne.w 800162c { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* UART4 clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 80014ec: 2300 movs r3, #0 80014ee: 62bb str r3, [r7, #40] @ 0x28 80014f0: 4b48 ldr r3, [pc, #288] @ (8001614 ) 80014f2: 6c1b ldr r3, [r3, #64] @ 0x40 80014f4: 4a47 ldr r2, [pc, #284] @ (8001614 ) 80014f6: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80014fa: 6413 str r3, [r2, #64] @ 0x40 80014fc: 4b45 ldr r3, [pc, #276] @ (8001614 ) 80014fe: 6c1b ldr r3, [r3, #64] @ 0x40 8001500: f403 2300 and.w r3, r3, #524288 @ 0x80000 8001504: 62bb str r3, [r7, #40] @ 0x28 8001506: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001508: 2300 movs r3, #0 800150a: 627b str r3, [r7, #36] @ 0x24 800150c: 4b41 ldr r3, [pc, #260] @ (8001614 ) 800150e: 6b1b ldr r3, [r3, #48] @ 0x30 8001510: 4a40 ldr r2, [pc, #256] @ (8001614 ) 8001512: f043 0301 orr.w r3, r3, #1 8001516: 6313 str r3, [r2, #48] @ 0x30 8001518: 4b3e ldr r3, [pc, #248] @ (8001614 ) 800151a: 6b1b ldr r3, [r3, #48] @ 0x30 800151c: f003 0301 and.w r3, r3, #1 8001520: 627b str r3, [r7, #36] @ 0x24 8001522: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART4 GPIO Configuration PA0-WKUP ------> UART4_TX PA1 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8001524: 2303 movs r3, #3 8001526: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001528: 2302 movs r3, #2 800152a: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 800152c: 2300 movs r3, #0 800152e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001530: 2303 movs r3, #3 8001532: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 8001534: 2308 movs r3, #8 8001536: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001538: f107 032c add.w r3, r7, #44 @ 0x2c 800153c: 4619 mov r1, r3 800153e: 4836 ldr r0, [pc, #216] @ (8001618 ) 8001540: f001 f858 bl 80025f4 /* UART4 DMA Init */ /* UART4_RX Init */ hdma_uart4_rx.Instance = DMA1_Stream2; 8001544: 4b35 ldr r3, [pc, #212] @ (800161c ) 8001546: 4a36 ldr r2, [pc, #216] @ (8001620 ) 8001548: 601a str r2, [r3, #0] hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; 800154a: 4b34 ldr r3, [pc, #208] @ (800161c ) 800154c: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001550: 605a str r2, [r3, #4] hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001552: 4b32 ldr r3, [pc, #200] @ (800161c ) 8001554: 2200 movs r2, #0 8001556: 609a str r2, [r3, #8] hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001558: 4b30 ldr r3, [pc, #192] @ (800161c ) 800155a: 2200 movs r2, #0 800155c: 60da str r2, [r3, #12] hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; 800155e: 4b2f ldr r3, [pc, #188] @ (800161c ) 8001560: f44f 6280 mov.w r2, #1024 @ 0x400 8001564: 611a str r2, [r3, #16] hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001566: 4b2d ldr r3, [pc, #180] @ (800161c ) 8001568: 2200 movs r2, #0 800156a: 615a str r2, [r3, #20] hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800156c: 4b2b ldr r3, [pc, #172] @ (800161c ) 800156e: 2200 movs r2, #0 8001570: 619a str r2, [r3, #24] hdma_uart4_rx.Init.Mode = DMA_NORMAL; 8001572: 4b2a ldr r3, [pc, #168] @ (800161c ) 8001574: 2200 movs r2, #0 8001576: 61da str r2, [r3, #28] hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; 8001578: 4b28 ldr r3, [pc, #160] @ (800161c ) 800157a: 2200 movs r2, #0 800157c: 621a str r2, [r3, #32] hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800157e: 4b27 ldr r3, [pc, #156] @ (800161c ) 8001580: 2200 movs r2, #0 8001582: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) 8001584: 4825 ldr r0, [pc, #148] @ (800161c ) 8001586: f000 fc33 bl 8001df0 800158a: 4603 mov r3, r0 800158c: 2b00 cmp r3, #0 800158e: d001 beq.n 8001594 { Error_Handler(); 8001590: f7ff fcb4 bl 8000efc } __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); 8001594: 687b ldr r3, [r7, #4] 8001596: 4a21 ldr r2, [pc, #132] @ (800161c ) 8001598: 63da str r2, [r3, #60] @ 0x3c 800159a: 4a20 ldr r2, [pc, #128] @ (800161c ) 800159c: 687b ldr r3, [r7, #4] 800159e: 6393 str r3, [r2, #56] @ 0x38 /* UART4_TX Init */ hdma_uart4_tx.Instance = DMA1_Stream4; 80015a0: 4b20 ldr r3, [pc, #128] @ (8001624 ) 80015a2: 4a21 ldr r2, [pc, #132] @ (8001628 ) 80015a4: 601a str r2, [r3, #0] hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; 80015a6: 4b1f ldr r3, [pc, #124] @ (8001624 ) 80015a8: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80015ac: 605a str r2, [r3, #4] hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80015ae: 4b1d ldr r3, [pc, #116] @ (8001624 ) 80015b0: 2240 movs r2, #64 @ 0x40 80015b2: 609a str r2, [r3, #8] hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80015b4: 4b1b ldr r3, [pc, #108] @ (8001624 ) 80015b6: 2200 movs r2, #0 80015b8: 60da str r2, [r3, #12] hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; 80015ba: 4b1a ldr r3, [pc, #104] @ (8001624 ) 80015bc: f44f 6280 mov.w r2, #1024 @ 0x400 80015c0: 611a str r2, [r3, #16] hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80015c2: 4b18 ldr r3, [pc, #96] @ (8001624 ) 80015c4: 2200 movs r2, #0 80015c6: 615a str r2, [r3, #20] hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80015c8: 4b16 ldr r3, [pc, #88] @ (8001624 ) 80015ca: 2200 movs r2, #0 80015cc: 619a str r2, [r3, #24] hdma_uart4_tx.Init.Mode = DMA_NORMAL; 80015ce: 4b15 ldr r3, [pc, #84] @ (8001624 ) 80015d0: 2200 movs r2, #0 80015d2: 61da str r2, [r3, #28] hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; 80015d4: 4b13 ldr r3, [pc, #76] @ (8001624 ) 80015d6: 2200 movs r2, #0 80015d8: 621a str r2, [r3, #32] hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80015da: 4b12 ldr r3, [pc, #72] @ (8001624 ) 80015dc: 2200 movs r2, #0 80015de: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) 80015e0: 4810 ldr r0, [pc, #64] @ (8001624 ) 80015e2: f000 fc05 bl 8001df0 80015e6: 4603 mov r3, r0 80015e8: 2b00 cmp r3, #0 80015ea: d001 beq.n 80015f0 { Error_Handler(); 80015ec: f7ff fc86 bl 8000efc } __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); 80015f0: 687b ldr r3, [r7, #4] 80015f2: 4a0c ldr r2, [pc, #48] @ (8001624 ) 80015f4: 639a str r2, [r3, #56] @ 0x38 80015f6: 4a0b ldr r2, [pc, #44] @ (8001624 ) 80015f8: 687b ldr r3, [r7, #4] 80015fa: 6393 str r3, [r2, #56] @ 0x38 /* UART4 interrupt Init */ HAL_NVIC_SetPriority(UART4_IRQn, 5, 0); 80015fc: 2200 movs r2, #0 80015fe: 2105 movs r1, #5 8001600: 2034 movs r0, #52 @ 0x34 8001602: f000 fbbe bl 8001d82 HAL_NVIC_EnableIRQ(UART4_IRQn); 8001606: 2034 movs r0, #52 @ 0x34 8001608: f000 fbd7 bl 8001dba HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 800160c: e202 b.n 8001a14 800160e: bf00 nop 8001610: 40004c00 .word 0x40004c00 8001614: 40023800 .word 0x40023800 8001618: 40020000 .word 0x40020000 800161c: 20000430 .word 0x20000430 8001620: 40026040 .word 0x40026040 8001624: 20000490 .word 0x20000490 8001628: 40026070 .word 0x40026070 else if(uartHandle->Instance==UART5) 800162c: 687b ldr r3, [r7, #4] 800162e: 681b ldr r3, [r3, #0] 8001630: 4a59 ldr r2, [pc, #356] @ (8001798 ) 8001632: 4293 cmp r3, r2 8001634: f040 80c0 bne.w 80017b8 __HAL_RCC_UART5_CLK_ENABLE(); 8001638: 2300 movs r3, #0 800163a: 623b str r3, [r7, #32] 800163c: 4b57 ldr r3, [pc, #348] @ (800179c ) 800163e: 6c1b ldr r3, [r3, #64] @ 0x40 8001640: 4a56 ldr r2, [pc, #344] @ (800179c ) 8001642: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8001646: 6413 str r3, [r2, #64] @ 0x40 8001648: 4b54 ldr r3, [pc, #336] @ (800179c ) 800164a: 6c1b ldr r3, [r3, #64] @ 0x40 800164c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8001650: 623b str r3, [r7, #32] 8001652: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001654: 2300 movs r3, #0 8001656: 61fb str r3, [r7, #28] 8001658: 4b50 ldr r3, [pc, #320] @ (800179c ) 800165a: 6b1b ldr r3, [r3, #48] @ 0x30 800165c: 4a4f ldr r2, [pc, #316] @ (800179c ) 800165e: f043 0304 orr.w r3, r3, #4 8001662: 6313 str r3, [r2, #48] @ 0x30 8001664: 4b4d ldr r3, [pc, #308] @ (800179c ) 8001666: 6b1b ldr r3, [r3, #48] @ 0x30 8001668: f003 0304 and.w r3, r3, #4 800166c: 61fb str r3, [r7, #28] 800166e: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001670: 2300 movs r3, #0 8001672: 61bb str r3, [r7, #24] 8001674: 4b49 ldr r3, [pc, #292] @ (800179c ) 8001676: 6b1b ldr r3, [r3, #48] @ 0x30 8001678: 4a48 ldr r2, [pc, #288] @ (800179c ) 800167a: f043 0308 orr.w r3, r3, #8 800167e: 6313 str r3, [r2, #48] @ 0x30 8001680: 4b46 ldr r3, [pc, #280] @ (800179c ) 8001682: 6b1b ldr r3, [r3, #48] @ 0x30 8001684: f003 0308 and.w r3, r3, #8 8001688: 61bb str r3, [r7, #24] 800168a: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_12; 800168c: f44f 5380 mov.w r3, #4096 @ 0x1000 8001690: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001692: 2302 movs r3, #2 8001694: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001696: 2300 movs r3, #0 8001698: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800169a: 2303 movs r3, #3 800169c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 800169e: 2308 movs r3, #8 80016a0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80016a2: f107 032c add.w r3, r7, #44 @ 0x2c 80016a6: 4619 mov r1, r3 80016a8: 483d ldr r0, [pc, #244] @ (80017a0 ) 80016aa: f000 ffa3 bl 80025f4 GPIO_InitStruct.Pin = GPIO_PIN_2; 80016ae: 2304 movs r3, #4 80016b0: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80016b2: 2302 movs r3, #2 80016b4: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80016b6: 2300 movs r3, #0 80016b8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80016ba: 2303 movs r3, #3 80016bc: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 80016be: 2308 movs r3, #8 80016c0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80016c2: f107 032c add.w r3, r7, #44 @ 0x2c 80016c6: 4619 mov r1, r3 80016c8: 4836 ldr r0, [pc, #216] @ (80017a4 ) 80016ca: f000 ff93 bl 80025f4 hdma_uart5_rx.Instance = DMA1_Stream0; 80016ce: 4b36 ldr r3, [pc, #216] @ (80017a8 ) 80016d0: 4a36 ldr r2, [pc, #216] @ (80017ac ) 80016d2: 601a str r2, [r3, #0] hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; 80016d4: 4b34 ldr r3, [pc, #208] @ (80017a8 ) 80016d6: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80016da: 605a str r2, [r3, #4] hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80016dc: 4b32 ldr r3, [pc, #200] @ (80017a8 ) 80016de: 2200 movs r2, #0 80016e0: 609a str r2, [r3, #8] hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80016e2: 4b31 ldr r3, [pc, #196] @ (80017a8 ) 80016e4: 2200 movs r2, #0 80016e6: 60da str r2, [r3, #12] hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; 80016e8: 4b2f ldr r3, [pc, #188] @ (80017a8 ) 80016ea: f44f 6280 mov.w r2, #1024 @ 0x400 80016ee: 611a str r2, [r3, #16] hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80016f0: 4b2d ldr r3, [pc, #180] @ (80017a8 ) 80016f2: 2200 movs r2, #0 80016f4: 615a str r2, [r3, #20] hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80016f6: 4b2c ldr r3, [pc, #176] @ (80017a8 ) 80016f8: 2200 movs r2, #0 80016fa: 619a str r2, [r3, #24] hdma_uart5_rx.Init.Mode = DMA_NORMAL; 80016fc: 4b2a ldr r3, [pc, #168] @ (80017a8 ) 80016fe: 2200 movs r2, #0 8001700: 61da str r2, [r3, #28] hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; 8001702: 4b29 ldr r3, [pc, #164] @ (80017a8 ) 8001704: 2200 movs r2, #0 8001706: 621a str r2, [r3, #32] hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001708: 4b27 ldr r3, [pc, #156] @ (80017a8 ) 800170a: 2200 movs r2, #0 800170c: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) 800170e: 4826 ldr r0, [pc, #152] @ (80017a8 ) 8001710: f000 fb6e bl 8001df0 8001714: 4603 mov r3, r0 8001716: 2b00 cmp r3, #0 8001718: d001 beq.n 800171e Error_Handler(); 800171a: f7ff fbef bl 8000efc __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); 800171e: 687b ldr r3, [r7, #4] 8001720: 4a21 ldr r2, [pc, #132] @ (80017a8 ) 8001722: 63da str r2, [r3, #60] @ 0x3c 8001724: 4a20 ldr r2, [pc, #128] @ (80017a8 ) 8001726: 687b ldr r3, [r7, #4] 8001728: 6393 str r3, [r2, #56] @ 0x38 hdma_uart5_tx.Instance = DMA1_Stream7; 800172a: 4b21 ldr r3, [pc, #132] @ (80017b0 ) 800172c: 4a21 ldr r2, [pc, #132] @ (80017b4 ) 800172e: 601a str r2, [r3, #0] hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; 8001730: 4b1f ldr r3, [pc, #124] @ (80017b0 ) 8001732: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001736: 605a str r2, [r3, #4] hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001738: 4b1d ldr r3, [pc, #116] @ (80017b0 ) 800173a: 2240 movs r2, #64 @ 0x40 800173c: 609a str r2, [r3, #8] hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800173e: 4b1c ldr r3, [pc, #112] @ (80017b0 ) 8001740: 2200 movs r2, #0 8001742: 60da str r2, [r3, #12] hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; 8001744: 4b1a ldr r3, [pc, #104] @ (80017b0 ) 8001746: f44f 6280 mov.w r2, #1024 @ 0x400 800174a: 611a str r2, [r3, #16] hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800174c: 4b18 ldr r3, [pc, #96] @ (80017b0 ) 800174e: 2200 movs r2, #0 8001750: 615a str r2, [r3, #20] hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001752: 4b17 ldr r3, [pc, #92] @ (80017b0 ) 8001754: 2200 movs r2, #0 8001756: 619a str r2, [r3, #24] hdma_uart5_tx.Init.Mode = DMA_NORMAL; 8001758: 4b15 ldr r3, [pc, #84] @ (80017b0 ) 800175a: 2200 movs r2, #0 800175c: 61da str r2, [r3, #28] hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; 800175e: 4b14 ldr r3, [pc, #80] @ (80017b0 ) 8001760: 2200 movs r2, #0 8001762: 621a str r2, [r3, #32] hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001764: 4b12 ldr r3, [pc, #72] @ (80017b0 ) 8001766: 2200 movs r2, #0 8001768: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) 800176a: 4811 ldr r0, [pc, #68] @ (80017b0 ) 800176c: f000 fb40 bl 8001df0 8001770: 4603 mov r3, r0 8001772: 2b00 cmp r3, #0 8001774: d001 beq.n 800177a Error_Handler(); 8001776: f7ff fbc1 bl 8000efc __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); 800177a: 687b ldr r3, [r7, #4] 800177c: 4a0c ldr r2, [pc, #48] @ (80017b0 ) 800177e: 639a str r2, [r3, #56] @ 0x38 8001780: 4a0b ldr r2, [pc, #44] @ (80017b0 ) 8001782: 687b ldr r3, [r7, #4] 8001784: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); 8001786: 2200 movs r2, #0 8001788: 2105 movs r1, #5 800178a: 2035 movs r0, #53 @ 0x35 800178c: f000 faf9 bl 8001d82 HAL_NVIC_EnableIRQ(UART5_IRQn); 8001790: 2035 movs r0, #53 @ 0x35 8001792: f000 fb12 bl 8001dba } 8001796: e13d b.n 8001a14 8001798: 40005000 .word 0x40005000 800179c: 40023800 .word 0x40023800 80017a0: 40020800 .word 0x40020800 80017a4: 40020c00 .word 0x40020c00 80017a8: 200004f0 .word 0x200004f0 80017ac: 40026010 .word 0x40026010 80017b0: 20000550 .word 0x20000550 80017b4: 400260b8 .word 0x400260b8 else if(uartHandle->Instance==USART1) 80017b8: 687b ldr r3, [r7, #4] 80017ba: 681b ldr r3, [r3, #0] 80017bc: 4a97 ldr r2, [pc, #604] @ (8001a1c ) 80017be: 4293 cmp r3, r2 80017c0: f040 8092 bne.w 80018e8 __HAL_RCC_USART1_CLK_ENABLE(); 80017c4: 2300 movs r3, #0 80017c6: 617b str r3, [r7, #20] 80017c8: 4b95 ldr r3, [pc, #596] @ (8001a20 ) 80017ca: 6c5b ldr r3, [r3, #68] @ 0x44 80017cc: 4a94 ldr r2, [pc, #592] @ (8001a20 ) 80017ce: f043 0310 orr.w r3, r3, #16 80017d2: 6453 str r3, [r2, #68] @ 0x44 80017d4: 4b92 ldr r3, [pc, #584] @ (8001a20 ) 80017d6: 6c5b ldr r3, [r3, #68] @ 0x44 80017d8: f003 0310 and.w r3, r3, #16 80017dc: 617b str r3, [r7, #20] 80017de: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80017e0: 2300 movs r3, #0 80017e2: 613b str r3, [r7, #16] 80017e4: 4b8e ldr r3, [pc, #568] @ (8001a20 ) 80017e6: 6b1b ldr r3, [r3, #48] @ 0x30 80017e8: 4a8d ldr r2, [pc, #564] @ (8001a20 ) 80017ea: f043 0301 orr.w r3, r3, #1 80017ee: 6313 str r3, [r2, #48] @ 0x30 80017f0: 4b8b ldr r3, [pc, #556] @ (8001a20 ) 80017f2: 6b1b ldr r3, [r3, #48] @ 0x30 80017f4: f003 0301 and.w r3, r3, #1 80017f8: 613b str r3, [r7, #16] 80017fa: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 80017fc: f44f 63c0 mov.w r3, #1536 @ 0x600 8001800: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001802: 2302 movs r3, #2 8001804: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001806: 2300 movs r3, #0 8001808: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800180a: 2303 movs r3, #3 800180c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 800180e: 2307 movs r3, #7 8001810: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001812: f107 032c add.w r3, r7, #44 @ 0x2c 8001816: 4619 mov r1, r3 8001818: 4882 ldr r0, [pc, #520] @ (8001a24 ) 800181a: f000 feeb bl 80025f4 hdma_usart1_rx.Instance = DMA2_Stream2; 800181e: 4b82 ldr r3, [pc, #520] @ (8001a28 ) 8001820: 4a82 ldr r2, [pc, #520] @ (8001a2c ) 8001822: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; 8001824: 4b80 ldr r3, [pc, #512] @ (8001a28 ) 8001826: f04f 6200 mov.w r2, #134217728 @ 0x8000000 800182a: 605a str r2, [r3, #4] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800182c: 4b7e ldr r3, [pc, #504] @ (8001a28 ) 800182e: 2200 movs r2, #0 8001830: 609a str r2, [r3, #8] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001832: 4b7d ldr r3, [pc, #500] @ (8001a28 ) 8001834: 2200 movs r2, #0 8001836: 60da str r2, [r3, #12] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8001838: 4b7b ldr r3, [pc, #492] @ (8001a28 ) 800183a: f44f 6280 mov.w r2, #1024 @ 0x400 800183e: 611a str r2, [r3, #16] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001840: 4b79 ldr r3, [pc, #484] @ (8001a28 ) 8001842: 2200 movs r2, #0 8001844: 615a str r2, [r3, #20] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001846: 4b78 ldr r3, [pc, #480] @ (8001a28 ) 8001848: 2200 movs r2, #0 800184a: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 800184c: 4b76 ldr r3, [pc, #472] @ (8001a28 ) 800184e: 2200 movs r2, #0 8001850: 61da str r2, [r3, #28] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 8001852: 4b75 ldr r3, [pc, #468] @ (8001a28 ) 8001854: 2200 movs r2, #0 8001856: 621a str r2, [r3, #32] hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001858: 4b73 ldr r3, [pc, #460] @ (8001a28 ) 800185a: 2200 movs r2, #0 800185c: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 800185e: 4872 ldr r0, [pc, #456] @ (8001a28 ) 8001860: f000 fac6 bl 8001df0 8001864: 4603 mov r3, r0 8001866: 2b00 cmp r3, #0 8001868: d001 beq.n 800186e Error_Handler(); 800186a: f7ff fb47 bl 8000efc __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); 800186e: 687b ldr r3, [r7, #4] 8001870: 4a6d ldr r2, [pc, #436] @ (8001a28 ) 8001872: 63da str r2, [r3, #60] @ 0x3c 8001874: 4a6c ldr r2, [pc, #432] @ (8001a28 ) 8001876: 687b ldr r3, [r7, #4] 8001878: 6393 str r3, [r2, #56] @ 0x38 hdma_usart1_tx.Instance = DMA2_Stream7; 800187a: 4b6d ldr r3, [pc, #436] @ (8001a30 ) 800187c: 4a6d ldr r2, [pc, #436] @ (8001a34 ) 800187e: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; 8001880: 4b6b ldr r3, [pc, #428] @ (8001a30 ) 8001882: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001886: 605a str r2, [r3, #4] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001888: 4b69 ldr r3, [pc, #420] @ (8001a30 ) 800188a: 2240 movs r2, #64 @ 0x40 800188c: 609a str r2, [r3, #8] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800188e: 4b68 ldr r3, [pc, #416] @ (8001a30 ) 8001890: 2200 movs r2, #0 8001892: 60da str r2, [r3, #12] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 8001894: 4b66 ldr r3, [pc, #408] @ (8001a30 ) 8001896: f44f 6280 mov.w r2, #1024 @ 0x400 800189a: 611a str r2, [r3, #16] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800189c: 4b64 ldr r3, [pc, #400] @ (8001a30 ) 800189e: 2200 movs r2, #0 80018a0: 615a str r2, [r3, #20] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80018a2: 4b63 ldr r3, [pc, #396] @ (8001a30 ) 80018a4: 2200 movs r2, #0 80018a6: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 80018a8: 4b61 ldr r3, [pc, #388] @ (8001a30 ) 80018aa: 2200 movs r2, #0 80018ac: 61da str r2, [r3, #28] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 80018ae: 4b60 ldr r3, [pc, #384] @ (8001a30 ) 80018b0: 2200 movs r2, #0 80018b2: 621a str r2, [r3, #32] hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80018b4: 4b5e ldr r3, [pc, #376] @ (8001a30 ) 80018b6: 2200 movs r2, #0 80018b8: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 80018ba: 485d ldr r0, [pc, #372] @ (8001a30 ) 80018bc: f000 fa98 bl 8001df0 80018c0: 4603 mov r3, r0 80018c2: 2b00 cmp r3, #0 80018c4: d001 beq.n 80018ca Error_Handler(); 80018c6: f7ff fb19 bl 8000efc __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); 80018ca: 687b ldr r3, [r7, #4] 80018cc: 4a58 ldr r2, [pc, #352] @ (8001a30 ) 80018ce: 639a str r2, [r3, #56] @ 0x38 80018d0: 4a57 ldr r2, [pc, #348] @ (8001a30 ) 80018d2: 687b ldr r3, [r7, #4] 80018d4: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 80018d6: 2200 movs r2, #0 80018d8: 2105 movs r1, #5 80018da: 2025 movs r0, #37 @ 0x25 80018dc: f000 fa51 bl 8001d82 HAL_NVIC_EnableIRQ(USART1_IRQn); 80018e0: 2025 movs r0, #37 @ 0x25 80018e2: f000 fa6a bl 8001dba } 80018e6: e095 b.n 8001a14 else if(uartHandle->Instance==USART2) 80018e8: 687b ldr r3, [r7, #4] 80018ea: 681b ldr r3, [r3, #0] 80018ec: 4a52 ldr r2, [pc, #328] @ (8001a38 ) 80018ee: 4293 cmp r3, r2 80018f0: f040 8090 bne.w 8001a14 __HAL_RCC_USART2_CLK_ENABLE(); 80018f4: 2300 movs r3, #0 80018f6: 60fb str r3, [r7, #12] 80018f8: 4b49 ldr r3, [pc, #292] @ (8001a20 ) 80018fa: 6c1b ldr r3, [r3, #64] @ 0x40 80018fc: 4a48 ldr r2, [pc, #288] @ (8001a20 ) 80018fe: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001902: 6413 str r3, [r2, #64] @ 0x40 8001904: 4b46 ldr r3, [pc, #280] @ (8001a20 ) 8001906: 6c1b ldr r3, [r3, #64] @ 0x40 8001908: f403 3300 and.w r3, r3, #131072 @ 0x20000 800190c: 60fb str r3, [r7, #12] 800190e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001910: 2300 movs r3, #0 8001912: 60bb str r3, [r7, #8] 8001914: 4b42 ldr r3, [pc, #264] @ (8001a20 ) 8001916: 6b1b ldr r3, [r3, #48] @ 0x30 8001918: 4a41 ldr r2, [pc, #260] @ (8001a20 ) 800191a: f043 0301 orr.w r3, r3, #1 800191e: 6313 str r3, [r2, #48] @ 0x30 8001920: 4b3f ldr r3, [pc, #252] @ (8001a20 ) 8001922: 6b1b ldr r3, [r3, #48] @ 0x30 8001924: f003 0301 and.w r3, r3, #1 8001928: 60bb str r3, [r7, #8] 800192a: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 800192c: 230c movs r3, #12 800192e: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001930: 2302 movs r3, #2 8001932: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001934: 2300 movs r3, #0 8001936: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001938: 2303 movs r3, #3 800193a: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 800193c: 2307 movs r3, #7 800193e: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001940: f107 032c add.w r3, r7, #44 @ 0x2c 8001944: 4619 mov r1, r3 8001946: 4837 ldr r0, [pc, #220] @ (8001a24 ) 8001948: f000 fe54 bl 80025f4 hdma_usart2_rx.Instance = DMA1_Stream5; 800194c: 4b3b ldr r3, [pc, #236] @ (8001a3c ) 800194e: 4a3c ldr r2, [pc, #240] @ (8001a40 ) 8001950: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; 8001952: 4b3a ldr r3, [pc, #232] @ (8001a3c ) 8001954: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001958: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800195a: 4b38 ldr r3, [pc, #224] @ (8001a3c ) 800195c: 2200 movs r2, #0 800195e: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001960: 4b36 ldr r3, [pc, #216] @ (8001a3c ) 8001962: 2200 movs r2, #0 8001964: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 8001966: 4b35 ldr r3, [pc, #212] @ (8001a3c ) 8001968: f44f 6280 mov.w r2, #1024 @ 0x400 800196c: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800196e: 4b33 ldr r3, [pc, #204] @ (8001a3c ) 8001970: 2200 movs r2, #0 8001972: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001974: 4b31 ldr r3, [pc, #196] @ (8001a3c ) 8001976: 2200 movs r2, #0 8001978: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 800197a: 4b30 ldr r3, [pc, #192] @ (8001a3c ) 800197c: 2200 movs r2, #0 800197e: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 8001980: 4b2e ldr r3, [pc, #184] @ (8001a3c ) 8001982: 2200 movs r2, #0 8001984: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001986: 4b2d ldr r3, [pc, #180] @ (8001a3c ) 8001988: 2200 movs r2, #0 800198a: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 800198c: 482b ldr r0, [pc, #172] @ (8001a3c ) 800198e: f000 fa2f bl 8001df0 8001992: 4603 mov r3, r0 8001994: 2b00 cmp r3, #0 8001996: d001 beq.n 800199c Error_Handler(); 8001998: f7ff fab0 bl 8000efc __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 800199c: 687b ldr r3, [r7, #4] 800199e: 4a27 ldr r2, [pc, #156] @ (8001a3c ) 80019a0: 63da str r2, [r3, #60] @ 0x3c 80019a2: 4a26 ldr r2, [pc, #152] @ (8001a3c ) 80019a4: 687b ldr r3, [r7, #4] 80019a6: 6393 str r3, [r2, #56] @ 0x38 hdma_usart2_tx.Instance = DMA1_Stream6; 80019a8: 4b26 ldr r3, [pc, #152] @ (8001a44 ) 80019aa: 4a27 ldr r2, [pc, #156] @ (8001a48 ) 80019ac: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; 80019ae: 4b25 ldr r3, [pc, #148] @ (8001a44 ) 80019b0: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80019b4: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80019b6: 4b23 ldr r3, [pc, #140] @ (8001a44 ) 80019b8: 2240 movs r2, #64 @ 0x40 80019ba: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80019bc: 4b21 ldr r3, [pc, #132] @ (8001a44 ) 80019be: 2200 movs r2, #0 80019c0: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 80019c2: 4b20 ldr r3, [pc, #128] @ (8001a44 ) 80019c4: f44f 6280 mov.w r2, #1024 @ 0x400 80019c8: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80019ca: 4b1e ldr r3, [pc, #120] @ (8001a44 ) 80019cc: 2200 movs r2, #0 80019ce: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80019d0: 4b1c ldr r3, [pc, #112] @ (8001a44 ) 80019d2: 2200 movs r2, #0 80019d4: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 80019d6: 4b1b ldr r3, [pc, #108] @ (8001a44 ) 80019d8: 2200 movs r2, #0 80019da: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 80019dc: 4b19 ldr r3, [pc, #100] @ (8001a44 ) 80019de: 2200 movs r2, #0 80019e0: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80019e2: 4b18 ldr r3, [pc, #96] @ (8001a44 ) 80019e4: 2200 movs r2, #0 80019e6: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 80019e8: 4816 ldr r0, [pc, #88] @ (8001a44 ) 80019ea: f000 fa01 bl 8001df0 80019ee: 4603 mov r3, r0 80019f0: 2b00 cmp r3, #0 80019f2: d001 beq.n 80019f8 Error_Handler(); 80019f4: f7ff fa82 bl 8000efc __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 80019f8: 687b ldr r3, [r7, #4] 80019fa: 4a12 ldr r2, [pc, #72] @ (8001a44 ) 80019fc: 639a str r2, [r3, #56] @ 0x38 80019fe: 4a11 ldr r2, [pc, #68] @ (8001a44 ) 8001a00: 687b ldr r3, [r7, #4] 8001a02: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); 8001a04: 2200 movs r2, #0 8001a06: 2105 movs r1, #5 8001a08: 2026 movs r0, #38 @ 0x26 8001a0a: f000 f9ba bl 8001d82 HAL_NVIC_EnableIRQ(USART2_IRQn); 8001a0e: 2026 movs r0, #38 @ 0x26 8001a10: f000 f9d3 bl 8001dba } 8001a14: bf00 nop 8001a16: 3740 adds r7, #64 @ 0x40 8001a18: 46bd mov sp, r7 8001a1a: bd80 pop {r7, pc} 8001a1c: 40011000 .word 0x40011000 8001a20: 40023800 .word 0x40023800 8001a24: 40020000 .word 0x40020000 8001a28: 200005b0 .word 0x200005b0 8001a2c: 40026440 .word 0x40026440 8001a30: 20000610 .word 0x20000610 8001a34: 400264b8 .word 0x400264b8 8001a38: 40004400 .word 0x40004400 8001a3c: 20000670 .word 0x20000670 8001a40: 40026088 .word 0x40026088 8001a44: 200006d0 .word 0x200006d0 8001a48: 400260a0 .word 0x400260a0 08001a4c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001a4c: f8df d034 ldr.w sp, [pc, #52] @ 8001a84 /* Call the clock system initialization function.*/ bl SystemInit 8001a50: f7ff fb34 bl 80010bc /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001a54: 480c ldr r0, [pc, #48] @ (8001a88 ) ldr r1, =_edata 8001a56: 490d ldr r1, [pc, #52] @ (8001a8c ) ldr r2, =_sidata 8001a58: 4a0d ldr r2, [pc, #52] @ (8001a90 ) movs r3, #0 8001a5a: 2300 movs r3, #0 b LoopCopyDataInit 8001a5c: e002 b.n 8001a64 08001a5e : CopyDataInit: ldr r4, [r2, r3] 8001a5e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001a60: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001a62: 3304 adds r3, #4 08001a64 : LoopCopyDataInit: adds r4, r0, r3 8001a64: 18c4 adds r4, r0, r3 cmp r4, r1 8001a66: 428c cmp r4, r1 bcc CopyDataInit 8001a68: d3f9 bcc.n 8001a5e /* Zero fill the bss segment. */ ldr r2, =_sbss 8001a6a: 4a0a ldr r2, [pc, #40] @ (8001a94 ) ldr r4, =_ebss 8001a6c: 4c0a ldr r4, [pc, #40] @ (8001a98 ) movs r3, #0 8001a6e: 2300 movs r3, #0 b LoopFillZerobss 8001a70: e001 b.n 8001a76 08001a72 : FillZerobss: str r3, [r2] 8001a72: 6013 str r3, [r2, #0] adds r2, r2, #4 8001a74: 3204 adds r2, #4 08001a76 : LoopFillZerobss: cmp r2, r4 8001a76: 42a2 cmp r2, r4 bcc FillZerobss 8001a78: d3fb bcc.n 8001a72 /* Call static constructors */ bl __libc_init_array 8001a7a: f008 fffd bl 800aa78 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001a7e: f7fe fed3 bl 8000828
bx lr 8001a82: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001a84: 20020000 .word 0x20020000 ldr r0, =_sdata 8001a88: 20000000 .word 0x20000000 ldr r1, =_edata 8001a8c: 200001a0 .word 0x200001a0 ldr r2, =_sidata 8001a90: 0800ab44 .word 0x0800ab44 ldr r2, =_sbss 8001a94: 200001a0 .word 0x200001a0 ldr r4, =_ebss 8001a98: 2000110c .word 0x2000110c 08001a9c : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001a9c: e7fe b.n 8001a9c ... 08001aa0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001aa0: b580 push {r7, lr} 8001aa2: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8001aa4: 4b0e ldr r3, [pc, #56] @ (8001ae0 ) 8001aa6: 681b ldr r3, [r3, #0] 8001aa8: 4a0d ldr r2, [pc, #52] @ (8001ae0 ) 8001aaa: f443 7300 orr.w r3, r3, #512 @ 0x200 8001aae: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8001ab0: 4b0b ldr r3, [pc, #44] @ (8001ae0 ) 8001ab2: 681b ldr r3, [r3, #0] 8001ab4: 4a0a ldr r2, [pc, #40] @ (8001ae0 ) 8001ab6: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001aba: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001abc: 4b08 ldr r3, [pc, #32] @ (8001ae0 ) 8001abe: 681b ldr r3, [r3, #0] 8001ac0: 4a07 ldr r2, [pc, #28] @ (8001ae0 ) 8001ac2: f443 7380 orr.w r3, r3, #256 @ 0x100 8001ac6: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001ac8: 2003 movs r0, #3 8001aca: f000 f94f bl 8001d6c /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001ace: 200f movs r0, #15 8001ad0: f000 f808 bl 8001ae4 /* Init the low level hardware */ HAL_MspInit(); 8001ad4: f7ff fa18 bl 8000f08 /* Return function status */ return HAL_OK; 8001ad8: 2300 movs r3, #0 } 8001ada: 4618 mov r0, r3 8001adc: bd80 pop {r7, pc} 8001ade: bf00 nop 8001ae0: 40023c00 .word 0x40023c00 08001ae4 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001ae4: b580 push {r7, lr} 8001ae6: b082 sub sp, #8 8001ae8: af00 add r7, sp, #0 8001aea: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001aec: 4b12 ldr r3, [pc, #72] @ (8001b38 ) 8001aee: 681a ldr r2, [r3, #0] 8001af0: 4b12 ldr r3, [pc, #72] @ (8001b3c ) 8001af2: 781b ldrb r3, [r3, #0] 8001af4: 4619 mov r1, r3 8001af6: f44f 737a mov.w r3, #1000 @ 0x3e8 8001afa: fbb3 f3f1 udiv r3, r3, r1 8001afe: fbb2 f3f3 udiv r3, r2, r3 8001b02: 4618 mov r0, r3 8001b04: f000 f967 bl 8001dd6 8001b08: 4603 mov r3, r0 8001b0a: 2b00 cmp r3, #0 8001b0c: d001 beq.n 8001b12 { return HAL_ERROR; 8001b0e: 2301 movs r3, #1 8001b10: e00e b.n 8001b30 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001b12: 687b ldr r3, [r7, #4] 8001b14: 2b0f cmp r3, #15 8001b16: d80a bhi.n 8001b2e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001b18: 2200 movs r2, #0 8001b1a: 6879 ldr r1, [r7, #4] 8001b1c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001b20: f000 f92f bl 8001d82 uwTickPrio = TickPriority; 8001b24: 4a06 ldr r2, [pc, #24] @ (8001b40 ) 8001b26: 687b ldr r3, [r7, #4] 8001b28: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8001b2a: 2300 movs r3, #0 8001b2c: e000 b.n 8001b30 return HAL_ERROR; 8001b2e: 2301 movs r3, #1 } 8001b30: 4618 mov r0, r3 8001b32: 3708 adds r7, #8 8001b34: 46bd mov sp, r7 8001b36: bd80 pop {r7, pc} 8001b38: 20000090 .word 0x20000090 8001b3c: 20000098 .word 0x20000098 8001b40: 20000094 .word 0x20000094 08001b44 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001b44: b480 push {r7} 8001b46: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001b48: 4b06 ldr r3, [pc, #24] @ (8001b64 ) 8001b4a: 781b ldrb r3, [r3, #0] 8001b4c: 461a mov r2, r3 8001b4e: 4b06 ldr r3, [pc, #24] @ (8001b68 ) 8001b50: 681b ldr r3, [r3, #0] 8001b52: 4413 add r3, r2 8001b54: 4a04 ldr r2, [pc, #16] @ (8001b68 ) 8001b56: 6013 str r3, [r2, #0] } 8001b58: bf00 nop 8001b5a: 46bd mov sp, r7 8001b5c: f85d 7b04 ldr.w r7, [sp], #4 8001b60: 4770 bx lr 8001b62: bf00 nop 8001b64: 20000098 .word 0x20000098 8001b68: 20000730 .word 0x20000730 08001b6c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001b6c: b480 push {r7} 8001b6e: af00 add r7, sp, #0 return uwTick; 8001b70: 4b03 ldr r3, [pc, #12] @ (8001b80 ) 8001b72: 681b ldr r3, [r3, #0] } 8001b74: 4618 mov r0, r3 8001b76: 46bd mov sp, r7 8001b78: f85d 7b04 ldr.w r7, [sp], #4 8001b7c: 4770 bx lr 8001b7e: bf00 nop 8001b80: 20000730 .word 0x20000730 08001b84 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001b84: b580 push {r7, lr} 8001b86: b084 sub sp, #16 8001b88: af00 add r7, sp, #0 8001b8a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001b8c: f7ff ffee bl 8001b6c 8001b90: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001b92: 687b ldr r3, [r7, #4] 8001b94: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001b96: 68fb ldr r3, [r7, #12] 8001b98: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001b9c: d005 beq.n 8001baa { wait += (uint32_t)(uwTickFreq); 8001b9e: 4b0a ldr r3, [pc, #40] @ (8001bc8 ) 8001ba0: 781b ldrb r3, [r3, #0] 8001ba2: 461a mov r2, r3 8001ba4: 68fb ldr r3, [r7, #12] 8001ba6: 4413 add r3, r2 8001ba8: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001baa: bf00 nop 8001bac: f7ff ffde bl 8001b6c 8001bb0: 4602 mov r2, r0 8001bb2: 68bb ldr r3, [r7, #8] 8001bb4: 1ad3 subs r3, r2, r3 8001bb6: 68fa ldr r2, [r7, #12] 8001bb8: 429a cmp r2, r3 8001bba: d8f7 bhi.n 8001bac { } } 8001bbc: bf00 nop 8001bbe: bf00 nop 8001bc0: 3710 adds r7, #16 8001bc2: 46bd mov sp, r7 8001bc4: bd80 pop {r7, pc} 8001bc6: bf00 nop 8001bc8: 20000098 .word 0x20000098 08001bcc <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001bcc: b480 push {r7} 8001bce: b085 sub sp, #20 8001bd0: af00 add r7, sp, #0 8001bd2: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001bd4: 687b ldr r3, [r7, #4] 8001bd6: f003 0307 and.w r3, r3, #7 8001bda: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001bdc: 4b0c ldr r3, [pc, #48] @ (8001c10 <__NVIC_SetPriorityGrouping+0x44>) 8001bde: 68db ldr r3, [r3, #12] 8001be0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001be2: 68ba ldr r2, [r7, #8] 8001be4: f64f 03ff movw r3, #63743 @ 0xf8ff 8001be8: 4013 ands r3, r2 8001bea: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001bec: 68fb ldr r3, [r7, #12] 8001bee: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001bf0: 68bb ldr r3, [r7, #8] 8001bf2: 4313 orrs r3, r2 reg_value = (reg_value | 8001bf4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8001bf8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001bfc: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001bfe: 4a04 ldr r2, [pc, #16] @ (8001c10 <__NVIC_SetPriorityGrouping+0x44>) 8001c00: 68bb ldr r3, [r7, #8] 8001c02: 60d3 str r3, [r2, #12] } 8001c04: bf00 nop 8001c06: 3714 adds r7, #20 8001c08: 46bd mov sp, r7 8001c0a: f85d 7b04 ldr.w r7, [sp], #4 8001c0e: 4770 bx lr 8001c10: e000ed00 .word 0xe000ed00 08001c14 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001c14: b480 push {r7} 8001c16: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001c18: 4b04 ldr r3, [pc, #16] @ (8001c2c <__NVIC_GetPriorityGrouping+0x18>) 8001c1a: 68db ldr r3, [r3, #12] 8001c1c: 0a1b lsrs r3, r3, #8 8001c1e: f003 0307 and.w r3, r3, #7 } 8001c22: 4618 mov r0, r3 8001c24: 46bd mov sp, r7 8001c26: f85d 7b04 ldr.w r7, [sp], #4 8001c2a: 4770 bx lr 8001c2c: e000ed00 .word 0xe000ed00 08001c30 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001c30: b480 push {r7} 8001c32: b083 sub sp, #12 8001c34: af00 add r7, sp, #0 8001c36: 4603 mov r3, r0 8001c38: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001c3a: f997 3007 ldrsb.w r3, [r7, #7] 8001c3e: 2b00 cmp r3, #0 8001c40: db0b blt.n 8001c5a <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001c42: 79fb ldrb r3, [r7, #7] 8001c44: f003 021f and.w r2, r3, #31 8001c48: 4907 ldr r1, [pc, #28] @ (8001c68 <__NVIC_EnableIRQ+0x38>) 8001c4a: f997 3007 ldrsb.w r3, [r7, #7] 8001c4e: 095b lsrs r3, r3, #5 8001c50: 2001 movs r0, #1 8001c52: fa00 f202 lsl.w r2, r0, r2 8001c56: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001c5a: bf00 nop 8001c5c: 370c adds r7, #12 8001c5e: 46bd mov sp, r7 8001c60: f85d 7b04 ldr.w r7, [sp], #4 8001c64: 4770 bx lr 8001c66: bf00 nop 8001c68: e000e100 .word 0xe000e100 08001c6c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001c6c: b480 push {r7} 8001c6e: b083 sub sp, #12 8001c70: af00 add r7, sp, #0 8001c72: 4603 mov r3, r0 8001c74: 6039 str r1, [r7, #0] 8001c76: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001c78: f997 3007 ldrsb.w r3, [r7, #7] 8001c7c: 2b00 cmp r3, #0 8001c7e: db0a blt.n 8001c96 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001c80: 683b ldr r3, [r7, #0] 8001c82: b2da uxtb r2, r3 8001c84: 490c ldr r1, [pc, #48] @ (8001cb8 <__NVIC_SetPriority+0x4c>) 8001c86: f997 3007 ldrsb.w r3, [r7, #7] 8001c8a: 0112 lsls r2, r2, #4 8001c8c: b2d2 uxtb r2, r2 8001c8e: 440b add r3, r1 8001c90: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001c94: e00a b.n 8001cac <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001c96: 683b ldr r3, [r7, #0] 8001c98: b2da uxtb r2, r3 8001c9a: 4908 ldr r1, [pc, #32] @ (8001cbc <__NVIC_SetPriority+0x50>) 8001c9c: 79fb ldrb r3, [r7, #7] 8001c9e: f003 030f and.w r3, r3, #15 8001ca2: 3b04 subs r3, #4 8001ca4: 0112 lsls r2, r2, #4 8001ca6: b2d2 uxtb r2, r2 8001ca8: 440b add r3, r1 8001caa: 761a strb r2, [r3, #24] } 8001cac: bf00 nop 8001cae: 370c adds r7, #12 8001cb0: 46bd mov sp, r7 8001cb2: f85d 7b04 ldr.w r7, [sp], #4 8001cb6: 4770 bx lr 8001cb8: e000e100 .word 0xe000e100 8001cbc: e000ed00 .word 0xe000ed00 08001cc0 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001cc0: b480 push {r7} 8001cc2: b089 sub sp, #36 @ 0x24 8001cc4: af00 add r7, sp, #0 8001cc6: 60f8 str r0, [r7, #12] 8001cc8: 60b9 str r1, [r7, #8] 8001cca: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001ccc: 68fb ldr r3, [r7, #12] 8001cce: f003 0307 and.w r3, r3, #7 8001cd2: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001cd4: 69fb ldr r3, [r7, #28] 8001cd6: f1c3 0307 rsb r3, r3, #7 8001cda: 2b04 cmp r3, #4 8001cdc: bf28 it cs 8001cde: 2304 movcs r3, #4 8001ce0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001ce2: 69fb ldr r3, [r7, #28] 8001ce4: 3304 adds r3, #4 8001ce6: 2b06 cmp r3, #6 8001ce8: d902 bls.n 8001cf0 8001cea: 69fb ldr r3, [r7, #28] 8001cec: 3b03 subs r3, #3 8001cee: e000 b.n 8001cf2 8001cf0: 2300 movs r3, #0 8001cf2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001cf4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001cf8: 69bb ldr r3, [r7, #24] 8001cfa: fa02 f303 lsl.w r3, r2, r3 8001cfe: 43da mvns r2, r3 8001d00: 68bb ldr r3, [r7, #8] 8001d02: 401a ands r2, r3 8001d04: 697b ldr r3, [r7, #20] 8001d06: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001d08: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001d0c: 697b ldr r3, [r7, #20] 8001d0e: fa01 f303 lsl.w r3, r1, r3 8001d12: 43d9 mvns r1, r3 8001d14: 687b ldr r3, [r7, #4] 8001d16: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001d18: 4313 orrs r3, r2 ); } 8001d1a: 4618 mov r0, r3 8001d1c: 3724 adds r7, #36 @ 0x24 8001d1e: 46bd mov sp, r7 8001d20: f85d 7b04 ldr.w r7, [sp], #4 8001d24: 4770 bx lr ... 08001d28 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001d28: b580 push {r7, lr} 8001d2a: b082 sub sp, #8 8001d2c: af00 add r7, sp, #0 8001d2e: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001d30: 687b ldr r3, [r7, #4] 8001d32: 3b01 subs r3, #1 8001d34: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8001d38: d301 bcc.n 8001d3e { return (1UL); /* Reload value impossible */ 8001d3a: 2301 movs r3, #1 8001d3c: e00f b.n 8001d5e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001d3e: 4a0a ldr r2, [pc, #40] @ (8001d68 ) 8001d40: 687b ldr r3, [r7, #4] 8001d42: 3b01 subs r3, #1 8001d44: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001d46: 210f movs r1, #15 8001d48: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001d4c: f7ff ff8e bl 8001c6c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001d50: 4b05 ldr r3, [pc, #20] @ (8001d68 ) 8001d52: 2200 movs r2, #0 8001d54: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001d56: 4b04 ldr r3, [pc, #16] @ (8001d68 ) 8001d58: 2207 movs r2, #7 8001d5a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001d5c: 2300 movs r3, #0 } 8001d5e: 4618 mov r0, r3 8001d60: 3708 adds r7, #8 8001d62: 46bd mov sp, r7 8001d64: bd80 pop {r7, pc} 8001d66: bf00 nop 8001d68: e000e010 .word 0xe000e010 08001d6c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001d6c: b580 push {r7, lr} 8001d6e: b082 sub sp, #8 8001d70: af00 add r7, sp, #0 8001d72: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001d74: 6878 ldr r0, [r7, #4] 8001d76: f7ff ff29 bl 8001bcc <__NVIC_SetPriorityGrouping> } 8001d7a: bf00 nop 8001d7c: 3708 adds r7, #8 8001d7e: 46bd mov sp, r7 8001d80: bd80 pop {r7, pc} 08001d82 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001d82: b580 push {r7, lr} 8001d84: b086 sub sp, #24 8001d86: af00 add r7, sp, #0 8001d88: 4603 mov r3, r0 8001d8a: 60b9 str r1, [r7, #8] 8001d8c: 607a str r2, [r7, #4] 8001d8e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001d90: 2300 movs r3, #0 8001d92: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001d94: f7ff ff3e bl 8001c14 <__NVIC_GetPriorityGrouping> 8001d98: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001d9a: 687a ldr r2, [r7, #4] 8001d9c: 68b9 ldr r1, [r7, #8] 8001d9e: 6978 ldr r0, [r7, #20] 8001da0: f7ff ff8e bl 8001cc0 8001da4: 4602 mov r2, r0 8001da6: f997 300f ldrsb.w r3, [r7, #15] 8001daa: 4611 mov r1, r2 8001dac: 4618 mov r0, r3 8001dae: f7ff ff5d bl 8001c6c <__NVIC_SetPriority> } 8001db2: bf00 nop 8001db4: 3718 adds r7, #24 8001db6: 46bd mov sp, r7 8001db8: bd80 pop {r7, pc} 08001dba : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001dba: b580 push {r7, lr} 8001dbc: b082 sub sp, #8 8001dbe: af00 add r7, sp, #0 8001dc0: 4603 mov r3, r0 8001dc2: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001dc4: f997 3007 ldrsb.w r3, [r7, #7] 8001dc8: 4618 mov r0, r3 8001dca: f7ff ff31 bl 8001c30 <__NVIC_EnableIRQ> } 8001dce: bf00 nop 8001dd0: 3708 adds r7, #8 8001dd2: 46bd mov sp, r7 8001dd4: bd80 pop {r7, pc} 08001dd6 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001dd6: b580 push {r7, lr} 8001dd8: b082 sub sp, #8 8001dda: af00 add r7, sp, #0 8001ddc: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001dde: 6878 ldr r0, [r7, #4] 8001de0: f7ff ffa2 bl 8001d28 8001de4: 4603 mov r3, r0 } 8001de6: 4618 mov r0, r3 8001de8: 3708 adds r7, #8 8001dea: 46bd mov sp, r7 8001dec: bd80 pop {r7, pc} ... 08001df0 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8001df0: b580 push {r7, lr} 8001df2: b086 sub sp, #24 8001df4: af00 add r7, sp, #0 8001df6: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8001df8: 2300 movs r3, #0 8001dfa: 617b str r3, [r7, #20] uint32_t tickstart = HAL_GetTick(); 8001dfc: f7ff feb6 bl 8001b6c 8001e00: 6138 str r0, [r7, #16] DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) 8001e02: 687b ldr r3, [r7, #4] 8001e04: 2b00 cmp r3, #0 8001e06: d101 bne.n 8001e0c { return HAL_ERROR; 8001e08: 2301 movs r3, #1 8001e0a: e099 b.n 8001f40 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001e0c: 687b ldr r3, [r7, #4] 8001e0e: 2202 movs r2, #2 8001e10: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8001e14: 687b ldr r3, [r7, #4] 8001e16: 2200 movs r2, #0 8001e18: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8001e1c: 687b ldr r3, [r7, #4] 8001e1e: 681b ldr r3, [r3, #0] 8001e20: 681a ldr r2, [r3, #0] 8001e22: 687b ldr r3, [r7, #4] 8001e24: 681b ldr r3, [r3, #0] 8001e26: f022 0201 bic.w r2, r2, #1 8001e2a: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001e2c: e00f b.n 8001e4e { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001e2e: f7ff fe9d bl 8001b6c 8001e32: 4602 mov r2, r0 8001e34: 693b ldr r3, [r7, #16] 8001e36: 1ad3 subs r3, r2, r3 8001e38: 2b05 cmp r3, #5 8001e3a: d908 bls.n 8001e4e { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001e3c: 687b ldr r3, [r7, #4] 8001e3e: 2220 movs r2, #32 8001e40: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001e42: 687b ldr r3, [r7, #4] 8001e44: 2203 movs r2, #3 8001e46: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_TIMEOUT; 8001e4a: 2303 movs r3, #3 8001e4c: e078 b.n 8001f40 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001e4e: 687b ldr r3, [r7, #4] 8001e50: 681b ldr r3, [r3, #0] 8001e52: 681b ldr r3, [r3, #0] 8001e54: f003 0301 and.w r3, r3, #1 8001e58: 2b00 cmp r3, #0 8001e5a: d1e8 bne.n 8001e2e } } /* Get the CR register value */ tmp = hdma->Instance->CR; 8001e5c: 687b ldr r3, [r7, #4] 8001e5e: 681b ldr r3, [r3, #0] 8001e60: 681b ldr r3, [r3, #0] 8001e62: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8001e64: 697a ldr r2, [r7, #20] 8001e66: 4b38 ldr r3, [pc, #224] @ (8001f48 ) 8001e68: 4013 ands r3, r2 8001e6a: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: 685a ldr r2, [r3, #4] 8001e70: 687b ldr r3, [r7, #4] 8001e72: 689b ldr r3, [r3, #8] 8001e74: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001e76: 687b ldr r3, [r7, #4] 8001e78: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001e7a: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001e7c: 687b ldr r3, [r7, #4] 8001e7e: 691b ldr r3, [r3, #16] 8001e80: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001e82: 687b ldr r3, [r7, #4] 8001e84: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001e86: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001e88: 687b ldr r3, [r7, #4] 8001e8a: 699b ldr r3, [r3, #24] 8001e8c: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001e8e: 687b ldr r3, [r7, #4] 8001e90: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001e92: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001e94: 687b ldr r3, [r7, #4] 8001e96: 6a1b ldr r3, [r3, #32] 8001e98: 4313 orrs r3, r2 tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001e9a: 697a ldr r2, [r7, #20] 8001e9c: 4313 orrs r3, r2 8001e9e: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001ea0: 687b ldr r3, [r7, #4] 8001ea2: 6a5b ldr r3, [r3, #36] @ 0x24 8001ea4: 2b04 cmp r3, #4 8001ea6: d107 bne.n 8001eb8 { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8001ea8: 687b ldr r3, [r7, #4] 8001eaa: 6ada ldr r2, [r3, #44] @ 0x2c 8001eac: 687b ldr r3, [r7, #4] 8001eae: 6b1b ldr r3, [r3, #48] @ 0x30 8001eb0: 4313 orrs r3, r2 8001eb2: 697a ldr r2, [r7, #20] 8001eb4: 4313 orrs r3, r2 8001eb6: 617b str r3, [r7, #20] } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; 8001eb8: 687b ldr r3, [r7, #4] 8001eba: 681b ldr r3, [r3, #0] 8001ebc: 697a ldr r2, [r7, #20] 8001ebe: 601a str r2, [r3, #0] /* Get the FCR register value */ tmp = hdma->Instance->FCR; 8001ec0: 687b ldr r3, [r7, #4] 8001ec2: 681b ldr r3, [r3, #0] 8001ec4: 695b ldr r3, [r3, #20] 8001ec6: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8001ec8: 697b ldr r3, [r7, #20] 8001eca: f023 0307 bic.w r3, r3, #7 8001ece: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; 8001ed0: 687b ldr r3, [r7, #4] 8001ed2: 6a5b ldr r3, [r3, #36] @ 0x24 8001ed4: 697a ldr r2, [r7, #20] 8001ed6: 4313 orrs r3, r2 8001ed8: 617b str r3, [r7, #20] /* The FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001eda: 687b ldr r3, [r7, #4] 8001edc: 6a5b ldr r3, [r3, #36] @ 0x24 8001ede: 2b04 cmp r3, #4 8001ee0: d117 bne.n 8001f12 { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; 8001ee2: 687b ldr r3, [r7, #4] 8001ee4: 6a9b ldr r3, [r3, #40] @ 0x28 8001ee6: 697a ldr r2, [r7, #20] 8001ee8: 4313 orrs r3, r2 8001eea: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8001eec: 687b ldr r3, [r7, #4] 8001eee: 6adb ldr r3, [r3, #44] @ 0x2c 8001ef0: 2b00 cmp r3, #0 8001ef2: d00e beq.n 8001f12 { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8001ef4: 6878 ldr r0, [r7, #4] 8001ef6: f000 fb01 bl 80024fc 8001efa: 4603 mov r3, r0 8001efc: 2b00 cmp r3, #0 8001efe: d008 beq.n 8001f12 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8001f00: 687b ldr r3, [r7, #4] 8001f02: 2240 movs r2, #64 @ 0x40 8001f04: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001f06: 687b ldr r3, [r7, #4] 8001f08: 2201 movs r2, #1 8001f0a: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8001f0e: 2301 movs r3, #1 8001f10: e016 b.n 8001f40 } } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; 8001f12: 687b ldr r3, [r7, #4] 8001f14: 681b ldr r3, [r3, #0] 8001f16: 697a ldr r2, [r7, #20] 8001f18: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8001f1a: 6878 ldr r0, [r7, #4] 8001f1c: f000 fab8 bl 8002490 8001f20: 4603 mov r3, r0 8001f22: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001f24: 687b ldr r3, [r7, #4] 8001f26: 6ddb ldr r3, [r3, #92] @ 0x5c 8001f28: 223f movs r2, #63 @ 0x3f 8001f2a: 409a lsls r2, r3 8001f2c: 68fb ldr r3, [r7, #12] 8001f2e: 609a str r2, [r3, #8] /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001f30: 687b ldr r3, [r7, #4] 8001f32: 2200 movs r2, #0 8001f34: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001f36: 687b ldr r3, [r7, #4] 8001f38: 2201 movs r2, #1 8001f3a: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8001f3e: 2300 movs r3, #0 } 8001f40: 4618 mov r0, r3 8001f42: 3718 adds r7, #24 8001f44: 46bd mov sp, r7 8001f46: bd80 pop {r7, pc} 8001f48: f010803f .word 0xf010803f 08001f4c : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8001f4c: b580 push {r7, lr} 8001f4e: b086 sub sp, #24 8001f50: af00 add r7, sp, #0 8001f52: 60f8 str r0, [r7, #12] 8001f54: 60b9 str r1, [r7, #8] 8001f56: 607a str r2, [r7, #4] 8001f58: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8001f5a: 2300 movs r3, #0 8001f5c: 75fb strb r3, [r7, #23] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001f5e: 68fb ldr r3, [r7, #12] 8001f60: 6d9b ldr r3, [r3, #88] @ 0x58 8001f62: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8001f64: 68fb ldr r3, [r7, #12] 8001f66: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8001f6a: 2b01 cmp r3, #1 8001f6c: d101 bne.n 8001f72 8001f6e: 2302 movs r3, #2 8001f70: e040 b.n 8001ff4 8001f72: 68fb ldr r3, [r7, #12] 8001f74: 2201 movs r2, #1 8001f76: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8001f7a: 68fb ldr r3, [r7, #12] 8001f7c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001f80: b2db uxtb r3, r3 8001f82: 2b01 cmp r3, #1 8001f84: d12f bne.n 8001fe6 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001f86: 68fb ldr r3, [r7, #12] 8001f88: 2202 movs r2, #2 8001f8a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001f8e: 68fb ldr r3, [r7, #12] 8001f90: 2200 movs r2, #0 8001f92: 655a str r2, [r3, #84] @ 0x54 /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8001f94: 683b ldr r3, [r7, #0] 8001f96: 687a ldr r2, [r7, #4] 8001f98: 68b9 ldr r1, [r7, #8] 8001f9a: 68f8 ldr r0, [r7, #12] 8001f9c: f000 fa4a bl 8002434 /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001fa0: 68fb ldr r3, [r7, #12] 8001fa2: 6ddb ldr r3, [r3, #92] @ 0x5c 8001fa4: 223f movs r2, #63 @ 0x3f 8001fa6: 409a lsls r2, r3 8001fa8: 693b ldr r3, [r7, #16] 8001faa: 609a str r2, [r3, #8] /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 8001fac: 68fb ldr r3, [r7, #12] 8001fae: 681b ldr r3, [r3, #0] 8001fb0: 681a ldr r2, [r3, #0] 8001fb2: 68fb ldr r3, [r7, #12] 8001fb4: 681b ldr r3, [r3, #0] 8001fb6: f042 0216 orr.w r2, r2, #22 8001fba: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8001fbc: 68fb ldr r3, [r7, #12] 8001fbe: 6c1b ldr r3, [r3, #64] @ 0x40 8001fc0: 2b00 cmp r3, #0 8001fc2: d007 beq.n 8001fd4 { hdma->Instance->CR |= DMA_IT_HT; 8001fc4: 68fb ldr r3, [r7, #12] 8001fc6: 681b ldr r3, [r3, #0] 8001fc8: 681a ldr r2, [r3, #0] 8001fca: 68fb ldr r3, [r7, #12] 8001fcc: 681b ldr r3, [r3, #0] 8001fce: f042 0208 orr.w r2, r2, #8 8001fd2: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8001fd4: 68fb ldr r3, [r7, #12] 8001fd6: 681b ldr r3, [r3, #0] 8001fd8: 681a ldr r2, [r3, #0] 8001fda: 68fb ldr r3, [r7, #12] 8001fdc: 681b ldr r3, [r3, #0] 8001fde: f042 0201 orr.w r2, r2, #1 8001fe2: 601a str r2, [r3, #0] 8001fe4: e005 b.n 8001ff2 } else { /* Process unlocked */ __HAL_UNLOCK(hdma); 8001fe6: 68fb ldr r3, [r7, #12] 8001fe8: 2200 movs r2, #0 8001fea: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_BUSY; 8001fee: 2302 movs r3, #2 8001ff0: 75fb strb r3, [r7, #23] } return status; 8001ff2: 7dfb ldrb r3, [r7, #23] } 8001ff4: 4618 mov r0, r3 8001ff6: 3718 adds r7, #24 8001ff8: 46bd mov sp, r7 8001ffa: bd80 pop {r7, pc} 08001ffc : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8001ffc: b580 push {r7, lr} 8001ffe: b084 sub sp, #16 8002000: af00 add r7, sp, #0 8002002: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8002004: 687b ldr r3, [r7, #4] 8002006: 6d9b ldr r3, [r3, #88] @ 0x58 8002008: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 800200a: f7ff fdaf bl 8001b6c 800200e: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 8002010: 687b ldr r3, [r7, #4] 8002012: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8002016: b2db uxtb r3, r3 8002018: 2b02 cmp r3, #2 800201a: d008 beq.n 800202e { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800201c: 687b ldr r3, [r7, #4] 800201e: 2280 movs r2, #128 @ 0x80 8002020: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002022: 687b ldr r3, [r7, #4] 8002024: 2200 movs r2, #0 8002026: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 800202a: 2301 movs r3, #1 800202c: e052 b.n 80020d4 } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800202e: 687b ldr r3, [r7, #4] 8002030: 681b ldr r3, [r3, #0] 8002032: 681a ldr r2, [r3, #0] 8002034: 687b ldr r3, [r7, #4] 8002036: 681b ldr r3, [r3, #0] 8002038: f022 0216 bic.w r2, r2, #22 800203c: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 800203e: 687b ldr r3, [r7, #4] 8002040: 681b ldr r3, [r3, #0] 8002042: 695a ldr r2, [r3, #20] 8002044: 687b ldr r3, [r7, #4] 8002046: 681b ldr r3, [r3, #0] 8002048: f022 0280 bic.w r2, r2, #128 @ 0x80 800204c: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800204e: 687b ldr r3, [r7, #4] 8002050: 6c1b ldr r3, [r3, #64] @ 0x40 8002052: 2b00 cmp r3, #0 8002054: d103 bne.n 800205e 8002056: 687b ldr r3, [r7, #4] 8002058: 6c9b ldr r3, [r3, #72] @ 0x48 800205a: 2b00 cmp r3, #0 800205c: d007 beq.n 800206e { hdma->Instance->CR &= ~(DMA_IT_HT); 800205e: 687b ldr r3, [r7, #4] 8002060: 681b ldr r3, [r3, #0] 8002062: 681a ldr r2, [r3, #0] 8002064: 687b ldr r3, [r7, #4] 8002066: 681b ldr r3, [r3, #0] 8002068: f022 0208 bic.w r2, r2, #8 800206c: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800206e: 687b ldr r3, [r7, #4] 8002070: 681b ldr r3, [r3, #0] 8002072: 681a ldr r2, [r3, #0] 8002074: 687b ldr r3, [r7, #4] 8002076: 681b ldr r3, [r3, #0] 8002078: f022 0201 bic.w r2, r2, #1 800207c: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 800207e: e013 b.n 80020a8 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8002080: f7ff fd74 bl 8001b6c 8002084: 4602 mov r2, r0 8002086: 68bb ldr r3, [r7, #8] 8002088: 1ad3 subs r3, r2, r3 800208a: 2b05 cmp r3, #5 800208c: d90c bls.n 80020a8 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800208e: 687b ldr r3, [r7, #4] 8002090: 2220 movs r2, #32 8002092: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8002094: 687b ldr r3, [r7, #4] 8002096: 2203 movs r2, #3 8002098: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800209c: 687b ldr r3, [r7, #4] 800209e: 2200 movs r2, #0 80020a0: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_TIMEOUT; 80020a4: 2303 movs r3, #3 80020a6: e015 b.n 80020d4 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 80020a8: 687b ldr r3, [r7, #4] 80020aa: 681b ldr r3, [r3, #0] 80020ac: 681b ldr r3, [r3, #0] 80020ae: f003 0301 and.w r3, r3, #1 80020b2: 2b00 cmp r3, #0 80020b4: d1e4 bne.n 8002080 } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 80020b6: 687b ldr r3, [r7, #4] 80020b8: 6ddb ldr r3, [r3, #92] @ 0x5c 80020ba: 223f movs r2, #63 @ 0x3f 80020bc: 409a lsls r2, r3 80020be: 68fb ldr r3, [r7, #12] 80020c0: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 80020c2: 687b ldr r3, [r7, #4] 80020c4: 2201 movs r2, #1 80020c6: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80020ca: 687b ldr r3, [r7, #4] 80020cc: 2200 movs r2, #0 80020ce: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 80020d2: 2300 movs r3, #0 } 80020d4: 4618 mov r0, r3 80020d6: 3710 adds r7, #16 80020d8: 46bd mov sp, r7 80020da: bd80 pop {r7, pc} 080020dc : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80020dc: b480 push {r7} 80020de: b083 sub sp, #12 80020e0: af00 add r7, sp, #0 80020e2: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 80020e4: 687b ldr r3, [r7, #4] 80020e6: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80020ea: b2db uxtb r3, r3 80020ec: 2b02 cmp r3, #2 80020ee: d004 beq.n 80020fa { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80020f0: 687b ldr r3, [r7, #4] 80020f2: 2280 movs r2, #128 @ 0x80 80020f4: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 80020f6: 2301 movs r3, #1 80020f8: e00c b.n 8002114 } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 80020fa: 687b ldr r3, [r7, #4] 80020fc: 2205 movs r2, #5 80020fe: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8002102: 687b ldr r3, [r7, #4] 8002104: 681b ldr r3, [r3, #0] 8002106: 681a ldr r2, [r3, #0] 8002108: 687b ldr r3, [r7, #4] 800210a: 681b ldr r3, [r3, #0] 800210c: f022 0201 bic.w r2, r2, #1 8002110: 601a str r2, [r3, #0] } return HAL_OK; 8002112: 2300 movs r3, #0 } 8002114: 4618 mov r0, r3 8002116: 370c adds r7, #12 8002118: 46bd mov sp, r7 800211a: f85d 7b04 ldr.w r7, [sp], #4 800211e: 4770 bx lr 08002120 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8002120: b580 push {r7, lr} 8002122: b086 sub sp, #24 8002124: af00 add r7, sp, #0 8002126: 6078 str r0, [r7, #4] uint32_t tmpisr; __IO uint32_t count = 0U; 8002128: 2300 movs r3, #0 800212a: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 800212c: 4b8e ldr r3, [pc, #568] @ (8002368 ) 800212e: 681b ldr r3, [r3, #0] 8002130: 4a8e ldr r2, [pc, #568] @ (800236c ) 8002132: fba2 2303 umull r2, r3, r2, r3 8002136: 0a9b lsrs r3, r3, #10 8002138: 617b str r3, [r7, #20] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800213a: 687b ldr r3, [r7, #4] 800213c: 6d9b ldr r3, [r3, #88] @ 0x58 800213e: 613b str r3, [r7, #16] tmpisr = regs->ISR; 8002140: 693b ldr r3, [r7, #16] 8002142: 681b ldr r3, [r3, #0] 8002144: 60fb str r3, [r7, #12] /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) 8002146: 687b ldr r3, [r7, #4] 8002148: 6ddb ldr r3, [r3, #92] @ 0x5c 800214a: 2208 movs r2, #8 800214c: 409a lsls r2, r3 800214e: 68fb ldr r3, [r7, #12] 8002150: 4013 ands r3, r2 8002152: 2b00 cmp r3, #0 8002154: d01a beq.n 800218c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) 8002156: 687b ldr r3, [r7, #4] 8002158: 681b ldr r3, [r3, #0] 800215a: 681b ldr r3, [r3, #0] 800215c: f003 0304 and.w r3, r3, #4 8002160: 2b00 cmp r3, #0 8002162: d013 beq.n 800218c { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); 8002164: 687b ldr r3, [r7, #4] 8002166: 681b ldr r3, [r3, #0] 8002168: 681a ldr r2, [r3, #0] 800216a: 687b ldr r3, [r7, #4] 800216c: 681b ldr r3, [r3, #0] 800216e: f022 0204 bic.w r2, r2, #4 8002172: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; 8002174: 687b ldr r3, [r7, #4] 8002176: 6ddb ldr r3, [r3, #92] @ 0x5c 8002178: 2208 movs r2, #8 800217a: 409a lsls r2, r3 800217c: 693b ldr r3, [r7, #16] 800217e: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8002180: 687b ldr r3, [r7, #4] 8002182: 6d5b ldr r3, [r3, #84] @ 0x54 8002184: f043 0201 orr.w r2, r3, #1 8002188: 687b ldr r3, [r7, #4] 800218a: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) 800218c: 687b ldr r3, [r7, #4] 800218e: 6ddb ldr r3, [r3, #92] @ 0x5c 8002190: 2201 movs r2, #1 8002192: 409a lsls r2, r3 8002194: 68fb ldr r3, [r7, #12] 8002196: 4013 ands r3, r2 8002198: 2b00 cmp r3, #0 800219a: d012 beq.n 80021c2 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) 800219c: 687b ldr r3, [r7, #4] 800219e: 681b ldr r3, [r3, #0] 80021a0: 695b ldr r3, [r3, #20] 80021a2: f003 0380 and.w r3, r3, #128 @ 0x80 80021a6: 2b00 cmp r3, #0 80021a8: d00b beq.n 80021c2 { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; 80021aa: 687b ldr r3, [r7, #4] 80021ac: 6ddb ldr r3, [r3, #92] @ 0x5c 80021ae: 2201 movs r2, #1 80021b0: 409a lsls r2, r3 80021b2: 693b ldr r3, [r7, #16] 80021b4: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 80021b6: 687b ldr r3, [r7, #4] 80021b8: 6d5b ldr r3, [r3, #84] @ 0x54 80021ba: f043 0202 orr.w r2, r3, #2 80021be: 687b ldr r3, [r7, #4] 80021c0: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) 80021c2: 687b ldr r3, [r7, #4] 80021c4: 6ddb ldr r3, [r3, #92] @ 0x5c 80021c6: 2204 movs r2, #4 80021c8: 409a lsls r2, r3 80021ca: 68fb ldr r3, [r7, #12] 80021cc: 4013 ands r3, r2 80021ce: 2b00 cmp r3, #0 80021d0: d012 beq.n 80021f8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) 80021d2: 687b ldr r3, [r7, #4] 80021d4: 681b ldr r3, [r3, #0] 80021d6: 681b ldr r3, [r3, #0] 80021d8: f003 0302 and.w r3, r3, #2 80021dc: 2b00 cmp r3, #0 80021de: d00b beq.n 80021f8 { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; 80021e0: 687b ldr r3, [r7, #4] 80021e2: 6ddb ldr r3, [r3, #92] @ 0x5c 80021e4: 2204 movs r2, #4 80021e6: 409a lsls r2, r3 80021e8: 693b ldr r3, [r7, #16] 80021ea: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 80021ec: 687b ldr r3, [r7, #4] 80021ee: 6d5b ldr r3, [r3, #84] @ 0x54 80021f0: f043 0204 orr.w r2, r3, #4 80021f4: 687b ldr r3, [r7, #4] 80021f6: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) 80021f8: 687b ldr r3, [r7, #4] 80021fa: 6ddb ldr r3, [r3, #92] @ 0x5c 80021fc: 2210 movs r2, #16 80021fe: 409a lsls r2, r3 8002200: 68fb ldr r3, [r7, #12] 8002202: 4013 ands r3, r2 8002204: 2b00 cmp r3, #0 8002206: d043 beq.n 8002290 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) 8002208: 687b ldr r3, [r7, #4] 800220a: 681b ldr r3, [r3, #0] 800220c: 681b ldr r3, [r3, #0] 800220e: f003 0308 and.w r3, r3, #8 8002212: 2b00 cmp r3, #0 8002214: d03c beq.n 8002290 { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; 8002216: 687b ldr r3, [r7, #4] 8002218: 6ddb ldr r3, [r3, #92] @ 0x5c 800221a: 2210 movs r2, #16 800221c: 409a lsls r2, r3 800221e: 693b ldr r3, [r7, #16] 8002220: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8002222: 687b ldr r3, [r7, #4] 8002224: 681b ldr r3, [r3, #0] 8002226: 681b ldr r3, [r3, #0] 8002228: f403 2380 and.w r3, r3, #262144 @ 0x40000 800222c: 2b00 cmp r3, #0 800222e: d018 beq.n 8002262 { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8002230: 687b ldr r3, [r7, #4] 8002232: 681b ldr r3, [r3, #0] 8002234: 681b ldr r3, [r3, #0] 8002236: f403 2300 and.w r3, r3, #524288 @ 0x80000 800223a: 2b00 cmp r3, #0 800223c: d108 bne.n 8002250 { if(hdma->XferHalfCpltCallback != NULL) 800223e: 687b ldr r3, [r7, #4] 8002240: 6c1b ldr r3, [r3, #64] @ 0x40 8002242: 2b00 cmp r3, #0 8002244: d024 beq.n 8002290 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002246: 687b ldr r3, [r7, #4] 8002248: 6c1b ldr r3, [r3, #64] @ 0x40 800224a: 6878 ldr r0, [r7, #4] 800224c: 4798 blx r3 800224e: e01f b.n 8002290 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 8002250: 687b ldr r3, [r7, #4] 8002252: 6c9b ldr r3, [r3, #72] @ 0x48 8002254: 2b00 cmp r3, #0 8002256: d01b beq.n 8002290 { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8002258: 687b ldr r3, [r7, #4] 800225a: 6c9b ldr r3, [r3, #72] @ 0x48 800225c: 6878 ldr r0, [r7, #4] 800225e: 4798 blx r3 8002260: e016 b.n 8002290 } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 8002262: 687b ldr r3, [r7, #4] 8002264: 681b ldr r3, [r3, #0] 8002266: 681b ldr r3, [r3, #0] 8002268: f403 7380 and.w r3, r3, #256 @ 0x100 800226c: 2b00 cmp r3, #0 800226e: d107 bne.n 8002280 { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); 8002270: 687b ldr r3, [r7, #4] 8002272: 681b ldr r3, [r3, #0] 8002274: 681a ldr r2, [r3, #0] 8002276: 687b ldr r3, [r7, #4] 8002278: 681b ldr r3, [r3, #0] 800227a: f022 0208 bic.w r2, r2, #8 800227e: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 8002280: 687b ldr r3, [r7, #4] 8002282: 6c1b ldr r3, [r3, #64] @ 0x40 8002284: 2b00 cmp r3, #0 8002286: d003 beq.n 8002290 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002288: 687b ldr r3, [r7, #4] 800228a: 6c1b ldr r3, [r3, #64] @ 0x40 800228c: 6878 ldr r0, [r7, #4] 800228e: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) 8002290: 687b ldr r3, [r7, #4] 8002292: 6ddb ldr r3, [r3, #92] @ 0x5c 8002294: 2220 movs r2, #32 8002296: 409a lsls r2, r3 8002298: 68fb ldr r3, [r7, #12] 800229a: 4013 ands r3, r2 800229c: 2b00 cmp r3, #0 800229e: f000 808f beq.w 80023c0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) 80022a2: 687b ldr r3, [r7, #4] 80022a4: 681b ldr r3, [r3, #0] 80022a6: 681b ldr r3, [r3, #0] 80022a8: f003 0310 and.w r3, r3, #16 80022ac: 2b00 cmp r3, #0 80022ae: f000 8087 beq.w 80023c0 { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; 80022b2: 687b ldr r3, [r7, #4] 80022b4: 6ddb ldr r3, [r3, #92] @ 0x5c 80022b6: 2220 movs r2, #32 80022b8: 409a lsls r2, r3 80022ba: 693b ldr r3, [r7, #16] 80022bc: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 80022be: 687b ldr r3, [r7, #4] 80022c0: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80022c4: b2db uxtb r3, r3 80022c6: 2b05 cmp r3, #5 80022c8: d136 bne.n 8002338 { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 80022ca: 687b ldr r3, [r7, #4] 80022cc: 681b ldr r3, [r3, #0] 80022ce: 681a ldr r2, [r3, #0] 80022d0: 687b ldr r3, [r7, #4] 80022d2: 681b ldr r3, [r3, #0] 80022d4: f022 0216 bic.w r2, r2, #22 80022d8: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 80022da: 687b ldr r3, [r7, #4] 80022dc: 681b ldr r3, [r3, #0] 80022de: 695a ldr r2, [r3, #20] 80022e0: 687b ldr r3, [r7, #4] 80022e2: 681b ldr r3, [r3, #0] 80022e4: f022 0280 bic.w r2, r2, #128 @ 0x80 80022e8: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 80022ea: 687b ldr r3, [r7, #4] 80022ec: 6c1b ldr r3, [r3, #64] @ 0x40 80022ee: 2b00 cmp r3, #0 80022f0: d103 bne.n 80022fa 80022f2: 687b ldr r3, [r7, #4] 80022f4: 6c9b ldr r3, [r3, #72] @ 0x48 80022f6: 2b00 cmp r3, #0 80022f8: d007 beq.n 800230a { hdma->Instance->CR &= ~(DMA_IT_HT); 80022fa: 687b ldr r3, [r7, #4] 80022fc: 681b ldr r3, [r3, #0] 80022fe: 681a ldr r2, [r3, #0] 8002300: 687b ldr r3, [r7, #4] 8002302: 681b ldr r3, [r3, #0] 8002304: f022 0208 bic.w r2, r2, #8 8002308: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 800230a: 687b ldr r3, [r7, #4] 800230c: 6ddb ldr r3, [r3, #92] @ 0x5c 800230e: 223f movs r2, #63 @ 0x3f 8002310: 409a lsls r2, r3 8002312: 693b ldr r3, [r7, #16] 8002314: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002316: 687b ldr r3, [r7, #4] 8002318: 2201 movs r2, #1 800231a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800231e: 687b ldr r3, [r7, #4] 8002320: 2200 movs r2, #0 8002322: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8002326: 687b ldr r3, [r7, #4] 8002328: 6d1b ldr r3, [r3, #80] @ 0x50 800232a: 2b00 cmp r3, #0 800232c: d07e beq.n 800242c { hdma->XferAbortCallback(hdma); 800232e: 687b ldr r3, [r7, #4] 8002330: 6d1b ldr r3, [r3, #80] @ 0x50 8002332: 6878 ldr r0, [r7, #4] 8002334: 4798 blx r3 } return; 8002336: e079 b.n 800242c } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8002338: 687b ldr r3, [r7, #4] 800233a: 681b ldr r3, [r3, #0] 800233c: 681b ldr r3, [r3, #0] 800233e: f403 2380 and.w r3, r3, #262144 @ 0x40000 8002342: 2b00 cmp r3, #0 8002344: d01d beq.n 8002382 { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8002346: 687b ldr r3, [r7, #4] 8002348: 681b ldr r3, [r3, #0] 800234a: 681b ldr r3, [r3, #0] 800234c: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002350: 2b00 cmp r3, #0 8002352: d10d bne.n 8002370 { if(hdma->XferM1CpltCallback != NULL) 8002354: 687b ldr r3, [r7, #4] 8002356: 6c5b ldr r3, [r3, #68] @ 0x44 8002358: 2b00 cmp r3, #0 800235a: d031 beq.n 80023c0 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 800235c: 687b ldr r3, [r7, #4] 800235e: 6c5b ldr r3, [r3, #68] @ 0x44 8002360: 6878 ldr r0, [r7, #4] 8002362: 4798 blx r3 8002364: e02c b.n 80023c0 8002366: bf00 nop 8002368: 20000090 .word 0x20000090 800236c: 1b4e81b5 .word 0x1b4e81b5 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8002370: 687b ldr r3, [r7, #4] 8002372: 6bdb ldr r3, [r3, #60] @ 0x3c 8002374: 2b00 cmp r3, #0 8002376: d023 beq.n 80023c0 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8002378: 687b ldr r3, [r7, #4] 800237a: 6bdb ldr r3, [r3, #60] @ 0x3c 800237c: 6878 ldr r0, [r7, #4] 800237e: 4798 blx r3 8002380: e01e b.n 80023c0 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 8002382: 687b ldr r3, [r7, #4] 8002384: 681b ldr r3, [r3, #0] 8002386: 681b ldr r3, [r3, #0] 8002388: f403 7380 and.w r3, r3, #256 @ 0x100 800238c: 2b00 cmp r3, #0 800238e: d10f bne.n 80023b0 { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); 8002390: 687b ldr r3, [r7, #4] 8002392: 681b ldr r3, [r3, #0] 8002394: 681a ldr r2, [r3, #0] 8002396: 687b ldr r3, [r7, #4] 8002398: 681b ldr r3, [r3, #0] 800239a: f022 0210 bic.w r2, r2, #16 800239e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80023a0: 687b ldr r3, [r7, #4] 80023a2: 2201 movs r2, #1 80023a4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80023a8: 687b ldr r3, [r7, #4] 80023aa: 2200 movs r2, #0 80023ac: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 80023b0: 687b ldr r3, [r7, #4] 80023b2: 6bdb ldr r3, [r3, #60] @ 0x3c 80023b4: 2b00 cmp r3, #0 80023b6: d003 beq.n 80023c0 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 80023b8: 687b ldr r3, [r7, #4] 80023ba: 6bdb ldr r3, [r3, #60] @ 0x3c 80023bc: 6878 ldr r0, [r7, #4] 80023be: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 80023c0: 687b ldr r3, [r7, #4] 80023c2: 6d5b ldr r3, [r3, #84] @ 0x54 80023c4: 2b00 cmp r3, #0 80023c6: d032 beq.n 800242e { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) 80023c8: 687b ldr r3, [r7, #4] 80023ca: 6d5b ldr r3, [r3, #84] @ 0x54 80023cc: f003 0301 and.w r3, r3, #1 80023d0: 2b00 cmp r3, #0 80023d2: d022 beq.n 800241a { hdma->State = HAL_DMA_STATE_ABORT; 80023d4: 687b ldr r3, [r7, #4] 80023d6: 2205 movs r2, #5 80023d8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80023dc: 687b ldr r3, [r7, #4] 80023de: 681b ldr r3, [r3, #0] 80023e0: 681a ldr r2, [r3, #0] 80023e2: 687b ldr r3, [r7, #4] 80023e4: 681b ldr r3, [r3, #0] 80023e6: f022 0201 bic.w r2, r2, #1 80023ea: 601a str r2, [r3, #0] do { if (++count > timeout) 80023ec: 68bb ldr r3, [r7, #8] 80023ee: 3301 adds r3, #1 80023f0: 60bb str r3, [r7, #8] 80023f2: 697a ldr r2, [r7, #20] 80023f4: 429a cmp r2, r3 80023f6: d307 bcc.n 8002408 { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); 80023f8: 687b ldr r3, [r7, #4] 80023fa: 681b ldr r3, [r3, #0] 80023fc: 681b ldr r3, [r3, #0] 80023fe: f003 0301 and.w r3, r3, #1 8002402: 2b00 cmp r3, #0 8002404: d1f2 bne.n 80023ec 8002406: e000 b.n 800240a break; 8002408: bf00 nop /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800240a: 687b ldr r3, [r7, #4] 800240c: 2201 movs r2, #1 800240e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002412: 687b ldr r3, [r7, #4] 8002414: 2200 movs r2, #0 8002416: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 800241a: 687b ldr r3, [r7, #4] 800241c: 6cdb ldr r3, [r3, #76] @ 0x4c 800241e: 2b00 cmp r3, #0 8002420: d005 beq.n 800242e { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8002422: 687b ldr r3, [r7, #4] 8002424: 6cdb ldr r3, [r3, #76] @ 0x4c 8002426: 6878 ldr r0, [r7, #4] 8002428: 4798 blx r3 800242a: e000 b.n 800242e return; 800242c: bf00 nop } } } 800242e: 3718 adds r7, #24 8002430: 46bd mov sp, r7 8002432: bd80 pop {r7, pc} 08002434 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002434: b480 push {r7} 8002436: b085 sub sp, #20 8002438: af00 add r7, sp, #0 800243a: 60f8 str r0, [r7, #12] 800243c: 60b9 str r1, [r7, #8] 800243e: 607a str r2, [r7, #4] 8002440: 603b str r3, [r7, #0] /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); 8002442: 68fb ldr r3, [r7, #12] 8002444: 681b ldr r3, [r3, #0] 8002446: 681a ldr r2, [r3, #0] 8002448: 68fb ldr r3, [r7, #12] 800244a: 681b ldr r3, [r3, #0] 800244c: f422 2280 bic.w r2, r2, #262144 @ 0x40000 8002450: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; 8002452: 68fb ldr r3, [r7, #12] 8002454: 681b ldr r3, [r3, #0] 8002456: 683a ldr r2, [r7, #0] 8002458: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800245a: 68fb ldr r3, [r7, #12] 800245c: 689b ldr r3, [r3, #8] 800245e: 2b40 cmp r3, #64 @ 0x40 8002460: d108 bne.n 8002474 { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; 8002462: 68fb ldr r3, [r7, #12] 8002464: 681b ldr r3, [r3, #0] 8002466: 687a ldr r2, [r7, #4] 8002468: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; 800246a: 68fb ldr r3, [r7, #12] 800246c: 681b ldr r3, [r3, #0] 800246e: 68ba ldr r2, [r7, #8] 8002470: 60da str r2, [r3, #12] hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } 8002472: e007 b.n 8002484 hdma->Instance->PAR = SrcAddress; 8002474: 68fb ldr r3, [r7, #12] 8002476: 681b ldr r3, [r3, #0] 8002478: 68ba ldr r2, [r7, #8] 800247a: 609a str r2, [r3, #8] hdma->Instance->M0AR = DstAddress; 800247c: 68fb ldr r3, [r7, #12] 800247e: 681b ldr r3, [r3, #0] 8002480: 687a ldr r2, [r7, #4] 8002482: 60da str r2, [r3, #12] } 8002484: bf00 nop 8002486: 3714 adds r7, #20 8002488: 46bd mov sp, r7 800248a: f85d 7b04 ldr.w r7, [sp], #4 800248e: 4770 bx lr 08002490 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 8002490: b480 push {r7} 8002492: b085 sub sp, #20 8002494: af00 add r7, sp, #0 8002496: 6078 str r0, [r7, #4] uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; 8002498: 687b ldr r3, [r7, #4] 800249a: 681b ldr r3, [r3, #0] 800249c: b2db uxtb r3, r3 800249e: 3b10 subs r3, #16 80024a0: 4a14 ldr r2, [pc, #80] @ (80024f4 ) 80024a2: fba2 2303 umull r2, r3, r2, r3 80024a6: 091b lsrs r3, r3, #4 80024a8: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; 80024aa: 4a13 ldr r2, [pc, #76] @ (80024f8 ) 80024ac: 68fb ldr r3, [r7, #12] 80024ae: 4413 add r3, r2 80024b0: 781b ldrb r3, [r3, #0] 80024b2: 461a mov r2, r3 80024b4: 687b ldr r3, [r7, #4] 80024b6: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 80024b8: 68fb ldr r3, [r7, #12] 80024ba: 2b03 cmp r3, #3 80024bc: d909 bls.n 80024d2 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); 80024be: 687b ldr r3, [r7, #4] 80024c0: 681b ldr r3, [r3, #0] 80024c2: f423 737f bic.w r3, r3, #1020 @ 0x3fc 80024c6: f023 0303 bic.w r3, r3, #3 80024ca: 1d1a adds r2, r3, #4 80024cc: 687b ldr r3, [r7, #4] 80024ce: 659a str r2, [r3, #88] @ 0x58 80024d0: e007 b.n 80024e2 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); 80024d2: 687b ldr r3, [r7, #4] 80024d4: 681b ldr r3, [r3, #0] 80024d6: f423 737f bic.w r3, r3, #1020 @ 0x3fc 80024da: f023 0303 bic.w r3, r3, #3 80024de: 687a ldr r2, [r7, #4] 80024e0: 6593 str r3, [r2, #88] @ 0x58 } return hdma->StreamBaseAddress; 80024e2: 687b ldr r3, [r7, #4] 80024e4: 6d9b ldr r3, [r3, #88] @ 0x58 } 80024e6: 4618 mov r0, r3 80024e8: 3714 adds r7, #20 80024ea: 46bd mov sp, r7 80024ec: f85d 7b04 ldr.w r7, [sp], #4 80024f0: 4770 bx lr 80024f2: bf00 nop 80024f4: aaaaaaab .word 0xaaaaaaab 80024f8: 0800ab2c .word 0x0800ab2c 080024fc : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 80024fc: b480 push {r7} 80024fe: b085 sub sp, #20 8002500: af00 add r7, sp, #0 8002502: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002504: 2300 movs r3, #0 8002506: 73fb strb r3, [r7, #15] uint32_t tmp = hdma->Init.FIFOThreshold; 8002508: 687b ldr r3, [r7, #4] 800250a: 6a9b ldr r3, [r3, #40] @ 0x28 800250c: 60bb str r3, [r7, #8] /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800250e: 687b ldr r3, [r7, #4] 8002510: 699b ldr r3, [r3, #24] 8002512: 2b00 cmp r3, #0 8002514: d11f bne.n 8002556 { switch (tmp) 8002516: 68bb ldr r3, [r7, #8] 8002518: 2b03 cmp r3, #3 800251a: d856 bhi.n 80025ca 800251c: a201 add r2, pc, #4 @ (adr r2, 8002524 ) 800251e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002522: bf00 nop 8002524: 08002535 .word 0x08002535 8002528: 08002547 .word 0x08002547 800252c: 08002535 .word 0x08002535 8002530: 080025cb .word 0x080025cb { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002534: 687b ldr r3, [r7, #4] 8002536: 6adb ldr r3, [r3, #44] @ 0x2c 8002538: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800253c: 2b00 cmp r3, #0 800253e: d046 beq.n 80025ce { status = HAL_ERROR; 8002540: 2301 movs r3, #1 8002542: 73fb strb r3, [r7, #15] } break; 8002544: e043 b.n 80025ce case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002546: 687b ldr r3, [r7, #4] 8002548: 6adb ldr r3, [r3, #44] @ 0x2c 800254a: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800254e: d140 bne.n 80025d2 { status = HAL_ERROR; 8002550: 2301 movs r3, #1 8002552: 73fb strb r3, [r7, #15] } break; 8002554: e03d b.n 80025d2 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8002556: 687b ldr r3, [r7, #4] 8002558: 699b ldr r3, [r3, #24] 800255a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800255e: d121 bne.n 80025a4 { switch (tmp) 8002560: 68bb ldr r3, [r7, #8] 8002562: 2b03 cmp r3, #3 8002564: d837 bhi.n 80025d6 8002566: a201 add r2, pc, #4 @ (adr r2, 800256c ) 8002568: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800256c: 0800257d .word 0x0800257d 8002570: 08002583 .word 0x08002583 8002574: 0800257d .word 0x0800257d 8002578: 08002595 .word 0x08002595 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800257c: 2301 movs r3, #1 800257e: 73fb strb r3, [r7, #15] break; 8002580: e030 b.n 80025e4 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002582: 687b ldr r3, [r7, #4] 8002584: 6adb ldr r3, [r3, #44] @ 0x2c 8002586: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800258a: 2b00 cmp r3, #0 800258c: d025 beq.n 80025da { status = HAL_ERROR; 800258e: 2301 movs r3, #1 8002590: 73fb strb r3, [r7, #15] } break; 8002592: e022 b.n 80025da case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002594: 687b ldr r3, [r7, #4] 8002596: 6adb ldr r3, [r3, #44] @ 0x2c 8002598: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800259c: d11f bne.n 80025de { status = HAL_ERROR; 800259e: 2301 movs r3, #1 80025a0: 73fb strb r3, [r7, #15] } break; 80025a2: e01c b.n 80025de } /* Memory Data size equal to Word */ else { switch (tmp) 80025a4: 68bb ldr r3, [r7, #8] 80025a6: 2b02 cmp r3, #2 80025a8: d903 bls.n 80025b2 80025aa: 68bb ldr r3, [r7, #8] 80025ac: 2b03 cmp r3, #3 80025ae: d003 beq.n 80025b8 { status = HAL_ERROR; } break; default: break; 80025b0: e018 b.n 80025e4 status = HAL_ERROR; 80025b2: 2301 movs r3, #1 80025b4: 73fb strb r3, [r7, #15] break; 80025b6: e015 b.n 80025e4 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 80025b8: 687b ldr r3, [r7, #4] 80025ba: 6adb ldr r3, [r3, #44] @ 0x2c 80025bc: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80025c0: 2b00 cmp r3, #0 80025c2: d00e beq.n 80025e2 status = HAL_ERROR; 80025c4: 2301 movs r3, #1 80025c6: 73fb strb r3, [r7, #15] break; 80025c8: e00b b.n 80025e2 break; 80025ca: bf00 nop 80025cc: e00a b.n 80025e4 break; 80025ce: bf00 nop 80025d0: e008 b.n 80025e4 break; 80025d2: bf00 nop 80025d4: e006 b.n 80025e4 break; 80025d6: bf00 nop 80025d8: e004 b.n 80025e4 break; 80025da: bf00 nop 80025dc: e002 b.n 80025e4 break; 80025de: bf00 nop 80025e0: e000 b.n 80025e4 break; 80025e2: bf00 nop } } return status; 80025e4: 7bfb ldrb r3, [r7, #15] } 80025e6: 4618 mov r0, r3 80025e8: 3714 adds r7, #20 80025ea: 46bd mov sp, r7 80025ec: f85d 7b04 ldr.w r7, [sp], #4 80025f0: 4770 bx lr 80025f2: bf00 nop 080025f4 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80025f4: b480 push {r7} 80025f6: b089 sub sp, #36 @ 0x24 80025f8: af00 add r7, sp, #0 80025fa: 6078 str r0, [r7, #4] 80025fc: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 80025fe: 2300 movs r3, #0 8002600: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8002602: 2300 movs r3, #0 8002604: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8002606: 2300 movs r3, #0 8002608: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 800260a: 2300 movs r3, #0 800260c: 61fb str r3, [r7, #28] 800260e: e165 b.n 80028dc { /* Get the IO position */ ioposition = 0x01U << position; 8002610: 2201 movs r2, #1 8002612: 69fb ldr r3, [r7, #28] 8002614: fa02 f303 lsl.w r3, r2, r3 8002618: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800261a: 683b ldr r3, [r7, #0] 800261c: 681b ldr r3, [r3, #0] 800261e: 697a ldr r2, [r7, #20] 8002620: 4013 ands r3, r2 8002622: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8002624: 693a ldr r2, [r7, #16] 8002626: 697b ldr r3, [r7, #20] 8002628: 429a cmp r2, r3 800262a: f040 8154 bne.w 80028d6 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 800262e: 683b ldr r3, [r7, #0] 8002630: 685b ldr r3, [r3, #4] 8002632: f003 0303 and.w r3, r3, #3 8002636: 2b01 cmp r3, #1 8002638: d005 beq.n 8002646 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800263a: 683b ldr r3, [r7, #0] 800263c: 685b ldr r3, [r3, #4] 800263e: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8002642: 2b02 cmp r3, #2 8002644: d130 bne.n 80026a8 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002646: 687b ldr r3, [r7, #4] 8002648: 689b ldr r3, [r3, #8] 800264a: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 800264c: 69fb ldr r3, [r7, #28] 800264e: 005b lsls r3, r3, #1 8002650: 2203 movs r2, #3 8002652: fa02 f303 lsl.w r3, r2, r3 8002656: 43db mvns r3, r3 8002658: 69ba ldr r2, [r7, #24] 800265a: 4013 ands r3, r2 800265c: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800265e: 683b ldr r3, [r7, #0] 8002660: 68da ldr r2, [r3, #12] 8002662: 69fb ldr r3, [r7, #28] 8002664: 005b lsls r3, r3, #1 8002666: fa02 f303 lsl.w r3, r2, r3 800266a: 69ba ldr r2, [r7, #24] 800266c: 4313 orrs r3, r2 800266e: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8002670: 687b ldr r3, [r7, #4] 8002672: 69ba ldr r2, [r7, #24] 8002674: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8002676: 687b ldr r3, [r7, #4] 8002678: 685b ldr r3, [r3, #4] 800267a: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 800267c: 2201 movs r2, #1 800267e: 69fb ldr r3, [r7, #28] 8002680: fa02 f303 lsl.w r3, r2, r3 8002684: 43db mvns r3, r3 8002686: 69ba ldr r2, [r7, #24] 8002688: 4013 ands r3, r2 800268a: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800268c: 683b ldr r3, [r7, #0] 800268e: 685b ldr r3, [r3, #4] 8002690: 091b lsrs r3, r3, #4 8002692: f003 0201 and.w r2, r3, #1 8002696: 69fb ldr r3, [r7, #28] 8002698: fa02 f303 lsl.w r3, r2, r3 800269c: 69ba ldr r2, [r7, #24] 800269e: 4313 orrs r3, r2 80026a0: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 80026a2: 687b ldr r3, [r7, #4] 80026a4: 69ba ldr r2, [r7, #24] 80026a6: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 80026a8: 683b ldr r3, [r7, #0] 80026aa: 685b ldr r3, [r3, #4] 80026ac: f003 0303 and.w r3, r3, #3 80026b0: 2b03 cmp r3, #3 80026b2: d017 beq.n 80026e4 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 80026b4: 687b ldr r3, [r7, #4] 80026b6: 68db ldr r3, [r3, #12] 80026b8: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 80026ba: 69fb ldr r3, [r7, #28] 80026bc: 005b lsls r3, r3, #1 80026be: 2203 movs r2, #3 80026c0: fa02 f303 lsl.w r3, r2, r3 80026c4: 43db mvns r3, r3 80026c6: 69ba ldr r2, [r7, #24] 80026c8: 4013 ands r3, r2 80026ca: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 80026cc: 683b ldr r3, [r7, #0] 80026ce: 689a ldr r2, [r3, #8] 80026d0: 69fb ldr r3, [r7, #28] 80026d2: 005b lsls r3, r3, #1 80026d4: fa02 f303 lsl.w r3, r2, r3 80026d8: 69ba ldr r2, [r7, #24] 80026da: 4313 orrs r3, r2 80026dc: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 80026de: 687b ldr r3, [r7, #4] 80026e0: 69ba ldr r2, [r7, #24] 80026e2: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80026e4: 683b ldr r3, [r7, #0] 80026e6: 685b ldr r3, [r3, #4] 80026e8: f003 0303 and.w r3, r3, #3 80026ec: 2b02 cmp r3, #2 80026ee: d123 bne.n 8002738 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 80026f0: 69fb ldr r3, [r7, #28] 80026f2: 08da lsrs r2, r3, #3 80026f4: 687b ldr r3, [r7, #4] 80026f6: 3208 adds r2, #8 80026f8: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80026fc: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 80026fe: 69fb ldr r3, [r7, #28] 8002700: f003 0307 and.w r3, r3, #7 8002704: 009b lsls r3, r3, #2 8002706: 220f movs r2, #15 8002708: fa02 f303 lsl.w r3, r2, r3 800270c: 43db mvns r3, r3 800270e: 69ba ldr r2, [r7, #24] 8002710: 4013 ands r3, r2 8002712: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8002714: 683b ldr r3, [r7, #0] 8002716: 691a ldr r2, [r3, #16] 8002718: 69fb ldr r3, [r7, #28] 800271a: f003 0307 and.w r3, r3, #7 800271e: 009b lsls r3, r3, #2 8002720: fa02 f303 lsl.w r3, r2, r3 8002724: 69ba ldr r2, [r7, #24] 8002726: 4313 orrs r3, r2 8002728: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 800272a: 69fb ldr r3, [r7, #28] 800272c: 08da lsrs r2, r3, #3 800272e: 687b ldr r3, [r7, #4] 8002730: 3208 adds r2, #8 8002732: 69b9 ldr r1, [r7, #24] 8002734: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002738: 687b ldr r3, [r7, #4] 800273a: 681b ldr r3, [r3, #0] 800273c: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 800273e: 69fb ldr r3, [r7, #28] 8002740: 005b lsls r3, r3, #1 8002742: 2203 movs r2, #3 8002744: fa02 f303 lsl.w r3, r2, r3 8002748: 43db mvns r3, r3 800274a: 69ba ldr r2, [r7, #24] 800274c: 4013 ands r3, r2 800274e: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8002750: 683b ldr r3, [r7, #0] 8002752: 685b ldr r3, [r3, #4] 8002754: f003 0203 and.w r2, r3, #3 8002758: 69fb ldr r3, [r7, #28] 800275a: 005b lsls r3, r3, #1 800275c: fa02 f303 lsl.w r3, r2, r3 8002760: 69ba ldr r2, [r7, #24] 8002762: 4313 orrs r3, r2 8002764: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8002766: 687b ldr r3, [r7, #4] 8002768: 69ba ldr r2, [r7, #24] 800276a: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800276c: 683b ldr r3, [r7, #0] 800276e: 685b ldr r3, [r3, #4] 8002770: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002774: 2b00 cmp r3, #0 8002776: f000 80ae beq.w 80028d6 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800277a: 2300 movs r3, #0 800277c: 60fb str r3, [r7, #12] 800277e: 4b5d ldr r3, [pc, #372] @ (80028f4 ) 8002780: 6c5b ldr r3, [r3, #68] @ 0x44 8002782: 4a5c ldr r2, [pc, #368] @ (80028f4 ) 8002784: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002788: 6453 str r3, [r2, #68] @ 0x44 800278a: 4b5a ldr r3, [pc, #360] @ (80028f4 ) 800278c: 6c5b ldr r3, [r3, #68] @ 0x44 800278e: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002792: 60fb str r3, [r7, #12] 8002794: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8002796: 4a58 ldr r2, [pc, #352] @ (80028f8 ) 8002798: 69fb ldr r3, [r7, #28] 800279a: 089b lsrs r3, r3, #2 800279c: 3302 adds r3, #2 800279e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80027a2: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 80027a4: 69fb ldr r3, [r7, #28] 80027a6: f003 0303 and.w r3, r3, #3 80027aa: 009b lsls r3, r3, #2 80027ac: 220f movs r2, #15 80027ae: fa02 f303 lsl.w r3, r2, r3 80027b2: 43db mvns r3, r3 80027b4: 69ba ldr r2, [r7, #24] 80027b6: 4013 ands r3, r2 80027b8: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 80027ba: 687b ldr r3, [r7, #4] 80027bc: 4a4f ldr r2, [pc, #316] @ (80028fc ) 80027be: 4293 cmp r3, r2 80027c0: d025 beq.n 800280e 80027c2: 687b ldr r3, [r7, #4] 80027c4: 4a4e ldr r2, [pc, #312] @ (8002900 ) 80027c6: 4293 cmp r3, r2 80027c8: d01f beq.n 800280a 80027ca: 687b ldr r3, [r7, #4] 80027cc: 4a4d ldr r2, [pc, #308] @ (8002904 ) 80027ce: 4293 cmp r3, r2 80027d0: d019 beq.n 8002806 80027d2: 687b ldr r3, [r7, #4] 80027d4: 4a4c ldr r2, [pc, #304] @ (8002908 ) 80027d6: 4293 cmp r3, r2 80027d8: d013 beq.n 8002802 80027da: 687b ldr r3, [r7, #4] 80027dc: 4a4b ldr r2, [pc, #300] @ (800290c ) 80027de: 4293 cmp r3, r2 80027e0: d00d beq.n 80027fe 80027e2: 687b ldr r3, [r7, #4] 80027e4: 4a4a ldr r2, [pc, #296] @ (8002910 ) 80027e6: 4293 cmp r3, r2 80027e8: d007 beq.n 80027fa 80027ea: 687b ldr r3, [r7, #4] 80027ec: 4a49 ldr r2, [pc, #292] @ (8002914 ) 80027ee: 4293 cmp r3, r2 80027f0: d101 bne.n 80027f6 80027f2: 2306 movs r3, #6 80027f4: e00c b.n 8002810 80027f6: 2307 movs r3, #7 80027f8: e00a b.n 8002810 80027fa: 2305 movs r3, #5 80027fc: e008 b.n 8002810 80027fe: 2304 movs r3, #4 8002800: e006 b.n 8002810 8002802: 2303 movs r3, #3 8002804: e004 b.n 8002810 8002806: 2302 movs r3, #2 8002808: e002 b.n 8002810 800280a: 2301 movs r3, #1 800280c: e000 b.n 8002810 800280e: 2300 movs r3, #0 8002810: 69fa ldr r2, [r7, #28] 8002812: f002 0203 and.w r2, r2, #3 8002816: 0092 lsls r2, r2, #2 8002818: 4093 lsls r3, r2 800281a: 69ba ldr r2, [r7, #24] 800281c: 4313 orrs r3, r2 800281e: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8002820: 4935 ldr r1, [pc, #212] @ (80028f8 ) 8002822: 69fb ldr r3, [r7, #28] 8002824: 089b lsrs r3, r3, #2 8002826: 3302 adds r3, #2 8002828: 69ba ldr r2, [r7, #24] 800282a: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 800282e: 4b3a ldr r3, [pc, #232] @ (8002918 ) 8002830: 689b ldr r3, [r3, #8] 8002832: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002834: 693b ldr r3, [r7, #16] 8002836: 43db mvns r3, r3 8002838: 69ba ldr r2, [r7, #24] 800283a: 4013 ands r3, r2 800283c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800283e: 683b ldr r3, [r7, #0] 8002840: 685b ldr r3, [r3, #4] 8002842: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8002846: 2b00 cmp r3, #0 8002848: d003 beq.n 8002852 { temp |= iocurrent; 800284a: 69ba ldr r2, [r7, #24] 800284c: 693b ldr r3, [r7, #16] 800284e: 4313 orrs r3, r2 8002850: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8002852: 4a31 ldr r2, [pc, #196] @ (8002918 ) 8002854: 69bb ldr r3, [r7, #24] 8002856: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8002858: 4b2f ldr r3, [pc, #188] @ (8002918 ) 800285a: 68db ldr r3, [r3, #12] 800285c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800285e: 693b ldr r3, [r7, #16] 8002860: 43db mvns r3, r3 8002862: 69ba ldr r2, [r7, #24] 8002864: 4013 ands r3, r2 8002866: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8002868: 683b ldr r3, [r7, #0] 800286a: 685b ldr r3, [r3, #4] 800286c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8002870: 2b00 cmp r3, #0 8002872: d003 beq.n 800287c { temp |= iocurrent; 8002874: 69ba ldr r2, [r7, #24] 8002876: 693b ldr r3, [r7, #16] 8002878: 4313 orrs r3, r2 800287a: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 800287c: 4a26 ldr r2, [pc, #152] @ (8002918 ) 800287e: 69bb ldr r3, [r7, #24] 8002880: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 8002882: 4b25 ldr r3, [pc, #148] @ (8002918 ) 8002884: 685b ldr r3, [r3, #4] 8002886: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002888: 693b ldr r3, [r7, #16] 800288a: 43db mvns r3, r3 800288c: 69ba ldr r2, [r7, #24] 800288e: 4013 ands r3, r2 8002890: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8002892: 683b ldr r3, [r7, #0] 8002894: 685b ldr r3, [r3, #4] 8002896: f403 3300 and.w r3, r3, #131072 @ 0x20000 800289a: 2b00 cmp r3, #0 800289c: d003 beq.n 80028a6 { temp |= iocurrent; 800289e: 69ba ldr r2, [r7, #24] 80028a0: 693b ldr r3, [r7, #16] 80028a2: 4313 orrs r3, r2 80028a4: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 80028a6: 4a1c ldr r2, [pc, #112] @ (8002918 ) 80028a8: 69bb ldr r3, [r7, #24] 80028aa: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 80028ac: 4b1a ldr r3, [pc, #104] @ (8002918 ) 80028ae: 681b ldr r3, [r3, #0] 80028b0: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 80028b2: 693b ldr r3, [r7, #16] 80028b4: 43db mvns r3, r3 80028b6: 69ba ldr r2, [r7, #24] 80028b8: 4013 ands r3, r2 80028ba: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 80028bc: 683b ldr r3, [r7, #0] 80028be: 685b ldr r3, [r3, #4] 80028c0: f403 3380 and.w r3, r3, #65536 @ 0x10000 80028c4: 2b00 cmp r3, #0 80028c6: d003 beq.n 80028d0 { temp |= iocurrent; 80028c8: 69ba ldr r2, [r7, #24] 80028ca: 693b ldr r3, [r7, #16] 80028cc: 4313 orrs r3, r2 80028ce: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 80028d0: 4a11 ldr r2, [pc, #68] @ (8002918 ) 80028d2: 69bb ldr r3, [r7, #24] 80028d4: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 80028d6: 69fb ldr r3, [r7, #28] 80028d8: 3301 adds r3, #1 80028da: 61fb str r3, [r7, #28] 80028dc: 69fb ldr r3, [r7, #28] 80028de: 2b0f cmp r3, #15 80028e0: f67f ae96 bls.w 8002610 } } } } 80028e4: bf00 nop 80028e6: bf00 nop 80028e8: 3724 adds r7, #36 @ 0x24 80028ea: 46bd mov sp, r7 80028ec: f85d 7b04 ldr.w r7, [sp], #4 80028f0: 4770 bx lr 80028f2: bf00 nop 80028f4: 40023800 .word 0x40023800 80028f8: 40013800 .word 0x40013800 80028fc: 40020000 .word 0x40020000 8002900: 40020400 .word 0x40020400 8002904: 40020800 .word 0x40020800 8002908: 40020c00 .word 0x40020c00 800290c: 40021000 .word 0x40021000 8002910: 40021400 .word 0x40021400 8002914: 40021800 .word 0x40021800 8002918: 40013c00 .word 0x40013c00 0800291c : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 800291c: b480 push {r7} 800291e: b085 sub sp, #20 8002920: af00 add r7, sp, #0 8002922: 6078 str r0, [r7, #4] 8002924: 460b mov r3, r1 8002926: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8002928: 687b ldr r3, [r7, #4] 800292a: 691a ldr r2, [r3, #16] 800292c: 887b ldrh r3, [r7, #2] 800292e: 4013 ands r3, r2 8002930: 2b00 cmp r3, #0 8002932: d002 beq.n 800293a { bitstatus = GPIO_PIN_SET; 8002934: 2301 movs r3, #1 8002936: 73fb strb r3, [r7, #15] 8002938: e001 b.n 800293e } else { bitstatus = GPIO_PIN_RESET; 800293a: 2300 movs r3, #0 800293c: 73fb strb r3, [r7, #15] } return bitstatus; 800293e: 7bfb ldrb r3, [r7, #15] } 8002940: 4618 mov r0, r3 8002942: 3714 adds r7, #20 8002944: 46bd mov sp, r7 8002946: f85d 7b04 ldr.w r7, [sp], #4 800294a: 4770 bx lr 0800294c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800294c: b480 push {r7} 800294e: b083 sub sp, #12 8002950: af00 add r7, sp, #0 8002952: 6078 str r0, [r7, #4] 8002954: 460b mov r3, r1 8002956: 807b strh r3, [r7, #2] 8002958: 4613 mov r3, r2 800295a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 800295c: 787b ldrb r3, [r7, #1] 800295e: 2b00 cmp r3, #0 8002960: d003 beq.n 800296a { GPIOx->BSRR = GPIO_Pin; 8002962: 887a ldrh r2, [r7, #2] 8002964: 687b ldr r3, [r7, #4] 8002966: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002968: e003 b.n 8002972 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 800296a: 887b ldrh r3, [r7, #2] 800296c: 041a lsls r2, r3, #16 800296e: 687b ldr r3, [r7, #4] 8002970: 619a str r2, [r3, #24] } 8002972: bf00 nop 8002974: 370c adds r7, #12 8002976: 46bd mov sp, r7 8002978: f85d 7b04 ldr.w r7, [sp], #4 800297c: 4770 bx lr ... 08002980 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8002980: b580 push {r7, lr} 8002982: b084 sub sp, #16 8002984: af00 add r7, sp, #0 8002986: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8002988: 687b ldr r3, [r7, #4] 800298a: 2b00 cmp r3, #0 800298c: d101 bne.n 8002992 { return HAL_ERROR; 800298e: 2301 movs r3, #1 8002990: e12b b.n 8002bea assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8002992: 687b ldr r3, [r7, #4] 8002994: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8002998: b2db uxtb r3, r3 800299a: 2b00 cmp r3, #0 800299c: d106 bne.n 80029ac { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 800299e: 687b ldr r3, [r7, #4] 80029a0: 2200 movs r2, #0 80029a2: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 80029a6: 6878 ldr r0, [r7, #4] 80029a8: f7fd fef6 bl 8000798 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 80029ac: 687b ldr r3, [r7, #4] 80029ae: 2224 movs r2, #36 @ 0x24 80029b0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 80029b4: 687b ldr r3, [r7, #4] 80029b6: 681b ldr r3, [r3, #0] 80029b8: 681a ldr r2, [r3, #0] 80029ba: 687b ldr r3, [r7, #4] 80029bc: 681b ldr r3, [r3, #0] 80029be: f022 0201 bic.w r2, r2, #1 80029c2: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 80029c4: 687b ldr r3, [r7, #4] 80029c6: 681b ldr r3, [r3, #0] 80029c8: 681a ldr r2, [r3, #0] 80029ca: 687b ldr r3, [r7, #4] 80029cc: 681b ldr r3, [r3, #0] 80029ce: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80029d2: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 80029d4: 687b ldr r3, [r7, #4] 80029d6: 681b ldr r3, [r3, #0] 80029d8: 681a ldr r2, [r3, #0] 80029da: 687b ldr r3, [r7, #4] 80029dc: 681b ldr r3, [r3, #0] 80029de: f422 4200 bic.w r2, r2, #32768 @ 0x8000 80029e2: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 80029e4: f001 fc88 bl 80042f8 80029e8: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 80029ea: 687b ldr r3, [r7, #4] 80029ec: 685b ldr r3, [r3, #4] 80029ee: 4a81 ldr r2, [pc, #516] @ (8002bf4 ) 80029f0: 4293 cmp r3, r2 80029f2: d807 bhi.n 8002a04 80029f4: 68fb ldr r3, [r7, #12] 80029f6: 4a80 ldr r2, [pc, #512] @ (8002bf8 ) 80029f8: 4293 cmp r3, r2 80029fa: bf94 ite ls 80029fc: 2301 movls r3, #1 80029fe: 2300 movhi r3, #0 8002a00: b2db uxtb r3, r3 8002a02: e006 b.n 8002a12 8002a04: 68fb ldr r3, [r7, #12] 8002a06: 4a7d ldr r2, [pc, #500] @ (8002bfc ) 8002a08: 4293 cmp r3, r2 8002a0a: bf94 ite ls 8002a0c: 2301 movls r3, #1 8002a0e: 2300 movhi r3, #0 8002a10: b2db uxtb r3, r3 8002a12: 2b00 cmp r3, #0 8002a14: d001 beq.n 8002a1a { return HAL_ERROR; 8002a16: 2301 movs r3, #1 8002a18: e0e7 b.n 8002bea } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8002a1a: 68fb ldr r3, [r7, #12] 8002a1c: 4a78 ldr r2, [pc, #480] @ (8002c00 ) 8002a1e: fba2 2303 umull r2, r3, r2, r3 8002a22: 0c9b lsrs r3, r3, #18 8002a24: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8002a26: 687b ldr r3, [r7, #4] 8002a28: 681b ldr r3, [r3, #0] 8002a2a: 685b ldr r3, [r3, #4] 8002a2c: f023 013f bic.w r1, r3, #63 @ 0x3f 8002a30: 687b ldr r3, [r7, #4] 8002a32: 681b ldr r3, [r3, #0] 8002a34: 68ba ldr r2, [r7, #8] 8002a36: 430a orrs r2, r1 8002a38: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8002a3a: 687b ldr r3, [r7, #4] 8002a3c: 681b ldr r3, [r3, #0] 8002a3e: 6a1b ldr r3, [r3, #32] 8002a40: f023 013f bic.w r1, r3, #63 @ 0x3f 8002a44: 687b ldr r3, [r7, #4] 8002a46: 685b ldr r3, [r3, #4] 8002a48: 4a6a ldr r2, [pc, #424] @ (8002bf4 ) 8002a4a: 4293 cmp r3, r2 8002a4c: d802 bhi.n 8002a54 8002a4e: 68bb ldr r3, [r7, #8] 8002a50: 3301 adds r3, #1 8002a52: e009 b.n 8002a68 8002a54: 68bb ldr r3, [r7, #8] 8002a56: f44f 7296 mov.w r2, #300 @ 0x12c 8002a5a: fb02 f303 mul.w r3, r2, r3 8002a5e: 4a69 ldr r2, [pc, #420] @ (8002c04 ) 8002a60: fba2 2303 umull r2, r3, r2, r3 8002a64: 099b lsrs r3, r3, #6 8002a66: 3301 adds r3, #1 8002a68: 687a ldr r2, [r7, #4] 8002a6a: 6812 ldr r2, [r2, #0] 8002a6c: 430b orrs r3, r1 8002a6e: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8002a70: 687b ldr r3, [r7, #4] 8002a72: 681b ldr r3, [r3, #0] 8002a74: 69db ldr r3, [r3, #28] 8002a76: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8002a7a: f022 02ff bic.w r2, r2, #255 @ 0xff 8002a7e: 687b ldr r3, [r7, #4] 8002a80: 685b ldr r3, [r3, #4] 8002a82: 495c ldr r1, [pc, #368] @ (8002bf4 ) 8002a84: 428b cmp r3, r1 8002a86: d819 bhi.n 8002abc 8002a88: 68fb ldr r3, [r7, #12] 8002a8a: 1e59 subs r1, r3, #1 8002a8c: 687b ldr r3, [r7, #4] 8002a8e: 685b ldr r3, [r3, #4] 8002a90: 005b lsls r3, r3, #1 8002a92: fbb1 f3f3 udiv r3, r1, r3 8002a96: 1c59 adds r1, r3, #1 8002a98: f640 73fc movw r3, #4092 @ 0xffc 8002a9c: 400b ands r3, r1 8002a9e: 2b00 cmp r3, #0 8002aa0: d00a beq.n 8002ab8 8002aa2: 68fb ldr r3, [r7, #12] 8002aa4: 1e59 subs r1, r3, #1 8002aa6: 687b ldr r3, [r7, #4] 8002aa8: 685b ldr r3, [r3, #4] 8002aaa: 005b lsls r3, r3, #1 8002aac: fbb1 f3f3 udiv r3, r1, r3 8002ab0: 3301 adds r3, #1 8002ab2: f3c3 030b ubfx r3, r3, #0, #12 8002ab6: e051 b.n 8002b5c 8002ab8: 2304 movs r3, #4 8002aba: e04f b.n 8002b5c 8002abc: 687b ldr r3, [r7, #4] 8002abe: 689b ldr r3, [r3, #8] 8002ac0: 2b00 cmp r3, #0 8002ac2: d111 bne.n 8002ae8 8002ac4: 68fb ldr r3, [r7, #12] 8002ac6: 1e58 subs r0, r3, #1 8002ac8: 687b ldr r3, [r7, #4] 8002aca: 6859 ldr r1, [r3, #4] 8002acc: 460b mov r3, r1 8002ace: 005b lsls r3, r3, #1 8002ad0: 440b add r3, r1 8002ad2: fbb0 f3f3 udiv r3, r0, r3 8002ad6: 3301 adds r3, #1 8002ad8: f3c3 030b ubfx r3, r3, #0, #12 8002adc: 2b00 cmp r3, #0 8002ade: bf0c ite eq 8002ae0: 2301 moveq r3, #1 8002ae2: 2300 movne r3, #0 8002ae4: b2db uxtb r3, r3 8002ae6: e012 b.n 8002b0e 8002ae8: 68fb ldr r3, [r7, #12] 8002aea: 1e58 subs r0, r3, #1 8002aec: 687b ldr r3, [r7, #4] 8002aee: 6859 ldr r1, [r3, #4] 8002af0: 460b mov r3, r1 8002af2: 009b lsls r3, r3, #2 8002af4: 440b add r3, r1 8002af6: 0099 lsls r1, r3, #2 8002af8: 440b add r3, r1 8002afa: fbb0 f3f3 udiv r3, r0, r3 8002afe: 3301 adds r3, #1 8002b00: f3c3 030b ubfx r3, r3, #0, #12 8002b04: 2b00 cmp r3, #0 8002b06: bf0c ite eq 8002b08: 2301 moveq r3, #1 8002b0a: 2300 movne r3, #0 8002b0c: b2db uxtb r3, r3 8002b0e: 2b00 cmp r3, #0 8002b10: d001 beq.n 8002b16 8002b12: 2301 movs r3, #1 8002b14: e022 b.n 8002b5c 8002b16: 687b ldr r3, [r7, #4] 8002b18: 689b ldr r3, [r3, #8] 8002b1a: 2b00 cmp r3, #0 8002b1c: d10e bne.n 8002b3c 8002b1e: 68fb ldr r3, [r7, #12] 8002b20: 1e58 subs r0, r3, #1 8002b22: 687b ldr r3, [r7, #4] 8002b24: 6859 ldr r1, [r3, #4] 8002b26: 460b mov r3, r1 8002b28: 005b lsls r3, r3, #1 8002b2a: 440b add r3, r1 8002b2c: fbb0 f3f3 udiv r3, r0, r3 8002b30: 3301 adds r3, #1 8002b32: f3c3 030b ubfx r3, r3, #0, #12 8002b36: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002b3a: e00f b.n 8002b5c 8002b3c: 68fb ldr r3, [r7, #12] 8002b3e: 1e58 subs r0, r3, #1 8002b40: 687b ldr r3, [r7, #4] 8002b42: 6859 ldr r1, [r3, #4] 8002b44: 460b mov r3, r1 8002b46: 009b lsls r3, r3, #2 8002b48: 440b add r3, r1 8002b4a: 0099 lsls r1, r3, #2 8002b4c: 440b add r3, r1 8002b4e: fbb0 f3f3 udiv r3, r0, r3 8002b52: 3301 adds r3, #1 8002b54: f3c3 030b ubfx r3, r3, #0, #12 8002b58: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8002b5c: 6879 ldr r1, [r7, #4] 8002b5e: 6809 ldr r1, [r1, #0] 8002b60: 4313 orrs r3, r2 8002b62: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002b64: 687b ldr r3, [r7, #4] 8002b66: 681b ldr r3, [r3, #0] 8002b68: 681b ldr r3, [r3, #0] 8002b6a: f023 01c0 bic.w r1, r3, #192 @ 0xc0 8002b6e: 687b ldr r3, [r7, #4] 8002b70: 69da ldr r2, [r3, #28] 8002b72: 687b ldr r3, [r7, #4] 8002b74: 6a1b ldr r3, [r3, #32] 8002b76: 431a orrs r2, r3 8002b78: 687b ldr r3, [r7, #4] 8002b7a: 681b ldr r3, [r3, #0] 8002b7c: 430a orrs r2, r1 8002b7e: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002b80: 687b ldr r3, [r7, #4] 8002b82: 681b ldr r3, [r3, #0] 8002b84: 689b ldr r3, [r3, #8] 8002b86: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8002b8a: f023 03ff bic.w r3, r3, #255 @ 0xff 8002b8e: 687a ldr r2, [r7, #4] 8002b90: 6911 ldr r1, [r2, #16] 8002b92: 687a ldr r2, [r7, #4] 8002b94: 68d2 ldr r2, [r2, #12] 8002b96: 4311 orrs r1, r2 8002b98: 687a ldr r2, [r7, #4] 8002b9a: 6812 ldr r2, [r2, #0] 8002b9c: 430b orrs r3, r1 8002b9e: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8002ba0: 687b ldr r3, [r7, #4] 8002ba2: 681b ldr r3, [r3, #0] 8002ba4: 68db ldr r3, [r3, #12] 8002ba6: f023 01ff bic.w r1, r3, #255 @ 0xff 8002baa: 687b ldr r3, [r7, #4] 8002bac: 695a ldr r2, [r3, #20] 8002bae: 687b ldr r3, [r7, #4] 8002bb0: 699b ldr r3, [r3, #24] 8002bb2: 431a orrs r2, r3 8002bb4: 687b ldr r3, [r7, #4] 8002bb6: 681b ldr r3, [r3, #0] 8002bb8: 430a orrs r2, r1 8002bba: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002bbc: 687b ldr r3, [r7, #4] 8002bbe: 681b ldr r3, [r3, #0] 8002bc0: 681a ldr r2, [r3, #0] 8002bc2: 687b ldr r3, [r7, #4] 8002bc4: 681b ldr r3, [r3, #0] 8002bc6: f042 0201 orr.w r2, r2, #1 8002bca: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002bcc: 687b ldr r3, [r7, #4] 8002bce: 2200 movs r2, #0 8002bd0: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8002bd2: 687b ldr r3, [r7, #4] 8002bd4: 2220 movs r2, #32 8002bd6: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8002bda: 687b ldr r3, [r7, #4] 8002bdc: 2200 movs r2, #0 8002bde: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002be0: 687b ldr r3, [r7, #4] 8002be2: 2200 movs r2, #0 8002be4: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8002be8: 2300 movs r3, #0 } 8002bea: 4618 mov r0, r3 8002bec: 3710 adds r7, #16 8002bee: 46bd mov sp, r7 8002bf0: bd80 pop {r7, pc} 8002bf2: bf00 nop 8002bf4: 000186a0 .word 0x000186a0 8002bf8: 001e847f .word 0x001e847f 8002bfc: 003d08ff .word 0x003d08ff 8002c00: 431bde83 .word 0x431bde83 8002c04: 10624dd3 .word 0x10624dd3 08002c08 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8002c08: b580 push {r7, lr} 8002c0a: b086 sub sp, #24 8002c0c: af02 add r7, sp, #8 8002c0e: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8002c10: 687b ldr r3, [r7, #4] 8002c12: 2b00 cmp r3, #0 8002c14: d101 bne.n 8002c1a { return HAL_ERROR; 8002c16: 2301 movs r3, #1 8002c18: e108 b.n 8002e2c /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); #if defined (USB_OTG_FS) USBx = hpcd->Instance; 8002c1a: 687b ldr r3, [r7, #4] 8002c1c: 681b ldr r3, [r3, #0] 8002c1e: 60bb str r3, [r7, #8] #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) 8002c20: 687b ldr r3, [r7, #4] 8002c22: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 8002c26: b2db uxtb r3, r3 8002c28: 2b00 cmp r3, #0 8002c2a: d106 bne.n 8002c3a { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8002c2c: 687b ldr r3, [r7, #4] 8002c2e: 2200 movs r2, #0 8002c30: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8002c34: 6878 ldr r0, [r7, #4] 8002c36: f007 fbb1 bl 800a39c #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8002c3a: 687b ldr r3, [r7, #4] 8002c3c: 2203 movs r2, #3 8002c3e: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ if (USBx == USB_OTG_FS) 8002c42: 68bb ldr r3, [r7, #8] 8002c44: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002c48: d102 bne.n 8002c50 { hpcd->Init.dma_enable = 0U; 8002c4a: 687b ldr r3, [r7, #4] 8002c4c: 2200 movs r2, #0 8002c4e: 719a strb r2, [r3, #6] } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8002c50: 687b ldr r3, [r7, #4] 8002c52: 681b ldr r3, [r3, #0] 8002c54: 4618 mov r0, r3 8002c56: f004 faa6 bl 80071a6 /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002c5a: 687b ldr r3, [r7, #4] 8002c5c: 6818 ldr r0, [r3, #0] 8002c5e: 687b ldr r3, [r7, #4] 8002c60: 7c1a ldrb r2, [r3, #16] 8002c62: f88d 2000 strb.w r2, [sp] 8002c66: 3304 adds r3, #4 8002c68: cb0e ldmia r3, {r1, r2, r3} 8002c6a: f004 f985 bl 8006f78 8002c6e: 4603 mov r3, r0 8002c70: 2b00 cmp r3, #0 8002c72: d005 beq.n 8002c80 { hpcd->State = HAL_PCD_STATE_ERROR; 8002c74: 687b ldr r3, [r7, #4] 8002c76: 2202 movs r2, #2 8002c78: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002c7c: 2301 movs r3, #1 8002c7e: e0d5 b.n 8002e2c } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 8002c80: 687b ldr r3, [r7, #4] 8002c82: 681b ldr r3, [r3, #0] 8002c84: 2100 movs r1, #0 8002c86: 4618 mov r0, r3 8002c88: f004 fa9e bl 80071c8 8002c8c: 4603 mov r3, r0 8002c8e: 2b00 cmp r3, #0 8002c90: d005 beq.n 8002c9e { hpcd->State = HAL_PCD_STATE_ERROR; 8002c92: 687b ldr r3, [r7, #4] 8002c94: 2202 movs r2, #2 8002c96: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002c9a: 2301 movs r3, #1 8002c9c: e0c6 b.n 8002e2c } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002c9e: 2300 movs r3, #0 8002ca0: 73fb strb r3, [r7, #15] 8002ca2: e04a b.n 8002d3a { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8002ca4: 7bfa ldrb r2, [r7, #15] 8002ca6: 6879 ldr r1, [r7, #4] 8002ca8: 4613 mov r3, r2 8002caa: 00db lsls r3, r3, #3 8002cac: 4413 add r3, r2 8002cae: 009b lsls r3, r3, #2 8002cb0: 440b add r3, r1 8002cb2: 3315 adds r3, #21 8002cb4: 2201 movs r2, #1 8002cb6: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8002cb8: 7bfa ldrb r2, [r7, #15] 8002cba: 6879 ldr r1, [r7, #4] 8002cbc: 4613 mov r3, r2 8002cbe: 00db lsls r3, r3, #3 8002cc0: 4413 add r3, r2 8002cc2: 009b lsls r3, r3, #2 8002cc4: 440b add r3, r1 8002cc6: 3314 adds r3, #20 8002cc8: 7bfa ldrb r2, [r7, #15] 8002cca: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8002ccc: 7bfa ldrb r2, [r7, #15] 8002cce: 7bfb ldrb r3, [r7, #15] 8002cd0: b298 uxth r0, r3 8002cd2: 6879 ldr r1, [r7, #4] 8002cd4: 4613 mov r3, r2 8002cd6: 00db lsls r3, r3, #3 8002cd8: 4413 add r3, r2 8002cda: 009b lsls r3, r3, #2 8002cdc: 440b add r3, r1 8002cde: 332e adds r3, #46 @ 0x2e 8002ce0: 4602 mov r2, r0 8002ce2: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8002ce4: 7bfa ldrb r2, [r7, #15] 8002ce6: 6879 ldr r1, [r7, #4] 8002ce8: 4613 mov r3, r2 8002cea: 00db lsls r3, r3, #3 8002cec: 4413 add r3, r2 8002cee: 009b lsls r3, r3, #2 8002cf0: 440b add r3, r1 8002cf2: 3318 adds r3, #24 8002cf4: 2200 movs r2, #0 8002cf6: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8002cf8: 7bfa ldrb r2, [r7, #15] 8002cfa: 6879 ldr r1, [r7, #4] 8002cfc: 4613 mov r3, r2 8002cfe: 00db lsls r3, r3, #3 8002d00: 4413 add r3, r2 8002d02: 009b lsls r3, r3, #2 8002d04: 440b add r3, r1 8002d06: 331c adds r3, #28 8002d08: 2200 movs r2, #0 8002d0a: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8002d0c: 7bfa ldrb r2, [r7, #15] 8002d0e: 6879 ldr r1, [r7, #4] 8002d10: 4613 mov r3, r2 8002d12: 00db lsls r3, r3, #3 8002d14: 4413 add r3, r2 8002d16: 009b lsls r3, r3, #2 8002d18: 440b add r3, r1 8002d1a: 3320 adds r3, #32 8002d1c: 2200 movs r2, #0 8002d1e: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8002d20: 7bfa ldrb r2, [r7, #15] 8002d22: 6879 ldr r1, [r7, #4] 8002d24: 4613 mov r3, r2 8002d26: 00db lsls r3, r3, #3 8002d28: 4413 add r3, r2 8002d2a: 009b lsls r3, r3, #2 8002d2c: 440b add r3, r1 8002d2e: 3324 adds r3, #36 @ 0x24 8002d30: 2200 movs r2, #0 8002d32: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002d34: 7bfb ldrb r3, [r7, #15] 8002d36: 3301 adds r3, #1 8002d38: 73fb strb r3, [r7, #15] 8002d3a: 687b ldr r3, [r7, #4] 8002d3c: 791b ldrb r3, [r3, #4] 8002d3e: 7bfa ldrb r2, [r7, #15] 8002d40: 429a cmp r2, r3 8002d42: d3af bcc.n 8002ca4 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002d44: 2300 movs r3, #0 8002d46: 73fb strb r3, [r7, #15] 8002d48: e044 b.n 8002dd4 { hpcd->OUT_ep[i].is_in = 0U; 8002d4a: 7bfa ldrb r2, [r7, #15] 8002d4c: 6879 ldr r1, [r7, #4] 8002d4e: 4613 mov r3, r2 8002d50: 00db lsls r3, r3, #3 8002d52: 4413 add r3, r2 8002d54: 009b lsls r3, r3, #2 8002d56: 440b add r3, r1 8002d58: f203 2355 addw r3, r3, #597 @ 0x255 8002d5c: 2200 movs r2, #0 8002d5e: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8002d60: 7bfa ldrb r2, [r7, #15] 8002d62: 6879 ldr r1, [r7, #4] 8002d64: 4613 mov r3, r2 8002d66: 00db lsls r3, r3, #3 8002d68: 4413 add r3, r2 8002d6a: 009b lsls r3, r3, #2 8002d6c: 440b add r3, r1 8002d6e: f503 7315 add.w r3, r3, #596 @ 0x254 8002d72: 7bfa ldrb r2, [r7, #15] 8002d74: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8002d76: 7bfa ldrb r2, [r7, #15] 8002d78: 6879 ldr r1, [r7, #4] 8002d7a: 4613 mov r3, r2 8002d7c: 00db lsls r3, r3, #3 8002d7e: 4413 add r3, r2 8002d80: 009b lsls r3, r3, #2 8002d82: 440b add r3, r1 8002d84: f503 7316 add.w r3, r3, #600 @ 0x258 8002d88: 2200 movs r2, #0 8002d8a: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8002d8c: 7bfa ldrb r2, [r7, #15] 8002d8e: 6879 ldr r1, [r7, #4] 8002d90: 4613 mov r3, r2 8002d92: 00db lsls r3, r3, #3 8002d94: 4413 add r3, r2 8002d96: 009b lsls r3, r3, #2 8002d98: 440b add r3, r1 8002d9a: f503 7317 add.w r3, r3, #604 @ 0x25c 8002d9e: 2200 movs r2, #0 8002da0: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 8002da2: 7bfa ldrb r2, [r7, #15] 8002da4: 6879 ldr r1, [r7, #4] 8002da6: 4613 mov r3, r2 8002da8: 00db lsls r3, r3, #3 8002daa: 4413 add r3, r2 8002dac: 009b lsls r3, r3, #2 8002dae: 440b add r3, r1 8002db0: f503 7318 add.w r3, r3, #608 @ 0x260 8002db4: 2200 movs r2, #0 8002db6: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8002db8: 7bfa ldrb r2, [r7, #15] 8002dba: 6879 ldr r1, [r7, #4] 8002dbc: 4613 mov r3, r2 8002dbe: 00db lsls r3, r3, #3 8002dc0: 4413 add r3, r2 8002dc2: 009b lsls r3, r3, #2 8002dc4: 440b add r3, r1 8002dc6: f503 7319 add.w r3, r3, #612 @ 0x264 8002dca: 2200 movs r2, #0 8002dcc: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002dce: 7bfb ldrb r3, [r7, #15] 8002dd0: 3301 adds r3, #1 8002dd2: 73fb strb r3, [r7, #15] 8002dd4: 687b ldr r3, [r7, #4] 8002dd6: 791b ldrb r3, [r3, #4] 8002dd8: 7bfa ldrb r2, [r7, #15] 8002dda: 429a cmp r2, r3 8002ddc: d3b5 bcc.n 8002d4a } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002dde: 687b ldr r3, [r7, #4] 8002de0: 6818 ldr r0, [r3, #0] 8002de2: 687b ldr r3, [r7, #4] 8002de4: 7c1a ldrb r2, [r3, #16] 8002de6: f88d 2000 strb.w r2, [sp] 8002dea: 3304 adds r3, #4 8002dec: cb0e ldmia r3, {r1, r2, r3} 8002dee: f004 fa37 bl 8007260 8002df2: 4603 mov r3, r0 8002df4: 2b00 cmp r3, #0 8002df6: d005 beq.n 8002e04 { hpcd->State = HAL_PCD_STATE_ERROR; 8002df8: 687b ldr r3, [r7, #4] 8002dfa: 2202 movs r2, #2 8002dfc: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002e00: 2301 movs r3, #1 8002e02: e013 b.n 8002e2c } hpcd->USB_Address = 0U; 8002e04: 687b ldr r3, [r7, #4] 8002e06: 2200 movs r2, #0 8002e08: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 8002e0a: 687b ldr r3, [r7, #4] 8002e0c: 2201 movs r2, #1 8002e0e: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8002e12: 687b ldr r3, [r7, #4] 8002e14: 7b1b ldrb r3, [r3, #12] 8002e16: 2b01 cmp r3, #1 8002e18: d102 bne.n 8002e20 { (void)HAL_PCDEx_ActivateLPM(hpcd); 8002e1a: 6878 ldr r0, [r7, #4] 8002e1c: f001 f956 bl 80040cc } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 8002e20: 687b ldr r3, [r7, #4] 8002e22: 681b ldr r3, [r3, #0] 8002e24: 4618 mov r0, r3 8002e26: f005 fa74 bl 8008312 return HAL_OK; 8002e2a: 2300 movs r3, #0 } 8002e2c: 4618 mov r0, r3 8002e2e: 3710 adds r7, #16 8002e30: 46bd mov sp, r7 8002e32: bd80 pop {r7, pc} 08002e34 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8002e34: b580 push {r7, lr} 8002e36: b084 sub sp, #16 8002e38: af00 add r7, sp, #0 8002e3a: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002e3c: 687b ldr r3, [r7, #4] 8002e3e: 681b ldr r3, [r3, #0] 8002e40: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8002e42: 687b ldr r3, [r7, #4] 8002e44: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8002e48: 2b01 cmp r3, #1 8002e4a: d101 bne.n 8002e50 8002e4c: 2302 movs r3, #2 8002e4e: e022 b.n 8002e96 8002e50: 687b ldr r3, [r7, #4] 8002e52: 2201 movs r2, #1 8002e54: f883 2494 strb.w r2, [r3, #1172] @ 0x494 if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002e58: 68fb ldr r3, [r7, #12] 8002e5a: 68db ldr r3, [r3, #12] 8002e5c: f003 0340 and.w r3, r3, #64 @ 0x40 8002e60: 2b00 cmp r3, #0 8002e62: d009 beq.n 8002e78 (hpcd->Init.battery_charging_enable == 1U)) 8002e64: 687b ldr r3, [r7, #4] 8002e66: 7b5b ldrb r3, [r3, #13] if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002e68: 2b01 cmp r3, #1 8002e6a: d105 bne.n 8002e78 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8002e6c: 68fb ldr r3, [r7, #12] 8002e6e: 6b9b ldr r3, [r3, #56] @ 0x38 8002e70: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8002e74: 68fb ldr r3, [r7, #12] 8002e76: 639a str r2, [r3, #56] @ 0x38 } __HAL_PCD_ENABLE(hpcd); 8002e78: 687b ldr r3, [r7, #4] 8002e7a: 681b ldr r3, [r3, #0] 8002e7c: 4618 mov r0, r3 8002e7e: f004 f981 bl 8007184 (void)USB_DevConnect(hpcd->Instance); 8002e82: 687b ldr r3, [r7, #4] 8002e84: 681b ldr r3, [r3, #0] 8002e86: 4618 mov r0, r3 8002e88: f005 fa22 bl 80082d0 __HAL_UNLOCK(hpcd); 8002e8c: 687b ldr r3, [r7, #4] 8002e8e: 2200 movs r2, #0 8002e90: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8002e94: 2300 movs r3, #0 } 8002e96: 4618 mov r0, r3 8002e98: 3710 adds r7, #16 8002e9a: 46bd mov sp, r7 8002e9c: bd80 pop {r7, pc} 08002e9e : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8002e9e: b590 push {r4, r7, lr} 8002ea0: b08d sub sp, #52 @ 0x34 8002ea2: af00 add r7, sp, #0 8002ea4: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002ea6: 687b ldr r3, [r7, #4] 8002ea8: 681b ldr r3, [r3, #0] 8002eaa: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8002eac: 6a3b ldr r3, [r7, #32] 8002eae: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 8002eb0: 687b ldr r3, [r7, #4] 8002eb2: 681b ldr r3, [r3, #0] 8002eb4: 4618 mov r0, r3 8002eb6: f005 fae0 bl 800847a 8002eba: 4603 mov r3, r0 8002ebc: 2b00 cmp r3, #0 8002ebe: f040 84b9 bne.w 8003834 { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 8002ec2: 687b ldr r3, [r7, #4] 8002ec4: 681b ldr r3, [r3, #0] 8002ec6: 4618 mov r0, r3 8002ec8: f005 fa44 bl 8008354 8002ecc: 4603 mov r3, r0 8002ece: 2b00 cmp r3, #0 8002ed0: f000 84af beq.w 8003832 { return; } /* store current frame number */ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; 8002ed4: 69fb ldr r3, [r7, #28] 8002ed6: f503 6300 add.w r3, r3, #2048 @ 0x800 8002eda: 689b ldr r3, [r3, #8] 8002edc: 0a1b lsrs r3, r3, #8 8002ede: f3c3 020d ubfx r2, r3, #0, #14 8002ee2: 687b ldr r3, [r7, #4] 8002ee4: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8002ee8: 687b ldr r3, [r7, #4] 8002eea: 681b ldr r3, [r3, #0] 8002eec: 4618 mov r0, r3 8002eee: f005 fa31 bl 8008354 8002ef2: 4603 mov r3, r0 8002ef4: f003 0302 and.w r3, r3, #2 8002ef8: 2b02 cmp r3, #2 8002efa: d107 bne.n 8002f0c { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8002efc: 687b ldr r3, [r7, #4] 8002efe: 681b ldr r3, [r3, #0] 8002f00: 695a ldr r2, [r3, #20] 8002f02: 687b ldr r3, [r7, #4] 8002f04: 681b ldr r3, [r3, #0] 8002f06: f002 0202 and.w r2, r2, #2 8002f0a: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8002f0c: 687b ldr r3, [r7, #4] 8002f0e: 681b ldr r3, [r3, #0] 8002f10: 4618 mov r0, r3 8002f12: f005 fa1f bl 8008354 8002f16: 4603 mov r3, r0 8002f18: f003 0310 and.w r3, r3, #16 8002f1c: 2b10 cmp r3, #16 8002f1e: d161 bne.n 8002fe4 { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002f20: 687b ldr r3, [r7, #4] 8002f22: 681b ldr r3, [r3, #0] 8002f24: 699a ldr r2, [r3, #24] 8002f26: 687b ldr r3, [r7, #4] 8002f28: 681b ldr r3, [r3, #0] 8002f2a: f022 0210 bic.w r2, r2, #16 8002f2e: 619a str r2, [r3, #24] RegVal = USBx->GRXSTSP; 8002f30: 6a3b ldr r3, [r7, #32] 8002f32: 6a1b ldr r3, [r3, #32] 8002f34: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; 8002f36: 69bb ldr r3, [r7, #24] 8002f38: f003 020f and.w r2, r3, #15 8002f3c: 4613 mov r3, r2 8002f3e: 00db lsls r3, r3, #3 8002f40: 4413 add r3, r2 8002f42: 009b lsls r3, r3, #2 8002f44: f503 7314 add.w r3, r3, #592 @ 0x250 8002f48: 687a ldr r2, [r7, #4] 8002f4a: 4413 add r3, r2 8002f4c: 3304 adds r3, #4 8002f4e: 617b str r3, [r7, #20] if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 8002f50: 69bb ldr r3, [r7, #24] 8002f52: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002f56: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8002f5a: d124 bne.n 8002fa6 { if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) 8002f5c: 69ba ldr r2, [r7, #24] 8002f5e: f647 73f0 movw r3, #32752 @ 0x7ff0 8002f62: 4013 ands r3, r2 8002f64: 2b00 cmp r3, #0 8002f66: d035 beq.n 8002fd4 { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002f68: 697b ldr r3, [r7, #20] 8002f6a: 68d9 ldr r1, [r3, #12] (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); 8002f6c: 69bb ldr r3, [r7, #24] 8002f6e: 091b lsrs r3, r3, #4 8002f70: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002f72: f3c3 030a ubfx r3, r3, #0, #11 8002f76: b29b uxth r3, r3 8002f78: 461a mov r2, r3 8002f7a: 6a38 ldr r0, [r7, #32] 8002f7c: f005 f856 bl 800802c ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002f80: 697b ldr r3, [r7, #20] 8002f82: 68da ldr r2, [r3, #12] 8002f84: 69bb ldr r3, [r7, #24] 8002f86: 091b lsrs r3, r3, #4 8002f88: f3c3 030a ubfx r3, r3, #0, #11 8002f8c: 441a add r2, r3 8002f8e: 697b ldr r3, [r7, #20] 8002f90: 60da str r2, [r3, #12] ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002f92: 697b ldr r3, [r7, #20] 8002f94: 695a ldr r2, [r3, #20] 8002f96: 69bb ldr r3, [r7, #24] 8002f98: 091b lsrs r3, r3, #4 8002f9a: f3c3 030a ubfx r3, r3, #0, #11 8002f9e: 441a add r2, r3 8002fa0: 697b ldr r3, [r7, #20] 8002fa2: 615a str r2, [r3, #20] 8002fa4: e016 b.n 8002fd4 } } else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 8002fa6: 69bb ldr r3, [r7, #24] 8002fa8: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002fac: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8002fb0: d110 bne.n 8002fd4 { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 8002fb2: 687b ldr r3, [r7, #4] 8002fb4: f203 439c addw r3, r3, #1180 @ 0x49c 8002fb8: 2208 movs r2, #8 8002fba: 4619 mov r1, r3 8002fbc: 6a38 ldr r0, [r7, #32] 8002fbe: f005 f835 bl 800802c ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002fc2: 697b ldr r3, [r7, #20] 8002fc4: 695a ldr r2, [r3, #20] 8002fc6: 69bb ldr r3, [r7, #24] 8002fc8: 091b lsrs r3, r3, #4 8002fca: f3c3 030a ubfx r3, r3, #0, #11 8002fce: 441a add r2, r3 8002fd0: 697b ldr r3, [r7, #20] 8002fd2: 615a str r2, [r3, #20] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002fd4: 687b ldr r3, [r7, #4] 8002fd6: 681b ldr r3, [r3, #0] 8002fd8: 699a ldr r2, [r3, #24] 8002fda: 687b ldr r3, [r7, #4] 8002fdc: 681b ldr r3, [r3, #0] 8002fde: f042 0210 orr.w r2, r2, #16 8002fe2: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 8002fe4: 687b ldr r3, [r7, #4] 8002fe6: 681b ldr r3, [r3, #0] 8002fe8: 4618 mov r0, r3 8002fea: f005 f9b3 bl 8008354 8002fee: 4603 mov r3, r0 8002ff0: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002ff4: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8002ff8: f040 80a7 bne.w 800314a { epnum = 0U; 8002ffc: 2300 movs r3, #0 8002ffe: 627b str r3, [r7, #36] @ 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8003000: 687b ldr r3, [r7, #4] 8003002: 681b ldr r3, [r3, #0] 8003004: 4618 mov r0, r3 8003006: f005 f9b8 bl 800837a 800300a: 62b8 str r0, [r7, #40] @ 0x28 while (ep_intr != 0U) 800300c: e099 b.n 8003142 { if ((ep_intr & 0x1U) != 0U) 800300e: 6abb ldr r3, [r7, #40] @ 0x28 8003010: f003 0301 and.w r3, r3, #1 8003014: 2b00 cmp r3, #0 8003016: f000 808e beq.w 8003136 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 800301a: 687b ldr r3, [r7, #4] 800301c: 681b ldr r3, [r3, #0] 800301e: 6a7a ldr r2, [r7, #36] @ 0x24 8003020: b2d2 uxtb r2, r2 8003022: 4611 mov r1, r2 8003024: 4618 mov r0, r3 8003026: f005 f9dc bl 80083e2 800302a: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 800302c: 693b ldr r3, [r7, #16] 800302e: f003 0301 and.w r3, r3, #1 8003032: 2b00 cmp r3, #0 8003034: d00c beq.n 8003050 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 8003036: 6a7b ldr r3, [r7, #36] @ 0x24 8003038: 015a lsls r2, r3, #5 800303a: 69fb ldr r3, [r7, #28] 800303c: 4413 add r3, r2 800303e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003042: 461a mov r2, r3 8003044: 2301 movs r3, #1 8003046: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 8003048: 6a79 ldr r1, [r7, #36] @ 0x24 800304a: 6878 ldr r0, [r7, #4] 800304c: f000 feb8 bl 8003dc0 } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 8003050: 693b ldr r3, [r7, #16] 8003052: f003 0308 and.w r3, r3, #8 8003056: 2b00 cmp r3, #0 8003058: d00c beq.n 8003074 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 800305a: 6a7b ldr r3, [r7, #36] @ 0x24 800305c: 015a lsls r2, r3, #5 800305e: 69fb ldr r3, [r7, #28] 8003060: 4413 add r3, r2 8003062: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003066: 461a mov r2, r3 8003068: 2308 movs r3, #8 800306a: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 800306c: 6a79 ldr r1, [r7, #36] @ 0x24 800306e: 6878 ldr r0, [r7, #4] 8003070: f000 ff8e bl 8003f90 } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 8003074: 693b ldr r3, [r7, #16] 8003076: f003 0310 and.w r3, r3, #16 800307a: 2b00 cmp r3, #0 800307c: d008 beq.n 8003090 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 800307e: 6a7b ldr r3, [r7, #36] @ 0x24 8003080: 015a lsls r2, r3, #5 8003082: 69fb ldr r3, [r7, #28] 8003084: 4413 add r3, r2 8003086: f503 6330 add.w r3, r3, #2816 @ 0xb00 800308a: 461a mov r2, r3 800308c: 2310 movs r3, #16 800308e: 6093 str r3, [r2, #8] } /* Clear OUT Endpoint disable interrupt */ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) 8003090: 693b ldr r3, [r7, #16] 8003092: f003 0302 and.w r3, r3, #2 8003096: 2b00 cmp r3, #0 8003098: d030 beq.n 80030fc { if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) 800309a: 6a3b ldr r3, [r7, #32] 800309c: 695b ldr r3, [r3, #20] 800309e: f003 0380 and.w r3, r3, #128 @ 0x80 80030a2: 2b80 cmp r3, #128 @ 0x80 80030a4: d109 bne.n 80030ba { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; 80030a6: 69fb ldr r3, [r7, #28] 80030a8: f503 6300 add.w r3, r3, #2048 @ 0x800 80030ac: 685b ldr r3, [r3, #4] 80030ae: 69fa ldr r2, [r7, #28] 80030b0: f502 6200 add.w r2, r2, #2048 @ 0x800 80030b4: f443 6380 orr.w r3, r3, #1024 @ 0x400 80030b8: 6053 str r3, [r2, #4] } ep = &hpcd->OUT_ep[epnum]; 80030ba: 6a7a ldr r2, [r7, #36] @ 0x24 80030bc: 4613 mov r3, r2 80030be: 00db lsls r3, r3, #3 80030c0: 4413 add r3, r2 80030c2: 009b lsls r3, r3, #2 80030c4: f503 7314 add.w r3, r3, #592 @ 0x250 80030c8: 687a ldr r2, [r7, #4] 80030ca: 4413 add r3, r2 80030cc: 3304 adds r3, #4 80030ce: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 80030d0: 697b ldr r3, [r7, #20] 80030d2: 78db ldrb r3, [r3, #3] 80030d4: 2b01 cmp r3, #1 80030d6: d108 bne.n 80030ea { ep->is_iso_incomplete = 0U; 80030d8: 697b ldr r3, [r7, #20] 80030da: 2200 movs r2, #0 80030dc: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 80030de: 6a7b ldr r3, [r7, #36] @ 0x24 80030e0: b2db uxtb r3, r3 80030e2: 4619 mov r1, r3 80030e4: 6878 ldr r0, [r7, #4] 80030e6: f007 fa75 bl 800a5d4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); 80030ea: 6a7b ldr r3, [r7, #36] @ 0x24 80030ec: 015a lsls r2, r3, #5 80030ee: 69fb ldr r3, [r7, #28] 80030f0: 4413 add r3, r2 80030f2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80030f6: 461a mov r2, r3 80030f8: 2302 movs r3, #2 80030fa: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 80030fc: 693b ldr r3, [r7, #16] 80030fe: f003 0320 and.w r3, r3, #32 8003102: 2b00 cmp r3, #0 8003104: d008 beq.n 8003118 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003106: 6a7b ldr r3, [r7, #36] @ 0x24 8003108: 015a lsls r2, r3, #5 800310a: 69fb ldr r3, [r7, #28] 800310c: 4413 add r3, r2 800310e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003112: 461a mov r2, r3 8003114: 2320 movs r3, #32 8003116: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 8003118: 693b ldr r3, [r7, #16] 800311a: f403 5300 and.w r3, r3, #8192 @ 0x2000 800311e: 2b00 cmp r3, #0 8003120: d009 beq.n 8003136 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 8003122: 6a7b ldr r3, [r7, #36] @ 0x24 8003124: 015a lsls r2, r3, #5 8003126: 69fb ldr r3, [r7, #28] 8003128: 4413 add r3, r2 800312a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800312e: 461a mov r2, r3 8003130: f44f 5300 mov.w r3, #8192 @ 0x2000 8003134: 6093 str r3, [r2, #8] } } epnum++; 8003136: 6a7b ldr r3, [r7, #36] @ 0x24 8003138: 3301 adds r3, #1 800313a: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 800313c: 6abb ldr r3, [r7, #40] @ 0x28 800313e: 085b lsrs r3, r3, #1 8003140: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 8003142: 6abb ldr r3, [r7, #40] @ 0x28 8003144: 2b00 cmp r3, #0 8003146: f47f af62 bne.w 800300e } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 800314a: 687b ldr r3, [r7, #4] 800314c: 681b ldr r3, [r3, #0] 800314e: 4618 mov r0, r3 8003150: f005 f900 bl 8008354 8003154: 4603 mov r3, r0 8003156: f403 2380 and.w r3, r3, #262144 @ 0x40000 800315a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800315e: f040 80db bne.w 8003318 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 8003162: 687b ldr r3, [r7, #4] 8003164: 681b ldr r3, [r3, #0] 8003166: 4618 mov r0, r3 8003168: f005 f921 bl 80083ae 800316c: 62b8 str r0, [r7, #40] @ 0x28 epnum = 0U; 800316e: 2300 movs r3, #0 8003170: 627b str r3, [r7, #36] @ 0x24 while (ep_intr != 0U) 8003172: e0cd b.n 8003310 { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 8003174: 6abb ldr r3, [r7, #40] @ 0x28 8003176: f003 0301 and.w r3, r3, #1 800317a: 2b00 cmp r3, #0 800317c: f000 80c2 beq.w 8003304 { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8003180: 687b ldr r3, [r7, #4] 8003182: 681b ldr r3, [r3, #0] 8003184: 6a7a ldr r2, [r7, #36] @ 0x24 8003186: b2d2 uxtb r2, r2 8003188: 4611 mov r1, r2 800318a: 4618 mov r0, r3 800318c: f005 f947 bl 800841e 8003190: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 8003192: 693b ldr r3, [r7, #16] 8003194: f003 0301 and.w r3, r3, #1 8003198: 2b00 cmp r3, #0 800319a: d057 beq.n 800324c { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 800319c: 6a7b ldr r3, [r7, #36] @ 0x24 800319e: f003 030f and.w r3, r3, #15 80031a2: 2201 movs r2, #1 80031a4: fa02 f303 lsl.w r3, r2, r3 80031a8: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 80031aa: 69fb ldr r3, [r7, #28] 80031ac: f503 6300 add.w r3, r3, #2048 @ 0x800 80031b0: 6b5a ldr r2, [r3, #52] @ 0x34 80031b2: 68fb ldr r3, [r7, #12] 80031b4: 43db mvns r3, r3 80031b6: 69f9 ldr r1, [r7, #28] 80031b8: f501 6100 add.w r1, r1, #2048 @ 0x800 80031bc: 4013 ands r3, r2 80031be: 634b str r3, [r1, #52] @ 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 80031c0: 6a7b ldr r3, [r7, #36] @ 0x24 80031c2: 015a lsls r2, r3, #5 80031c4: 69fb ldr r3, [r7, #28] 80031c6: 4413 add r3, r2 80031c8: f503 6310 add.w r3, r3, #2304 @ 0x900 80031cc: 461a mov r2, r3 80031ce: 2301 movs r3, #1 80031d0: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 80031d2: 687b ldr r3, [r7, #4] 80031d4: 799b ldrb r3, [r3, #6] 80031d6: 2b01 cmp r3, #1 80031d8: d132 bne.n 8003240 { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 80031da: 6879 ldr r1, [r7, #4] 80031dc: 6a7a ldr r2, [r7, #36] @ 0x24 80031de: 4613 mov r3, r2 80031e0: 00db lsls r3, r3, #3 80031e2: 4413 add r3, r2 80031e4: 009b lsls r3, r3, #2 80031e6: 440b add r3, r1 80031e8: 3320 adds r3, #32 80031ea: 6819 ldr r1, [r3, #0] 80031ec: 6878 ldr r0, [r7, #4] 80031ee: 6a7a ldr r2, [r7, #36] @ 0x24 80031f0: 4613 mov r3, r2 80031f2: 00db lsls r3, r3, #3 80031f4: 4413 add r3, r2 80031f6: 009b lsls r3, r3, #2 80031f8: 4403 add r3, r0 80031fa: 331c adds r3, #28 80031fc: 681b ldr r3, [r3, #0] 80031fe: 4419 add r1, r3 8003200: 6878 ldr r0, [r7, #4] 8003202: 6a7a ldr r2, [r7, #36] @ 0x24 8003204: 4613 mov r3, r2 8003206: 00db lsls r3, r3, #3 8003208: 4413 add r3, r2 800320a: 009b lsls r3, r3, #2 800320c: 4403 add r3, r0 800320e: 3320 adds r3, #32 8003210: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 8003212: 6a7b ldr r3, [r7, #36] @ 0x24 8003214: 2b00 cmp r3, #0 8003216: d113 bne.n 8003240 8003218: 6879 ldr r1, [r7, #4] 800321a: 6a7a ldr r2, [r7, #36] @ 0x24 800321c: 4613 mov r3, r2 800321e: 00db lsls r3, r3, #3 8003220: 4413 add r3, r2 8003222: 009b lsls r3, r3, #2 8003224: 440b add r3, r1 8003226: 3324 adds r3, #36 @ 0x24 8003228: 681b ldr r3, [r3, #0] 800322a: 2b00 cmp r3, #0 800322c: d108 bne.n 8003240 { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 800322e: 687b ldr r3, [r7, #4] 8003230: 6818 ldr r0, [r3, #0] 8003232: 687b ldr r3, [r7, #4] 8003234: f203 439c addw r3, r3, #1180 @ 0x49c 8003238: 461a mov r2, r3 800323a: 2101 movs r1, #1 800323c: f005 f94e bl 80084dc } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 8003240: 6a7b ldr r3, [r7, #36] @ 0x24 8003242: b2db uxtb r3, r3 8003244: 4619 mov r1, r3 8003246: 6878 ldr r0, [r7, #4] 8003248: f007 f93f bl 800a4ca #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 800324c: 693b ldr r3, [r7, #16] 800324e: f003 0308 and.w r3, r3, #8 8003252: 2b00 cmp r3, #0 8003254: d008 beq.n 8003268 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 8003256: 6a7b ldr r3, [r7, #36] @ 0x24 8003258: 015a lsls r2, r3, #5 800325a: 69fb ldr r3, [r7, #28] 800325c: 4413 add r3, r2 800325e: f503 6310 add.w r3, r3, #2304 @ 0x900 8003262: 461a mov r2, r3 8003264: 2308 movs r3, #8 8003266: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 8003268: 693b ldr r3, [r7, #16] 800326a: f003 0310 and.w r3, r3, #16 800326e: 2b00 cmp r3, #0 8003270: d008 beq.n 8003284 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 8003272: 6a7b ldr r3, [r7, #36] @ 0x24 8003274: 015a lsls r2, r3, #5 8003276: 69fb ldr r3, [r7, #28] 8003278: 4413 add r3, r2 800327a: f503 6310 add.w r3, r3, #2304 @ 0x900 800327e: 461a mov r2, r3 8003280: 2310 movs r3, #16 8003282: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 8003284: 693b ldr r3, [r7, #16] 8003286: f003 0340 and.w r3, r3, #64 @ 0x40 800328a: 2b00 cmp r3, #0 800328c: d008 beq.n 80032a0 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 800328e: 6a7b ldr r3, [r7, #36] @ 0x24 8003290: 015a lsls r2, r3, #5 8003292: 69fb ldr r3, [r7, #28] 8003294: 4413 add r3, r2 8003296: f503 6310 add.w r3, r3, #2304 @ 0x900 800329a: 461a mov r2, r3 800329c: 2340 movs r3, #64 @ 0x40 800329e: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 80032a0: 693b ldr r3, [r7, #16] 80032a2: f003 0302 and.w r3, r3, #2 80032a6: 2b00 cmp r3, #0 80032a8: d023 beq.n 80032f2 { (void)USB_FlushTxFifo(USBx, epnum); 80032aa: 6a79 ldr r1, [r7, #36] @ 0x24 80032ac: 6a38 ldr r0, [r7, #32] 80032ae: f004 f935 bl 800751c ep = &hpcd->IN_ep[epnum]; 80032b2: 6a7a ldr r2, [r7, #36] @ 0x24 80032b4: 4613 mov r3, r2 80032b6: 00db lsls r3, r3, #3 80032b8: 4413 add r3, r2 80032ba: 009b lsls r3, r3, #2 80032bc: 3310 adds r3, #16 80032be: 687a ldr r2, [r7, #4] 80032c0: 4413 add r3, r2 80032c2: 3304 adds r3, #4 80032c4: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 80032c6: 697b ldr r3, [r7, #20] 80032c8: 78db ldrb r3, [r3, #3] 80032ca: 2b01 cmp r3, #1 80032cc: d108 bne.n 80032e0 { ep->is_iso_incomplete = 0U; 80032ce: 697b ldr r3, [r7, #20] 80032d0: 2200 movs r2, #0 80032d2: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 80032d4: 6a7b ldr r3, [r7, #36] @ 0x24 80032d6: b2db uxtb r3, r3 80032d8: 4619 mov r1, r3 80032da: 6878 ldr r0, [r7, #4] 80032dc: f007 f98c bl 800a5f8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 80032e0: 6a7b ldr r3, [r7, #36] @ 0x24 80032e2: 015a lsls r2, r3, #5 80032e4: 69fb ldr r3, [r7, #28] 80032e6: 4413 add r3, r2 80032e8: f503 6310 add.w r3, r3, #2304 @ 0x900 80032ec: 461a mov r2, r3 80032ee: 2302 movs r3, #2 80032f0: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 80032f2: 693b ldr r3, [r7, #16] 80032f4: f003 0380 and.w r3, r3, #128 @ 0x80 80032f8: 2b00 cmp r3, #0 80032fa: d003 beq.n 8003304 { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 80032fc: 6a79 ldr r1, [r7, #36] @ 0x24 80032fe: 6878 ldr r0, [r7, #4] 8003300: f000 fcd2 bl 8003ca8 } } epnum++; 8003304: 6a7b ldr r3, [r7, #36] @ 0x24 8003306: 3301 adds r3, #1 8003308: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 800330a: 6abb ldr r3, [r7, #40] @ 0x28 800330c: 085b lsrs r3, r3, #1 800330e: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 8003310: 6abb ldr r3, [r7, #40] @ 0x28 8003312: 2b00 cmp r3, #0 8003314: f47f af2e bne.w 8003174 } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 8003318: 687b ldr r3, [r7, #4] 800331a: 681b ldr r3, [r3, #0] 800331c: 4618 mov r0, r3 800331e: f005 f819 bl 8008354 8003322: 4603 mov r3, r0 8003324: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8003328: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800332c: d122 bne.n 8003374 { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 800332e: 69fb ldr r3, [r7, #28] 8003330: f503 6300 add.w r3, r3, #2048 @ 0x800 8003334: 685b ldr r3, [r3, #4] 8003336: 69fa ldr r2, [r7, #28] 8003338: f502 6200 add.w r2, r2, #2048 @ 0x800 800333c: f023 0301 bic.w r3, r3, #1 8003340: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 8003342: 687b ldr r3, [r7, #4] 8003344: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003348: 2b01 cmp r3, #1 800334a: d108 bne.n 800335e { hpcd->LPM_State = LPM_L0; 800334c: 687b ldr r3, [r7, #4] 800334e: 2200 movs r2, #0 8003350: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 8003354: 2100 movs r1, #0 8003356: 6878 ldr r0, [r7, #4] 8003358: f007 faf4 bl 800a944 800335c: e002 b.n 8003364 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 800335e: 6878 ldr r0, [r7, #4] 8003360: f007 f92a bl 800a5b8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 8003364: 687b ldr r3, [r7, #4] 8003366: 681b ldr r3, [r3, #0] 8003368: 695a ldr r2, [r3, #20] 800336a: 687b ldr r3, [r7, #4] 800336c: 681b ldr r3, [r3, #0] 800336e: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 8003372: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 8003374: 687b ldr r3, [r7, #4] 8003376: 681b ldr r3, [r3, #0] 8003378: 4618 mov r0, r3 800337a: f004 ffeb bl 8008354 800337e: 4603 mov r3, r0 8003380: f403 6300 and.w r3, r3, #2048 @ 0x800 8003384: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8003388: d112 bne.n 80033b0 { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 800338a: 69fb ldr r3, [r7, #28] 800338c: f503 6300 add.w r3, r3, #2048 @ 0x800 8003390: 689b ldr r3, [r3, #8] 8003392: f003 0301 and.w r3, r3, #1 8003396: 2b01 cmp r3, #1 8003398: d102 bne.n 80033a0 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 800339a: 6878 ldr r0, [r7, #4] 800339c: f007 f8e6 bl 800a56c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 80033a0: 687b ldr r3, [r7, #4] 80033a2: 681b ldr r3, [r3, #0] 80033a4: 695a ldr r2, [r3, #20] 80033a6: 687b ldr r3, [r7, #4] 80033a8: 681b ldr r3, [r3, #0] 80033aa: f402 6200 and.w r2, r2, #2048 @ 0x800 80033ae: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 80033b0: 687b ldr r3, [r7, #4] 80033b2: 681b ldr r3, [r3, #0] 80033b4: 4618 mov r0, r3 80033b6: f004 ffcd bl 8008354 80033ba: 4603 mov r3, r0 80033bc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80033c0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80033c4: d121 bne.n 800340a { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 80033c6: 687b ldr r3, [r7, #4] 80033c8: 681b ldr r3, [r3, #0] 80033ca: 695a ldr r2, [r3, #20] 80033cc: 687b ldr r3, [r7, #4] 80033ce: 681b ldr r3, [r3, #0] 80033d0: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 80033d4: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 80033d6: 687b ldr r3, [r7, #4] 80033d8: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 80033dc: 2b00 cmp r3, #0 80033de: d111 bne.n 8003404 { hpcd->LPM_State = LPM_L1; 80033e0: 687b ldr r3, [r7, #4] 80033e2: 2201 movs r2, #1 80033e4: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 80033e8: 687b ldr r3, [r7, #4] 80033ea: 681b ldr r3, [r3, #0] 80033ec: 6d5b ldr r3, [r3, #84] @ 0x54 80033ee: 089b lsrs r3, r3, #2 80033f0: f003 020f and.w r2, r3, #15 80033f4: 687b ldr r3, [r7, #4] 80033f6: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 80033fa: 2101 movs r1, #1 80033fc: 6878 ldr r0, [r7, #4] 80033fe: f007 faa1 bl 800a944 8003402: e002 b.n 800340a else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8003404: 6878 ldr r0, [r7, #4] 8003406: f007 f8b1 bl 800a56c } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 800340a: 687b ldr r3, [r7, #4] 800340c: 681b ldr r3, [r3, #0] 800340e: 4618 mov r0, r3 8003410: f004 ffa0 bl 8008354 8003414: 4603 mov r3, r0 8003416: f403 5380 and.w r3, r3, #4096 @ 0x1000 800341a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800341e: f040 80b7 bne.w 8003590 { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 8003422: 69fb ldr r3, [r7, #28] 8003424: f503 6300 add.w r3, r3, #2048 @ 0x800 8003428: 685b ldr r3, [r3, #4] 800342a: 69fa ldr r2, [r7, #28] 800342c: f502 6200 add.w r2, r2, #2048 @ 0x800 8003430: f023 0301 bic.w r3, r3, #1 8003434: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 8003436: 687b ldr r3, [r7, #4] 8003438: 681b ldr r3, [r3, #0] 800343a: 2110 movs r1, #16 800343c: 4618 mov r0, r3 800343e: f004 f86d bl 800751c for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8003442: 2300 movs r3, #0 8003444: 62fb str r3, [r7, #44] @ 0x2c 8003446: e046 b.n 80034d6 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 8003448: 6afb ldr r3, [r7, #44] @ 0x2c 800344a: 015a lsls r2, r3, #5 800344c: 69fb ldr r3, [r7, #28] 800344e: 4413 add r3, r2 8003450: f503 6310 add.w r3, r3, #2304 @ 0x900 8003454: 461a mov r2, r3 8003456: f64f 337f movw r3, #64383 @ 0xfb7f 800345a: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 800345c: 6afb ldr r3, [r7, #44] @ 0x2c 800345e: 015a lsls r2, r3, #5 8003460: 69fb ldr r3, [r7, #28] 8003462: 4413 add r3, r2 8003464: f503 6310 add.w r3, r3, #2304 @ 0x900 8003468: 681b ldr r3, [r3, #0] 800346a: 6afa ldr r2, [r7, #44] @ 0x2c 800346c: 0151 lsls r1, r2, #5 800346e: 69fa ldr r2, [r7, #28] 8003470: 440a add r2, r1 8003472: f502 6210 add.w r2, r2, #2304 @ 0x900 8003476: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800347a: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 800347c: 6afb ldr r3, [r7, #44] @ 0x2c 800347e: 015a lsls r2, r3, #5 8003480: 69fb ldr r3, [r7, #28] 8003482: 4413 add r3, r2 8003484: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003488: 461a mov r2, r3 800348a: f64f 337f movw r3, #64383 @ 0xfb7f 800348e: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8003490: 6afb ldr r3, [r7, #44] @ 0x2c 8003492: 015a lsls r2, r3, #5 8003494: 69fb ldr r3, [r7, #28] 8003496: 4413 add r3, r2 8003498: f503 6330 add.w r3, r3, #2816 @ 0xb00 800349c: 681b ldr r3, [r3, #0] 800349e: 6afa ldr r2, [r7, #44] @ 0x2c 80034a0: 0151 lsls r1, r2, #5 80034a2: 69fa ldr r2, [r7, #28] 80034a4: 440a add r2, r1 80034a6: f502 6230 add.w r2, r2, #2816 @ 0xb00 80034aa: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80034ae: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 80034b0: 6afb ldr r3, [r7, #44] @ 0x2c 80034b2: 015a lsls r2, r3, #5 80034b4: 69fb ldr r3, [r7, #28] 80034b6: 4413 add r3, r2 80034b8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80034bc: 681b ldr r3, [r3, #0] 80034be: 6afa ldr r2, [r7, #44] @ 0x2c 80034c0: 0151 lsls r1, r2, #5 80034c2: 69fa ldr r2, [r7, #28] 80034c4: 440a add r2, r1 80034c6: f502 6230 add.w r2, r2, #2816 @ 0xb00 80034ca: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80034ce: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80034d0: 6afb ldr r3, [r7, #44] @ 0x2c 80034d2: 3301 adds r3, #1 80034d4: 62fb str r3, [r7, #44] @ 0x2c 80034d6: 687b ldr r3, [r7, #4] 80034d8: 791b ldrb r3, [r3, #4] 80034da: 461a mov r2, r3 80034dc: 6afb ldr r3, [r7, #44] @ 0x2c 80034de: 4293 cmp r3, r2 80034e0: d3b2 bcc.n 8003448 } USBx_DEVICE->DAINTMSK |= 0x10001U; 80034e2: 69fb ldr r3, [r7, #28] 80034e4: f503 6300 add.w r3, r3, #2048 @ 0x800 80034e8: 69db ldr r3, [r3, #28] 80034ea: 69fa ldr r2, [r7, #28] 80034ec: f502 6200 add.w r2, r2, #2048 @ 0x800 80034f0: f043 1301 orr.w r3, r3, #65537 @ 0x10001 80034f4: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 80034f6: 687b ldr r3, [r7, #4] 80034f8: 7bdb ldrb r3, [r3, #15] 80034fa: 2b00 cmp r3, #0 80034fc: d016 beq.n 800352c { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 80034fe: 69fb ldr r3, [r7, #28] 8003500: f503 6300 add.w r3, r3, #2048 @ 0x800 8003504: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8003508: 69fa ldr r2, [r7, #28] 800350a: f502 6200 add.w r2, r2, #2048 @ 0x800 800350e: f043 030b orr.w r3, r3, #11 8003512: f8c2 3084 str.w r3, [r2, #132] @ 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 8003516: 69fb ldr r3, [r7, #28] 8003518: f503 6300 add.w r3, r3, #2048 @ 0x800 800351c: 6c5b ldr r3, [r3, #68] @ 0x44 800351e: 69fa ldr r2, [r7, #28] 8003520: f502 6200 add.w r2, r2, #2048 @ 0x800 8003524: f043 030b orr.w r3, r3, #11 8003528: 6453 str r3, [r2, #68] @ 0x44 800352a: e015 b.n 8003558 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 800352c: 69fb ldr r3, [r7, #28] 800352e: f503 6300 add.w r3, r3, #2048 @ 0x800 8003532: 695b ldr r3, [r3, #20] 8003534: 69fa ldr r2, [r7, #28] 8003536: f502 6200 add.w r2, r2, #2048 @ 0x800 800353a: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800353e: f043 032b orr.w r3, r3, #43 @ 0x2b 8003542: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 8003544: 69fb ldr r3, [r7, #28] 8003546: f503 6300 add.w r3, r3, #2048 @ 0x800 800354a: 691b ldr r3, [r3, #16] 800354c: 69fa ldr r2, [r7, #28] 800354e: f502 6200 add.w r2, r2, #2048 @ 0x800 8003552: f043 030b orr.w r3, r3, #11 8003556: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8003558: 69fb ldr r3, [r7, #28] 800355a: f503 6300 add.w r3, r3, #2048 @ 0x800 800355e: 681b ldr r3, [r3, #0] 8003560: 69fa ldr r2, [r7, #28] 8003562: f502 6200 add.w r2, r2, #2048 @ 0x800 8003566: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 800356a: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 800356c: 687b ldr r3, [r7, #4] 800356e: 6818 ldr r0, [r3, #0] 8003570: 687b ldr r3, [r7, #4] 8003572: 7999 ldrb r1, [r3, #6] (uint8_t *)hpcd->Setup); 8003574: 687b ldr r3, [r7, #4] 8003576: f203 439c addw r3, r3, #1180 @ 0x49c (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 800357a: 461a mov r2, r3 800357c: f004 ffae bl 80084dc __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 8003580: 687b ldr r3, [r7, #4] 8003582: 681b ldr r3, [r3, #0] 8003584: 695a ldr r2, [r3, #20] 8003586: 687b ldr r3, [r7, #4] 8003588: 681b ldr r3, [r3, #0] 800358a: f402 5280 and.w r2, r2, #4096 @ 0x1000 800358e: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 8003590: 687b ldr r3, [r7, #4] 8003592: 681b ldr r3, [r3, #0] 8003594: 4618 mov r0, r3 8003596: f004 fedd bl 8008354 800359a: 4603 mov r3, r0 800359c: f403 5300 and.w r3, r3, #8192 @ 0x2000 80035a0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80035a4: d123 bne.n 80035ee { (void)USB_ActivateSetup(hpcd->Instance); 80035a6: 687b ldr r3, [r7, #4] 80035a8: 681b ldr r3, [r3, #0] 80035aa: 4618 mov r0, r3 80035ac: f004 ff73 bl 8008496 hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 80035b0: 687b ldr r3, [r7, #4] 80035b2: 681b ldr r3, [r3, #0] 80035b4: 4618 mov r0, r3 80035b6: f004 f82a bl 800760e 80035ba: 4603 mov r3, r0 80035bc: 461a mov r2, r3 80035be: 687b ldr r3, [r7, #4] 80035c0: 71da strb r2, [r3, #7] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 80035c2: 687b ldr r3, [r7, #4] 80035c4: 681c ldr r4, [r3, #0] 80035c6: f000 fe8b bl 80042e0 80035ca: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 80035cc: 687b ldr r3, [r7, #4] 80035ce: 79db ldrb r3, [r3, #7] (void)USB_SetTurnaroundTime(hpcd->Instance, 80035d0: 461a mov r2, r3 80035d2: 4620 mov r0, r4 80035d4: f003 fd34 bl 8007040 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 80035d8: 6878 ldr r0, [r7, #4] 80035da: f006 ff9e bl 800a51a #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 80035de: 687b ldr r3, [r7, #4] 80035e0: 681b ldr r3, [r3, #0] 80035e2: 695a ldr r2, [r3, #20] 80035e4: 687b ldr r3, [r7, #4] 80035e6: 681b ldr r3, [r3, #0] 80035e8: f402 5200 and.w r2, r2, #8192 @ 0x2000 80035ec: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 80035ee: 687b ldr r3, [r7, #4] 80035f0: 681b ldr r3, [r3, #0] 80035f2: 4618 mov r0, r3 80035f4: f004 feae bl 8008354 80035f8: 4603 mov r3, r0 80035fa: f003 0308 and.w r3, r3, #8 80035fe: 2b08 cmp r3, #8 8003600: d10a bne.n 8003618 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 8003602: 6878 ldr r0, [r7, #4] 8003604: f006 ff7b bl 800a4fe #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 8003608: 687b ldr r3, [r7, #4] 800360a: 681b ldr r3, [r3, #0] 800360c: 695a ldr r2, [r3, #20] 800360e: 687b ldr r3, [r7, #4] 8003610: 681b ldr r3, [r3, #0] 8003612: f002 0208 and.w r2, r2, #8 8003616: 615a str r2, [r3, #20] } /* Handle Global OUT NAK effective Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) 8003618: 687b ldr r3, [r7, #4] 800361a: 681b ldr r3, [r3, #0] 800361c: 4618 mov r0, r3 800361e: f004 fe99 bl 8008354 8003622: 4603 mov r3, r0 8003624: f003 0380 and.w r3, r3, #128 @ 0x80 8003628: 2b80 cmp r3, #128 @ 0x80 800362a: d123 bne.n 8003674 { USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; 800362c: 6a3b ldr r3, [r7, #32] 800362e: 699b ldr r3, [r3, #24] 8003630: f023 0280 bic.w r2, r3, #128 @ 0x80 8003634: 6a3b ldr r3, [r7, #32] 8003636: 619a str r2, [r3, #24] for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003638: 2301 movs r3, #1 800363a: 627b str r3, [r7, #36] @ 0x24 800363c: e014 b.n 8003668 { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) 800363e: 6879 ldr r1, [r7, #4] 8003640: 6a7a ldr r2, [r7, #36] @ 0x24 8003642: 4613 mov r3, r2 8003644: 00db lsls r3, r3, #3 8003646: 4413 add r3, r2 8003648: 009b lsls r3, r3, #2 800364a: 440b add r3, r1 800364c: f203 2357 addw r3, r3, #599 @ 0x257 8003650: 781b ldrb r3, [r3, #0] 8003652: 2b01 cmp r3, #1 8003654: d105 bne.n 8003662 { /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); 8003656: 6a7b ldr r3, [r7, #36] @ 0x24 8003658: b2db uxtb r3, r3 800365a: 4619 mov r1, r3 800365c: 6878 ldr r0, [r7, #4] 800365e: f000 faf2 bl 8003c46 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003662: 6a7b ldr r3, [r7, #36] @ 0x24 8003664: 3301 adds r3, #1 8003666: 627b str r3, [r7, #36] @ 0x24 8003668: 687b ldr r3, [r7, #4] 800366a: 791b ldrb r3, [r3, #4] 800366c: 461a mov r2, r3 800366e: 6a7b ldr r3, [r7, #36] @ 0x24 8003670: 4293 cmp r3, r2 8003672: d3e4 bcc.n 800363e } } } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 8003674: 687b ldr r3, [r7, #4] 8003676: 681b ldr r3, [r3, #0] 8003678: 4618 mov r0, r3 800367a: f004 fe6b bl 8008354 800367e: 4603 mov r3, r0 8003680: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003684: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003688: d13c bne.n 8003704 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800368a: 2301 movs r3, #1 800368c: 627b str r3, [r7, #36] @ 0x24 800368e: e02b b.n 80036e8 { RegVal = USBx_INEP(epnum)->DIEPCTL; 8003690: 6a7b ldr r3, [r7, #36] @ 0x24 8003692: 015a lsls r2, r3, #5 8003694: 69fb ldr r3, [r7, #28] 8003696: 4413 add r3, r2 8003698: f503 6310 add.w r3, r3, #2304 @ 0x900 800369c: 681b ldr r3, [r3, #0] 800369e: 61bb str r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 80036a0: 6879 ldr r1, [r7, #4] 80036a2: 6a7a ldr r2, [r7, #36] @ 0x24 80036a4: 4613 mov r3, r2 80036a6: 00db lsls r3, r3, #3 80036a8: 4413 add r3, r2 80036aa: 009b lsls r3, r3, #2 80036ac: 440b add r3, r1 80036ae: 3318 adds r3, #24 80036b0: 781b ldrb r3, [r3, #0] 80036b2: 2b01 cmp r3, #1 80036b4: d115 bne.n 80036e2 ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) 80036b6: 69bb ldr r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 80036b8: 2b00 cmp r3, #0 80036ba: da12 bge.n 80036e2 { hpcd->IN_ep[epnum].is_iso_incomplete = 1U; 80036bc: 6879 ldr r1, [r7, #4] 80036be: 6a7a ldr r2, [r7, #36] @ 0x24 80036c0: 4613 mov r3, r2 80036c2: 00db lsls r3, r3, #3 80036c4: 4413 add r3, r2 80036c6: 009b lsls r3, r3, #2 80036c8: 440b add r3, r1 80036ca: 3317 adds r3, #23 80036cc: 2201 movs r2, #1 80036ce: 701a strb r2, [r3, #0] /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); 80036d0: 6a7b ldr r3, [r7, #36] @ 0x24 80036d2: b2db uxtb r3, r3 80036d4: f063 037f orn r3, r3, #127 @ 0x7f 80036d8: b2db uxtb r3, r3 80036da: 4619 mov r1, r3 80036dc: 6878 ldr r0, [r7, #4] 80036de: f000 fab2 bl 8003c46 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80036e2: 6a7b ldr r3, [r7, #36] @ 0x24 80036e4: 3301 adds r3, #1 80036e6: 627b str r3, [r7, #36] @ 0x24 80036e8: 687b ldr r3, [r7, #4] 80036ea: 791b ldrb r3, [r3, #4] 80036ec: 461a mov r2, r3 80036ee: 6a7b ldr r3, [r7, #36] @ 0x24 80036f0: 4293 cmp r3, r2 80036f2: d3cd bcc.n 8003690 } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 80036f4: 687b ldr r3, [r7, #4] 80036f6: 681b ldr r3, [r3, #0] 80036f8: 695a ldr r2, [r3, #20] 80036fa: 687b ldr r3, [r7, #4] 80036fc: 681b ldr r3, [r3, #0] 80036fe: f402 1280 and.w r2, r2, #1048576 @ 0x100000 8003702: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 8003704: 687b ldr r3, [r7, #4] 8003706: 681b ldr r3, [r3, #0] 8003708: 4618 mov r0, r3 800370a: f004 fe23 bl 8008354 800370e: 4603 mov r3, r0 8003710: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003714: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003718: d156 bne.n 80037c8 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800371a: 2301 movs r3, #1 800371c: 627b str r3, [r7, #36] @ 0x24 800371e: e045 b.n 80037ac { RegVal = USBx_OUTEP(epnum)->DOEPCTL; 8003720: 6a7b ldr r3, [r7, #36] @ 0x24 8003722: 015a lsls r2, r3, #5 8003724: 69fb ldr r3, [r7, #28] 8003726: 4413 add r3, r2 8003728: f503 6330 add.w r3, r3, #2816 @ 0xb00 800372c: 681b ldr r3, [r3, #0] 800372e: 61bb str r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003730: 6879 ldr r1, [r7, #4] 8003732: 6a7a ldr r2, [r7, #36] @ 0x24 8003734: 4613 mov r3, r2 8003736: 00db lsls r3, r3, #3 8003738: 4413 add r3, r2 800373a: 009b lsls r3, r3, #2 800373c: 440b add r3, r1 800373e: f503 7316 add.w r3, r3, #600 @ 0x258 8003742: 781b ldrb r3, [r3, #0] 8003744: 2b01 cmp r3, #1 8003746: d12e bne.n 80037a6 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003748: 69bb ldr r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 800374a: 2b00 cmp r3, #0 800374c: da2b bge.n 80037a6 (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) 800374e: 69bb ldr r3, [r7, #24] 8003750: 0c1a lsrs r2, r3, #16 8003752: 687b ldr r3, [r7, #4] 8003754: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 8003758: 4053 eors r3, r2 800375a: f003 0301 and.w r3, r3, #1 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 800375e: 2b00 cmp r3, #0 8003760: d121 bne.n 80037a6 { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; 8003762: 6879 ldr r1, [r7, #4] 8003764: 6a7a ldr r2, [r7, #36] @ 0x24 8003766: 4613 mov r3, r2 8003768: 00db lsls r3, r3, #3 800376a: 4413 add r3, r2 800376c: 009b lsls r3, r3, #2 800376e: 440b add r3, r1 8003770: f203 2357 addw r3, r3, #599 @ 0x257 8003774: 2201 movs r2, #1 8003776: 701a strb r2, [r3, #0] USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; 8003778: 6a3b ldr r3, [r7, #32] 800377a: 699b ldr r3, [r3, #24] 800377c: f043 0280 orr.w r2, r3, #128 @ 0x80 8003780: 6a3b ldr r3, [r7, #32] 8003782: 619a str r2, [r3, #24] if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) 8003784: 6a3b ldr r3, [r7, #32] 8003786: 695b ldr r3, [r3, #20] 8003788: f003 0380 and.w r3, r3, #128 @ 0x80 800378c: 2b00 cmp r3, #0 800378e: d10a bne.n 80037a6 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; 8003790: 69fb ldr r3, [r7, #28] 8003792: f503 6300 add.w r3, r3, #2048 @ 0x800 8003796: 685b ldr r3, [r3, #4] 8003798: 69fa ldr r2, [r7, #28] 800379a: f502 6200 add.w r2, r2, #2048 @ 0x800 800379e: f443 7300 orr.w r3, r3, #512 @ 0x200 80037a2: 6053 str r3, [r2, #4] break; 80037a4: e008 b.n 80037b8 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80037a6: 6a7b ldr r3, [r7, #36] @ 0x24 80037a8: 3301 adds r3, #1 80037aa: 627b str r3, [r7, #36] @ 0x24 80037ac: 687b ldr r3, [r7, #4] 80037ae: 791b ldrb r3, [r3, #4] 80037b0: 461a mov r2, r3 80037b2: 6a7b ldr r3, [r7, #36] @ 0x24 80037b4: 4293 cmp r3, r2 80037b6: d3b3 bcc.n 8003720 } } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 80037b8: 687b ldr r3, [r7, #4] 80037ba: 681b ldr r3, [r3, #0] 80037bc: 695a ldr r2, [r3, #20] 80037be: 687b ldr r3, [r7, #4] 80037c0: 681b ldr r3, [r3, #0] 80037c2: f402 1200 and.w r2, r2, #2097152 @ 0x200000 80037c6: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 80037c8: 687b ldr r3, [r7, #4] 80037ca: 681b ldr r3, [r3, #0] 80037cc: 4618 mov r0, r3 80037ce: f004 fdc1 bl 8008354 80037d2: 4603 mov r3, r0 80037d4: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 80037d8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80037dc: d10a bne.n 80037f4 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 80037de: 6878 ldr r0, [r7, #4] 80037e0: f006 ff1c bl 800a61c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 80037e4: 687b ldr r3, [r7, #4] 80037e6: 681b ldr r3, [r3, #0] 80037e8: 695a ldr r2, [r3, #20] 80037ea: 687b ldr r3, [r7, #4] 80037ec: 681b ldr r3, [r3, #0] 80037ee: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 80037f2: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 80037f4: 687b ldr r3, [r7, #4] 80037f6: 681b ldr r3, [r3, #0] 80037f8: 4618 mov r0, r3 80037fa: f004 fdab bl 8008354 80037fe: 4603 mov r3, r0 8003800: f003 0304 and.w r3, r3, #4 8003804: 2b04 cmp r3, #4 8003806: d115 bne.n 8003834 { RegVal = hpcd->Instance->GOTGINT; 8003808: 687b ldr r3, [r7, #4] 800380a: 681b ldr r3, [r3, #0] 800380c: 685b ldr r3, [r3, #4] 800380e: 61bb str r3, [r7, #24] if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 8003810: 69bb ldr r3, [r7, #24] 8003812: f003 0304 and.w r3, r3, #4 8003816: 2b00 cmp r3, #0 8003818: d002 beq.n 8003820 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 800381a: 6878 ldr r0, [r7, #4] 800381c: f006 ff0c bl 800a638 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= RegVal; 8003820: 687b ldr r3, [r7, #4] 8003822: 681b ldr r3, [r3, #0] 8003824: 6859 ldr r1, [r3, #4] 8003826: 687b ldr r3, [r7, #4] 8003828: 681b ldr r3, [r3, #0] 800382a: 69ba ldr r2, [r7, #24] 800382c: 430a orrs r2, r1 800382e: 605a str r2, [r3, #4] 8003830: e000 b.n 8003834 return; 8003832: bf00 nop } } } 8003834: 3734 adds r7, #52 @ 0x34 8003836: 46bd mov sp, r7 8003838: bd90 pop {r4, r7, pc} 0800383a : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 800383a: b580 push {r7, lr} 800383c: b082 sub sp, #8 800383e: af00 add r7, sp, #0 8003840: 6078 str r0, [r7, #4] 8003842: 460b mov r3, r1 8003844: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 8003846: 687b ldr r3, [r7, #4] 8003848: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 800384c: 2b01 cmp r3, #1 800384e: d101 bne.n 8003854 8003850: 2302 movs r3, #2 8003852: e012 b.n 800387a 8003854: 687b ldr r3, [r7, #4] 8003856: 2201 movs r2, #1 8003858: f883 2494 strb.w r2, [r3, #1172] @ 0x494 hpcd->USB_Address = address; 800385c: 687b ldr r3, [r7, #4] 800385e: 78fa ldrb r2, [r7, #3] 8003860: 745a strb r2, [r3, #17] (void)USB_SetDevAddress(hpcd->Instance, address); 8003862: 687b ldr r3, [r7, #4] 8003864: 681b ldr r3, [r3, #0] 8003866: 78fa ldrb r2, [r7, #3] 8003868: 4611 mov r1, r2 800386a: 4618 mov r0, r3 800386c: f004 fd0a bl 8008284 __HAL_UNLOCK(hpcd); 8003870: 687b ldr r3, [r7, #4] 8003872: 2200 movs r2, #0 8003874: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003878: 2300 movs r3, #0 } 800387a: 4618 mov r0, r3 800387c: 3708 adds r7, #8 800387e: 46bd mov sp, r7 8003880: bd80 pop {r7, pc} 08003882 : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 8003882: b580 push {r7, lr} 8003884: b084 sub sp, #16 8003886: af00 add r7, sp, #0 8003888: 6078 str r0, [r7, #4] 800388a: 4608 mov r0, r1 800388c: 4611 mov r1, r2 800388e: 461a mov r2, r3 8003890: 4603 mov r3, r0 8003892: 70fb strb r3, [r7, #3] 8003894: 460b mov r3, r1 8003896: 803b strh r3, [r7, #0] 8003898: 4613 mov r3, r2 800389a: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 800389c: 2300 movs r3, #0 800389e: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 80038a0: f997 3003 ldrsb.w r3, [r7, #3] 80038a4: 2b00 cmp r3, #0 80038a6: da0f bge.n 80038c8 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80038a8: 78fb ldrb r3, [r7, #3] 80038aa: f003 020f and.w r2, r3, #15 80038ae: 4613 mov r3, r2 80038b0: 00db lsls r3, r3, #3 80038b2: 4413 add r3, r2 80038b4: 009b lsls r3, r3, #2 80038b6: 3310 adds r3, #16 80038b8: 687a ldr r2, [r7, #4] 80038ba: 4413 add r3, r2 80038bc: 3304 adds r3, #4 80038be: 60fb str r3, [r7, #12] ep->is_in = 1U; 80038c0: 68fb ldr r3, [r7, #12] 80038c2: 2201 movs r2, #1 80038c4: 705a strb r2, [r3, #1] 80038c6: e00f b.n 80038e8 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80038c8: 78fb ldrb r3, [r7, #3] 80038ca: f003 020f and.w r2, r3, #15 80038ce: 4613 mov r3, r2 80038d0: 00db lsls r3, r3, #3 80038d2: 4413 add r3, r2 80038d4: 009b lsls r3, r3, #2 80038d6: f503 7314 add.w r3, r3, #592 @ 0x250 80038da: 687a ldr r2, [r7, #4] 80038dc: 4413 add r3, r2 80038de: 3304 adds r3, #4 80038e0: 60fb str r3, [r7, #12] ep->is_in = 0U; 80038e2: 68fb ldr r3, [r7, #12] 80038e4: 2200 movs r2, #0 80038e6: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 80038e8: 78fb ldrb r3, [r7, #3] 80038ea: f003 030f and.w r3, r3, #15 80038ee: b2da uxtb r2, r3 80038f0: 68fb ldr r3, [r7, #12] 80038f2: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 80038f4: 883b ldrh r3, [r7, #0] 80038f6: f3c3 020a ubfx r2, r3, #0, #11 80038fa: 68fb ldr r3, [r7, #12] 80038fc: 609a str r2, [r3, #8] ep->type = ep_type; 80038fe: 68fb ldr r3, [r7, #12] 8003900: 78ba ldrb r2, [r7, #2] 8003902: 711a strb r2, [r3, #4] if (ep->is_in != 0U) 8003904: 68fb ldr r3, [r7, #12] 8003906: 785b ldrb r3, [r3, #1] 8003908: 2b00 cmp r3, #0 800390a: d004 beq.n 8003916 { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 800390c: 68fb ldr r3, [r7, #12] 800390e: 781b ldrb r3, [r3, #0] 8003910: 461a mov r2, r3 8003912: 68fb ldr r3, [r7, #12] 8003914: 835a strh r2, [r3, #26] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8003916: 78bb ldrb r3, [r7, #2] 8003918: 2b02 cmp r3, #2 800391a: d102 bne.n 8003922 { ep->data_pid_start = 0U; 800391c: 68fb ldr r3, [r7, #12] 800391e: 2200 movs r2, #0 8003920: 715a strb r2, [r3, #5] } __HAL_LOCK(hpcd); 8003922: 687b ldr r3, [r7, #4] 8003924: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003928: 2b01 cmp r3, #1 800392a: d101 bne.n 8003930 800392c: 2302 movs r3, #2 800392e: e00e b.n 800394e 8003930: 687b ldr r3, [r7, #4] 8003932: 2201 movs r2, #1 8003934: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 8003938: 687b ldr r3, [r7, #4] 800393a: 681b ldr r3, [r3, #0] 800393c: 68f9 ldr r1, [r7, #12] 800393e: 4618 mov r0, r3 8003940: f003 fe8a bl 8007658 __HAL_UNLOCK(hpcd); 8003944: 687b ldr r3, [r7, #4] 8003946: 2200 movs r2, #0 8003948: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return ret; 800394c: 7afb ldrb r3, [r7, #11] } 800394e: 4618 mov r0, r3 8003950: 3710 adds r7, #16 8003952: 46bd mov sp, r7 8003954: bd80 pop {r7, pc} 08003956 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003956: b580 push {r7, lr} 8003958: b084 sub sp, #16 800395a: af00 add r7, sp, #0 800395c: 6078 str r0, [r7, #4] 800395e: 460b mov r3, r1 8003960: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8003962: f997 3003 ldrsb.w r3, [r7, #3] 8003966: 2b00 cmp r3, #0 8003968: da0f bge.n 800398a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800396a: 78fb ldrb r3, [r7, #3] 800396c: f003 020f and.w r2, r3, #15 8003970: 4613 mov r3, r2 8003972: 00db lsls r3, r3, #3 8003974: 4413 add r3, r2 8003976: 009b lsls r3, r3, #2 8003978: 3310 adds r3, #16 800397a: 687a ldr r2, [r7, #4] 800397c: 4413 add r3, r2 800397e: 3304 adds r3, #4 8003980: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003982: 68fb ldr r3, [r7, #12] 8003984: 2201 movs r2, #1 8003986: 705a strb r2, [r3, #1] 8003988: e00f b.n 80039aa } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 800398a: 78fb ldrb r3, [r7, #3] 800398c: f003 020f and.w r2, r3, #15 8003990: 4613 mov r3, r2 8003992: 00db lsls r3, r3, #3 8003994: 4413 add r3, r2 8003996: 009b lsls r3, r3, #2 8003998: f503 7314 add.w r3, r3, #592 @ 0x250 800399c: 687a ldr r2, [r7, #4] 800399e: 4413 add r3, r2 80039a0: 3304 adds r3, #4 80039a2: 60fb str r3, [r7, #12] ep->is_in = 0U; 80039a4: 68fb ldr r3, [r7, #12] 80039a6: 2200 movs r2, #0 80039a8: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 80039aa: 78fb ldrb r3, [r7, #3] 80039ac: f003 030f and.w r3, r3, #15 80039b0: b2da uxtb r2, r3 80039b2: 68fb ldr r3, [r7, #12] 80039b4: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 80039b6: 687b ldr r3, [r7, #4] 80039b8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80039bc: 2b01 cmp r3, #1 80039be: d101 bne.n 80039c4 80039c0: 2302 movs r3, #2 80039c2: e00e b.n 80039e2 80039c4: 687b ldr r3, [r7, #4] 80039c6: 2201 movs r2, #1 80039c8: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 80039cc: 687b ldr r3, [r7, #4] 80039ce: 681b ldr r3, [r3, #0] 80039d0: 68f9 ldr r1, [r7, #12] 80039d2: 4618 mov r0, r3 80039d4: f003 fec8 bl 8007768 __HAL_UNLOCK(hpcd); 80039d8: 687b ldr r3, [r7, #4] 80039da: 2200 movs r2, #0 80039dc: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 80039e0: 2300 movs r3, #0 } 80039e2: 4618 mov r0, r3 80039e4: 3710 adds r7, #16 80039e6: 46bd mov sp, r7 80039e8: bd80 pop {r7, pc} 080039ea : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 80039ea: b580 push {r7, lr} 80039ec: b086 sub sp, #24 80039ee: af00 add r7, sp, #0 80039f0: 60f8 str r0, [r7, #12] 80039f2: 607a str r2, [r7, #4] 80039f4: 603b str r3, [r7, #0] 80039f6: 460b mov r3, r1 80039f8: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80039fa: 7afb ldrb r3, [r7, #11] 80039fc: f003 020f and.w r2, r3, #15 8003a00: 4613 mov r3, r2 8003a02: 00db lsls r3, r3, #3 8003a04: 4413 add r3, r2 8003a06: 009b lsls r3, r3, #2 8003a08: f503 7314 add.w r3, r3, #592 @ 0x250 8003a0c: 68fa ldr r2, [r7, #12] 8003a0e: 4413 add r3, r2 8003a10: 3304 adds r3, #4 8003a12: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003a14: 697b ldr r3, [r7, #20] 8003a16: 687a ldr r2, [r7, #4] 8003a18: 60da str r2, [r3, #12] ep->xfer_len = len; 8003a1a: 697b ldr r3, [r7, #20] 8003a1c: 683a ldr r2, [r7, #0] 8003a1e: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003a20: 697b ldr r3, [r7, #20] 8003a22: 2200 movs r2, #0 8003a24: 615a str r2, [r3, #20] ep->is_in = 0U; 8003a26: 697b ldr r3, [r7, #20] 8003a28: 2200 movs r2, #0 8003a2a: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003a2c: 7afb ldrb r3, [r7, #11] 8003a2e: f003 030f and.w r3, r3, #15 8003a32: b2da uxtb r2, r3 8003a34: 697b ldr r3, [r7, #20] 8003a36: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003a38: 68fb ldr r3, [r7, #12] 8003a3a: 799b ldrb r3, [r3, #6] 8003a3c: 2b01 cmp r3, #1 8003a3e: d102 bne.n 8003a46 { ep->dma_addr = (uint32_t)pBuf; 8003a40: 687a ldr r2, [r7, #4] 8003a42: 697b ldr r3, [r7, #20] 8003a44: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003a46: 68fb ldr r3, [r7, #12] 8003a48: 6818 ldr r0, [r3, #0] 8003a4a: 68fb ldr r3, [r7, #12] 8003a4c: 799b ldrb r3, [r3, #6] 8003a4e: 461a mov r2, r3 8003a50: 6979 ldr r1, [r7, #20] 8003a52: f003 ff65 bl 8007920 return HAL_OK; 8003a56: 2300 movs r3, #0 } 8003a58: 4618 mov r0, r3 8003a5a: 3718 adds r7, #24 8003a5c: 46bd mov sp, r7 8003a5e: bd80 pop {r7, pc} 08003a60 : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003a60: b580 push {r7, lr} 8003a62: b086 sub sp, #24 8003a64: af00 add r7, sp, #0 8003a66: 60f8 str r0, [r7, #12] 8003a68: 607a str r2, [r7, #4] 8003a6a: 603b str r3, [r7, #0] 8003a6c: 460b mov r3, r1 8003a6e: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003a70: 7afb ldrb r3, [r7, #11] 8003a72: f003 020f and.w r2, r3, #15 8003a76: 4613 mov r3, r2 8003a78: 00db lsls r3, r3, #3 8003a7a: 4413 add r3, r2 8003a7c: 009b lsls r3, r3, #2 8003a7e: 3310 adds r3, #16 8003a80: 68fa ldr r2, [r7, #12] 8003a82: 4413 add r3, r2 8003a84: 3304 adds r3, #4 8003a86: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003a88: 697b ldr r3, [r7, #20] 8003a8a: 687a ldr r2, [r7, #4] 8003a8c: 60da str r2, [r3, #12] ep->xfer_len = len; 8003a8e: 697b ldr r3, [r7, #20] 8003a90: 683a ldr r2, [r7, #0] 8003a92: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003a94: 697b ldr r3, [r7, #20] 8003a96: 2200 movs r2, #0 8003a98: 615a str r2, [r3, #20] ep->is_in = 1U; 8003a9a: 697b ldr r3, [r7, #20] 8003a9c: 2201 movs r2, #1 8003a9e: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003aa0: 7afb ldrb r3, [r7, #11] 8003aa2: f003 030f and.w r3, r3, #15 8003aa6: b2da uxtb r2, r3 8003aa8: 697b ldr r3, [r7, #20] 8003aaa: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003aac: 68fb ldr r3, [r7, #12] 8003aae: 799b ldrb r3, [r3, #6] 8003ab0: 2b01 cmp r3, #1 8003ab2: d102 bne.n 8003aba { ep->dma_addr = (uint32_t)pBuf; 8003ab4: 687a ldr r2, [r7, #4] 8003ab6: 697b ldr r3, [r7, #20] 8003ab8: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003aba: 68fb ldr r3, [r7, #12] 8003abc: 6818 ldr r0, [r3, #0] 8003abe: 68fb ldr r3, [r7, #12] 8003ac0: 799b ldrb r3, [r3, #6] 8003ac2: 461a mov r2, r3 8003ac4: 6979 ldr r1, [r7, #20] 8003ac6: f003 ff2b bl 8007920 return HAL_OK; 8003aca: 2300 movs r3, #0 } 8003acc: 4618 mov r0, r3 8003ace: 3718 adds r7, #24 8003ad0: 46bd mov sp, r7 8003ad2: bd80 pop {r7, pc} 08003ad4 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003ad4: b580 push {r7, lr} 8003ad6: b084 sub sp, #16 8003ad8: af00 add r7, sp, #0 8003ada: 6078 str r0, [r7, #4] 8003adc: 460b mov r3, r1 8003ade: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 8003ae0: 78fb ldrb r3, [r7, #3] 8003ae2: f003 030f and.w r3, r3, #15 8003ae6: 687a ldr r2, [r7, #4] 8003ae8: 7912 ldrb r2, [r2, #4] 8003aea: 4293 cmp r3, r2 8003aec: d901 bls.n 8003af2 { return HAL_ERROR; 8003aee: 2301 movs r3, #1 8003af0: e04f b.n 8003b92 } if ((0x80U & ep_addr) == 0x80U) 8003af2: f997 3003 ldrsb.w r3, [r7, #3] 8003af6: 2b00 cmp r3, #0 8003af8: da0f bge.n 8003b1a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003afa: 78fb ldrb r3, [r7, #3] 8003afc: f003 020f and.w r2, r3, #15 8003b00: 4613 mov r3, r2 8003b02: 00db lsls r3, r3, #3 8003b04: 4413 add r3, r2 8003b06: 009b lsls r3, r3, #2 8003b08: 3310 adds r3, #16 8003b0a: 687a ldr r2, [r7, #4] 8003b0c: 4413 add r3, r2 8003b0e: 3304 adds r3, #4 8003b10: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003b12: 68fb ldr r3, [r7, #12] 8003b14: 2201 movs r2, #1 8003b16: 705a strb r2, [r3, #1] 8003b18: e00d b.n 8003b36 } else { ep = &hpcd->OUT_ep[ep_addr]; 8003b1a: 78fa ldrb r2, [r7, #3] 8003b1c: 4613 mov r3, r2 8003b1e: 00db lsls r3, r3, #3 8003b20: 4413 add r3, r2 8003b22: 009b lsls r3, r3, #2 8003b24: f503 7314 add.w r3, r3, #592 @ 0x250 8003b28: 687a ldr r2, [r7, #4] 8003b2a: 4413 add r3, r2 8003b2c: 3304 adds r3, #4 8003b2e: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003b30: 68fb ldr r3, [r7, #12] 8003b32: 2200 movs r2, #0 8003b34: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8003b36: 68fb ldr r3, [r7, #12] 8003b38: 2201 movs r2, #1 8003b3a: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003b3c: 78fb ldrb r3, [r7, #3] 8003b3e: f003 030f and.w r3, r3, #15 8003b42: b2da uxtb r2, r3 8003b44: 68fb ldr r3, [r7, #12] 8003b46: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003b48: 687b ldr r3, [r7, #4] 8003b4a: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003b4e: 2b01 cmp r3, #1 8003b50: d101 bne.n 8003b56 8003b52: 2302 movs r3, #2 8003b54: e01d b.n 8003b92 8003b56: 687b ldr r3, [r7, #4] 8003b58: 2201 movs r2, #1 8003b5a: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPSetStall(hpcd->Instance, ep); 8003b5e: 687b ldr r3, [r7, #4] 8003b60: 681b ldr r3, [r3, #0] 8003b62: 68f9 ldr r1, [r7, #12] 8003b64: 4618 mov r0, r3 8003b66: f004 fab9 bl 80080dc if ((ep_addr & EP_ADDR_MSK) == 0U) 8003b6a: 78fb ldrb r3, [r7, #3] 8003b6c: f003 030f and.w r3, r3, #15 8003b70: 2b00 cmp r3, #0 8003b72: d109 bne.n 8003b88 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8003b74: 687b ldr r3, [r7, #4] 8003b76: 6818 ldr r0, [r3, #0] 8003b78: 687b ldr r3, [r7, #4] 8003b7a: 7999 ldrb r1, [r3, #6] 8003b7c: 687b ldr r3, [r7, #4] 8003b7e: f203 439c addw r3, r3, #1180 @ 0x49c 8003b82: 461a mov r2, r3 8003b84: f004 fcaa bl 80084dc } __HAL_UNLOCK(hpcd); 8003b88: 687b ldr r3, [r7, #4] 8003b8a: 2200 movs r2, #0 8003b8c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003b90: 2300 movs r3, #0 } 8003b92: 4618 mov r0, r3 8003b94: 3710 adds r7, #16 8003b96: 46bd mov sp, r7 8003b98: bd80 pop {r7, pc} 08003b9a : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003b9a: b580 push {r7, lr} 8003b9c: b084 sub sp, #16 8003b9e: af00 add r7, sp, #0 8003ba0: 6078 str r0, [r7, #4] 8003ba2: 460b mov r3, r1 8003ba4: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8003ba6: 78fb ldrb r3, [r7, #3] 8003ba8: f003 030f and.w r3, r3, #15 8003bac: 687a ldr r2, [r7, #4] 8003bae: 7912 ldrb r2, [r2, #4] 8003bb0: 4293 cmp r3, r2 8003bb2: d901 bls.n 8003bb8 { return HAL_ERROR; 8003bb4: 2301 movs r3, #1 8003bb6: e042 b.n 8003c3e } if ((0x80U & ep_addr) == 0x80U) 8003bb8: f997 3003 ldrsb.w r3, [r7, #3] 8003bbc: 2b00 cmp r3, #0 8003bbe: da0f bge.n 8003be0 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003bc0: 78fb ldrb r3, [r7, #3] 8003bc2: f003 020f and.w r2, r3, #15 8003bc6: 4613 mov r3, r2 8003bc8: 00db lsls r3, r3, #3 8003bca: 4413 add r3, r2 8003bcc: 009b lsls r3, r3, #2 8003bce: 3310 adds r3, #16 8003bd0: 687a ldr r2, [r7, #4] 8003bd2: 4413 add r3, r2 8003bd4: 3304 adds r3, #4 8003bd6: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003bd8: 68fb ldr r3, [r7, #12] 8003bda: 2201 movs r2, #1 8003bdc: 705a strb r2, [r3, #1] 8003bde: e00f b.n 8003c00 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003be0: 78fb ldrb r3, [r7, #3] 8003be2: f003 020f and.w r2, r3, #15 8003be6: 4613 mov r3, r2 8003be8: 00db lsls r3, r3, #3 8003bea: 4413 add r3, r2 8003bec: 009b lsls r3, r3, #2 8003bee: f503 7314 add.w r3, r3, #592 @ 0x250 8003bf2: 687a ldr r2, [r7, #4] 8003bf4: 4413 add r3, r2 8003bf6: 3304 adds r3, #4 8003bf8: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003bfa: 68fb ldr r3, [r7, #12] 8003bfc: 2200 movs r2, #0 8003bfe: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8003c00: 68fb ldr r3, [r7, #12] 8003c02: 2200 movs r2, #0 8003c04: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003c06: 78fb ldrb r3, [r7, #3] 8003c08: f003 030f and.w r3, r3, #15 8003c0c: b2da uxtb r2, r3 8003c0e: 68fb ldr r3, [r7, #12] 8003c10: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003c12: 687b ldr r3, [r7, #4] 8003c14: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003c18: 2b01 cmp r3, #1 8003c1a: d101 bne.n 8003c20 8003c1c: 2302 movs r3, #2 8003c1e: e00e b.n 8003c3e 8003c20: 687b ldr r3, [r7, #4] 8003c22: 2201 movs r2, #1 8003c24: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPClearStall(hpcd->Instance, ep); 8003c28: 687b ldr r3, [r7, #4] 8003c2a: 681b ldr r3, [r3, #0] 8003c2c: 68f9 ldr r1, [r7, #12] 8003c2e: 4618 mov r0, r3 8003c30: f004 fac2 bl 80081b8 __HAL_UNLOCK(hpcd); 8003c34: 687b ldr r3, [r7, #4] 8003c36: 2200 movs r2, #0 8003c38: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003c3c: 2300 movs r3, #0 } 8003c3e: 4618 mov r0, r3 8003c40: 3710 adds r7, #16 8003c42: 46bd mov sp, r7 8003c44: bd80 pop {r7, pc} 08003c46 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003c46: b580 push {r7, lr} 8003c48: b084 sub sp, #16 8003c4a: af00 add r7, sp, #0 8003c4c: 6078 str r0, [r7, #4] 8003c4e: 460b mov r3, r1 8003c50: 70fb strb r3, [r7, #3] HAL_StatusTypeDef ret; PCD_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) 8003c52: f997 3003 ldrsb.w r3, [r7, #3] 8003c56: 2b00 cmp r3, #0 8003c58: da0c bge.n 8003c74 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003c5a: 78fb ldrb r3, [r7, #3] 8003c5c: f003 020f and.w r2, r3, #15 8003c60: 4613 mov r3, r2 8003c62: 00db lsls r3, r3, #3 8003c64: 4413 add r3, r2 8003c66: 009b lsls r3, r3, #2 8003c68: 3310 adds r3, #16 8003c6a: 687a ldr r2, [r7, #4] 8003c6c: 4413 add r3, r2 8003c6e: 3304 adds r3, #4 8003c70: 60fb str r3, [r7, #12] 8003c72: e00c b.n 8003c8e } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003c74: 78fb ldrb r3, [r7, #3] 8003c76: f003 020f and.w r2, r3, #15 8003c7a: 4613 mov r3, r2 8003c7c: 00db lsls r3, r3, #3 8003c7e: 4413 add r3, r2 8003c80: 009b lsls r3, r3, #2 8003c82: f503 7314 add.w r3, r3, #592 @ 0x250 8003c86: 687a ldr r2, [r7, #4] 8003c88: 4413 add r3, r2 8003c8a: 3304 adds r3, #4 8003c8c: 60fb str r3, [r7, #12] } /* Stop Xfer */ ret = USB_EPStopXfer(hpcd->Instance, ep); 8003c8e: 687b ldr r3, [r7, #4] 8003c90: 681b ldr r3, [r3, #0] 8003c92: 68f9 ldr r1, [r7, #12] 8003c94: 4618 mov r0, r3 8003c96: f004 f8e1 bl 8007e5c 8003c9a: 4603 mov r3, r0 8003c9c: 72fb strb r3, [r7, #11] return ret; 8003c9e: 7afb ldrb r3, [r7, #11] } 8003ca0: 4618 mov r0, r3 8003ca2: 3710 adds r7, #16 8003ca4: 46bd mov sp, r7 8003ca6: bd80 pop {r7, pc} 08003ca8 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003ca8: b580 push {r7, lr} 8003caa: b08a sub sp, #40 @ 0x28 8003cac: af02 add r7, sp, #8 8003cae: 6078 str r0, [r7, #4] 8003cb0: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003cb2: 687b ldr r3, [r7, #4] 8003cb4: 681b ldr r3, [r3, #0] 8003cb6: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003cb8: 697b ldr r3, [r7, #20] 8003cba: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8003cbc: 683a ldr r2, [r7, #0] 8003cbe: 4613 mov r3, r2 8003cc0: 00db lsls r3, r3, #3 8003cc2: 4413 add r3, r2 8003cc4: 009b lsls r3, r3, #2 8003cc6: 3310 adds r3, #16 8003cc8: 687a ldr r2, [r7, #4] 8003cca: 4413 add r3, r2 8003ccc: 3304 adds r3, #4 8003cce: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 8003cd0: 68fb ldr r3, [r7, #12] 8003cd2: 695a ldr r2, [r3, #20] 8003cd4: 68fb ldr r3, [r7, #12] 8003cd6: 691b ldr r3, [r3, #16] 8003cd8: 429a cmp r2, r3 8003cda: d901 bls.n 8003ce0 { return HAL_ERROR; 8003cdc: 2301 movs r3, #1 8003cde: e06b b.n 8003db8 } len = ep->xfer_len - ep->xfer_count; 8003ce0: 68fb ldr r3, [r7, #12] 8003ce2: 691a ldr r2, [r3, #16] 8003ce4: 68fb ldr r3, [r7, #12] 8003ce6: 695b ldr r3, [r3, #20] 8003ce8: 1ad3 subs r3, r2, r3 8003cea: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003cec: 68fb ldr r3, [r7, #12] 8003cee: 689b ldr r3, [r3, #8] 8003cf0: 69fa ldr r2, [r7, #28] 8003cf2: 429a cmp r2, r3 8003cf4: d902 bls.n 8003cfc { len = ep->maxpacket; 8003cf6: 68fb ldr r3, [r7, #12] 8003cf8: 689b ldr r3, [r3, #8] 8003cfa: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003cfc: 69fb ldr r3, [r7, #28] 8003cfe: 3303 adds r3, #3 8003d00: 089b lsrs r3, r3, #2 8003d02: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003d04: e02a b.n 8003d5c (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 8003d06: 68fb ldr r3, [r7, #12] 8003d08: 691a ldr r2, [r3, #16] 8003d0a: 68fb ldr r3, [r7, #12] 8003d0c: 695b ldr r3, [r3, #20] 8003d0e: 1ad3 subs r3, r2, r3 8003d10: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003d12: 68fb ldr r3, [r7, #12] 8003d14: 689b ldr r3, [r3, #8] 8003d16: 69fa ldr r2, [r7, #28] 8003d18: 429a cmp r2, r3 8003d1a: d902 bls.n 8003d22 { len = ep->maxpacket; 8003d1c: 68fb ldr r3, [r7, #12] 8003d1e: 689b ldr r3, [r3, #8] 8003d20: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003d22: 69fb ldr r3, [r7, #28] 8003d24: 3303 adds r3, #3 8003d26: 089b lsrs r3, r3, #2 8003d28: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003d2a: 68fb ldr r3, [r7, #12] 8003d2c: 68d9 ldr r1, [r3, #12] 8003d2e: 683b ldr r3, [r7, #0] 8003d30: b2da uxtb r2, r3 8003d32: 69fb ldr r3, [r7, #28] 8003d34: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8003d36: 687b ldr r3, [r7, #4] 8003d38: 799b ldrb r3, [r3, #6] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003d3a: 9300 str r3, [sp, #0] 8003d3c: 4603 mov r3, r0 8003d3e: 6978 ldr r0, [r7, #20] 8003d40: f004 f936 bl 8007fb0 ep->xfer_buff += len; 8003d44: 68fb ldr r3, [r7, #12] 8003d46: 68da ldr r2, [r3, #12] 8003d48: 69fb ldr r3, [r7, #28] 8003d4a: 441a add r2, r3 8003d4c: 68fb ldr r3, [r7, #12] 8003d4e: 60da str r2, [r3, #12] ep->xfer_count += len; 8003d50: 68fb ldr r3, [r7, #12] 8003d52: 695a ldr r2, [r3, #20] 8003d54: 69fb ldr r3, [r7, #28] 8003d56: 441a add r2, r3 8003d58: 68fb ldr r3, [r7, #12] 8003d5a: 615a str r2, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003d5c: 683b ldr r3, [r7, #0] 8003d5e: 015a lsls r2, r3, #5 8003d60: 693b ldr r3, [r7, #16] 8003d62: 4413 add r3, r2 8003d64: f503 6310 add.w r3, r3, #2304 @ 0x900 8003d68: 699b ldr r3, [r3, #24] 8003d6a: b29b uxth r3, r3 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003d6c: 69ba ldr r2, [r7, #24] 8003d6e: 429a cmp r2, r3 8003d70: d809 bhi.n 8003d86 8003d72: 68fb ldr r3, [r7, #12] 8003d74: 695a ldr r2, [r3, #20] 8003d76: 68fb ldr r3, [r7, #12] 8003d78: 691b ldr r3, [r3, #16] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003d7a: 429a cmp r2, r3 8003d7c: d203 bcs.n 8003d86 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003d7e: 68fb ldr r3, [r7, #12] 8003d80: 691b ldr r3, [r3, #16] 8003d82: 2b00 cmp r3, #0 8003d84: d1bf bne.n 8003d06 } if (ep->xfer_len <= ep->xfer_count) 8003d86: 68fb ldr r3, [r7, #12] 8003d88: 691a ldr r2, [r3, #16] 8003d8a: 68fb ldr r3, [r7, #12] 8003d8c: 695b ldr r3, [r3, #20] 8003d8e: 429a cmp r2, r3 8003d90: d811 bhi.n 8003db6 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8003d92: 683b ldr r3, [r7, #0] 8003d94: f003 030f and.w r3, r3, #15 8003d98: 2201 movs r2, #1 8003d9a: fa02 f303 lsl.w r3, r2, r3 8003d9e: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003da0: 693b ldr r3, [r7, #16] 8003da2: f503 6300 add.w r3, r3, #2048 @ 0x800 8003da6: 6b5a ldr r2, [r3, #52] @ 0x34 8003da8: 68bb ldr r3, [r7, #8] 8003daa: 43db mvns r3, r3 8003dac: 6939 ldr r1, [r7, #16] 8003dae: f501 6100 add.w r1, r1, #2048 @ 0x800 8003db2: 4013 ands r3, r2 8003db4: 634b str r3, [r1, #52] @ 0x34 } return HAL_OK; 8003db6: 2300 movs r3, #0 } 8003db8: 4618 mov r0, r3 8003dba: 3720 adds r7, #32 8003dbc: 46bd mov sp, r7 8003dbe: bd80 pop {r7, pc} 08003dc0 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003dc0: b580 push {r7, lr} 8003dc2: b088 sub sp, #32 8003dc4: af00 add r7, sp, #0 8003dc6: 6078 str r0, [r7, #4] 8003dc8: 6039 str r1, [r7, #0] USB_OTG_EPTypeDef *ep; const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003dca: 687b ldr r3, [r7, #4] 8003dcc: 681b ldr r3, [r3, #0] 8003dce: 61fb str r3, [r7, #28] uint32_t USBx_BASE = (uint32_t)USBx; 8003dd0: 69fb ldr r3, [r7, #28] 8003dd2: 61bb str r3, [r7, #24] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003dd4: 69fb ldr r3, [r7, #28] 8003dd6: 333c adds r3, #60 @ 0x3c 8003dd8: 3304 adds r3, #4 8003dda: 681b ldr r3, [r3, #0] 8003ddc: 617b str r3, [r7, #20] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003dde: 683b ldr r3, [r7, #0] 8003de0: 015a lsls r2, r3, #5 8003de2: 69bb ldr r3, [r7, #24] 8003de4: 4413 add r3, r2 8003de6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003dea: 689b ldr r3, [r3, #8] 8003dec: 613b str r3, [r7, #16] if (hpcd->Init.dma_enable == 1U) 8003dee: 687b ldr r3, [r7, #4] 8003df0: 799b ldrb r3, [r3, #6] 8003df2: 2b01 cmp r3, #1 8003df4: d17b bne.n 8003eee { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8003df6: 693b ldr r3, [r7, #16] 8003df8: f003 0308 and.w r3, r3, #8 8003dfc: 2b00 cmp r3, #0 8003dfe: d015 beq.n 8003e2c { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003e00: 697b ldr r3, [r7, #20] 8003e02: 4a61 ldr r2, [pc, #388] @ (8003f88 ) 8003e04: 4293 cmp r3, r2 8003e06: f240 80b9 bls.w 8003f7c ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003e0a: 693b ldr r3, [r7, #16] 8003e0c: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003e10: 2b00 cmp r3, #0 8003e12: f000 80b3 beq.w 8003f7c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003e16: 683b ldr r3, [r7, #0] 8003e18: 015a lsls r2, r3, #5 8003e1a: 69bb ldr r3, [r7, #24] 8003e1c: 4413 add r3, r2 8003e1e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e22: 461a mov r2, r3 8003e24: f44f 4300 mov.w r3, #32768 @ 0x8000 8003e28: 6093 str r3, [r2, #8] 8003e2a: e0a7 b.n 8003f7c } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8003e2c: 693b ldr r3, [r7, #16] 8003e2e: f003 0320 and.w r3, r3, #32 8003e32: 2b00 cmp r3, #0 8003e34: d009 beq.n 8003e4a { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003e36: 683b ldr r3, [r7, #0] 8003e38: 015a lsls r2, r3, #5 8003e3a: 69bb ldr r3, [r7, #24] 8003e3c: 4413 add r3, r2 8003e3e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e42: 461a mov r2, r3 8003e44: 2320 movs r3, #32 8003e46: 6093 str r3, [r2, #8] 8003e48: e098 b.n 8003f7c } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8003e4a: 693b ldr r3, [r7, #16] 8003e4c: f003 0328 and.w r3, r3, #40 @ 0x28 8003e50: 2b00 cmp r3, #0 8003e52: f040 8093 bne.w 8003f7c { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003e56: 697b ldr r3, [r7, #20] 8003e58: 4a4b ldr r2, [pc, #300] @ (8003f88 ) 8003e5a: 4293 cmp r3, r2 8003e5c: d90f bls.n 8003e7e ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003e5e: 693b ldr r3, [r7, #16] 8003e60: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003e64: 2b00 cmp r3, #0 8003e66: d00a beq.n 8003e7e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003e68: 683b ldr r3, [r7, #0] 8003e6a: 015a lsls r2, r3, #5 8003e6c: 69bb ldr r3, [r7, #24] 8003e6e: 4413 add r3, r2 8003e70: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e74: 461a mov r2, r3 8003e76: f44f 4300 mov.w r3, #32768 @ 0x8000 8003e7a: 6093 str r3, [r2, #8] 8003e7c: e07e b.n 8003f7c } else { ep = &hpcd->OUT_ep[epnum]; 8003e7e: 683a ldr r2, [r7, #0] 8003e80: 4613 mov r3, r2 8003e82: 00db lsls r3, r3, #3 8003e84: 4413 add r3, r2 8003e86: 009b lsls r3, r3, #2 8003e88: f503 7314 add.w r3, r3, #592 @ 0x250 8003e8c: 687a ldr r2, [r7, #4] 8003e8e: 4413 add r3, r2 8003e90: 3304 adds r3, #4 8003e92: 60fb str r3, [r7, #12] /* out data packet received over EP */ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8003e94: 68fb ldr r3, [r7, #12] 8003e96: 6a1a ldr r2, [r3, #32] 8003e98: 683b ldr r3, [r7, #0] 8003e9a: 0159 lsls r1, r3, #5 8003e9c: 69bb ldr r3, [r7, #24] 8003e9e: 440b add r3, r1 8003ea0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003ea4: 691b ldr r3, [r3, #16] 8003ea6: f3c3 0312 ubfx r3, r3, #0, #19 8003eaa: 1ad2 subs r2, r2, r3 8003eac: 68fb ldr r3, [r7, #12] 8003eae: 615a str r2, [r3, #20] if (epnum == 0U) 8003eb0: 683b ldr r3, [r7, #0] 8003eb2: 2b00 cmp r3, #0 8003eb4: d114 bne.n 8003ee0 { if (ep->xfer_len == 0U) 8003eb6: 68fb ldr r3, [r7, #12] 8003eb8: 691b ldr r3, [r3, #16] 8003eba: 2b00 cmp r3, #0 8003ebc: d109 bne.n 8003ed2 { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003ebe: 687b ldr r3, [r7, #4] 8003ec0: 6818 ldr r0, [r3, #0] 8003ec2: 687b ldr r3, [r7, #4] 8003ec4: f203 439c addw r3, r3, #1180 @ 0x49c 8003ec8: 461a mov r2, r3 8003eca: 2101 movs r1, #1 8003ecc: f004 fb06 bl 80084dc 8003ed0: e006 b.n 8003ee0 } else { ep->xfer_buff += ep->xfer_count; 8003ed2: 68fb ldr r3, [r7, #12] 8003ed4: 68da ldr r2, [r3, #12] 8003ed6: 68fb ldr r3, [r7, #12] 8003ed8: 695b ldr r3, [r3, #20] 8003eda: 441a add r2, r3 8003edc: 68fb ldr r3, [r7, #12] 8003ede: 60da str r2, [r3, #12] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003ee0: 683b ldr r3, [r7, #0] 8003ee2: b2db uxtb r3, r3 8003ee4: 4619 mov r1, r3 8003ee6: 6878 ldr r0, [r7, #4] 8003ee8: f006 fad4 bl 800a494 8003eec: e046 b.n 8003f7c /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8003eee: 697b ldr r3, [r7, #20] 8003ef0: 4a26 ldr r2, [pc, #152] @ (8003f8c ) 8003ef2: 4293 cmp r3, r2 8003ef4: d124 bne.n 8003f40 { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8003ef6: 693b ldr r3, [r7, #16] 8003ef8: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003efc: 2b00 cmp r3, #0 8003efe: d00a beq.n 8003f16 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003f00: 683b ldr r3, [r7, #0] 8003f02: 015a lsls r2, r3, #5 8003f04: 69bb ldr r3, [r7, #24] 8003f06: 4413 add r3, r2 8003f08: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003f0c: 461a mov r2, r3 8003f0e: f44f 4300 mov.w r3, #32768 @ 0x8000 8003f12: 6093 str r3, [r2, #8] 8003f14: e032 b.n 8003f7c } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8003f16: 693b ldr r3, [r7, #16] 8003f18: f003 0320 and.w r3, r3, #32 8003f1c: 2b00 cmp r3, #0 8003f1e: d008 beq.n 8003f32 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003f20: 683b ldr r3, [r7, #0] 8003f22: 015a lsls r2, r3, #5 8003f24: 69bb ldr r3, [r7, #24] 8003f26: 4413 add r3, r2 8003f28: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003f2c: 461a mov r2, r3 8003f2e: 2320 movs r3, #32 8003f30: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003f32: 683b ldr r3, [r7, #0] 8003f34: b2db uxtb r3, r3 8003f36: 4619 mov r1, r3 8003f38: 6878 ldr r0, [r7, #4] 8003f3a: f006 faab bl 800a494 8003f3e: e01d b.n 8003f7c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8003f40: 683b ldr r3, [r7, #0] 8003f42: 2b00 cmp r3, #0 8003f44: d114 bne.n 8003f70 8003f46: 6879 ldr r1, [r7, #4] 8003f48: 683a ldr r2, [r7, #0] 8003f4a: 4613 mov r3, r2 8003f4c: 00db lsls r3, r3, #3 8003f4e: 4413 add r3, r2 8003f50: 009b lsls r3, r3, #2 8003f52: 440b add r3, r1 8003f54: f503 7319 add.w r3, r3, #612 @ 0x264 8003f58: 681b ldr r3, [r3, #0] 8003f5a: 2b00 cmp r3, #0 8003f5c: d108 bne.n 8003f70 { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 8003f5e: 687b ldr r3, [r7, #4] 8003f60: 6818 ldr r0, [r3, #0] 8003f62: 687b ldr r3, [r7, #4] 8003f64: f203 439c addw r3, r3, #1180 @ 0x49c 8003f68: 461a mov r2, r3 8003f6a: 2100 movs r1, #0 8003f6c: f004 fab6 bl 80084dc } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003f70: 683b ldr r3, [r7, #0] 8003f72: b2db uxtb r3, r3 8003f74: 4619 mov r1, r3 8003f76: 6878 ldr r0, [r7, #4] 8003f78: f006 fa8c bl 800a494 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8003f7c: 2300 movs r3, #0 } 8003f7e: 4618 mov r0, r3 8003f80: 3720 adds r7, #32 8003f82: 46bd mov sp, r7 8003f84: bd80 pop {r7, pc} 8003f86: bf00 nop 8003f88: 4f54300a .word 0x4f54300a 8003f8c: 4f54310a .word 0x4f54310a 08003f90 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003f90: b580 push {r7, lr} 8003f92: b086 sub sp, #24 8003f94: af00 add r7, sp, #0 8003f96: 6078 str r0, [r7, #4] 8003f98: 6039 str r1, [r7, #0] const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003f9a: 687b ldr r3, [r7, #4] 8003f9c: 681b ldr r3, [r3, #0] 8003f9e: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003fa0: 697b ldr r3, [r7, #20] 8003fa2: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003fa4: 697b ldr r3, [r7, #20] 8003fa6: 333c adds r3, #60 @ 0x3c 8003fa8: 3304 adds r3, #4 8003faa: 681b ldr r3, [r3, #0] 8003fac: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003fae: 683b ldr r3, [r7, #0] 8003fb0: 015a lsls r2, r3, #5 8003fb2: 693b ldr r3, [r7, #16] 8003fb4: 4413 add r3, r2 8003fb6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003fba: 689b ldr r3, [r3, #8] 8003fbc: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003fbe: 68fb ldr r3, [r7, #12] 8003fc0: 4a15 ldr r2, [pc, #84] @ (8004018 ) 8003fc2: 4293 cmp r3, r2 8003fc4: d90e bls.n 8003fe4 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003fc6: 68bb ldr r3, [r7, #8] 8003fc8: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003fcc: 2b00 cmp r3, #0 8003fce: d009 beq.n 8003fe4 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003fd0: 683b ldr r3, [r7, #0] 8003fd2: 015a lsls r2, r3, #5 8003fd4: 693b ldr r3, [r7, #16] 8003fd6: 4413 add r3, r2 8003fd8: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003fdc: 461a mov r2, r3 8003fde: f44f 4300 mov.w r3, #32768 @ 0x8000 8003fe2: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 8003fe4: 6878 ldr r0, [r7, #4] 8003fe6: f006 fa43 bl 800a470 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 8003fea: 68fb ldr r3, [r7, #12] 8003fec: 4a0a ldr r2, [pc, #40] @ (8004018 ) 8003fee: 4293 cmp r3, r2 8003ff0: d90c bls.n 800400c 8003ff2: 687b ldr r3, [r7, #4] 8003ff4: 799b ldrb r3, [r3, #6] 8003ff6: 2b01 cmp r3, #1 8003ff8: d108 bne.n 800400c { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003ffa: 687b ldr r3, [r7, #4] 8003ffc: 6818 ldr r0, [r3, #0] 8003ffe: 687b ldr r3, [r7, #4] 8004000: f203 439c addw r3, r3, #1180 @ 0x49c 8004004: 461a mov r2, r3 8004006: 2101 movs r1, #1 8004008: f004 fa68 bl 80084dc } return HAL_OK; 800400c: 2300 movs r3, #0 } 800400e: 4618 mov r0, r3 8004010: 3718 adds r7, #24 8004012: 46bd mov sp, r7 8004014: bd80 pop {r7, pc} 8004016: bf00 nop 8004018: 4f54300a .word 0x4f54300a 0800401c : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 800401c: b480 push {r7} 800401e: b085 sub sp, #20 8004020: af00 add r7, sp, #0 8004022: 6078 str r0, [r7, #4] 8004024: 460b mov r3, r1 8004026: 70fb strb r3, [r7, #3] 8004028: 4613 mov r3, r2 800402a: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 800402c: 687b ldr r3, [r7, #4] 800402e: 681b ldr r3, [r3, #0] 8004030: 6a5b ldr r3, [r3, #36] @ 0x24 8004032: 60bb str r3, [r7, #8] if (fifo == 0U) 8004034: 78fb ldrb r3, [r7, #3] 8004036: 2b00 cmp r3, #0 8004038: d107 bne.n 800404a { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 800403a: 883b ldrh r3, [r7, #0] 800403c: 0419 lsls r1, r3, #16 800403e: 687b ldr r3, [r7, #4] 8004040: 681b ldr r3, [r3, #0] 8004042: 68ba ldr r2, [r7, #8] 8004044: 430a orrs r2, r1 8004046: 629a str r2, [r3, #40] @ 0x28 8004048: e028 b.n 800409c } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 800404a: 687b ldr r3, [r7, #4] 800404c: 681b ldr r3, [r3, #0] 800404e: 6a9b ldr r3, [r3, #40] @ 0x28 8004050: 0c1b lsrs r3, r3, #16 8004052: 68ba ldr r2, [r7, #8] 8004054: 4413 add r3, r2 8004056: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8004058: 2300 movs r3, #0 800405a: 73fb strb r3, [r7, #15] 800405c: e00d b.n 800407a { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 800405e: 687b ldr r3, [r7, #4] 8004060: 681a ldr r2, [r3, #0] 8004062: 7bfb ldrb r3, [r7, #15] 8004064: 3340 adds r3, #64 @ 0x40 8004066: 009b lsls r3, r3, #2 8004068: 4413 add r3, r2 800406a: 685b ldr r3, [r3, #4] 800406c: 0c1b lsrs r3, r3, #16 800406e: 68ba ldr r2, [r7, #8] 8004070: 4413 add r3, r2 8004072: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8004074: 7bfb ldrb r3, [r7, #15] 8004076: 3301 adds r3, #1 8004078: 73fb strb r3, [r7, #15] 800407a: 7bfa ldrb r2, [r7, #15] 800407c: 78fb ldrb r3, [r7, #3] 800407e: 3b01 subs r3, #1 8004080: 429a cmp r2, r3 8004082: d3ec bcc.n 800405e } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 8004084: 883b ldrh r3, [r7, #0] 8004086: 0418 lsls r0, r3, #16 8004088: 687b ldr r3, [r7, #4] 800408a: 6819 ldr r1, [r3, #0] 800408c: 78fb ldrb r3, [r7, #3] 800408e: 3b01 subs r3, #1 8004090: 68ba ldr r2, [r7, #8] 8004092: 4302 orrs r2, r0 8004094: 3340 adds r3, #64 @ 0x40 8004096: 009b lsls r3, r3, #2 8004098: 440b add r3, r1 800409a: 605a str r2, [r3, #4] } return HAL_OK; 800409c: 2300 movs r3, #0 } 800409e: 4618 mov r0, r3 80040a0: 3714 adds r7, #20 80040a2: 46bd mov sp, r7 80040a4: f85d 7b04 ldr.w r7, [sp], #4 80040a8: 4770 bx lr 080040aa : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 80040aa: b480 push {r7} 80040ac: b083 sub sp, #12 80040ae: af00 add r7, sp, #0 80040b0: 6078 str r0, [r7, #4] 80040b2: 460b mov r3, r1 80040b4: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 80040b6: 687b ldr r3, [r7, #4] 80040b8: 681b ldr r3, [r3, #0] 80040ba: 887a ldrh r2, [r7, #2] 80040bc: 625a str r2, [r3, #36] @ 0x24 return HAL_OK; 80040be: 2300 movs r3, #0 } 80040c0: 4618 mov r0, r3 80040c2: 370c adds r7, #12 80040c4: 46bd mov sp, r7 80040c6: f85d 7b04 ldr.w r7, [sp], #4 80040ca: 4770 bx lr 080040cc : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 80040cc: b480 push {r7} 80040ce: b085 sub sp, #20 80040d0: af00 add r7, sp, #0 80040d2: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80040d4: 687b ldr r3, [r7, #4] 80040d6: 681b ldr r3, [r3, #0] 80040d8: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 80040da: 687b ldr r3, [r7, #4] 80040dc: 2201 movs r2, #1 80040de: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 80040e2: 687b ldr r3, [r7, #4] 80040e4: 2200 movs r2, #0 80040e6: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 80040ea: 68fb ldr r3, [r7, #12] 80040ec: 699b ldr r3, [r3, #24] 80040ee: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 80040f2: 68fb ldr r3, [r7, #12] 80040f4: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 80040f6: 68fb ldr r3, [r7, #12] 80040f8: 6d5b ldr r3, [r3, #84] @ 0x54 80040fa: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80040fe: f043 0303 orr.w r3, r3, #3 8004102: 68fa ldr r2, [r7, #12] 8004104: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 8004106: 2300 movs r3, #0 } 8004108: 4618 mov r0, r3 800410a: 3714 adds r7, #20 800410c: 46bd mov sp, r7 800410e: f85d 7b04 ldr.w r7, [sp], #4 8004112: 4770 bx lr 08004114 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8004114: b580 push {r7, lr} 8004116: b084 sub sp, #16 8004118: af00 add r7, sp, #0 800411a: 6078 str r0, [r7, #4] 800411c: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800411e: 687b ldr r3, [r7, #4] 8004120: 2b00 cmp r3, #0 8004122: d101 bne.n 8004128 { return HAL_ERROR; 8004124: 2301 movs r3, #1 8004126: e0cc b.n 80042c2 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004128: 4b68 ldr r3, [pc, #416] @ (80042cc ) 800412a: 681b ldr r3, [r3, #0] 800412c: f003 030f and.w r3, r3, #15 8004130: 683a ldr r2, [r7, #0] 8004132: 429a cmp r2, r3 8004134: d90c bls.n 8004150 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004136: 4b65 ldr r3, [pc, #404] @ (80042cc ) 8004138: 683a ldr r2, [r7, #0] 800413a: b2d2 uxtb r2, r2 800413c: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800413e: 4b63 ldr r3, [pc, #396] @ (80042cc ) 8004140: 681b ldr r3, [r3, #0] 8004142: f003 030f and.w r3, r3, #15 8004146: 683a ldr r2, [r7, #0] 8004148: 429a cmp r2, r3 800414a: d001 beq.n 8004150 { return HAL_ERROR; 800414c: 2301 movs r3, #1 800414e: e0b8 b.n 80042c2 } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8004150: 687b ldr r3, [r7, #4] 8004152: 681b ldr r3, [r3, #0] 8004154: f003 0302 and.w r3, r3, #2 8004158: 2b00 cmp r3, #0 800415a: d020 beq.n 800419e { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800415c: 687b ldr r3, [r7, #4] 800415e: 681b ldr r3, [r3, #0] 8004160: f003 0304 and.w r3, r3, #4 8004164: 2b00 cmp r3, #0 8004166: d005 beq.n 8004174 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004168: 4b59 ldr r3, [pc, #356] @ (80042d0 ) 800416a: 689b ldr r3, [r3, #8] 800416c: 4a58 ldr r2, [pc, #352] @ (80042d0 ) 800416e: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 8004172: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004174: 687b ldr r3, [r7, #4] 8004176: 681b ldr r3, [r3, #0] 8004178: f003 0308 and.w r3, r3, #8 800417c: 2b00 cmp r3, #0 800417e: d005 beq.n 800418c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8004180: 4b53 ldr r3, [pc, #332] @ (80042d0 ) 8004182: 689b ldr r3, [r3, #8] 8004184: 4a52 ldr r2, [pc, #328] @ (80042d0 ) 8004186: f443 4360 orr.w r3, r3, #57344 @ 0xe000 800418a: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800418c: 4b50 ldr r3, [pc, #320] @ (80042d0 ) 800418e: 689b ldr r3, [r3, #8] 8004190: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8004194: 687b ldr r3, [r7, #4] 8004196: 689b ldr r3, [r3, #8] 8004198: 494d ldr r1, [pc, #308] @ (80042d0 ) 800419a: 4313 orrs r3, r2 800419c: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800419e: 687b ldr r3, [r7, #4] 80041a0: 681b ldr r3, [r3, #0] 80041a2: f003 0301 and.w r3, r3, #1 80041a6: 2b00 cmp r3, #0 80041a8: d044 beq.n 8004234 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80041aa: 687b ldr r3, [r7, #4] 80041ac: 685b ldr r3, [r3, #4] 80041ae: 2b01 cmp r3, #1 80041b0: d107 bne.n 80041c2 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80041b2: 4b47 ldr r3, [pc, #284] @ (80042d0 ) 80041b4: 681b ldr r3, [r3, #0] 80041b6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80041ba: 2b00 cmp r3, #0 80041bc: d119 bne.n 80041f2 { return HAL_ERROR; 80041be: 2301 movs r3, #1 80041c0: e07f b.n 80042c2 } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80041c2: 687b ldr r3, [r7, #4] 80041c4: 685b ldr r3, [r3, #4] 80041c6: 2b02 cmp r3, #2 80041c8: d003 beq.n 80041d2 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 80041ca: 687b ldr r3, [r7, #4] 80041cc: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80041ce: 2b03 cmp r3, #3 80041d0: d107 bne.n 80041e2 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80041d2: 4b3f ldr r3, [pc, #252] @ (80042d0 ) 80041d4: 681b ldr r3, [r3, #0] 80041d6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80041da: 2b00 cmp r3, #0 80041dc: d109 bne.n 80041f2 { return HAL_ERROR; 80041de: 2301 movs r3, #1 80041e0: e06f b.n 80042c2 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80041e2: 4b3b ldr r3, [pc, #236] @ (80042d0 ) 80041e4: 681b ldr r3, [r3, #0] 80041e6: f003 0302 and.w r3, r3, #2 80041ea: 2b00 cmp r3, #0 80041ec: d101 bne.n 80041f2 { return HAL_ERROR; 80041ee: 2301 movs r3, #1 80041f0: e067 b.n 80042c2 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80041f2: 4b37 ldr r3, [pc, #220] @ (80042d0 ) 80041f4: 689b ldr r3, [r3, #8] 80041f6: f023 0203 bic.w r2, r3, #3 80041fa: 687b ldr r3, [r7, #4] 80041fc: 685b ldr r3, [r3, #4] 80041fe: 4934 ldr r1, [pc, #208] @ (80042d0 ) 8004200: 4313 orrs r3, r2 8004202: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004204: f7fd fcb2 bl 8001b6c 8004208: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800420a: e00a b.n 8004222 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800420c: f7fd fcae bl 8001b6c 8004210: 4602 mov r2, r0 8004212: 68fb ldr r3, [r7, #12] 8004214: 1ad3 subs r3, r2, r3 8004216: f241 3288 movw r2, #5000 @ 0x1388 800421a: 4293 cmp r3, r2 800421c: d901 bls.n 8004222 { return HAL_TIMEOUT; 800421e: 2303 movs r3, #3 8004220: e04f b.n 80042c2 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004222: 4b2b ldr r3, [pc, #172] @ (80042d0 ) 8004224: 689b ldr r3, [r3, #8] 8004226: f003 020c and.w r2, r3, #12 800422a: 687b ldr r3, [r7, #4] 800422c: 685b ldr r3, [r3, #4] 800422e: 009b lsls r3, r3, #2 8004230: 429a cmp r2, r3 8004232: d1eb bne.n 800420c } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004234: 4b25 ldr r3, [pc, #148] @ (80042cc ) 8004236: 681b ldr r3, [r3, #0] 8004238: f003 030f and.w r3, r3, #15 800423c: 683a ldr r2, [r7, #0] 800423e: 429a cmp r2, r3 8004240: d20c bcs.n 800425c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004242: 4b22 ldr r3, [pc, #136] @ (80042cc ) 8004244: 683a ldr r2, [r7, #0] 8004246: b2d2 uxtb r2, r2 8004248: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800424a: 4b20 ldr r3, [pc, #128] @ (80042cc ) 800424c: 681b ldr r3, [r3, #0] 800424e: f003 030f and.w r3, r3, #15 8004252: 683a ldr r2, [r7, #0] 8004254: 429a cmp r2, r3 8004256: d001 beq.n 800425c { return HAL_ERROR; 8004258: 2301 movs r3, #1 800425a: e032 b.n 80042c2 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800425c: 687b ldr r3, [r7, #4] 800425e: 681b ldr r3, [r3, #0] 8004260: f003 0304 and.w r3, r3, #4 8004264: 2b00 cmp r3, #0 8004266: d008 beq.n 800427a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004268: 4b19 ldr r3, [pc, #100] @ (80042d0 ) 800426a: 689b ldr r3, [r3, #8] 800426c: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 8004270: 687b ldr r3, [r7, #4] 8004272: 68db ldr r3, [r3, #12] 8004274: 4916 ldr r1, [pc, #88] @ (80042d0 ) 8004276: 4313 orrs r3, r2 8004278: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800427a: 687b ldr r3, [r7, #4] 800427c: 681b ldr r3, [r3, #0] 800427e: f003 0308 and.w r3, r3, #8 8004282: 2b00 cmp r3, #0 8004284: d009 beq.n 800429a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8004286: 4b12 ldr r3, [pc, #72] @ (80042d0 ) 8004288: 689b ldr r3, [r3, #8] 800428a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 800428e: 687b ldr r3, [r7, #4] 8004290: 691b ldr r3, [r3, #16] 8004292: 00db lsls r3, r3, #3 8004294: 490e ldr r1, [pc, #56] @ (80042d0 ) 8004296: 4313 orrs r3, r2 8004298: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 800429a: f000 fb7f bl 800499c 800429e: 4602 mov r2, r0 80042a0: 4b0b ldr r3, [pc, #44] @ (80042d0 ) 80042a2: 689b ldr r3, [r3, #8] 80042a4: 091b lsrs r3, r3, #4 80042a6: f003 030f and.w r3, r3, #15 80042aa: 490a ldr r1, [pc, #40] @ (80042d4 ) 80042ac: 5ccb ldrb r3, [r1, r3] 80042ae: fa22 f303 lsr.w r3, r2, r3 80042b2: 4a09 ldr r2, [pc, #36] @ (80042d8 ) 80042b4: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 80042b6: 4b09 ldr r3, [pc, #36] @ (80042dc ) 80042b8: 681b ldr r3, [r3, #0] 80042ba: 4618 mov r0, r3 80042bc: f7fd fc12 bl 8001ae4 return HAL_OK; 80042c0: 2300 movs r3, #0 } 80042c2: 4618 mov r0, r3 80042c4: 3710 adds r7, #16 80042c6: 46bd mov sp, r7 80042c8: bd80 pop {r7, pc} 80042ca: bf00 nop 80042cc: 40023c00 .word 0x40023c00 80042d0: 40023800 .word 0x40023800 80042d4: 0800ab14 .word 0x0800ab14 80042d8: 20000090 .word 0x20000090 80042dc: 20000094 .word 0x20000094 080042e0 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80042e0: b480 push {r7} 80042e2: af00 add r7, sp, #0 return SystemCoreClock; 80042e4: 4b03 ldr r3, [pc, #12] @ (80042f4 ) 80042e6: 681b ldr r3, [r3, #0] } 80042e8: 4618 mov r0, r3 80042ea: 46bd mov sp, r7 80042ec: f85d 7b04 ldr.w r7, [sp], #4 80042f0: 4770 bx lr 80042f2: bf00 nop 80042f4: 20000090 .word 0x20000090 080042f8 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80042f8: b580 push {r7, lr} 80042fa: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 80042fc: f7ff fff0 bl 80042e0 8004300: 4602 mov r2, r0 8004302: 4b05 ldr r3, [pc, #20] @ (8004318 ) 8004304: 689b ldr r3, [r3, #8] 8004306: 0a9b lsrs r3, r3, #10 8004308: f003 0307 and.w r3, r3, #7 800430c: 4903 ldr r1, [pc, #12] @ (800431c ) 800430e: 5ccb ldrb r3, [r1, r3] 8004310: fa22 f303 lsr.w r3, r2, r3 } 8004314: 4618 mov r0, r3 8004316: bd80 pop {r7, pc} 8004318: 40023800 .word 0x40023800 800431c: 0800ab24 .word 0x0800ab24 08004320 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8004320: b580 push {r7, lr} 8004322: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8004324: f7ff ffdc bl 80042e0 8004328: 4602 mov r2, r0 800432a: 4b05 ldr r3, [pc, #20] @ (8004340 ) 800432c: 689b ldr r3, [r3, #8] 800432e: 0b5b lsrs r3, r3, #13 8004330: f003 0307 and.w r3, r3, #7 8004334: 4903 ldr r1, [pc, #12] @ (8004344 ) 8004336: 5ccb ldrb r3, [r1, r3] 8004338: fa22 f303 lsr.w r3, r2, r3 } 800433c: 4618 mov r0, r3 800433e: bd80 pop {r7, pc} 8004340: 40023800 .word 0x40023800 8004344: 0800ab24 .word 0x0800ab24 08004348 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004348: b580 push {r7, lr} 800434a: b08c sub sp, #48 @ 0x30 800434c: af00 add r7, sp, #0 800434e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8004350: 2300 movs r3, #0 8004352: 627b str r3, [r7, #36] @ 0x24 uint32_t tmpreg1 = 0U; 8004354: 2300 movs r3, #0 8004356: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 8004358: 2300 movs r3, #0 800435a: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 800435c: 2300 movs r3, #0 800435e: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 8004360: 2300 movs r3, #0 8004362: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 8004364: 2300 movs r3, #0 8004366: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 8004368: 2300 movs r3, #0 800436a: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 800436c: 2300 movs r3, #0 800436e: 62fb str r3, [r7, #44] @ 0x2c uint32_t pllsaiused = 0U; 8004370: 2300 movs r3, #0 8004372: 62bb str r3, [r7, #40] @ 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 8004374: 687b ldr r3, [r7, #4] 8004376: 681b ldr r3, [r3, #0] 8004378: f003 0301 and.w r3, r3, #1 800437c: 2b00 cmp r3, #0 800437e: d010 beq.n 80043a2 { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 8004380: 4b6f ldr r3, [pc, #444] @ (8004540 ) 8004382: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004386: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 800438a: 687b ldr r3, [r7, #4] 800438c: 6b9b ldr r3, [r3, #56] @ 0x38 800438e: 496c ldr r1, [pc, #432] @ (8004540 ) 8004390: 4313 orrs r3, r2 8004392: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 8004396: 687b ldr r3, [r7, #4] 8004398: 6b9b ldr r3, [r3, #56] @ 0x38 800439a: 2b00 cmp r3, #0 800439c: d101 bne.n 80043a2 { plli2sused = 1U; 800439e: 2301 movs r3, #1 80043a0: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 80043a2: 687b ldr r3, [r7, #4] 80043a4: 681b ldr r3, [r3, #0] 80043a6: f003 0302 and.w r3, r3, #2 80043aa: 2b00 cmp r3, #0 80043ac: d010 beq.n 80043d0 { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 80043ae: 4b64 ldr r3, [pc, #400] @ (8004540 ) 80043b0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80043b4: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 80043b8: 687b ldr r3, [r7, #4] 80043ba: 6bdb ldr r3, [r3, #60] @ 0x3c 80043bc: 4960 ldr r1, [pc, #384] @ (8004540 ) 80043be: 4313 orrs r3, r2 80043c0: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 80043c4: 687b ldr r3, [r7, #4] 80043c6: 6bdb ldr r3, [r3, #60] @ 0x3c 80043c8: 2b00 cmp r3, #0 80043ca: d101 bne.n 80043d0 { plli2sused = 1U; 80043cc: 2301 movs r3, #1 80043ce: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 80043d0: 687b ldr r3, [r7, #4] 80043d2: 681b ldr r3, [r3, #0] 80043d4: f003 0304 and.w r3, r3, #4 80043d8: 2b00 cmp r3, #0 80043da: d017 beq.n 800440c { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80043dc: 4b58 ldr r3, [pc, #352] @ (8004540 ) 80043de: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80043e2: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 80043e6: 687b ldr r3, [r7, #4] 80043e8: 6b1b ldr r3, [r3, #48] @ 0x30 80043ea: 4955 ldr r1, [pc, #340] @ (8004540 ) 80043ec: 4313 orrs r3, r2 80043ee: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 80043f2: 687b ldr r3, [r7, #4] 80043f4: 6b1b ldr r3, [r3, #48] @ 0x30 80043f6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80043fa: d101 bne.n 8004400 { plli2sused = 1U; 80043fc: 2301 movs r3, #1 80043fe: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 8004400: 687b ldr r3, [r7, #4] 8004402: 6b1b ldr r3, [r3, #48] @ 0x30 8004404: 2b00 cmp r3, #0 8004406: d101 bne.n 800440c { pllsaiused = 1U; 8004408: 2301 movs r3, #1 800440a: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 800440c: 687b ldr r3, [r7, #4] 800440e: 681b ldr r3, [r3, #0] 8004410: f003 0308 and.w r3, r3, #8 8004414: 2b00 cmp r3, #0 8004416: d017 beq.n 8004448 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 8004418: 4b49 ldr r3, [pc, #292] @ (8004540 ) 800441a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800441e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 8004422: 687b ldr r3, [r7, #4] 8004424: 6b5b ldr r3, [r3, #52] @ 0x34 8004426: 4946 ldr r1, [pc, #280] @ (8004540 ) 8004428: 4313 orrs r3, r2 800442a: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 800442e: 687b ldr r3, [r7, #4] 8004430: 6b5b ldr r3, [r3, #52] @ 0x34 8004432: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004436: d101 bne.n 800443c { plli2sused = 1U; 8004438: 2301 movs r3, #1 800443a: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 800443c: 687b ldr r3, [r7, #4] 800443e: 6b5b ldr r3, [r3, #52] @ 0x34 8004440: 2b00 cmp r3, #0 8004442: d101 bne.n 8004448 { pllsaiused = 1U; 8004444: 2301 movs r3, #1 8004446: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8004448: 687b ldr r3, [r7, #4] 800444a: 681b ldr r3, [r3, #0] 800444c: f003 0320 and.w r3, r3, #32 8004450: 2b00 cmp r3, #0 8004452: f000 808a beq.w 800456a { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 8004456: 2300 movs r3, #0 8004458: 60bb str r3, [r7, #8] 800445a: 4b39 ldr r3, [pc, #228] @ (8004540 ) 800445c: 6c1b ldr r3, [r3, #64] @ 0x40 800445e: 4a38 ldr r2, [pc, #224] @ (8004540 ) 8004460: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004464: 6413 str r3, [r2, #64] @ 0x40 8004466: 4b36 ldr r3, [pc, #216] @ (8004540 ) 8004468: 6c1b ldr r3, [r3, #64] @ 0x40 800446a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800446e: 60bb str r3, [r7, #8] 8004470: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 8004472: 4b34 ldr r3, [pc, #208] @ (8004544 ) 8004474: 681b ldr r3, [r3, #0] 8004476: 4a33 ldr r2, [pc, #204] @ (8004544 ) 8004478: f443 7380 orr.w r3, r3, #256 @ 0x100 800447c: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 800447e: f7fd fb75 bl 8001b6c 8004482: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004484: e008 b.n 8004498 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004486: f7fd fb71 bl 8001b6c 800448a: 4602 mov r2, r0 800448c: 6a7b ldr r3, [r7, #36] @ 0x24 800448e: 1ad3 subs r3, r2, r3 8004490: 2b02 cmp r3, #2 8004492: d901 bls.n 8004498 { return HAL_TIMEOUT; 8004494: 2303 movs r3, #3 8004496: e278 b.n 800498a while ((PWR->CR & PWR_CR_DBP) == RESET) 8004498: 4b2a ldr r3, [pc, #168] @ (8004544 ) 800449a: 681b ldr r3, [r3, #0] 800449c: f403 7380 and.w r3, r3, #256 @ 0x100 80044a0: 2b00 cmp r3, #0 80044a2: d0f0 beq.n 8004486 } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 80044a4: 4b26 ldr r3, [pc, #152] @ (8004540 ) 80044a6: 6f1b ldr r3, [r3, #112] @ 0x70 80044a8: f403 7340 and.w r3, r3, #768 @ 0x300 80044ac: 623b str r3, [r7, #32] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 80044ae: 6a3b ldr r3, [r7, #32] 80044b0: 2b00 cmp r3, #0 80044b2: d02f beq.n 8004514 80044b4: 687b ldr r3, [r7, #4] 80044b6: 6c1b ldr r3, [r3, #64] @ 0x40 80044b8: f403 7340 and.w r3, r3, #768 @ 0x300 80044bc: 6a3a ldr r2, [r7, #32] 80044be: 429a cmp r2, r3 80044c0: d028 beq.n 8004514 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80044c2: 4b1f ldr r3, [pc, #124] @ (8004540 ) 80044c4: 6f1b ldr r3, [r3, #112] @ 0x70 80044c6: f423 7340 bic.w r3, r3, #768 @ 0x300 80044ca: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80044cc: 4b1e ldr r3, [pc, #120] @ (8004548 ) 80044ce: 2201 movs r2, #1 80044d0: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 80044d2: 4b1d ldr r3, [pc, #116] @ (8004548 ) 80044d4: 2200 movs r2, #0 80044d6: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 80044d8: 4a19 ldr r2, [pc, #100] @ (8004540 ) 80044da: 6a3b ldr r3, [r7, #32] 80044dc: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 80044de: 4b18 ldr r3, [pc, #96] @ (8004540 ) 80044e0: 6f1b ldr r3, [r3, #112] @ 0x70 80044e2: f003 0301 and.w r3, r3, #1 80044e6: 2b01 cmp r3, #1 80044e8: d114 bne.n 8004514 { /* Get tick */ tickstart = HAL_GetTick(); 80044ea: f7fd fb3f bl 8001b6c 80044ee: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80044f0: e00a b.n 8004508 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80044f2: f7fd fb3b bl 8001b6c 80044f6: 4602 mov r2, r0 80044f8: 6a7b ldr r3, [r7, #36] @ 0x24 80044fa: 1ad3 subs r3, r2, r3 80044fc: f241 3288 movw r2, #5000 @ 0x1388 8004500: 4293 cmp r3, r2 8004502: d901 bls.n 8004508 { return HAL_TIMEOUT; 8004504: 2303 movs r3, #3 8004506: e240 b.n 800498a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004508: 4b0d ldr r3, [pc, #52] @ (8004540 ) 800450a: 6f1b ldr r3, [r3, #112] @ 0x70 800450c: f003 0302 and.w r3, r3, #2 8004510: 2b00 cmp r3, #0 8004512: d0ee beq.n 80044f2 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8004514: 687b ldr r3, [r7, #4] 8004516: 6c1b ldr r3, [r3, #64] @ 0x40 8004518: f403 7340 and.w r3, r3, #768 @ 0x300 800451c: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004520: d114 bne.n 800454c 8004522: 4b07 ldr r3, [pc, #28] @ (8004540 ) 8004524: 689b ldr r3, [r3, #8] 8004526: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 800452a: 687b ldr r3, [r7, #4] 800452c: 6c1b ldr r3, [r3, #64] @ 0x40 800452e: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 8004532: f423 7340 bic.w r3, r3, #768 @ 0x300 8004536: 4902 ldr r1, [pc, #8] @ (8004540 ) 8004538: 4313 orrs r3, r2 800453a: 608b str r3, [r1, #8] 800453c: e00c b.n 8004558 800453e: bf00 nop 8004540: 40023800 .word 0x40023800 8004544: 40007000 .word 0x40007000 8004548: 42470e40 .word 0x42470e40 800454c: 4b4a ldr r3, [pc, #296] @ (8004678 ) 800454e: 689b ldr r3, [r3, #8] 8004550: 4a49 ldr r2, [pc, #292] @ (8004678 ) 8004552: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 8004556: 6093 str r3, [r2, #8] 8004558: 4b47 ldr r3, [pc, #284] @ (8004678 ) 800455a: 6f1a ldr r2, [r3, #112] @ 0x70 800455c: 687b ldr r3, [r7, #4] 800455e: 6c1b ldr r3, [r3, #64] @ 0x40 8004560: f3c3 030b ubfx r3, r3, #0, #12 8004564: 4944 ldr r1, [pc, #272] @ (8004678 ) 8004566: 4313 orrs r3, r2 8004568: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 800456a: 687b ldr r3, [r7, #4] 800456c: 681b ldr r3, [r3, #0] 800456e: f003 0310 and.w r3, r3, #16 8004572: 2b00 cmp r3, #0 8004574: d004 beq.n 8004580 { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8004576: 687b ldr r3, [r7, #4] 8004578: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 800457c: 4b3f ldr r3, [pc, #252] @ (800467c ) 800457e: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 8004580: 687b ldr r3, [r7, #4] 8004582: 681b ldr r3, [r3, #0] 8004584: f003 0380 and.w r3, r3, #128 @ 0x80 8004588: 2b00 cmp r3, #0 800458a: d00a beq.n 80045a2 { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 800458c: 4b3a ldr r3, [pc, #232] @ (8004678 ) 800458e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004592: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 8004596: 687b ldr r3, [r7, #4] 8004598: 6cdb ldr r3, [r3, #76] @ 0x4c 800459a: 4937 ldr r1, [pc, #220] @ (8004678 ) 800459c: 4313 orrs r3, r2 800459e: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80045a2: 687b ldr r3, [r7, #4] 80045a4: 681b ldr r3, [r3, #0] 80045a6: f003 0340 and.w r3, r3, #64 @ 0x40 80045aa: 2b00 cmp r3, #0 80045ac: d00a beq.n 80045c4 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 80045ae: 4b32 ldr r3, [pc, #200] @ (8004678 ) 80045b0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80045b4: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 80045b8: 687b ldr r3, [r7, #4] 80045ba: 6c9b ldr r3, [r3, #72] @ 0x48 80045bc: 492e ldr r1, [pc, #184] @ (8004678 ) 80045be: 4313 orrs r3, r2 80045c0: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 80045c4: 687b ldr r3, [r7, #4] 80045c6: 681b ldr r3, [r3, #0] 80045c8: f403 7380 and.w r3, r3, #256 @ 0x100 80045cc: 2b00 cmp r3, #0 80045ce: d011 beq.n 80045f4 { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 80045d0: 4b29 ldr r3, [pc, #164] @ (8004678 ) 80045d2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80045d6: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 80045da: 687b ldr r3, [r7, #4] 80045dc: 6d5b ldr r3, [r3, #84] @ 0x54 80045de: 4926 ldr r1, [pc, #152] @ (8004678 ) 80045e0: 4313 orrs r3, r2 80045e2: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 80045e6: 687b ldr r3, [r7, #4] 80045e8: 6d5b ldr r3, [r3, #84] @ 0x54 80045ea: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80045ee: d101 bne.n 80045f4 { pllsaiused = 1U; 80045f0: 2301 movs r3, #1 80045f2: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 80045f4: 687b ldr r3, [r7, #4] 80045f6: 681b ldr r3, [r3, #0] 80045f8: f403 7300 and.w r3, r3, #512 @ 0x200 80045fc: 2b00 cmp r3, #0 80045fe: d00a beq.n 8004616 { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 8004600: 4b1d ldr r3, [pc, #116] @ (8004678 ) 8004602: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004606: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 800460a: 687b ldr r3, [r7, #4] 800460c: 6c5b ldr r3, [r3, #68] @ 0x44 800460e: 491a ldr r1, [pc, #104] @ (8004678 ) 8004610: 4313 orrs r3, r2 8004612: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004616: 687b ldr r3, [r7, #4] 8004618: 681b ldr r3, [r3, #0] 800461a: f403 6380 and.w r3, r3, #1024 @ 0x400 800461e: 2b00 cmp r3, #0 8004620: d011 beq.n 8004646 { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 8004622: 4b15 ldr r3, [pc, #84] @ (8004678 ) 8004624: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004628: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 800462c: 687b ldr r3, [r7, #4] 800462e: 6d1b ldr r3, [r3, #80] @ 0x50 8004630: 4911 ldr r1, [pc, #68] @ (8004678 ) 8004632: 4313 orrs r3, r2 8004634: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 8004638: 687b ldr r3, [r7, #4] 800463a: 6d1b ldr r3, [r3, #80] @ 0x50 800463c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004640: d101 bne.n 8004646 { plli2sused = 1U; 8004642: 2301 movs r3, #1 8004644: 62fb str r3, [r7, #44] @ 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 8004646: 6afb ldr r3, [r7, #44] @ 0x2c 8004648: 2b01 cmp r3, #1 800464a: d005 beq.n 8004658 800464c: 687b ldr r3, [r7, #4] 800464e: 681b ldr r3, [r3, #0] 8004650: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004654: f040 80ff bne.w 8004856 { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8004658: 4b09 ldr r3, [pc, #36] @ (8004680 ) 800465a: 2200 movs r2, #0 800465c: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800465e: f7fd fa85 bl 8001b6c 8004662: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004664: e00e b.n 8004684 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004666: f7fd fa81 bl 8001b6c 800466a: 4602 mov r2, r0 800466c: 6a7b ldr r3, [r7, #36] @ 0x24 800466e: 1ad3 subs r3, r2, r3 8004670: 2b02 cmp r3, #2 8004672: d907 bls.n 8004684 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004674: 2303 movs r3, #3 8004676: e188 b.n 800498a 8004678: 40023800 .word 0x40023800 800467c: 424711e0 .word 0x424711e0 8004680: 42470068 .word 0x42470068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004684: 4b7e ldr r3, [pc, #504] @ (8004880 ) 8004686: 681b ldr r3, [r3, #0] 8004688: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800468c: 2b00 cmp r3, #0 800468e: d1ea bne.n 8004666 /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) 8004690: 687b ldr r3, [r7, #4] 8004692: 681b ldr r3, [r3, #0] 8004694: f003 0301 and.w r3, r3, #1 8004698: 2b00 cmp r3, #0 800469a: d003 beq.n 80046a4 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 800469c: 687b ldr r3, [r7, #4] 800469e: 6b9b ldr r3, [r3, #56] @ 0x38 80046a0: 2b00 cmp r3, #0 80046a2: d009 beq.n 80046b8 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 80046a4: 687b ldr r3, [r7, #4] 80046a6: 681b ldr r3, [r3, #0] 80046a8: f003 0302 and.w r3, r3, #2 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 80046ac: 2b00 cmp r3, #0 80046ae: d028 beq.n 8004702 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 80046b0: 687b ldr r3, [r7, #4] 80046b2: 6bdb ldr r3, [r3, #60] @ 0x3c 80046b4: 2b00 cmp r3, #0 80046b6: d124 bne.n 8004702 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 80046b8: 4b71 ldr r3, [pc, #452] @ (8004880 ) 80046ba: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80046be: 0c1b lsrs r3, r3, #16 80046c0: f003 0303 and.w r3, r3, #3 80046c4: 3301 adds r3, #1 80046c6: 005b lsls r3, r3, #1 80046c8: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 80046ca: 4b6d ldr r3, [pc, #436] @ (8004880 ) 80046cc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80046d0: 0e1b lsrs r3, r3, #24 80046d2: f003 030f and.w r3, r3, #15 80046d6: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, 80046d8: 687b ldr r3, [r7, #4] 80046da: 685a ldr r2, [r3, #4] 80046dc: 687b ldr r3, [r7, #4] 80046de: 689b ldr r3, [r3, #8] 80046e0: 019b lsls r3, r3, #6 80046e2: 431a orrs r2, r3 80046e4: 69fb ldr r3, [r7, #28] 80046e6: 085b lsrs r3, r3, #1 80046e8: 3b01 subs r3, #1 80046ea: 041b lsls r3, r3, #16 80046ec: 431a orrs r2, r3 80046ee: 69bb ldr r3, [r7, #24] 80046f0: 061b lsls r3, r3, #24 80046f2: 431a orrs r2, r3 80046f4: 687b ldr r3, [r7, #4] 80046f6: 695b ldr r3, [r3, #20] 80046f8: 071b lsls r3, r3, #28 80046fa: 4961 ldr r1, [pc, #388] @ (8004880 ) 80046fc: 4313 orrs r3, r2 80046fe: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004702: 687b ldr r3, [r7, #4] 8004704: 681b ldr r3, [r3, #0] 8004706: f003 0304 and.w r3, r3, #4 800470a: 2b00 cmp r3, #0 800470c: d004 beq.n 8004718 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 800470e: 687b ldr r3, [r7, #4] 8004710: 6b1b ldr r3, [r3, #48] @ 0x30 8004712: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8004716: d00a beq.n 800472e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004718: 687b ldr r3, [r7, #4] 800471a: 681b ldr r3, [r3, #0] 800471c: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 8004720: 2b00 cmp r3, #0 8004722: d035 beq.n 8004790 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004724: 687b ldr r3, [r7, #4] 8004726: 6b5b ldr r3, [r3, #52] @ 0x34 8004728: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800472c: d130 bne.n 8004790 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 800472e: 4b54 ldr r3, [pc, #336] @ (8004880 ) 8004730: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004734: 0c1b lsrs r3, r3, #16 8004736: f003 0303 and.w r3, r3, #3 800473a: 3301 adds r3, #1 800473c: 005b lsls r3, r3, #1 800473e: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004740: 4b4f ldr r3, [pc, #316] @ (8004880 ) 8004742: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004746: 0f1b lsrs r3, r3, #28 8004748: f003 0307 and.w r3, r3, #7 800474c: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, 800474e: 687b ldr r3, [r7, #4] 8004750: 685a ldr r2, [r3, #4] 8004752: 687b ldr r3, [r7, #4] 8004754: 689b ldr r3, [r3, #8] 8004756: 019b lsls r3, r3, #6 8004758: 431a orrs r2, r3 800475a: 69fb ldr r3, [r7, #28] 800475c: 085b lsrs r3, r3, #1 800475e: 3b01 subs r3, #1 8004760: 041b lsls r3, r3, #16 8004762: 431a orrs r2, r3 8004764: 687b ldr r3, [r7, #4] 8004766: 691b ldr r3, [r3, #16] 8004768: 061b lsls r3, r3, #24 800476a: 431a orrs r2, r3 800476c: 697b ldr r3, [r7, #20] 800476e: 071b lsls r3, r3, #28 8004770: 4943 ldr r1, [pc, #268] @ (8004880 ) 8004772: 4313 orrs r3, r2 8004774: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004778: 4b41 ldr r3, [pc, #260] @ (8004880 ) 800477a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800477e: f023 021f bic.w r2, r3, #31 8004782: 687b ldr r3, [r7, #4] 8004784: 6a9b ldr r3, [r3, #40] @ 0x28 8004786: 3b01 subs r3, #1 8004788: 493d ldr r1, [pc, #244] @ (8004880 ) 800478a: 4313 orrs r3, r2 800478c: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004790: 687b ldr r3, [r7, #4] 8004792: 681b ldr r3, [r3, #0] 8004794: f403 6380 and.w r3, r3, #1024 @ 0x400 8004798: 2b00 cmp r3, #0 800479a: d029 beq.n 80047f0 && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 800479c: 687b ldr r3, [r7, #4] 800479e: 6d1b ldr r3, [r3, #80] @ 0x50 80047a0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80047a4: d124 bne.n 80047f0 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 80047a6: 4b36 ldr r3, [pc, #216] @ (8004880 ) 80047a8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80047ac: 0c1b lsrs r3, r3, #16 80047ae: f003 0303 and.w r3, r3, #3 80047b2: 3301 adds r3, #1 80047b4: 005b lsls r3, r3, #1 80047b6: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 80047b8: 4b31 ldr r3, [pc, #196] @ (8004880 ) 80047ba: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80047be: 0f1b lsrs r3, r3, #28 80047c0: f003 0307 and.w r3, r3, #7 80047c4: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 80047c6: 687b ldr r3, [r7, #4] 80047c8: 685a ldr r2, [r3, #4] 80047ca: 687b ldr r3, [r7, #4] 80047cc: 689b ldr r3, [r3, #8] 80047ce: 019b lsls r3, r3, #6 80047d0: 431a orrs r2, r3 80047d2: 687b ldr r3, [r7, #4] 80047d4: 68db ldr r3, [r3, #12] 80047d6: 085b lsrs r3, r3, #1 80047d8: 3b01 subs r3, #1 80047da: 041b lsls r3, r3, #16 80047dc: 431a orrs r2, r3 80047de: 69bb ldr r3, [r7, #24] 80047e0: 061b lsls r3, r3, #24 80047e2: 431a orrs r2, r3 80047e4: 697b ldr r3, [r7, #20] 80047e6: 071b lsls r3, r3, #28 80047e8: 4925 ldr r1, [pc, #148] @ (8004880 ) 80047ea: 4313 orrs r3, r2 80047ec: f8c1 3084 str.w r3, [r1, #132] @ 0x84 plli2sq, plli2sr); } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 80047f0: 687b ldr r3, [r7, #4] 80047f2: 681b ldr r3, [r3, #0] 80047f4: f403 6300 and.w r3, r3, #2048 @ 0x800 80047f8: 2b00 cmp r3, #0 80047fa: d016 beq.n 800482a assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 80047fc: 687b ldr r3, [r7, #4] 80047fe: 685a ldr r2, [r3, #4] 8004800: 687b ldr r3, [r7, #4] 8004802: 689b ldr r3, [r3, #8] 8004804: 019b lsls r3, r3, #6 8004806: 431a orrs r2, r3 8004808: 687b ldr r3, [r7, #4] 800480a: 68db ldr r3, [r3, #12] 800480c: 085b lsrs r3, r3, #1 800480e: 3b01 subs r3, #1 8004810: 041b lsls r3, r3, #16 8004812: 431a orrs r2, r3 8004814: 687b ldr r3, [r7, #4] 8004816: 691b ldr r3, [r3, #16] 8004818: 061b lsls r3, r3, #24 800481a: 431a orrs r2, r3 800481c: 687b ldr r3, [r7, #4] 800481e: 695b ldr r3, [r3, #20] 8004820: 071b lsls r3, r3, #28 8004822: 4917 ldr r1, [pc, #92] @ (8004880 ) 8004824: 4313 orrs r3, r2 8004826: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 800482a: 4b16 ldr r3, [pc, #88] @ (8004884 ) 800482c: 2201 movs r2, #1 800482e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004830: f7fd f99c bl 8001b6c 8004834: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004836: e008 b.n 800484a { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004838: f7fd f998 bl 8001b6c 800483c: 4602 mov r2, r0 800483e: 6a7b ldr r3, [r7, #36] @ 0x24 8004840: 1ad3 subs r3, r2, r3 8004842: 2b02 cmp r3, #2 8004844: d901 bls.n 800484a { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004846: 2303 movs r3, #3 8004848: e09f b.n 800498a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 800484a: 4b0d ldr r3, [pc, #52] @ (8004880 ) 800484c: 681b ldr r3, [r3, #0] 800484e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004852: 2b00 cmp r3, #0 8004854: d0f0 beq.n 8004838 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if (pllsaiused == 1U) 8004856: 6abb ldr r3, [r7, #40] @ 0x28 8004858: 2b01 cmp r3, #1 800485a: f040 8095 bne.w 8004988 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 800485e: 4b0a ldr r3, [pc, #40] @ (8004888 ) 8004860: 2200 movs r2, #0 8004862: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004864: f7fd f982 bl 8001b6c 8004868: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 800486a: e00f b.n 800488c { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 800486c: f7fd f97e bl 8001b6c 8004870: 4602 mov r2, r0 8004872: 6a7b ldr r3, [r7, #36] @ 0x24 8004874: 1ad3 subs r3, r2, r3 8004876: 2b02 cmp r3, #2 8004878: d908 bls.n 800488c { /* return in case of Timeout detected */ return HAL_TIMEOUT; 800487a: 2303 movs r3, #3 800487c: e085 b.n 800498a 800487e: bf00 nop 8004880: 40023800 .word 0x40023800 8004884: 42470068 .word 0x42470068 8004888: 42470070 .word 0x42470070 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 800488c: 4b41 ldr r3, [pc, #260] @ (8004994 ) 800488e: 681b ldr r3, [r3, #0] 8004890: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004894: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004898: d0e8 beq.n 800486c /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800489a: 687b ldr r3, [r7, #4] 800489c: 681b ldr r3, [r3, #0] 800489e: f003 0304 and.w r3, r3, #4 80048a2: 2b00 cmp r3, #0 80048a4: d003 beq.n 80048ae && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 80048a6: 687b ldr r3, [r7, #4] 80048a8: 6b1b ldr r3, [r3, #48] @ 0x30 80048aa: 2b00 cmp r3, #0 80048ac: d009 beq.n 80048c2 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 80048ae: 687b ldr r3, [r7, #4] 80048b0: 681b ldr r3, [r3, #0] 80048b2: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 80048b6: 2b00 cmp r3, #0 80048b8: d02b beq.n 8004912 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 80048ba: 687b ldr r3, [r7, #4] 80048bc: 6b5b ldr r3, [r3, #52] @ 0x34 80048be: 2b00 cmp r3, #0 80048c0: d127 bne.n 8004912 assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 80048c2: 4b34 ldr r3, [pc, #208] @ (8004994 ) 80048c4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80048c8: 0c1b lsrs r3, r3, #16 80048ca: f003 0303 and.w r3, r3, #3 80048ce: 3301 adds r3, #1 80048d0: 005b lsls r3, r3, #1 80048d2: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, 80048d4: 687b ldr r3, [r7, #4] 80048d6: 699a ldr r2, [r3, #24] 80048d8: 687b ldr r3, [r7, #4] 80048da: 69db ldr r3, [r3, #28] 80048dc: 019b lsls r3, r3, #6 80048de: 431a orrs r2, r3 80048e0: 693b ldr r3, [r7, #16] 80048e2: 085b lsrs r3, r3, #1 80048e4: 3b01 subs r3, #1 80048e6: 041b lsls r3, r3, #16 80048e8: 431a orrs r2, r3 80048ea: 687b ldr r3, [r7, #4] 80048ec: 6a5b ldr r3, [r3, #36] @ 0x24 80048ee: 061b lsls r3, r3, #24 80048f0: 4928 ldr r1, [pc, #160] @ (8004994 ) 80048f2: 4313 orrs r3, r2 80048f4: f8c1 3088 str.w r3, [r1, #136] @ 0x88 PeriphClkInit->PLLSAI.PLLSAIQ, 0U); /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 80048f8: 4b26 ldr r3, [pc, #152] @ (8004994 ) 80048fa: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80048fe: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 8004902: 687b ldr r3, [r7, #4] 8004904: 6adb ldr r3, [r3, #44] @ 0x2c 8004906: 3b01 subs r3, #1 8004908: 021b lsls r3, r3, #8 800490a: 4922 ldr r1, [pc, #136] @ (8004994 ) 800490c: 4313 orrs r3, r2 800490e: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 8004912: 687b ldr r3, [r7, #4] 8004914: 681b ldr r3, [r3, #0] 8004916: f403 7380 and.w r3, r3, #256 @ 0x100 800491a: 2b00 cmp r3, #0 800491c: d01d beq.n 800495a && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 800491e: 687b ldr r3, [r7, #4] 8004920: 6d5b ldr r3, [r3, #84] @ 0x54 8004922: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004926: d118 bne.n 800495a { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 8004928: 4b1a ldr r3, [pc, #104] @ (8004994 ) 800492a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800492e: 0e1b lsrs r3, r3, #24 8004930: f003 030f and.w r3, r3, #15 8004934: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, 8004936: 687b ldr r3, [r7, #4] 8004938: 699a ldr r2, [r3, #24] 800493a: 687b ldr r3, [r7, #4] 800493c: 69db ldr r3, [r3, #28] 800493e: 019b lsls r3, r3, #6 8004940: 431a orrs r2, r3 8004942: 687b ldr r3, [r7, #4] 8004944: 6a1b ldr r3, [r3, #32] 8004946: 085b lsrs r3, r3, #1 8004948: 3b01 subs r3, #1 800494a: 041b lsls r3, r3, #16 800494c: 431a orrs r2, r3 800494e: 68fb ldr r3, [r7, #12] 8004950: 061b lsls r3, r3, #24 8004952: 4910 ldr r1, [pc, #64] @ (8004994 ) 8004954: 4313 orrs r3, r2 8004956: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pllsaiq, 0U); } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 800495a: 4b0f ldr r3, [pc, #60] @ (8004998 ) 800495c: 2201 movs r2, #1 800495e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004960: f7fd f904 bl 8001b6c 8004964: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004966: e008 b.n 800497a { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004968: f7fd f900 bl 8001b6c 800496c: 4602 mov r2, r0 800496e: 6a7b ldr r3, [r7, #36] @ 0x24 8004970: 1ad3 subs r3, r2, r3 8004972: 2b02 cmp r3, #2 8004974: d901 bls.n 800497a { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004976: 2303 movs r3, #3 8004978: e007 b.n 800498a while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 800497a: 4b06 ldr r3, [pc, #24] @ (8004994 ) 800497c: 681b ldr r3, [r3, #0] 800497e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004982: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004986: d1ef bne.n 8004968 } } } return HAL_OK; 8004988: 2300 movs r3, #0 } 800498a: 4618 mov r0, r3 800498c: 3730 adds r7, #48 @ 0x30 800498e: 46bd mov sp, r7 8004990: bd80 pop {r7, pc} 8004992: bf00 nop 8004994: 40023800 .word 0x40023800 8004998: 42470070 .word 0x42470070 0800499c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800499c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80049a0: b0ae sub sp, #184 @ 0xb8 80049a2: af00 add r7, sp, #0 uint32_t pllm = 0U; 80049a4: 2300 movs r3, #0 80049a6: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t pllvco = 0U; 80049aa: 2300 movs r3, #0 80049ac: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t pllp = 0U; 80049b0: 2300 movs r3, #0 80049b2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 uint32_t pllr = 0U; 80049b6: 2300 movs r3, #0 80049b8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t sysclockfreq = 0U; 80049bc: 2300 movs r3, #0 80049be: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 80049c2: 4bcb ldr r3, [pc, #812] @ (8004cf0 ) 80049c4: 689b ldr r3, [r3, #8] 80049c6: f003 030c and.w r3, r3, #12 80049ca: 2b0c cmp r3, #12 80049cc: f200 8206 bhi.w 8004ddc 80049d0: a201 add r2, pc, #4 @ (adr r2, 80049d8 ) 80049d2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80049d6: bf00 nop 80049d8: 08004a0d .word 0x08004a0d 80049dc: 08004ddd .word 0x08004ddd 80049e0: 08004ddd .word 0x08004ddd 80049e4: 08004ddd .word 0x08004ddd 80049e8: 08004a15 .word 0x08004a15 80049ec: 08004ddd .word 0x08004ddd 80049f0: 08004ddd .word 0x08004ddd 80049f4: 08004ddd .word 0x08004ddd 80049f8: 08004a1d .word 0x08004a1d 80049fc: 08004ddd .word 0x08004ddd 8004a00: 08004ddd .word 0x08004ddd 8004a04: 08004ddd .word 0x08004ddd 8004a08: 08004c0d .word 0x08004c0d { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8004a0c: 4bb9 ldr r3, [pc, #740] @ (8004cf4 ) 8004a0e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004a12: e1e7 b.n 8004de4 } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8004a14: 4bb8 ldr r3, [pc, #736] @ (8004cf8 ) 8004a16: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004a1a: e1e3 b.n 8004de4 } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004a1c: 4bb4 ldr r3, [pc, #720] @ (8004cf0 ) 8004a1e: 685b ldr r3, [r3, #4] 8004a20: f003 033f and.w r3, r3, #63 @ 0x3f 8004a24: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004a28: 4bb1 ldr r3, [pc, #708] @ (8004cf0 ) 8004a2a: 685b ldr r3, [r3, #4] 8004a2c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004a30: 2b00 cmp r3, #0 8004a32: d071 beq.n 8004b18 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004a34: 4bae ldr r3, [pc, #696] @ (8004cf0 ) 8004a36: 685b ldr r3, [r3, #4] 8004a38: 099b lsrs r3, r3, #6 8004a3a: 2200 movs r2, #0 8004a3c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8004a40: f8c7 209c str.w r2, [r7, #156] @ 0x9c 8004a44: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8004a48: f3c3 0308 ubfx r3, r3, #0, #9 8004a4c: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8004a50: 2300 movs r3, #0 8004a52: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8004a56: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8004a5a: 4622 mov r2, r4 8004a5c: 462b mov r3, r5 8004a5e: f04f 0000 mov.w r0, #0 8004a62: f04f 0100 mov.w r1, #0 8004a66: 0159 lsls r1, r3, #5 8004a68: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004a6c: 0150 lsls r0, r2, #5 8004a6e: 4602 mov r2, r0 8004a70: 460b mov r3, r1 8004a72: 4621 mov r1, r4 8004a74: 1a51 subs r1, r2, r1 8004a76: 6439 str r1, [r7, #64] @ 0x40 8004a78: 4629 mov r1, r5 8004a7a: eb63 0301 sbc.w r3, r3, r1 8004a7e: 647b str r3, [r7, #68] @ 0x44 8004a80: f04f 0200 mov.w r2, #0 8004a84: f04f 0300 mov.w r3, #0 8004a88: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 8004a8c: 4649 mov r1, r9 8004a8e: 018b lsls r3, r1, #6 8004a90: 4641 mov r1, r8 8004a92: ea43 6391 orr.w r3, r3, r1, lsr #26 8004a96: 4641 mov r1, r8 8004a98: 018a lsls r2, r1, #6 8004a9a: 4641 mov r1, r8 8004a9c: 1a51 subs r1, r2, r1 8004a9e: 63b9 str r1, [r7, #56] @ 0x38 8004aa0: 4649 mov r1, r9 8004aa2: eb63 0301 sbc.w r3, r3, r1 8004aa6: 63fb str r3, [r7, #60] @ 0x3c 8004aa8: f04f 0200 mov.w r2, #0 8004aac: f04f 0300 mov.w r3, #0 8004ab0: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 8004ab4: 4649 mov r1, r9 8004ab6: 00cb lsls r3, r1, #3 8004ab8: 4641 mov r1, r8 8004aba: ea43 7351 orr.w r3, r3, r1, lsr #29 8004abe: 4641 mov r1, r8 8004ac0: 00ca lsls r2, r1, #3 8004ac2: 4610 mov r0, r2 8004ac4: 4619 mov r1, r3 8004ac6: 4603 mov r3, r0 8004ac8: 4622 mov r2, r4 8004aca: 189b adds r3, r3, r2 8004acc: 633b str r3, [r7, #48] @ 0x30 8004ace: 462b mov r3, r5 8004ad0: 460a mov r2, r1 8004ad2: eb42 0303 adc.w r3, r2, r3 8004ad6: 637b str r3, [r7, #52] @ 0x34 8004ad8: f04f 0200 mov.w r2, #0 8004adc: f04f 0300 mov.w r3, #0 8004ae0: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 8004ae4: 4629 mov r1, r5 8004ae6: 024b lsls r3, r1, #9 8004ae8: 4621 mov r1, r4 8004aea: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004aee: 4621 mov r1, r4 8004af0: 024a lsls r2, r1, #9 8004af2: 4610 mov r0, r2 8004af4: 4619 mov r1, r3 8004af6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004afa: 2200 movs r2, #0 8004afc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8004b00: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8004b04: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 8004b08: f7fb fb7c bl 8000204 <__aeabi_uldivmod> 8004b0c: 4602 mov r2, r0 8004b0e: 460b mov r3, r1 8004b10: 4613 mov r3, r2 8004b12: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004b16: e067 b.n 8004be8 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004b18: 4b75 ldr r3, [pc, #468] @ (8004cf0 ) 8004b1a: 685b ldr r3, [r3, #4] 8004b1c: 099b lsrs r3, r3, #6 8004b1e: 2200 movs r2, #0 8004b20: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004b24: f8c7 2084 str.w r2, [r7, #132] @ 0x84 8004b28: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004b2c: f3c3 0308 ubfx r3, r3, #0, #9 8004b30: 67bb str r3, [r7, #120] @ 0x78 8004b32: 2300 movs r3, #0 8004b34: 67fb str r3, [r7, #124] @ 0x7c 8004b36: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 8004b3a: 4622 mov r2, r4 8004b3c: 462b mov r3, r5 8004b3e: f04f 0000 mov.w r0, #0 8004b42: f04f 0100 mov.w r1, #0 8004b46: 0159 lsls r1, r3, #5 8004b48: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004b4c: 0150 lsls r0, r2, #5 8004b4e: 4602 mov r2, r0 8004b50: 460b mov r3, r1 8004b52: 4621 mov r1, r4 8004b54: 1a51 subs r1, r2, r1 8004b56: 62b9 str r1, [r7, #40] @ 0x28 8004b58: 4629 mov r1, r5 8004b5a: eb63 0301 sbc.w r3, r3, r1 8004b5e: 62fb str r3, [r7, #44] @ 0x2c 8004b60: f04f 0200 mov.w r2, #0 8004b64: f04f 0300 mov.w r3, #0 8004b68: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 8004b6c: 4649 mov r1, r9 8004b6e: 018b lsls r3, r1, #6 8004b70: 4641 mov r1, r8 8004b72: ea43 6391 orr.w r3, r3, r1, lsr #26 8004b76: 4641 mov r1, r8 8004b78: 018a lsls r2, r1, #6 8004b7a: 4641 mov r1, r8 8004b7c: ebb2 0a01 subs.w sl, r2, r1 8004b80: 4649 mov r1, r9 8004b82: eb63 0b01 sbc.w fp, r3, r1 8004b86: f04f 0200 mov.w r2, #0 8004b8a: f04f 0300 mov.w r3, #0 8004b8e: ea4f 03cb mov.w r3, fp, lsl #3 8004b92: ea43 735a orr.w r3, r3, sl, lsr #29 8004b96: ea4f 02ca mov.w r2, sl, lsl #3 8004b9a: 4692 mov sl, r2 8004b9c: 469b mov fp, r3 8004b9e: 4623 mov r3, r4 8004ba0: eb1a 0303 adds.w r3, sl, r3 8004ba4: 623b str r3, [r7, #32] 8004ba6: 462b mov r3, r5 8004ba8: eb4b 0303 adc.w r3, fp, r3 8004bac: 627b str r3, [r7, #36] @ 0x24 8004bae: f04f 0200 mov.w r2, #0 8004bb2: f04f 0300 mov.w r3, #0 8004bb6: e9d7 4508 ldrd r4, r5, [r7, #32] 8004bba: 4629 mov r1, r5 8004bbc: 028b lsls r3, r1, #10 8004bbe: 4621 mov r1, r4 8004bc0: ea43 5391 orr.w r3, r3, r1, lsr #22 8004bc4: 4621 mov r1, r4 8004bc6: 028a lsls r2, r1, #10 8004bc8: 4610 mov r0, r2 8004bca: 4619 mov r1, r3 8004bcc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004bd0: 2200 movs r2, #0 8004bd2: 673b str r3, [r7, #112] @ 0x70 8004bd4: 677a str r2, [r7, #116] @ 0x74 8004bd6: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 8004bda: f7fb fb13 bl 8000204 <__aeabi_uldivmod> 8004bde: 4602 mov r2, r0 8004be0: 460b mov r3, r1 8004be2: 4613 mov r3, r2 8004be4: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004be8: 4b41 ldr r3, [pc, #260] @ (8004cf0 ) 8004bea: 685b ldr r3, [r3, #4] 8004bec: 0c1b lsrs r3, r3, #16 8004bee: f003 0303 and.w r3, r3, #3 8004bf2: 3301 adds r3, #1 8004bf4: 005b lsls r3, r3, #1 8004bf6: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 sysclockfreq = pllvco / pllp; 8004bfa: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004bfe: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8004c02: fbb2 f3f3 udiv r3, r2, r3 8004c06: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004c0a: e0eb b.n 8004de4 } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004c0c: 4b38 ldr r3, [pc, #224] @ (8004cf0 ) 8004c0e: 685b ldr r3, [r3, #4] 8004c10: f003 033f and.w r3, r3, #63 @ 0x3f 8004c14: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004c18: 4b35 ldr r3, [pc, #212] @ (8004cf0 ) 8004c1a: 685b ldr r3, [r3, #4] 8004c1c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004c20: 2b00 cmp r3, #0 8004c22: d06b beq.n 8004cfc { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004c24: 4b32 ldr r3, [pc, #200] @ (8004cf0 ) 8004c26: 685b ldr r3, [r3, #4] 8004c28: 099b lsrs r3, r3, #6 8004c2a: 2200 movs r2, #0 8004c2c: 66bb str r3, [r7, #104] @ 0x68 8004c2e: 66fa str r2, [r7, #108] @ 0x6c 8004c30: 6ebb ldr r3, [r7, #104] @ 0x68 8004c32: f3c3 0308 ubfx r3, r3, #0, #9 8004c36: 663b str r3, [r7, #96] @ 0x60 8004c38: 2300 movs r3, #0 8004c3a: 667b str r3, [r7, #100] @ 0x64 8004c3c: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 8004c40: 4622 mov r2, r4 8004c42: 462b mov r3, r5 8004c44: f04f 0000 mov.w r0, #0 8004c48: f04f 0100 mov.w r1, #0 8004c4c: 0159 lsls r1, r3, #5 8004c4e: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004c52: 0150 lsls r0, r2, #5 8004c54: 4602 mov r2, r0 8004c56: 460b mov r3, r1 8004c58: 4621 mov r1, r4 8004c5a: 1a51 subs r1, r2, r1 8004c5c: 61b9 str r1, [r7, #24] 8004c5e: 4629 mov r1, r5 8004c60: eb63 0301 sbc.w r3, r3, r1 8004c64: 61fb str r3, [r7, #28] 8004c66: f04f 0200 mov.w r2, #0 8004c6a: f04f 0300 mov.w r3, #0 8004c6e: e9d7 ab06 ldrd sl, fp, [r7, #24] 8004c72: 4659 mov r1, fp 8004c74: 018b lsls r3, r1, #6 8004c76: 4651 mov r1, sl 8004c78: ea43 6391 orr.w r3, r3, r1, lsr #26 8004c7c: 4651 mov r1, sl 8004c7e: 018a lsls r2, r1, #6 8004c80: 4651 mov r1, sl 8004c82: ebb2 0801 subs.w r8, r2, r1 8004c86: 4659 mov r1, fp 8004c88: eb63 0901 sbc.w r9, r3, r1 8004c8c: f04f 0200 mov.w r2, #0 8004c90: f04f 0300 mov.w r3, #0 8004c94: ea4f 03c9 mov.w r3, r9, lsl #3 8004c98: ea43 7358 orr.w r3, r3, r8, lsr #29 8004c9c: ea4f 02c8 mov.w r2, r8, lsl #3 8004ca0: 4690 mov r8, r2 8004ca2: 4699 mov r9, r3 8004ca4: 4623 mov r3, r4 8004ca6: eb18 0303 adds.w r3, r8, r3 8004caa: 613b str r3, [r7, #16] 8004cac: 462b mov r3, r5 8004cae: eb49 0303 adc.w r3, r9, r3 8004cb2: 617b str r3, [r7, #20] 8004cb4: f04f 0200 mov.w r2, #0 8004cb8: f04f 0300 mov.w r3, #0 8004cbc: e9d7 4504 ldrd r4, r5, [r7, #16] 8004cc0: 4629 mov r1, r5 8004cc2: 024b lsls r3, r1, #9 8004cc4: 4621 mov r1, r4 8004cc6: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004cca: 4621 mov r1, r4 8004ccc: 024a lsls r2, r1, #9 8004cce: 4610 mov r0, r2 8004cd0: 4619 mov r1, r3 8004cd2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004cd6: 2200 movs r2, #0 8004cd8: 65bb str r3, [r7, #88] @ 0x58 8004cda: 65fa str r2, [r7, #92] @ 0x5c 8004cdc: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8004ce0: f7fb fa90 bl 8000204 <__aeabi_uldivmod> 8004ce4: 4602 mov r2, r0 8004ce6: 460b mov r3, r1 8004ce8: 4613 mov r3, r2 8004cea: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004cee: e065 b.n 8004dbc 8004cf0: 40023800 .word 0x40023800 8004cf4: 00f42400 .word 0x00f42400 8004cf8: 007a1200 .word 0x007a1200 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004cfc: 4b3d ldr r3, [pc, #244] @ (8004df4 ) 8004cfe: 685b ldr r3, [r3, #4] 8004d00: 099b lsrs r3, r3, #6 8004d02: 2200 movs r2, #0 8004d04: 4618 mov r0, r3 8004d06: 4611 mov r1, r2 8004d08: f3c0 0308 ubfx r3, r0, #0, #9 8004d0c: 653b str r3, [r7, #80] @ 0x50 8004d0e: 2300 movs r3, #0 8004d10: 657b str r3, [r7, #84] @ 0x54 8004d12: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 8004d16: 4642 mov r2, r8 8004d18: 464b mov r3, r9 8004d1a: f04f 0000 mov.w r0, #0 8004d1e: f04f 0100 mov.w r1, #0 8004d22: 0159 lsls r1, r3, #5 8004d24: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004d28: 0150 lsls r0, r2, #5 8004d2a: 4602 mov r2, r0 8004d2c: 460b mov r3, r1 8004d2e: 4641 mov r1, r8 8004d30: 1a51 subs r1, r2, r1 8004d32: 60b9 str r1, [r7, #8] 8004d34: 4649 mov r1, r9 8004d36: eb63 0301 sbc.w r3, r3, r1 8004d3a: 60fb str r3, [r7, #12] 8004d3c: f04f 0200 mov.w r2, #0 8004d40: f04f 0300 mov.w r3, #0 8004d44: e9d7 ab02 ldrd sl, fp, [r7, #8] 8004d48: 4659 mov r1, fp 8004d4a: 018b lsls r3, r1, #6 8004d4c: 4651 mov r1, sl 8004d4e: ea43 6391 orr.w r3, r3, r1, lsr #26 8004d52: 4651 mov r1, sl 8004d54: 018a lsls r2, r1, #6 8004d56: 4651 mov r1, sl 8004d58: 1a54 subs r4, r2, r1 8004d5a: 4659 mov r1, fp 8004d5c: eb63 0501 sbc.w r5, r3, r1 8004d60: f04f 0200 mov.w r2, #0 8004d64: f04f 0300 mov.w r3, #0 8004d68: 00eb lsls r3, r5, #3 8004d6a: ea43 7354 orr.w r3, r3, r4, lsr #29 8004d6e: 00e2 lsls r2, r4, #3 8004d70: 4614 mov r4, r2 8004d72: 461d mov r5, r3 8004d74: 4643 mov r3, r8 8004d76: 18e3 adds r3, r4, r3 8004d78: 603b str r3, [r7, #0] 8004d7a: 464b mov r3, r9 8004d7c: eb45 0303 adc.w r3, r5, r3 8004d80: 607b str r3, [r7, #4] 8004d82: f04f 0200 mov.w r2, #0 8004d86: f04f 0300 mov.w r3, #0 8004d8a: e9d7 4500 ldrd r4, r5, [r7] 8004d8e: 4629 mov r1, r5 8004d90: 028b lsls r3, r1, #10 8004d92: 4621 mov r1, r4 8004d94: ea43 5391 orr.w r3, r3, r1, lsr #22 8004d98: 4621 mov r1, r4 8004d9a: 028a lsls r2, r1, #10 8004d9c: 4610 mov r0, r2 8004d9e: 4619 mov r1, r3 8004da0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004da4: 2200 movs r2, #0 8004da6: 64bb str r3, [r7, #72] @ 0x48 8004da8: 64fa str r2, [r7, #76] @ 0x4c 8004daa: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8004dae: f7fb fa29 bl 8000204 <__aeabi_uldivmod> 8004db2: 4602 mov r2, r0 8004db4: 460b mov r3, r1 8004db6: 4613 mov r3, r2 8004db8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 8004dbc: 4b0d ldr r3, [pc, #52] @ (8004df4 ) 8004dbe: 685b ldr r3, [r3, #4] 8004dc0: 0f1b lsrs r3, r3, #28 8004dc2: f003 0307 and.w r3, r3, #7 8004dc6: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 sysclockfreq = pllvco / pllr; 8004dca: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004dce: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8004dd2: fbb2 f3f3 udiv r3, r2, r3 8004dd6: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004dda: e003 b.n 8004de4 } default: { sysclockfreq = HSI_VALUE; 8004ddc: 4b06 ldr r3, [pc, #24] @ (8004df8 ) 8004dde: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004de2: bf00 nop } } return sysclockfreq; 8004de4: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 } 8004de8: 4618 mov r0, r3 8004dea: 37b8 adds r7, #184 @ 0xb8 8004dec: 46bd mov sp, r7 8004dee: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8004df2: bf00 nop 8004df4: 40023800 .word 0x40023800 8004df8: 00f42400 .word 0x00f42400 08004dfc : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004dfc: b580 push {r7, lr} 8004dfe: b086 sub sp, #24 8004e00: af00 add r7, sp, #0 8004e02: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8004e04: 687b ldr r3, [r7, #4] 8004e06: 2b00 cmp r3, #0 8004e08: d101 bne.n 8004e0e { return HAL_ERROR; 8004e0a: 2301 movs r3, #1 8004e0c: e28d b.n 800532a } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004e0e: 687b ldr r3, [r7, #4] 8004e10: 681b ldr r3, [r3, #0] 8004e12: f003 0301 and.w r3, r3, #1 8004e16: 2b00 cmp r3, #0 8004e18: f000 8083 beq.w 8004f22 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8004e1c: 4b94 ldr r3, [pc, #592] @ (8005070 ) 8004e1e: 689b ldr r3, [r3, #8] 8004e20: f003 030c and.w r3, r3, #12 8004e24: 2b04 cmp r3, #4 8004e26: d019 beq.n 8004e5c || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004e28: 4b91 ldr r3, [pc, #580] @ (8005070 ) 8004e2a: 689b ldr r3, [r3, #8] 8004e2c: f003 030c and.w r3, r3, #12 || \ 8004e30: 2b08 cmp r3, #8 8004e32: d106 bne.n 8004e42 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004e34: 4b8e ldr r3, [pc, #568] @ (8005070 ) 8004e36: 685b ldr r3, [r3, #4] 8004e38: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004e3c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004e40: d00c beq.n 8004e5c ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004e42: 4b8b ldr r3, [pc, #556] @ (8005070 ) 8004e44: 689b ldr r3, [r3, #8] 8004e46: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004e4a: 2b0c cmp r3, #12 8004e4c: d112 bne.n 8004e74 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004e4e: 4b88 ldr r3, [pc, #544] @ (8005070 ) 8004e50: 685b ldr r3, [r3, #4] 8004e52: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004e56: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004e5a: d10b bne.n 8004e74 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004e5c: 4b84 ldr r3, [pc, #528] @ (8005070 ) 8004e5e: 681b ldr r3, [r3, #0] 8004e60: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004e64: 2b00 cmp r3, #0 8004e66: d05b beq.n 8004f20 8004e68: 687b ldr r3, [r7, #4] 8004e6a: 685b ldr r3, [r3, #4] 8004e6c: 2b00 cmp r3, #0 8004e6e: d157 bne.n 8004f20 { return HAL_ERROR; 8004e70: 2301 movs r3, #1 8004e72: e25a b.n 800532a } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004e74: 687b ldr r3, [r7, #4] 8004e76: 685b ldr r3, [r3, #4] 8004e78: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004e7c: d106 bne.n 8004e8c 8004e7e: 4b7c ldr r3, [pc, #496] @ (8005070 ) 8004e80: 681b ldr r3, [r3, #0] 8004e82: 4a7b ldr r2, [pc, #492] @ (8005070 ) 8004e84: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004e88: 6013 str r3, [r2, #0] 8004e8a: e01d b.n 8004ec8 8004e8c: 687b ldr r3, [r7, #4] 8004e8e: 685b ldr r3, [r3, #4] 8004e90: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004e94: d10c bne.n 8004eb0 8004e96: 4b76 ldr r3, [pc, #472] @ (8005070 ) 8004e98: 681b ldr r3, [r3, #0] 8004e9a: 4a75 ldr r2, [pc, #468] @ (8005070 ) 8004e9c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8004ea0: 6013 str r3, [r2, #0] 8004ea2: 4b73 ldr r3, [pc, #460] @ (8005070 ) 8004ea4: 681b ldr r3, [r3, #0] 8004ea6: 4a72 ldr r2, [pc, #456] @ (8005070 ) 8004ea8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004eac: 6013 str r3, [r2, #0] 8004eae: e00b b.n 8004ec8 8004eb0: 4b6f ldr r3, [pc, #444] @ (8005070 ) 8004eb2: 681b ldr r3, [r3, #0] 8004eb4: 4a6e ldr r2, [pc, #440] @ (8005070 ) 8004eb6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004eba: 6013 str r3, [r2, #0] 8004ebc: 4b6c ldr r3, [pc, #432] @ (8005070 ) 8004ebe: 681b ldr r3, [r3, #0] 8004ec0: 4a6b ldr r2, [pc, #428] @ (8005070 ) 8004ec2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004ec6: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8004ec8: 687b ldr r3, [r7, #4] 8004eca: 685b ldr r3, [r3, #4] 8004ecc: 2b00 cmp r3, #0 8004ece: d013 beq.n 8004ef8 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004ed0: f7fc fe4c bl 8001b6c 8004ed4: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004ed6: e008 b.n 8004eea { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004ed8: f7fc fe48 bl 8001b6c 8004edc: 4602 mov r2, r0 8004ede: 693b ldr r3, [r7, #16] 8004ee0: 1ad3 subs r3, r2, r3 8004ee2: 2b64 cmp r3, #100 @ 0x64 8004ee4: d901 bls.n 8004eea { return HAL_TIMEOUT; 8004ee6: 2303 movs r3, #3 8004ee8: e21f b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004eea: 4b61 ldr r3, [pc, #388] @ (8005070 ) 8004eec: 681b ldr r3, [r3, #0] 8004eee: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004ef2: 2b00 cmp r3, #0 8004ef4: d0f0 beq.n 8004ed8 8004ef6: e014 b.n 8004f22 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004ef8: f7fc fe38 bl 8001b6c 8004efc: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004efe: e008 b.n 8004f12 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004f00: f7fc fe34 bl 8001b6c 8004f04: 4602 mov r2, r0 8004f06: 693b ldr r3, [r7, #16] 8004f08: 1ad3 subs r3, r2, r3 8004f0a: 2b64 cmp r3, #100 @ 0x64 8004f0c: d901 bls.n 8004f12 { return HAL_TIMEOUT; 8004f0e: 2303 movs r3, #3 8004f10: e20b b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004f12: 4b57 ldr r3, [pc, #348] @ (8005070 ) 8004f14: 681b ldr r3, [r3, #0] 8004f16: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004f1a: 2b00 cmp r3, #0 8004f1c: d1f0 bne.n 8004f00 8004f1e: e000 b.n 8004f22 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004f20: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004f22: 687b ldr r3, [r7, #4] 8004f24: 681b ldr r3, [r3, #0] 8004f26: f003 0302 and.w r3, r3, #2 8004f2a: 2b00 cmp r3, #0 8004f2c: d06f beq.n 800500e assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8004f2e: 4b50 ldr r3, [pc, #320] @ (8005070 ) 8004f30: 689b ldr r3, [r3, #8] 8004f32: f003 030c and.w r3, r3, #12 8004f36: 2b00 cmp r3, #0 8004f38: d017 beq.n 8004f6a || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004f3a: 4b4d ldr r3, [pc, #308] @ (8005070 ) 8004f3c: 689b ldr r3, [r3, #8] 8004f3e: f003 030c and.w r3, r3, #12 || \ 8004f42: 2b08 cmp r3, #8 8004f44: d105 bne.n 8004f52 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004f46: 4b4a ldr r3, [pc, #296] @ (8005070 ) 8004f48: 685b ldr r3, [r3, #4] 8004f4a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004f4e: 2b00 cmp r3, #0 8004f50: d00b beq.n 8004f6a ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004f52: 4b47 ldr r3, [pc, #284] @ (8005070 ) 8004f54: 689b ldr r3, [r3, #8] 8004f56: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004f5a: 2b0c cmp r3, #12 8004f5c: d11c bne.n 8004f98 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004f5e: 4b44 ldr r3, [pc, #272] @ (8005070 ) 8004f60: 685b ldr r3, [r3, #4] 8004f62: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004f66: 2b00 cmp r3, #0 8004f68: d116 bne.n 8004f98 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004f6a: 4b41 ldr r3, [pc, #260] @ (8005070 ) 8004f6c: 681b ldr r3, [r3, #0] 8004f6e: f003 0302 and.w r3, r3, #2 8004f72: 2b00 cmp r3, #0 8004f74: d005 beq.n 8004f82 8004f76: 687b ldr r3, [r7, #4] 8004f78: 68db ldr r3, [r3, #12] 8004f7a: 2b01 cmp r3, #1 8004f7c: d001 beq.n 8004f82 { return HAL_ERROR; 8004f7e: 2301 movs r3, #1 8004f80: e1d3 b.n 800532a } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004f82: 4b3b ldr r3, [pc, #236] @ (8005070 ) 8004f84: 681b ldr r3, [r3, #0] 8004f86: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004f8a: 687b ldr r3, [r7, #4] 8004f8c: 691b ldr r3, [r3, #16] 8004f8e: 00db lsls r3, r3, #3 8004f90: 4937 ldr r1, [pc, #220] @ (8005070 ) 8004f92: 4313 orrs r3, r2 8004f94: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004f96: e03a b.n 800500e } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8004f98: 687b ldr r3, [r7, #4] 8004f9a: 68db ldr r3, [r3, #12] 8004f9c: 2b00 cmp r3, #0 8004f9e: d020 beq.n 8004fe2 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8004fa0: 4b34 ldr r3, [pc, #208] @ (8005074 ) 8004fa2: 2201 movs r2, #1 8004fa4: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004fa6: f7fc fde1 bl 8001b6c 8004faa: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004fac: e008 b.n 8004fc0 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004fae: f7fc fddd bl 8001b6c 8004fb2: 4602 mov r2, r0 8004fb4: 693b ldr r3, [r7, #16] 8004fb6: 1ad3 subs r3, r2, r3 8004fb8: 2b02 cmp r3, #2 8004fba: d901 bls.n 8004fc0 { return HAL_TIMEOUT; 8004fbc: 2303 movs r3, #3 8004fbe: e1b4 b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004fc0: 4b2b ldr r3, [pc, #172] @ (8005070 ) 8004fc2: 681b ldr r3, [r3, #0] 8004fc4: f003 0302 and.w r3, r3, #2 8004fc8: 2b00 cmp r3, #0 8004fca: d0f0 beq.n 8004fae } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004fcc: 4b28 ldr r3, [pc, #160] @ (8005070 ) 8004fce: 681b ldr r3, [r3, #0] 8004fd0: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004fd4: 687b ldr r3, [r7, #4] 8004fd6: 691b ldr r3, [r3, #16] 8004fd8: 00db lsls r3, r3, #3 8004fda: 4925 ldr r1, [pc, #148] @ (8005070 ) 8004fdc: 4313 orrs r3, r2 8004fde: 600b str r3, [r1, #0] 8004fe0: e015 b.n 800500e } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8004fe2: 4b24 ldr r3, [pc, #144] @ (8005074 ) 8004fe4: 2200 movs r2, #0 8004fe6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004fe8: f7fc fdc0 bl 8001b6c 8004fec: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004fee: e008 b.n 8005002 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004ff0: f7fc fdbc bl 8001b6c 8004ff4: 4602 mov r2, r0 8004ff6: 693b ldr r3, [r7, #16] 8004ff8: 1ad3 subs r3, r2, r3 8004ffa: 2b02 cmp r3, #2 8004ffc: d901 bls.n 8005002 { return HAL_TIMEOUT; 8004ffe: 2303 movs r3, #3 8005000: e193 b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8005002: 4b1b ldr r3, [pc, #108] @ (8005070 ) 8005004: 681b ldr r3, [r3, #0] 8005006: f003 0302 and.w r3, r3, #2 800500a: 2b00 cmp r3, #0 800500c: d1f0 bne.n 8004ff0 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800500e: 687b ldr r3, [r7, #4] 8005010: 681b ldr r3, [r3, #0] 8005012: f003 0308 and.w r3, r3, #8 8005016: 2b00 cmp r3, #0 8005018: d036 beq.n 8005088 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800501a: 687b ldr r3, [r7, #4] 800501c: 695b ldr r3, [r3, #20] 800501e: 2b00 cmp r3, #0 8005020: d016 beq.n 8005050 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8005022: 4b15 ldr r3, [pc, #84] @ (8005078 ) 8005024: 2201 movs r2, #1 8005026: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005028: f7fc fda0 bl 8001b6c 800502c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800502e: e008 b.n 8005042 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8005030: f7fc fd9c bl 8001b6c 8005034: 4602 mov r2, r0 8005036: 693b ldr r3, [r7, #16] 8005038: 1ad3 subs r3, r2, r3 800503a: 2b02 cmp r3, #2 800503c: d901 bls.n 8005042 { return HAL_TIMEOUT; 800503e: 2303 movs r3, #3 8005040: e173 b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8005042: 4b0b ldr r3, [pc, #44] @ (8005070 ) 8005044: 6f5b ldr r3, [r3, #116] @ 0x74 8005046: f003 0302 and.w r3, r3, #2 800504a: 2b00 cmp r3, #0 800504c: d0f0 beq.n 8005030 800504e: e01b b.n 8005088 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8005050: 4b09 ldr r3, [pc, #36] @ (8005078 ) 8005052: 2200 movs r2, #0 8005054: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005056: f7fc fd89 bl 8001b6c 800505a: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800505c: e00e b.n 800507c { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800505e: f7fc fd85 bl 8001b6c 8005062: 4602 mov r2, r0 8005064: 693b ldr r3, [r7, #16] 8005066: 1ad3 subs r3, r2, r3 8005068: 2b02 cmp r3, #2 800506a: d907 bls.n 800507c { return HAL_TIMEOUT; 800506c: 2303 movs r3, #3 800506e: e15c b.n 800532a 8005070: 40023800 .word 0x40023800 8005074: 42470000 .word 0x42470000 8005078: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800507c: 4b8a ldr r3, [pc, #552] @ (80052a8 ) 800507e: 6f5b ldr r3, [r3, #116] @ 0x74 8005080: f003 0302 and.w r3, r3, #2 8005084: 2b00 cmp r3, #0 8005086: d1ea bne.n 800505e } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8005088: 687b ldr r3, [r7, #4] 800508a: 681b ldr r3, [r3, #0] 800508c: f003 0304 and.w r3, r3, #4 8005090: 2b00 cmp r3, #0 8005092: f000 8097 beq.w 80051c4 { FlagStatus pwrclkchanged = RESET; 8005096: 2300 movs r3, #0 8005098: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 800509a: 4b83 ldr r3, [pc, #524] @ (80052a8 ) 800509c: 6c1b ldr r3, [r3, #64] @ 0x40 800509e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80050a2: 2b00 cmp r3, #0 80050a4: d10f bne.n 80050c6 { __HAL_RCC_PWR_CLK_ENABLE(); 80050a6: 2300 movs r3, #0 80050a8: 60bb str r3, [r7, #8] 80050aa: 4b7f ldr r3, [pc, #508] @ (80052a8 ) 80050ac: 6c1b ldr r3, [r3, #64] @ 0x40 80050ae: 4a7e ldr r2, [pc, #504] @ (80052a8 ) 80050b0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80050b4: 6413 str r3, [r2, #64] @ 0x40 80050b6: 4b7c ldr r3, [pc, #496] @ (80052a8 ) 80050b8: 6c1b ldr r3, [r3, #64] @ 0x40 80050ba: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80050be: 60bb str r3, [r7, #8] 80050c0: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80050c2: 2301 movs r3, #1 80050c4: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80050c6: 4b79 ldr r3, [pc, #484] @ (80052ac ) 80050c8: 681b ldr r3, [r3, #0] 80050ca: f403 7380 and.w r3, r3, #256 @ 0x100 80050ce: 2b00 cmp r3, #0 80050d0: d118 bne.n 8005104 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80050d2: 4b76 ldr r3, [pc, #472] @ (80052ac ) 80050d4: 681b ldr r3, [r3, #0] 80050d6: 4a75 ldr r2, [pc, #468] @ (80052ac ) 80050d8: f443 7380 orr.w r3, r3, #256 @ 0x100 80050dc: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80050de: f7fc fd45 bl 8001b6c 80050e2: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80050e4: e008 b.n 80050f8 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80050e6: f7fc fd41 bl 8001b6c 80050ea: 4602 mov r2, r0 80050ec: 693b ldr r3, [r7, #16] 80050ee: 1ad3 subs r3, r2, r3 80050f0: 2b02 cmp r3, #2 80050f2: d901 bls.n 80050f8 { return HAL_TIMEOUT; 80050f4: 2303 movs r3, #3 80050f6: e118 b.n 800532a while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80050f8: 4b6c ldr r3, [pc, #432] @ (80052ac ) 80050fa: 681b ldr r3, [r3, #0] 80050fc: f403 7380 and.w r3, r3, #256 @ 0x100 8005100: 2b00 cmp r3, #0 8005102: d0f0 beq.n 80050e6 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8005104: 687b ldr r3, [r7, #4] 8005106: 689b ldr r3, [r3, #8] 8005108: 2b01 cmp r3, #1 800510a: d106 bne.n 800511a 800510c: 4b66 ldr r3, [pc, #408] @ (80052a8 ) 800510e: 6f1b ldr r3, [r3, #112] @ 0x70 8005110: 4a65 ldr r2, [pc, #404] @ (80052a8 ) 8005112: f043 0301 orr.w r3, r3, #1 8005116: 6713 str r3, [r2, #112] @ 0x70 8005118: e01c b.n 8005154 800511a: 687b ldr r3, [r7, #4] 800511c: 689b ldr r3, [r3, #8] 800511e: 2b05 cmp r3, #5 8005120: d10c bne.n 800513c 8005122: 4b61 ldr r3, [pc, #388] @ (80052a8 ) 8005124: 6f1b ldr r3, [r3, #112] @ 0x70 8005126: 4a60 ldr r2, [pc, #384] @ (80052a8 ) 8005128: f043 0304 orr.w r3, r3, #4 800512c: 6713 str r3, [r2, #112] @ 0x70 800512e: 4b5e ldr r3, [pc, #376] @ (80052a8 ) 8005130: 6f1b ldr r3, [r3, #112] @ 0x70 8005132: 4a5d ldr r2, [pc, #372] @ (80052a8 ) 8005134: f043 0301 orr.w r3, r3, #1 8005138: 6713 str r3, [r2, #112] @ 0x70 800513a: e00b b.n 8005154 800513c: 4b5a ldr r3, [pc, #360] @ (80052a8 ) 800513e: 6f1b ldr r3, [r3, #112] @ 0x70 8005140: 4a59 ldr r2, [pc, #356] @ (80052a8 ) 8005142: f023 0301 bic.w r3, r3, #1 8005146: 6713 str r3, [r2, #112] @ 0x70 8005148: 4b57 ldr r3, [pc, #348] @ (80052a8 ) 800514a: 6f1b ldr r3, [r3, #112] @ 0x70 800514c: 4a56 ldr r2, [pc, #344] @ (80052a8 ) 800514e: f023 0304 bic.w r3, r3, #4 8005152: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8005154: 687b ldr r3, [r7, #4] 8005156: 689b ldr r3, [r3, #8] 8005158: 2b00 cmp r3, #0 800515a: d015 beq.n 8005188 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800515c: f7fc fd06 bl 8001b6c 8005160: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005162: e00a b.n 800517a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005164: f7fc fd02 bl 8001b6c 8005168: 4602 mov r2, r0 800516a: 693b ldr r3, [r7, #16] 800516c: 1ad3 subs r3, r2, r3 800516e: f241 3288 movw r2, #5000 @ 0x1388 8005172: 4293 cmp r3, r2 8005174: d901 bls.n 800517a { return HAL_TIMEOUT; 8005176: 2303 movs r3, #3 8005178: e0d7 b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800517a: 4b4b ldr r3, [pc, #300] @ (80052a8 ) 800517c: 6f1b ldr r3, [r3, #112] @ 0x70 800517e: f003 0302 and.w r3, r3, #2 8005182: 2b00 cmp r3, #0 8005184: d0ee beq.n 8005164 8005186: e014 b.n 80051b2 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005188: f7fc fcf0 bl 8001b6c 800518c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800518e: e00a b.n 80051a6 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005190: f7fc fcec bl 8001b6c 8005194: 4602 mov r2, r0 8005196: 693b ldr r3, [r7, #16] 8005198: 1ad3 subs r3, r2, r3 800519a: f241 3288 movw r2, #5000 @ 0x1388 800519e: 4293 cmp r3, r2 80051a0: d901 bls.n 80051a6 { return HAL_TIMEOUT; 80051a2: 2303 movs r3, #3 80051a4: e0c1 b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80051a6: 4b40 ldr r3, [pc, #256] @ (80052a8 ) 80051a8: 6f1b ldr r3, [r3, #112] @ 0x70 80051aa: f003 0302 and.w r3, r3, #2 80051ae: 2b00 cmp r3, #0 80051b0: d1ee bne.n 8005190 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80051b2: 7dfb ldrb r3, [r7, #23] 80051b4: 2b01 cmp r3, #1 80051b6: d105 bne.n 80051c4 { __HAL_RCC_PWR_CLK_DISABLE(); 80051b8: 4b3b ldr r3, [pc, #236] @ (80052a8 ) 80051ba: 6c1b ldr r3, [r3, #64] @ 0x40 80051bc: 4a3a ldr r2, [pc, #232] @ (80052a8 ) 80051be: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80051c2: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80051c4: 687b ldr r3, [r7, #4] 80051c6: 699b ldr r3, [r3, #24] 80051c8: 2b00 cmp r3, #0 80051ca: f000 80ad beq.w 8005328 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 80051ce: 4b36 ldr r3, [pc, #216] @ (80052a8 ) 80051d0: 689b ldr r3, [r3, #8] 80051d2: f003 030c and.w r3, r3, #12 80051d6: 2b08 cmp r3, #8 80051d8: d060 beq.n 800529c { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80051da: 687b ldr r3, [r7, #4] 80051dc: 699b ldr r3, [r3, #24] 80051de: 2b02 cmp r3, #2 80051e0: d145 bne.n 800526e assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80051e2: 4b33 ldr r3, [pc, #204] @ (80052b0 ) 80051e4: 2200 movs r2, #0 80051e6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80051e8: f7fc fcc0 bl 8001b6c 80051ec: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80051ee: e008 b.n 8005202 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80051f0: f7fc fcbc bl 8001b6c 80051f4: 4602 mov r2, r0 80051f6: 693b ldr r3, [r7, #16] 80051f8: 1ad3 subs r3, r2, r3 80051fa: 2b02 cmp r3, #2 80051fc: d901 bls.n 8005202 { return HAL_TIMEOUT; 80051fe: 2303 movs r3, #3 8005200: e093 b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005202: 4b29 ldr r3, [pc, #164] @ (80052a8 ) 8005204: 681b ldr r3, [r3, #0] 8005206: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800520a: 2b00 cmp r3, #0 800520c: d1f0 bne.n 80051f0 } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 800520e: 687b ldr r3, [r7, #4] 8005210: 69da ldr r2, [r3, #28] 8005212: 687b ldr r3, [r7, #4] 8005214: 6a1b ldr r3, [r3, #32] 8005216: 431a orrs r2, r3 8005218: 687b ldr r3, [r7, #4] 800521a: 6a5b ldr r3, [r3, #36] @ 0x24 800521c: 019b lsls r3, r3, #6 800521e: 431a orrs r2, r3 8005220: 687b ldr r3, [r7, #4] 8005222: 6a9b ldr r3, [r3, #40] @ 0x28 8005224: 085b lsrs r3, r3, #1 8005226: 3b01 subs r3, #1 8005228: 041b lsls r3, r3, #16 800522a: 431a orrs r2, r3 800522c: 687b ldr r3, [r7, #4] 800522e: 6adb ldr r3, [r3, #44] @ 0x2c 8005230: 061b lsls r3, r3, #24 8005232: 431a orrs r2, r3 8005234: 687b ldr r3, [r7, #4] 8005236: 6b1b ldr r3, [r3, #48] @ 0x30 8005238: 071b lsls r3, r3, #28 800523a: 491b ldr r1, [pc, #108] @ (80052a8 ) 800523c: 4313 orrs r3, r2 800523e: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8005240: 4b1b ldr r3, [pc, #108] @ (80052b0 ) 8005242: 2201 movs r2, #1 8005244: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005246: f7fc fc91 bl 8001b6c 800524a: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800524c: e008 b.n 8005260 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800524e: f7fc fc8d bl 8001b6c 8005252: 4602 mov r2, r0 8005254: 693b ldr r3, [r7, #16] 8005256: 1ad3 subs r3, r2, r3 8005258: 2b02 cmp r3, #2 800525a: d901 bls.n 8005260 { return HAL_TIMEOUT; 800525c: 2303 movs r3, #3 800525e: e064 b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005260: 4b11 ldr r3, [pc, #68] @ (80052a8 ) 8005262: 681b ldr r3, [r3, #0] 8005264: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005268: 2b00 cmp r3, #0 800526a: d0f0 beq.n 800524e 800526c: e05c b.n 8005328 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800526e: 4b10 ldr r3, [pc, #64] @ (80052b0 ) 8005270: 2200 movs r2, #0 8005272: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005274: f7fc fc7a bl 8001b6c 8005278: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800527a: e008 b.n 800528e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800527c: f7fc fc76 bl 8001b6c 8005280: 4602 mov r2, r0 8005282: 693b ldr r3, [r7, #16] 8005284: 1ad3 subs r3, r2, r3 8005286: 2b02 cmp r3, #2 8005288: d901 bls.n 800528e { return HAL_TIMEOUT; 800528a: 2303 movs r3, #3 800528c: e04d b.n 800532a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800528e: 4b06 ldr r3, [pc, #24] @ (80052a8 ) 8005290: 681b ldr r3, [r3, #0] 8005292: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005296: 2b00 cmp r3, #0 8005298: d1f0 bne.n 800527c 800529a: e045 b.n 8005328 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 800529c: 687b ldr r3, [r7, #4] 800529e: 699b ldr r3, [r3, #24] 80052a0: 2b01 cmp r3, #1 80052a2: d107 bne.n 80052b4 { return HAL_ERROR; 80052a4: 2301 movs r3, #1 80052a6: e040 b.n 800532a 80052a8: 40023800 .word 0x40023800 80052ac: 40007000 .word 0x40007000 80052b0: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 80052b4: 4b1f ldr r3, [pc, #124] @ (8005334 ) 80052b6: 685b ldr r3, [r3, #4] 80052b8: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80052ba: 687b ldr r3, [r7, #4] 80052bc: 699b ldr r3, [r3, #24] 80052be: 2b01 cmp r3, #1 80052c0: d030 beq.n 8005324 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80052c2: 68fb ldr r3, [r7, #12] 80052c4: f403 0280 and.w r2, r3, #4194304 @ 0x400000 80052c8: 687b ldr r3, [r7, #4] 80052ca: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80052cc: 429a cmp r2, r3 80052ce: d129 bne.n 8005324 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80052d0: 68fb ldr r3, [r7, #12] 80052d2: f003 023f and.w r2, r3, #63 @ 0x3f 80052d6: 687b ldr r3, [r7, #4] 80052d8: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80052da: 429a cmp r2, r3 80052dc: d122 bne.n 8005324 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80052de: 68fa ldr r2, [r7, #12] 80052e0: f647 73c0 movw r3, #32704 @ 0x7fc0 80052e4: 4013 ands r3, r2 80052e6: 687a ldr r2, [r7, #4] 80052e8: 6a52 ldr r2, [r2, #36] @ 0x24 80052ea: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80052ec: 4293 cmp r3, r2 80052ee: d119 bne.n 8005324 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80052f0: 68fb ldr r3, [r7, #12] 80052f2: f403 3240 and.w r2, r3, #196608 @ 0x30000 80052f6: 687b ldr r3, [r7, #4] 80052f8: 6a9b ldr r3, [r3, #40] @ 0x28 80052fa: 085b lsrs r3, r3, #1 80052fc: 3b01 subs r3, #1 80052fe: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8005300: 429a cmp r2, r3 8005302: d10f bne.n 8005324 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8005304: 68fb ldr r3, [r7, #12] 8005306: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 800530a: 687b ldr r3, [r7, #4] 800530c: 6adb ldr r3, [r3, #44] @ 0x2c 800530e: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8005310: 429a cmp r2, r3 8005312: d107 bne.n 8005324 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 8005314: 68fb ldr r3, [r7, #12] 8005316: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 800531a: 687b ldr r3, [r7, #4] 800531c: 6b1b ldr r3, [r3, #48] @ 0x30 800531e: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8005320: 429a cmp r2, r3 8005322: d001 beq.n 8005328 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 8005324: 2301 movs r3, #1 8005326: e000 b.n 800532a } } } } return HAL_OK; 8005328: 2300 movs r3, #0 } 800532a: 4618 mov r0, r3 800532c: 3718 adds r7, #24 800532e: 46bd mov sp, r7 8005330: bd80 pop {r7, pc} 8005332: bf00 nop 8005334: 40023800 .word 0x40023800 08005338 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8005338: b580 push {r7, lr} 800533a: b082 sub sp, #8 800533c: af00 add r7, sp, #0 800533e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8005340: 687b ldr r3, [r7, #4] 8005342: 2b00 cmp r3, #0 8005344: d101 bne.n 800534a { return HAL_ERROR; 8005346: 2301 movs r3, #1 8005348: e041 b.n 80053ce assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800534a: 687b ldr r3, [r7, #4] 800534c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8005350: b2db uxtb r3, r3 8005352: 2b00 cmp r3, #0 8005354: d106 bne.n 8005364 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005356: 687b ldr r3, [r7, #4] 8005358: 2200 movs r2, #0 800535a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 800535e: 6878 ldr r0, [r7, #4] 8005360: f7fb ff6a bl 8001238 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005364: 687b ldr r3, [r7, #4] 8005366: 2202 movs r2, #2 8005368: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800536c: 687b ldr r3, [r7, #4] 800536e: 681a ldr r2, [r3, #0] 8005370: 687b ldr r3, [r7, #4] 8005372: 3304 adds r3, #4 8005374: 4619 mov r1, r3 8005376: 4610 mov r0, r2 8005378: f000 f930 bl 80055dc /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800537c: 687b ldr r3, [r7, #4] 800537e: 2201 movs r2, #1 8005380: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005384: 687b ldr r3, [r7, #4] 8005386: 2201 movs r2, #1 8005388: f883 203e strb.w r2, [r3, #62] @ 0x3e 800538c: 687b ldr r3, [r7, #4] 800538e: 2201 movs r2, #1 8005390: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005394: 687b ldr r3, [r7, #4] 8005396: 2201 movs r2, #1 8005398: f883 2040 strb.w r2, [r3, #64] @ 0x40 800539c: 687b ldr r3, [r7, #4] 800539e: 2201 movs r2, #1 80053a0: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80053a4: 687b ldr r3, [r7, #4] 80053a6: 2201 movs r2, #1 80053a8: f883 2042 strb.w r2, [r3, #66] @ 0x42 80053ac: 687b ldr r3, [r7, #4] 80053ae: 2201 movs r2, #1 80053b0: f883 2043 strb.w r2, [r3, #67] @ 0x43 80053b4: 687b ldr r3, [r7, #4] 80053b6: 2201 movs r2, #1 80053b8: f883 2044 strb.w r2, [r3, #68] @ 0x44 80053bc: 687b ldr r3, [r7, #4] 80053be: 2201 movs r2, #1 80053c0: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80053c4: 687b ldr r3, [r7, #4] 80053c6: 2201 movs r2, #1 80053c8: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80053cc: 2300 movs r3, #0 } 80053ce: 4618 mov r0, r3 80053d0: 3708 adds r7, #8 80053d2: 46bd mov sp, r7 80053d4: bd80 pop {r7, pc} 080053d6 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 80053d6: b580 push {r7, lr} 80053d8: b086 sub sp, #24 80053da: af00 add r7, sp, #0 80053dc: 6078 str r0, [r7, #4] 80053de: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 80053e0: 687b ldr r3, [r7, #4] 80053e2: 2b00 cmp r3, #0 80053e4: d101 bne.n 80053ea { return HAL_ERROR; 80053e6: 2301 movs r3, #1 80053e8: e097 b.n 800551a assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 80053ea: 687b ldr r3, [r7, #4] 80053ec: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80053f0: b2db uxtb r3, r3 80053f2: 2b00 cmp r3, #0 80053f4: d106 bne.n 8005404 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80053f6: 687b ldr r3, [r7, #4] 80053f8: 2200 movs r2, #0 80053fa: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 80053fe: 6878 ldr r0, [r7, #4] 8005400: f7fb ff3a bl 8001278 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005404: 687b ldr r3, [r7, #4] 8005406: 2202 movs r2, #2 8005408: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 800540c: 687b ldr r3, [r7, #4] 800540e: 681b ldr r3, [r3, #0] 8005410: 689b ldr r3, [r3, #8] 8005412: 687a ldr r2, [r7, #4] 8005414: 6812 ldr r2, [r2, #0] 8005416: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800541a: f023 0307 bic.w r3, r3, #7 800541e: 6093 str r3, [r2, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005420: 687b ldr r3, [r7, #4] 8005422: 681a ldr r2, [r3, #0] 8005424: 687b ldr r3, [r7, #4] 8005426: 3304 adds r3, #4 8005428: 4619 mov r1, r3 800542a: 4610 mov r0, r2 800542c: f000 f8d6 bl 80055dc /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005430: 687b ldr r3, [r7, #4] 8005432: 681b ldr r3, [r3, #0] 8005434: 689b ldr r3, [r3, #8] 8005436: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 8005438: 687b ldr r3, [r7, #4] 800543a: 681b ldr r3, [r3, #0] 800543c: 699b ldr r3, [r3, #24] 800543e: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 8005440: 687b ldr r3, [r7, #4] 8005442: 681b ldr r3, [r3, #0] 8005444: 6a1b ldr r3, [r3, #32] 8005446: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 8005448: 683b ldr r3, [r7, #0] 800544a: 681b ldr r3, [r3, #0] 800544c: 697a ldr r2, [r7, #20] 800544e: 4313 orrs r3, r2 8005450: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 8005452: 693b ldr r3, [r7, #16] 8005454: f423 7340 bic.w r3, r3, #768 @ 0x300 8005458: f023 0303 bic.w r3, r3, #3 800545c: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 800545e: 683b ldr r3, [r7, #0] 8005460: 689a ldr r2, [r3, #8] 8005462: 683b ldr r3, [r7, #0] 8005464: 699b ldr r3, [r3, #24] 8005466: 021b lsls r3, r3, #8 8005468: 4313 orrs r3, r2 800546a: 693a ldr r2, [r7, #16] 800546c: 4313 orrs r3, r2 800546e: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 8005470: 693b ldr r3, [r7, #16] 8005472: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8005476: f023 030c bic.w r3, r3, #12 800547a: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 800547c: 693b ldr r3, [r7, #16] 800547e: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8005482: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8005486: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 8005488: 683b ldr r3, [r7, #0] 800548a: 68da ldr r2, [r3, #12] 800548c: 683b ldr r3, [r7, #0] 800548e: 69db ldr r3, [r3, #28] 8005490: 021b lsls r3, r3, #8 8005492: 4313 orrs r3, r2 8005494: 693a ldr r2, [r7, #16] 8005496: 4313 orrs r3, r2 8005498: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 800549a: 683b ldr r3, [r7, #0] 800549c: 691b ldr r3, [r3, #16] 800549e: 011a lsls r2, r3, #4 80054a0: 683b ldr r3, [r7, #0] 80054a2: 6a1b ldr r3, [r3, #32] 80054a4: 031b lsls r3, r3, #12 80054a6: 4313 orrs r3, r2 80054a8: 693a ldr r2, [r7, #16] 80054aa: 4313 orrs r3, r2 80054ac: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 80054ae: 68fb ldr r3, [r7, #12] 80054b0: f023 0322 bic.w r3, r3, #34 @ 0x22 80054b4: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 80054b6: 68fb ldr r3, [r7, #12] 80054b8: f023 0388 bic.w r3, r3, #136 @ 0x88 80054bc: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 80054be: 683b ldr r3, [r7, #0] 80054c0: 685a ldr r2, [r3, #4] 80054c2: 683b ldr r3, [r7, #0] 80054c4: 695b ldr r3, [r3, #20] 80054c6: 011b lsls r3, r3, #4 80054c8: 4313 orrs r3, r2 80054ca: 68fa ldr r2, [r7, #12] 80054cc: 4313 orrs r3, r2 80054ce: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80054d0: 687b ldr r3, [r7, #4] 80054d2: 681b ldr r3, [r3, #0] 80054d4: 697a ldr r2, [r7, #20] 80054d6: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 80054d8: 687b ldr r3, [r7, #4] 80054da: 681b ldr r3, [r3, #0] 80054dc: 693a ldr r2, [r7, #16] 80054de: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 80054e0: 687b ldr r3, [r7, #4] 80054e2: 681b ldr r3, [r3, #0] 80054e4: 68fa ldr r2, [r7, #12] 80054e6: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80054e8: 687b ldr r3, [r7, #4] 80054ea: 2201 movs r2, #1 80054ec: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 80054f0: 687b ldr r3, [r7, #4] 80054f2: 2201 movs r2, #1 80054f4: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 80054f8: 687b ldr r3, [r7, #4] 80054fa: 2201 movs r2, #1 80054fc: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005500: 687b ldr r3, [r7, #4] 8005502: 2201 movs r2, #1 8005504: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005508: 687b ldr r3, [r7, #4] 800550a: 2201 movs r2, #1 800550c: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005510: 687b ldr r3, [r7, #4] 8005512: 2201 movs r2, #1 8005514: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005518: 2300 movs r3, #0 } 800551a: 4618 mov r0, r3 800551c: 3718 adds r7, #24 800551e: 46bd mov sp, r7 8005520: bd80 pop {r7, pc} ... 08005524 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8005524: b580 push {r7, lr} 8005526: b086 sub sp, #24 8005528: af00 add r7, sp, #0 800552a: 60f8 str r0, [r7, #12] 800552c: 60b9 str r1, [r7, #8] 800552e: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8005530: 2300 movs r3, #0 8005532: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 8005534: 68fb ldr r3, [r7, #12] 8005536: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800553a: 2b01 cmp r3, #1 800553c: d101 bne.n 8005542 800553e: 2302 movs r3, #2 8005540: e048 b.n 80055d4 8005542: 68fb ldr r3, [r7, #12] 8005544: 2201 movs r2, #1 8005546: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 800554a: 687b ldr r3, [r7, #4] 800554c: 2b0c cmp r3, #12 800554e: d839 bhi.n 80055c4 8005550: a201 add r2, pc, #4 @ (adr r2, 8005558 ) 8005552: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005556: bf00 nop 8005558: 0800558d .word 0x0800558d 800555c: 080055c5 .word 0x080055c5 8005560: 080055c5 .word 0x080055c5 8005564: 080055c5 .word 0x080055c5 8005568: 0800559b .word 0x0800559b 800556c: 080055c5 .word 0x080055c5 8005570: 080055c5 .word 0x080055c5 8005574: 080055c5 .word 0x080055c5 8005578: 080055a9 .word 0x080055a9 800557c: 080055c5 .word 0x080055c5 8005580: 080055c5 .word 0x080055c5 8005584: 080055c5 .word 0x080055c5 8005588: 080055b7 .word 0x080055b7 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 800558c: 68fb ldr r3, [r7, #12] 800558e: 681b ldr r3, [r3, #0] 8005590: 68b9 ldr r1, [r7, #8] 8005592: 4618 mov r0, r3 8005594: f000 f8c8 bl 8005728 break; 8005598: e017 b.n 80055ca { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 800559a: 68fb ldr r3, [r7, #12] 800559c: 681b ldr r3, [r3, #0] 800559e: 68b9 ldr r1, [r7, #8] 80055a0: 4618 mov r0, r3 80055a2: f000 f931 bl 8005808 break; 80055a6: e010 b.n 80055ca { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80055a8: 68fb ldr r3, [r7, #12] 80055aa: 681b ldr r3, [r3, #0] 80055ac: 68b9 ldr r1, [r7, #8] 80055ae: 4618 mov r0, r3 80055b0: f000 f9a0 bl 80058f4 break; 80055b4: e009 b.n 80055ca { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80055b6: 68fb ldr r3, [r7, #12] 80055b8: 681b ldr r3, [r3, #0] 80055ba: 68b9 ldr r1, [r7, #8] 80055bc: 4618 mov r0, r3 80055be: f000 fa0d bl 80059dc break; 80055c2: e002 b.n 80055ca } default: status = HAL_ERROR; 80055c4: 2301 movs r3, #1 80055c6: 75fb strb r3, [r7, #23] break; 80055c8: bf00 nop } __HAL_UNLOCK(htim); 80055ca: 68fb ldr r3, [r7, #12] 80055cc: 2200 movs r2, #0 80055ce: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80055d2: 7dfb ldrb r3, [r7, #23] } 80055d4: 4618 mov r0, r3 80055d6: 3718 adds r7, #24 80055d8: 46bd mov sp, r7 80055da: bd80 pop {r7, pc} 080055dc : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80055dc: b480 push {r7} 80055de: b085 sub sp, #20 80055e0: af00 add r7, sp, #0 80055e2: 6078 str r0, [r7, #4] 80055e4: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80055e6: 687b ldr r3, [r7, #4] 80055e8: 681b ldr r3, [r3, #0] 80055ea: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80055ec: 687b ldr r3, [r7, #4] 80055ee: 4a43 ldr r2, [pc, #268] @ (80056fc ) 80055f0: 4293 cmp r3, r2 80055f2: d013 beq.n 800561c 80055f4: 687b ldr r3, [r7, #4] 80055f6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80055fa: d00f beq.n 800561c 80055fc: 687b ldr r3, [r7, #4] 80055fe: 4a40 ldr r2, [pc, #256] @ (8005700 ) 8005600: 4293 cmp r3, r2 8005602: d00b beq.n 800561c 8005604: 687b ldr r3, [r7, #4] 8005606: 4a3f ldr r2, [pc, #252] @ (8005704 ) 8005608: 4293 cmp r3, r2 800560a: d007 beq.n 800561c 800560c: 687b ldr r3, [r7, #4] 800560e: 4a3e ldr r2, [pc, #248] @ (8005708 ) 8005610: 4293 cmp r3, r2 8005612: d003 beq.n 800561c 8005614: 687b ldr r3, [r7, #4] 8005616: 4a3d ldr r2, [pc, #244] @ (800570c ) 8005618: 4293 cmp r3, r2 800561a: d108 bne.n 800562e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800561c: 68fb ldr r3, [r7, #12] 800561e: f023 0370 bic.w r3, r3, #112 @ 0x70 8005622: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8005624: 683b ldr r3, [r7, #0] 8005626: 685b ldr r3, [r3, #4] 8005628: 68fa ldr r2, [r7, #12] 800562a: 4313 orrs r3, r2 800562c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800562e: 687b ldr r3, [r7, #4] 8005630: 4a32 ldr r2, [pc, #200] @ (80056fc ) 8005632: 4293 cmp r3, r2 8005634: d02b beq.n 800568e 8005636: 687b ldr r3, [r7, #4] 8005638: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800563c: d027 beq.n 800568e 800563e: 687b ldr r3, [r7, #4] 8005640: 4a2f ldr r2, [pc, #188] @ (8005700 ) 8005642: 4293 cmp r3, r2 8005644: d023 beq.n 800568e 8005646: 687b ldr r3, [r7, #4] 8005648: 4a2e ldr r2, [pc, #184] @ (8005704 ) 800564a: 4293 cmp r3, r2 800564c: d01f beq.n 800568e 800564e: 687b ldr r3, [r7, #4] 8005650: 4a2d ldr r2, [pc, #180] @ (8005708 ) 8005652: 4293 cmp r3, r2 8005654: d01b beq.n 800568e 8005656: 687b ldr r3, [r7, #4] 8005658: 4a2c ldr r2, [pc, #176] @ (800570c ) 800565a: 4293 cmp r3, r2 800565c: d017 beq.n 800568e 800565e: 687b ldr r3, [r7, #4] 8005660: 4a2b ldr r2, [pc, #172] @ (8005710 ) 8005662: 4293 cmp r3, r2 8005664: d013 beq.n 800568e 8005666: 687b ldr r3, [r7, #4] 8005668: 4a2a ldr r2, [pc, #168] @ (8005714 ) 800566a: 4293 cmp r3, r2 800566c: d00f beq.n 800568e 800566e: 687b ldr r3, [r7, #4] 8005670: 4a29 ldr r2, [pc, #164] @ (8005718 ) 8005672: 4293 cmp r3, r2 8005674: d00b beq.n 800568e 8005676: 687b ldr r3, [r7, #4] 8005678: 4a28 ldr r2, [pc, #160] @ (800571c ) 800567a: 4293 cmp r3, r2 800567c: d007 beq.n 800568e 800567e: 687b ldr r3, [r7, #4] 8005680: 4a27 ldr r2, [pc, #156] @ (8005720 ) 8005682: 4293 cmp r3, r2 8005684: d003 beq.n 800568e 8005686: 687b ldr r3, [r7, #4] 8005688: 4a26 ldr r2, [pc, #152] @ (8005724 ) 800568a: 4293 cmp r3, r2 800568c: d108 bne.n 80056a0 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800568e: 68fb ldr r3, [r7, #12] 8005690: f423 7340 bic.w r3, r3, #768 @ 0x300 8005694: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8005696: 683b ldr r3, [r7, #0] 8005698: 68db ldr r3, [r3, #12] 800569a: 68fa ldr r2, [r7, #12] 800569c: 4313 orrs r3, r2 800569e: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80056a0: 68fb ldr r3, [r7, #12] 80056a2: f023 0280 bic.w r2, r3, #128 @ 0x80 80056a6: 683b ldr r3, [r7, #0] 80056a8: 695b ldr r3, [r3, #20] 80056aa: 4313 orrs r3, r2 80056ac: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80056ae: 683b ldr r3, [r7, #0] 80056b0: 689a ldr r2, [r3, #8] 80056b2: 687b ldr r3, [r7, #4] 80056b4: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80056b6: 683b ldr r3, [r7, #0] 80056b8: 681a ldr r2, [r3, #0] 80056ba: 687b ldr r3, [r7, #4] 80056bc: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80056be: 687b ldr r3, [r7, #4] 80056c0: 4a0e ldr r2, [pc, #56] @ (80056fc ) 80056c2: 4293 cmp r3, r2 80056c4: d003 beq.n 80056ce 80056c6: 687b ldr r3, [r7, #4] 80056c8: 4a10 ldr r2, [pc, #64] @ (800570c ) 80056ca: 4293 cmp r3, r2 80056cc: d103 bne.n 80056d6 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80056ce: 683b ldr r3, [r7, #0] 80056d0: 691a ldr r2, [r3, #16] 80056d2: 687b ldr r3, [r7, #4] 80056d4: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 80056d6: 687b ldr r3, [r7, #4] 80056d8: 681b ldr r3, [r3, #0] 80056da: f043 0204 orr.w r2, r3, #4 80056de: 687b ldr r3, [r7, #4] 80056e0: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80056e2: 687b ldr r3, [r7, #4] 80056e4: 2201 movs r2, #1 80056e6: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 80056e8: 687b ldr r3, [r7, #4] 80056ea: 68fa ldr r2, [r7, #12] 80056ec: 601a str r2, [r3, #0] } 80056ee: bf00 nop 80056f0: 3714 adds r7, #20 80056f2: 46bd mov sp, r7 80056f4: f85d 7b04 ldr.w r7, [sp], #4 80056f8: 4770 bx lr 80056fa: bf00 nop 80056fc: 40010000 .word 0x40010000 8005700: 40000400 .word 0x40000400 8005704: 40000800 .word 0x40000800 8005708: 40000c00 .word 0x40000c00 800570c: 40010400 .word 0x40010400 8005710: 40014000 .word 0x40014000 8005714: 40014400 .word 0x40014400 8005718: 40014800 .word 0x40014800 800571c: 40001800 .word 0x40001800 8005720: 40001c00 .word 0x40001c00 8005724: 40002000 .word 0x40002000 08005728 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005728: b480 push {r7} 800572a: b087 sub sp, #28 800572c: af00 add r7, sp, #0 800572e: 6078 str r0, [r7, #4] 8005730: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005732: 687b ldr r3, [r7, #4] 8005734: 6a1b ldr r3, [r3, #32] 8005736: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8005738: 687b ldr r3, [r7, #4] 800573a: 6a1b ldr r3, [r3, #32] 800573c: f023 0201 bic.w r2, r3, #1 8005740: 687b ldr r3, [r7, #4] 8005742: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005744: 687b ldr r3, [r7, #4] 8005746: 685b ldr r3, [r3, #4] 8005748: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800574a: 687b ldr r3, [r7, #4] 800574c: 699b ldr r3, [r3, #24] 800574e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8005750: 68fb ldr r3, [r7, #12] 8005752: f023 0370 bic.w r3, r3, #112 @ 0x70 8005756: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8005758: 68fb ldr r3, [r7, #12] 800575a: f023 0303 bic.w r3, r3, #3 800575e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8005760: 683b ldr r3, [r7, #0] 8005762: 681b ldr r3, [r3, #0] 8005764: 68fa ldr r2, [r7, #12] 8005766: 4313 orrs r3, r2 8005768: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 800576a: 697b ldr r3, [r7, #20] 800576c: f023 0302 bic.w r3, r3, #2 8005770: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8005772: 683b ldr r3, [r7, #0] 8005774: 689b ldr r3, [r3, #8] 8005776: 697a ldr r2, [r7, #20] 8005778: 4313 orrs r3, r2 800577a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 800577c: 687b ldr r3, [r7, #4] 800577e: 4a20 ldr r2, [pc, #128] @ (8005800 ) 8005780: 4293 cmp r3, r2 8005782: d003 beq.n 800578c 8005784: 687b ldr r3, [r7, #4] 8005786: 4a1f ldr r2, [pc, #124] @ (8005804 ) 8005788: 4293 cmp r3, r2 800578a: d10c bne.n 80057a6 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 800578c: 697b ldr r3, [r7, #20] 800578e: f023 0308 bic.w r3, r3, #8 8005792: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8005794: 683b ldr r3, [r7, #0] 8005796: 68db ldr r3, [r3, #12] 8005798: 697a ldr r2, [r7, #20] 800579a: 4313 orrs r3, r2 800579c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800579e: 697b ldr r3, [r7, #20] 80057a0: f023 0304 bic.w r3, r3, #4 80057a4: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80057a6: 687b ldr r3, [r7, #4] 80057a8: 4a15 ldr r2, [pc, #84] @ (8005800 ) 80057aa: 4293 cmp r3, r2 80057ac: d003 beq.n 80057b6 80057ae: 687b ldr r3, [r7, #4] 80057b0: 4a14 ldr r2, [pc, #80] @ (8005804 ) 80057b2: 4293 cmp r3, r2 80057b4: d111 bne.n 80057da /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 80057b6: 693b ldr r3, [r7, #16] 80057b8: f423 7380 bic.w r3, r3, #256 @ 0x100 80057bc: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 80057be: 693b ldr r3, [r7, #16] 80057c0: f423 7300 bic.w r3, r3, #512 @ 0x200 80057c4: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 80057c6: 683b ldr r3, [r7, #0] 80057c8: 695b ldr r3, [r3, #20] 80057ca: 693a ldr r2, [r7, #16] 80057cc: 4313 orrs r3, r2 80057ce: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 80057d0: 683b ldr r3, [r7, #0] 80057d2: 699b ldr r3, [r3, #24] 80057d4: 693a ldr r2, [r7, #16] 80057d6: 4313 orrs r3, r2 80057d8: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80057da: 687b ldr r3, [r7, #4] 80057dc: 693a ldr r2, [r7, #16] 80057de: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80057e0: 687b ldr r3, [r7, #4] 80057e2: 68fa ldr r2, [r7, #12] 80057e4: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80057e6: 683b ldr r3, [r7, #0] 80057e8: 685a ldr r2, [r3, #4] 80057ea: 687b ldr r3, [r7, #4] 80057ec: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80057ee: 687b ldr r3, [r7, #4] 80057f0: 697a ldr r2, [r7, #20] 80057f2: 621a str r2, [r3, #32] } 80057f4: bf00 nop 80057f6: 371c adds r7, #28 80057f8: 46bd mov sp, r7 80057fa: f85d 7b04 ldr.w r7, [sp], #4 80057fe: 4770 bx lr 8005800: 40010000 .word 0x40010000 8005804: 40010400 .word 0x40010400 08005808 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005808: b480 push {r7} 800580a: b087 sub sp, #28 800580c: af00 add r7, sp, #0 800580e: 6078 str r0, [r7, #4] 8005810: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005812: 687b ldr r3, [r7, #4] 8005814: 6a1b ldr r3, [r3, #32] 8005816: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8005818: 687b ldr r3, [r7, #4] 800581a: 6a1b ldr r3, [r3, #32] 800581c: f023 0210 bic.w r2, r3, #16 8005820: 687b ldr r3, [r7, #4] 8005822: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005824: 687b ldr r3, [r7, #4] 8005826: 685b ldr r3, [r3, #4] 8005828: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800582a: 687b ldr r3, [r7, #4] 800582c: 699b ldr r3, [r3, #24] 800582e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8005830: 68fb ldr r3, [r7, #12] 8005832: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8005836: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8005838: 68fb ldr r3, [r7, #12] 800583a: f423 7340 bic.w r3, r3, #768 @ 0x300 800583e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8005840: 683b ldr r3, [r7, #0] 8005842: 681b ldr r3, [r3, #0] 8005844: 021b lsls r3, r3, #8 8005846: 68fa ldr r2, [r7, #12] 8005848: 4313 orrs r3, r2 800584a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 800584c: 697b ldr r3, [r7, #20] 800584e: f023 0320 bic.w r3, r3, #32 8005852: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8005854: 683b ldr r3, [r7, #0] 8005856: 689b ldr r3, [r3, #8] 8005858: 011b lsls r3, r3, #4 800585a: 697a ldr r2, [r7, #20] 800585c: 4313 orrs r3, r2 800585e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8005860: 687b ldr r3, [r7, #4] 8005862: 4a22 ldr r2, [pc, #136] @ (80058ec ) 8005864: 4293 cmp r3, r2 8005866: d003 beq.n 8005870 8005868: 687b ldr r3, [r7, #4] 800586a: 4a21 ldr r2, [pc, #132] @ (80058f0 ) 800586c: 4293 cmp r3, r2 800586e: d10d bne.n 800588c { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8005870: 697b ldr r3, [r7, #20] 8005872: f023 0380 bic.w r3, r3, #128 @ 0x80 8005876: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8005878: 683b ldr r3, [r7, #0] 800587a: 68db ldr r3, [r3, #12] 800587c: 011b lsls r3, r3, #4 800587e: 697a ldr r2, [r7, #20] 8005880: 4313 orrs r3, r2 8005882: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8005884: 697b ldr r3, [r7, #20] 8005886: f023 0340 bic.w r3, r3, #64 @ 0x40 800588a: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800588c: 687b ldr r3, [r7, #4] 800588e: 4a17 ldr r2, [pc, #92] @ (80058ec ) 8005890: 4293 cmp r3, r2 8005892: d003 beq.n 800589c 8005894: 687b ldr r3, [r7, #4] 8005896: 4a16 ldr r2, [pc, #88] @ (80058f0 ) 8005898: 4293 cmp r3, r2 800589a: d113 bne.n 80058c4 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 800589c: 693b ldr r3, [r7, #16] 800589e: f423 6380 bic.w r3, r3, #1024 @ 0x400 80058a2: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 80058a4: 693b ldr r3, [r7, #16] 80058a6: f423 6300 bic.w r3, r3, #2048 @ 0x800 80058aa: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 80058ac: 683b ldr r3, [r7, #0] 80058ae: 695b ldr r3, [r3, #20] 80058b0: 009b lsls r3, r3, #2 80058b2: 693a ldr r2, [r7, #16] 80058b4: 4313 orrs r3, r2 80058b6: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 80058b8: 683b ldr r3, [r7, #0] 80058ba: 699b ldr r3, [r3, #24] 80058bc: 009b lsls r3, r3, #2 80058be: 693a ldr r2, [r7, #16] 80058c0: 4313 orrs r3, r2 80058c2: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80058c4: 687b ldr r3, [r7, #4] 80058c6: 693a ldr r2, [r7, #16] 80058c8: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80058ca: 687b ldr r3, [r7, #4] 80058cc: 68fa ldr r2, [r7, #12] 80058ce: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 80058d0: 683b ldr r3, [r7, #0] 80058d2: 685a ldr r2, [r3, #4] 80058d4: 687b ldr r3, [r7, #4] 80058d6: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80058d8: 687b ldr r3, [r7, #4] 80058da: 697a ldr r2, [r7, #20] 80058dc: 621a str r2, [r3, #32] } 80058de: bf00 nop 80058e0: 371c adds r7, #28 80058e2: 46bd mov sp, r7 80058e4: f85d 7b04 ldr.w r7, [sp], #4 80058e8: 4770 bx lr 80058ea: bf00 nop 80058ec: 40010000 .word 0x40010000 80058f0: 40010400 .word 0x40010400 080058f4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80058f4: b480 push {r7} 80058f6: b087 sub sp, #28 80058f8: af00 add r7, sp, #0 80058fa: 6078 str r0, [r7, #4] 80058fc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80058fe: 687b ldr r3, [r7, #4] 8005900: 6a1b ldr r3, [r3, #32] 8005902: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8005904: 687b ldr r3, [r7, #4] 8005906: 6a1b ldr r3, [r3, #32] 8005908: f423 7280 bic.w r2, r3, #256 @ 0x100 800590c: 687b ldr r3, [r7, #4] 800590e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005910: 687b ldr r3, [r7, #4] 8005912: 685b ldr r3, [r3, #4] 8005914: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8005916: 687b ldr r3, [r7, #4] 8005918: 69db ldr r3, [r3, #28] 800591a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 800591c: 68fb ldr r3, [r7, #12] 800591e: f023 0370 bic.w r3, r3, #112 @ 0x70 8005922: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8005924: 68fb ldr r3, [r7, #12] 8005926: f023 0303 bic.w r3, r3, #3 800592a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800592c: 683b ldr r3, [r7, #0] 800592e: 681b ldr r3, [r3, #0] 8005930: 68fa ldr r2, [r7, #12] 8005932: 4313 orrs r3, r2 8005934: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8005936: 697b ldr r3, [r7, #20] 8005938: f423 7300 bic.w r3, r3, #512 @ 0x200 800593c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800593e: 683b ldr r3, [r7, #0] 8005940: 689b ldr r3, [r3, #8] 8005942: 021b lsls r3, r3, #8 8005944: 697a ldr r2, [r7, #20] 8005946: 4313 orrs r3, r2 8005948: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 800594a: 687b ldr r3, [r7, #4] 800594c: 4a21 ldr r2, [pc, #132] @ (80059d4 ) 800594e: 4293 cmp r3, r2 8005950: d003 beq.n 800595a 8005952: 687b ldr r3, [r7, #4] 8005954: 4a20 ldr r2, [pc, #128] @ (80059d8 ) 8005956: 4293 cmp r3, r2 8005958: d10d bne.n 8005976 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 800595a: 697b ldr r3, [r7, #20] 800595c: f423 6300 bic.w r3, r3, #2048 @ 0x800 8005960: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8005962: 683b ldr r3, [r7, #0] 8005964: 68db ldr r3, [r3, #12] 8005966: 021b lsls r3, r3, #8 8005968: 697a ldr r2, [r7, #20] 800596a: 4313 orrs r3, r2 800596c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 800596e: 697b ldr r3, [r7, #20] 8005970: f423 6380 bic.w r3, r3, #1024 @ 0x400 8005974: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005976: 687b ldr r3, [r7, #4] 8005978: 4a16 ldr r2, [pc, #88] @ (80059d4 ) 800597a: 4293 cmp r3, r2 800597c: d003 beq.n 8005986 800597e: 687b ldr r3, [r7, #4] 8005980: 4a15 ldr r2, [pc, #84] @ (80059d8 ) 8005982: 4293 cmp r3, r2 8005984: d113 bne.n 80059ae /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8005986: 693b ldr r3, [r7, #16] 8005988: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800598c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800598e: 693b ldr r3, [r7, #16] 8005990: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8005994: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8005996: 683b ldr r3, [r7, #0] 8005998: 695b ldr r3, [r3, #20] 800599a: 011b lsls r3, r3, #4 800599c: 693a ldr r2, [r7, #16] 800599e: 4313 orrs r3, r2 80059a0: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80059a2: 683b ldr r3, [r7, #0] 80059a4: 699b ldr r3, [r3, #24] 80059a6: 011b lsls r3, r3, #4 80059a8: 693a ldr r2, [r7, #16] 80059aa: 4313 orrs r3, r2 80059ac: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80059ae: 687b ldr r3, [r7, #4] 80059b0: 693a ldr r2, [r7, #16] 80059b2: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80059b4: 687b ldr r3, [r7, #4] 80059b6: 68fa ldr r2, [r7, #12] 80059b8: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 80059ba: 683b ldr r3, [r7, #0] 80059bc: 685a ldr r2, [r3, #4] 80059be: 687b ldr r3, [r7, #4] 80059c0: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80059c2: 687b ldr r3, [r7, #4] 80059c4: 697a ldr r2, [r7, #20] 80059c6: 621a str r2, [r3, #32] } 80059c8: bf00 nop 80059ca: 371c adds r7, #28 80059cc: 46bd mov sp, r7 80059ce: f85d 7b04 ldr.w r7, [sp], #4 80059d2: 4770 bx lr 80059d4: 40010000 .word 0x40010000 80059d8: 40010400 .word 0x40010400 080059dc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80059dc: b480 push {r7} 80059de: b087 sub sp, #28 80059e0: af00 add r7, sp, #0 80059e2: 6078 str r0, [r7, #4] 80059e4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80059e6: 687b ldr r3, [r7, #4] 80059e8: 6a1b ldr r3, [r3, #32] 80059ea: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 80059ec: 687b ldr r3, [r7, #4] 80059ee: 6a1b ldr r3, [r3, #32] 80059f0: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80059f4: 687b ldr r3, [r7, #4] 80059f6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80059f8: 687b ldr r3, [r7, #4] 80059fa: 685b ldr r3, [r3, #4] 80059fc: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80059fe: 687b ldr r3, [r7, #4] 8005a00: 69db ldr r3, [r3, #28] 8005a02: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8005a04: 68fb ldr r3, [r7, #12] 8005a06: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8005a0a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8005a0c: 68fb ldr r3, [r7, #12] 8005a0e: f423 7340 bic.w r3, r3, #768 @ 0x300 8005a12: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8005a14: 683b ldr r3, [r7, #0] 8005a16: 681b ldr r3, [r3, #0] 8005a18: 021b lsls r3, r3, #8 8005a1a: 68fa ldr r2, [r7, #12] 8005a1c: 4313 orrs r3, r2 8005a1e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8005a20: 693b ldr r3, [r7, #16] 8005a22: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8005a26: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8005a28: 683b ldr r3, [r7, #0] 8005a2a: 689b ldr r3, [r3, #8] 8005a2c: 031b lsls r3, r3, #12 8005a2e: 693a ldr r2, [r7, #16] 8005a30: 4313 orrs r3, r2 8005a32: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005a34: 687b ldr r3, [r7, #4] 8005a36: 4a12 ldr r2, [pc, #72] @ (8005a80 ) 8005a38: 4293 cmp r3, r2 8005a3a: d003 beq.n 8005a44 8005a3c: 687b ldr r3, [r7, #4] 8005a3e: 4a11 ldr r2, [pc, #68] @ (8005a84 ) 8005a40: 4293 cmp r3, r2 8005a42: d109 bne.n 8005a58 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8005a44: 697b ldr r3, [r7, #20] 8005a46: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8005a4a: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8005a4c: 683b ldr r3, [r7, #0] 8005a4e: 695b ldr r3, [r3, #20] 8005a50: 019b lsls r3, r3, #6 8005a52: 697a ldr r2, [r7, #20] 8005a54: 4313 orrs r3, r2 8005a56: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005a58: 687b ldr r3, [r7, #4] 8005a5a: 697a ldr r2, [r7, #20] 8005a5c: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8005a5e: 687b ldr r3, [r7, #4] 8005a60: 68fa ldr r2, [r7, #12] 8005a62: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8005a64: 683b ldr r3, [r7, #0] 8005a66: 685a ldr r2, [r3, #4] 8005a68: 687b ldr r3, [r7, #4] 8005a6a: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005a6c: 687b ldr r3, [r7, #4] 8005a6e: 693a ldr r2, [r7, #16] 8005a70: 621a str r2, [r3, #32] } 8005a72: bf00 nop 8005a74: 371c adds r7, #28 8005a76: 46bd mov sp, r7 8005a78: f85d 7b04 ldr.w r7, [sp], #4 8005a7c: 4770 bx lr 8005a7e: bf00 nop 8005a80: 40010000 .word 0x40010000 8005a84: 40010400 .word 0x40010400 08005a88 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8005a88: b480 push {r7} 8005a8a: b085 sub sp, #20 8005a8c: af00 add r7, sp, #0 8005a8e: 6078 str r0, [r7, #4] 8005a90: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8005a92: 687b ldr r3, [r7, #4] 8005a94: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005a98: 2b01 cmp r3, #1 8005a9a: d101 bne.n 8005aa0 8005a9c: 2302 movs r3, #2 8005a9e: e05a b.n 8005b56 8005aa0: 687b ldr r3, [r7, #4] 8005aa2: 2201 movs r2, #1 8005aa4: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005aa8: 687b ldr r3, [r7, #4] 8005aaa: 2202 movs r2, #2 8005aac: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8005ab0: 687b ldr r3, [r7, #4] 8005ab2: 681b ldr r3, [r3, #0] 8005ab4: 685b ldr r3, [r3, #4] 8005ab6: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005ab8: 687b ldr r3, [r7, #4] 8005aba: 681b ldr r3, [r3, #0] 8005abc: 689b ldr r3, [r3, #8] 8005abe: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8005ac0: 68fb ldr r3, [r7, #12] 8005ac2: f023 0370 bic.w r3, r3, #112 @ 0x70 8005ac6: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005ac8: 683b ldr r3, [r7, #0] 8005aca: 681b ldr r3, [r3, #0] 8005acc: 68fa ldr r2, [r7, #12] 8005ace: 4313 orrs r3, r2 8005ad0: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8005ad2: 687b ldr r3, [r7, #4] 8005ad4: 681b ldr r3, [r3, #0] 8005ad6: 68fa ldr r2, [r7, #12] 8005ad8: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005ada: 687b ldr r3, [r7, #4] 8005adc: 681b ldr r3, [r3, #0] 8005ade: 4a21 ldr r2, [pc, #132] @ (8005b64 ) 8005ae0: 4293 cmp r3, r2 8005ae2: d022 beq.n 8005b2a 8005ae4: 687b ldr r3, [r7, #4] 8005ae6: 681b ldr r3, [r3, #0] 8005ae8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005aec: d01d beq.n 8005b2a 8005aee: 687b ldr r3, [r7, #4] 8005af0: 681b ldr r3, [r3, #0] 8005af2: 4a1d ldr r2, [pc, #116] @ (8005b68 ) 8005af4: 4293 cmp r3, r2 8005af6: d018 beq.n 8005b2a 8005af8: 687b ldr r3, [r7, #4] 8005afa: 681b ldr r3, [r3, #0] 8005afc: 4a1b ldr r2, [pc, #108] @ (8005b6c ) 8005afe: 4293 cmp r3, r2 8005b00: d013 beq.n 8005b2a 8005b02: 687b ldr r3, [r7, #4] 8005b04: 681b ldr r3, [r3, #0] 8005b06: 4a1a ldr r2, [pc, #104] @ (8005b70 ) 8005b08: 4293 cmp r3, r2 8005b0a: d00e beq.n 8005b2a 8005b0c: 687b ldr r3, [r7, #4] 8005b0e: 681b ldr r3, [r3, #0] 8005b10: 4a18 ldr r2, [pc, #96] @ (8005b74 ) 8005b12: 4293 cmp r3, r2 8005b14: d009 beq.n 8005b2a 8005b16: 687b ldr r3, [r7, #4] 8005b18: 681b ldr r3, [r3, #0] 8005b1a: 4a17 ldr r2, [pc, #92] @ (8005b78 ) 8005b1c: 4293 cmp r3, r2 8005b1e: d004 beq.n 8005b2a 8005b20: 687b ldr r3, [r7, #4] 8005b22: 681b ldr r3, [r3, #0] 8005b24: 4a15 ldr r2, [pc, #84] @ (8005b7c ) 8005b26: 4293 cmp r3, r2 8005b28: d10c bne.n 8005b44 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8005b2a: 68bb ldr r3, [r7, #8] 8005b2c: f023 0380 bic.w r3, r3, #128 @ 0x80 8005b30: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8005b32: 683b ldr r3, [r7, #0] 8005b34: 685b ldr r3, [r3, #4] 8005b36: 68ba ldr r2, [r7, #8] 8005b38: 4313 orrs r3, r2 8005b3a: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005b3c: 687b ldr r3, [r7, #4] 8005b3e: 681b ldr r3, [r3, #0] 8005b40: 68ba ldr r2, [r7, #8] 8005b42: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8005b44: 687b ldr r3, [r7, #4] 8005b46: 2201 movs r2, #1 8005b48: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8005b4c: 687b ldr r3, [r7, #4] 8005b4e: 2200 movs r2, #0 8005b50: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8005b54: 2300 movs r3, #0 } 8005b56: 4618 mov r0, r3 8005b58: 3714 adds r7, #20 8005b5a: 46bd mov sp, r7 8005b5c: f85d 7b04 ldr.w r7, [sp], #4 8005b60: 4770 bx lr 8005b62: bf00 nop 8005b64: 40010000 .word 0x40010000 8005b68: 40000400 .word 0x40000400 8005b6c: 40000800 .word 0x40000800 8005b70: 40000c00 .word 0x40000c00 8005b74: 40010400 .word 0x40010400 8005b78: 40014000 .word 0x40014000 8005b7c: 40001800 .word 0x40001800 08005b80 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8005b80: b580 push {r7, lr} 8005b82: b082 sub sp, #8 8005b84: af00 add r7, sp, #0 8005b86: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8005b88: 687b ldr r3, [r7, #4] 8005b8a: 2b00 cmp r3, #0 8005b8c: d101 bne.n 8005b92 { return HAL_ERROR; 8005b8e: 2301 movs r3, #1 8005b90: e042 b.n 8005c18 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 8005b92: 687b ldr r3, [r7, #4] 8005b94: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005b98: b2db uxtb r3, r3 8005b9a: 2b00 cmp r3, #0 8005b9c: d106 bne.n 8005bac { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8005b9e: 687b ldr r3, [r7, #4] 8005ba0: 2200 movs r2, #0 8005ba2: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005ba6: 6878 ldr r0, [r7, #4] 8005ba8: f7fb fc8e bl 80014c8 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005bac: 687b ldr r3, [r7, #4] 8005bae: 2224 movs r2, #36 @ 0x24 8005bb0: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005bb4: 687b ldr r3, [r7, #4] 8005bb6: 681b ldr r3, [r3, #0] 8005bb8: 68da ldr r2, [r3, #12] 8005bba: 687b ldr r3, [r7, #4] 8005bbc: 681b ldr r3, [r3, #0] 8005bbe: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8005bc2: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005bc4: 6878 ldr r0, [r7, #4] 8005bc6: f000 ff63 bl 8006a90 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005bca: 687b ldr r3, [r7, #4] 8005bcc: 681b ldr r3, [r3, #0] 8005bce: 691a ldr r2, [r3, #16] 8005bd0: 687b ldr r3, [r7, #4] 8005bd2: 681b ldr r3, [r3, #0] 8005bd4: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8005bd8: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005bda: 687b ldr r3, [r7, #4] 8005bdc: 681b ldr r3, [r3, #0] 8005bde: 695a ldr r2, [r3, #20] 8005be0: 687b ldr r3, [r7, #4] 8005be2: 681b ldr r3, [r3, #0] 8005be4: f022 022a bic.w r2, r2, #42 @ 0x2a 8005be8: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005bea: 687b ldr r3, [r7, #4] 8005bec: 681b ldr r3, [r3, #0] 8005bee: 68da ldr r2, [r3, #12] 8005bf0: 687b ldr r3, [r7, #4] 8005bf2: 681b ldr r3, [r3, #0] 8005bf4: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8005bf8: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005bfa: 687b ldr r3, [r7, #4] 8005bfc: 2200 movs r2, #0 8005bfe: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8005c00: 687b ldr r3, [r7, #4] 8005c02: 2220 movs r2, #32 8005c04: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8005c08: 687b ldr r3, [r7, #4] 8005c0a: 2220 movs r2, #32 8005c0c: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8005c10: 687b ldr r3, [r7, #4] 8005c12: 2200 movs r2, #0 8005c14: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8005c16: 2300 movs r3, #0 } 8005c18: 4618 mov r0, r3 8005c1a: 3708 adds r7, #8 8005c1c: 46bd mov sp, r7 8005c1e: bd80 pop {r7, pc} 08005c20 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8005c20: b580 push {r7, lr} 8005c22: b08c sub sp, #48 @ 0x30 8005c24: af00 add r7, sp, #0 8005c26: 60f8 str r0, [r7, #12] 8005c28: 60b9 str r1, [r7, #8] 8005c2a: 4613 mov r3, r2 8005c2c: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8005c2e: 68fb ldr r3, [r7, #12] 8005c30: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005c34: b2db uxtb r3, r3 8005c36: 2b20 cmp r3, #32 8005c38: d162 bne.n 8005d00 { if ((pData == NULL) || (Size == 0U)) 8005c3a: 68bb ldr r3, [r7, #8] 8005c3c: 2b00 cmp r3, #0 8005c3e: d002 beq.n 8005c46 8005c40: 88fb ldrh r3, [r7, #6] 8005c42: 2b00 cmp r3, #0 8005c44: d101 bne.n 8005c4a { return HAL_ERROR; 8005c46: 2301 movs r3, #1 8005c48: e05b b.n 8005d02 } huart->pTxBuffPtr = pData; 8005c4a: 68ba ldr r2, [r7, #8] 8005c4c: 68fb ldr r3, [r7, #12] 8005c4e: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8005c50: 68fb ldr r3, [r7, #12] 8005c52: 88fa ldrh r2, [r7, #6] 8005c54: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8005c56: 68fb ldr r3, [r7, #12] 8005c58: 88fa ldrh r2, [r7, #6] 8005c5a: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8005c5c: 68fb ldr r3, [r7, #12] 8005c5e: 2200 movs r2, #0 8005c60: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8005c62: 68fb ldr r3, [r7, #12] 8005c64: 2221 movs r2, #33 @ 0x21 8005c66: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8005c6a: 68fb ldr r3, [r7, #12] 8005c6c: 6b9b ldr r3, [r3, #56] @ 0x38 8005c6e: 4a27 ldr r2, [pc, #156] @ (8005d0c ) 8005c70: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8005c72: 68fb ldr r3, [r7, #12] 8005c74: 6b9b ldr r3, [r3, #56] @ 0x38 8005c76: 4a26 ldr r2, [pc, #152] @ (8005d10 ) 8005c78: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8005c7a: 68fb ldr r3, [r7, #12] 8005c7c: 6b9b ldr r3, [r3, #56] @ 0x38 8005c7e: 4a25 ldr r2, [pc, #148] @ (8005d14 ) 8005c80: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8005c82: 68fb ldr r3, [r7, #12] 8005c84: 6b9b ldr r3, [r3, #56] @ 0x38 8005c86: 2200 movs r2, #0 8005c88: 651a str r2, [r3, #80] @ 0x50 /* Enable the UART transmit DMA stream */ tmp = (const uint32_t *)&pData; 8005c8a: f107 0308 add.w r3, r7, #8 8005c8e: 62fb str r3, [r7, #44] @ 0x2c if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) 8005c90: 68fb ldr r3, [r7, #12] 8005c92: 6b98 ldr r0, [r3, #56] @ 0x38 8005c94: 6afb ldr r3, [r7, #44] @ 0x2c 8005c96: 6819 ldr r1, [r3, #0] 8005c98: 68fb ldr r3, [r7, #12] 8005c9a: 681b ldr r3, [r3, #0] 8005c9c: 3304 adds r3, #4 8005c9e: 461a mov r2, r3 8005ca0: 88fb ldrh r3, [r7, #6] 8005ca2: f7fc f953 bl 8001f4c 8005ca6: 4603 mov r3, r0 8005ca8: 2b00 cmp r3, #0 8005caa: d008 beq.n 8005cbe { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8005cac: 68fb ldr r3, [r7, #12] 8005cae: 2210 movs r2, #16 8005cb0: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 8005cb2: 68fb ldr r3, [r7, #12] 8005cb4: 2220 movs r2, #32 8005cb6: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_ERROR; 8005cba: 2301 movs r3, #1 8005cbc: e021 b.n 8005d02 } /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8005cbe: 68fb ldr r3, [r7, #12] 8005cc0: 681b ldr r3, [r3, #0] 8005cc2: f06f 0240 mvn.w r2, #64 @ 0x40 8005cc6: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8005cc8: 68fb ldr r3, [r7, #12] 8005cca: 681b ldr r3, [r3, #0] 8005ccc: 3314 adds r3, #20 8005cce: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005cd0: 69bb ldr r3, [r7, #24] 8005cd2: e853 3f00 ldrex r3, [r3] 8005cd6: 617b str r3, [r7, #20] return(result); 8005cd8: 697b ldr r3, [r7, #20] 8005cda: f043 0380 orr.w r3, r3, #128 @ 0x80 8005cde: 62bb str r3, [r7, #40] @ 0x28 8005ce0: 68fb ldr r3, [r7, #12] 8005ce2: 681b ldr r3, [r3, #0] 8005ce4: 3314 adds r3, #20 8005ce6: 6aba ldr r2, [r7, #40] @ 0x28 8005ce8: 627a str r2, [r7, #36] @ 0x24 8005cea: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005cec: 6a39 ldr r1, [r7, #32] 8005cee: 6a7a ldr r2, [r7, #36] @ 0x24 8005cf0: e841 2300 strex r3, r2, [r1] 8005cf4: 61fb str r3, [r7, #28] return(result); 8005cf6: 69fb ldr r3, [r7, #28] 8005cf8: 2b00 cmp r3, #0 8005cfa: d1e5 bne.n 8005cc8 return HAL_OK; 8005cfc: 2300 movs r3, #0 8005cfe: e000 b.n 8005d02 } else { return HAL_BUSY; 8005d00: 2302 movs r3, #2 } } 8005d02: 4618 mov r0, r3 8005d04: 3730 adds r7, #48 @ 0x30 8005d06: 46bd mov sp, r7 8005d08: bd80 pop {r7, pc} 8005d0a: bf00 nop 8005d0c: 0800630d .word 0x0800630d 8005d10: 080063a7 .word 0x080063a7 8005d14: 0800652b .word 0x0800652b 08005d18 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8005d18: b580 push {r7, lr} 8005d1a: b084 sub sp, #16 8005d1c: af00 add r7, sp, #0 8005d1e: 60f8 str r0, [r7, #12] 8005d20: 60b9 str r1, [r7, #8] 8005d22: 4613 mov r3, r2 8005d24: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8005d26: 68fb ldr r3, [r7, #12] 8005d28: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8005d2c: b2db uxtb r3, r3 8005d2e: 2b20 cmp r3, #32 8005d30: d112 bne.n 8005d58 { if ((pData == NULL) || (Size == 0U)) 8005d32: 68bb ldr r3, [r7, #8] 8005d34: 2b00 cmp r3, #0 8005d36: d002 beq.n 8005d3e 8005d38: 88fb ldrh r3, [r7, #6] 8005d3a: 2b00 cmp r3, #0 8005d3c: d101 bne.n 8005d42 { return HAL_ERROR; 8005d3e: 2301 movs r3, #1 8005d40: e00b b.n 8005d5a } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005d42: 68fb ldr r3, [r7, #12] 8005d44: 2200 movs r2, #0 8005d46: 631a str r2, [r3, #48] @ 0x30 return (UART_Start_Receive_DMA(huart, pData, Size)); 8005d48: 88fb ldrh r3, [r7, #6] 8005d4a: 461a mov r2, r3 8005d4c: 68b9 ldr r1, [r7, #8] 8005d4e: 68f8 ldr r0, [r7, #12] 8005d50: f000 fc36 bl 80065c0 8005d54: 4603 mov r3, r0 8005d56: e000 b.n 8005d5a } else { return HAL_BUSY; 8005d58: 2302 movs r3, #2 } } 8005d5a: 4618 mov r0, r3 8005d5c: 3710 adds r7, #16 8005d5e: 46bd mov sp, r7 8005d60: bd80 pop {r7, pc} ... 08005d64 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8005d64: b580 push {r7, lr} 8005d66: b0ba sub sp, #232 @ 0xe8 8005d68: af00 add r7, sp, #0 8005d6a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8005d6c: 687b ldr r3, [r7, #4] 8005d6e: 681b ldr r3, [r3, #0] 8005d70: 681b ldr r3, [r3, #0] 8005d72: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8005d76: 687b ldr r3, [r7, #4] 8005d78: 681b ldr r3, [r3, #0] 8005d7a: 68db ldr r3, [r3, #12] 8005d7c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8005d80: 687b ldr r3, [r7, #4] 8005d82: 681b ldr r3, [r3, #0] 8005d84: 695b ldr r3, [r3, #20] 8005d86: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8005d8a: 2300 movs r3, #0 8005d8c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8005d90: 2300 movs r3, #0 8005d92: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8005d96: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d9a: f003 030f and.w r3, r3, #15 8005d9e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8005da2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005da6: 2b00 cmp r3, #0 8005da8: d10f bne.n 8005dca { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005daa: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005dae: f003 0320 and.w r3, r3, #32 8005db2: 2b00 cmp r3, #0 8005db4: d009 beq.n 8005dca 8005db6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005dba: f003 0320 and.w r3, r3, #32 8005dbe: 2b00 cmp r3, #0 8005dc0: d003 beq.n 8005dca { UART_Receive_IT(huart); 8005dc2: 6878 ldr r0, [r7, #4] 8005dc4: f000 fda6 bl 8006914 return; 8005dc8: e273 b.n 80062b2 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8005dca: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005dce: 2b00 cmp r3, #0 8005dd0: f000 80de beq.w 8005f90 8005dd4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005dd8: f003 0301 and.w r3, r3, #1 8005ddc: 2b00 cmp r3, #0 8005dde: d106 bne.n 8005dee || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8005de0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005de4: f403 7390 and.w r3, r3, #288 @ 0x120 8005de8: 2b00 cmp r3, #0 8005dea: f000 80d1 beq.w 8005f90 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8005dee: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005df2: f003 0301 and.w r3, r3, #1 8005df6: 2b00 cmp r3, #0 8005df8: d00b beq.n 8005e12 8005dfa: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005dfe: f403 7380 and.w r3, r3, #256 @ 0x100 8005e02: 2b00 cmp r3, #0 8005e04: d005 beq.n 8005e12 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8005e06: 687b ldr r3, [r7, #4] 8005e08: 6c5b ldr r3, [r3, #68] @ 0x44 8005e0a: f043 0201 orr.w r2, r3, #1 8005e0e: 687b ldr r3, [r7, #4] 8005e10: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005e12: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e16: f003 0304 and.w r3, r3, #4 8005e1a: 2b00 cmp r3, #0 8005e1c: d00b beq.n 8005e36 8005e1e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005e22: f003 0301 and.w r3, r3, #1 8005e26: 2b00 cmp r3, #0 8005e28: d005 beq.n 8005e36 { huart->ErrorCode |= HAL_UART_ERROR_NE; 8005e2a: 687b ldr r3, [r7, #4] 8005e2c: 6c5b ldr r3, [r3, #68] @ 0x44 8005e2e: f043 0202 orr.w r2, r3, #2 8005e32: 687b ldr r3, [r7, #4] 8005e34: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005e36: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e3a: f003 0302 and.w r3, r3, #2 8005e3e: 2b00 cmp r3, #0 8005e40: d00b beq.n 8005e5a 8005e42: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005e46: f003 0301 and.w r3, r3, #1 8005e4a: 2b00 cmp r3, #0 8005e4c: d005 beq.n 8005e5a { huart->ErrorCode |= HAL_UART_ERROR_FE; 8005e4e: 687b ldr r3, [r7, #4] 8005e50: 6c5b ldr r3, [r3, #68] @ 0x44 8005e52: f043 0204 orr.w r2, r3, #4 8005e56: 687b ldr r3, [r7, #4] 8005e58: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8005e5a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e5e: f003 0308 and.w r3, r3, #8 8005e62: 2b00 cmp r3, #0 8005e64: d011 beq.n 8005e8a 8005e66: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005e6a: f003 0320 and.w r3, r3, #32 8005e6e: 2b00 cmp r3, #0 8005e70: d105 bne.n 8005e7e || ((cr3its & USART_CR3_EIE) != RESET))) 8005e72: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005e76: f003 0301 and.w r3, r3, #1 8005e7a: 2b00 cmp r3, #0 8005e7c: d005 beq.n 8005e8a { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8005e7e: 687b ldr r3, [r7, #4] 8005e80: 6c5b ldr r3, [r3, #68] @ 0x44 8005e82: f043 0208 orr.w r2, r3, #8 8005e86: 687b ldr r3, [r7, #4] 8005e88: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8005e8a: 687b ldr r3, [r7, #4] 8005e8c: 6c5b ldr r3, [r3, #68] @ 0x44 8005e8e: 2b00 cmp r3, #0 8005e90: f000 820a beq.w 80062a8 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005e94: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e98: f003 0320 and.w r3, r3, #32 8005e9c: 2b00 cmp r3, #0 8005e9e: d008 beq.n 8005eb2 8005ea0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005ea4: f003 0320 and.w r3, r3, #32 8005ea8: 2b00 cmp r3, #0 8005eaa: d002 beq.n 8005eb2 { UART_Receive_IT(huart); 8005eac: 6878 ldr r0, [r7, #4] 8005eae: f000 fd31 bl 8006914 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8005eb2: 687b ldr r3, [r7, #4] 8005eb4: 681b ldr r3, [r3, #0] 8005eb6: 695b ldr r3, [r3, #20] 8005eb8: f003 0340 and.w r3, r3, #64 @ 0x40 8005ebc: 2b40 cmp r3, #64 @ 0x40 8005ebe: bf0c ite eq 8005ec0: 2301 moveq r3, #1 8005ec2: 2300 movne r3, #0 8005ec4: b2db uxtb r3, r3 8005ec6: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8005eca: 687b ldr r3, [r7, #4] 8005ecc: 6c5b ldr r3, [r3, #68] @ 0x44 8005ece: f003 0308 and.w r3, r3, #8 8005ed2: 2b00 cmp r3, #0 8005ed4: d103 bne.n 8005ede 8005ed6: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8005eda: 2b00 cmp r3, #0 8005edc: d04f beq.n 8005f7e { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8005ede: 6878 ldr r0, [r7, #4] 8005ee0: f000 fc3c bl 800675c /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005ee4: 687b ldr r3, [r7, #4] 8005ee6: 681b ldr r3, [r3, #0] 8005ee8: 695b ldr r3, [r3, #20] 8005eea: f003 0340 and.w r3, r3, #64 @ 0x40 8005eee: 2b40 cmp r3, #64 @ 0x40 8005ef0: d141 bne.n 8005f76 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005ef2: 687b ldr r3, [r7, #4] 8005ef4: 681b ldr r3, [r3, #0] 8005ef6: 3314 adds r3, #20 8005ef8: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005efc: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8005f00: e853 3f00 ldrex r3, [r3] 8005f04: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8005f08: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8005f0c: f023 0340 bic.w r3, r3, #64 @ 0x40 8005f10: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8005f14: 687b ldr r3, [r7, #4] 8005f16: 681b ldr r3, [r3, #0] 8005f18: 3314 adds r3, #20 8005f1a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8005f1e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8005f22: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005f26: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8005f2a: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8005f2e: e841 2300 strex r3, r2, [r1] 8005f32: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8005f36: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8005f3a: 2b00 cmp r3, #0 8005f3c: d1d9 bne.n 8005ef2 /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) 8005f3e: 687b ldr r3, [r7, #4] 8005f40: 6bdb ldr r3, [r3, #60] @ 0x3c 8005f42: 2b00 cmp r3, #0 8005f44: d013 beq.n 8005f6e { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8005f46: 687b ldr r3, [r7, #4] 8005f48: 6bdb ldr r3, [r3, #60] @ 0x3c 8005f4a: 4a8a ldr r2, [pc, #552] @ (8006174 ) 8005f4c: 651a str r2, [r3, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8005f4e: 687b ldr r3, [r7, #4] 8005f50: 6bdb ldr r3, [r3, #60] @ 0x3c 8005f52: 4618 mov r0, r3 8005f54: f7fc f8c2 bl 80020dc 8005f58: 4603 mov r3, r0 8005f5a: 2b00 cmp r3, #0 8005f5c: d016 beq.n 8005f8c { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8005f5e: 687b ldr r3, [r7, #4] 8005f60: 6bdb ldr r3, [r3, #60] @ 0x3c 8005f62: 6d1b ldr r3, [r3, #80] @ 0x50 8005f64: 687a ldr r2, [r7, #4] 8005f66: 6bd2 ldr r2, [r2, #60] @ 0x3c 8005f68: 4610 mov r0, r2 8005f6a: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f6c: e00e b.n 8005f8c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005f6e: 6878 ldr r0, [r7, #4] 8005f70: f7fa fe06 bl 8000b80 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f74: e00a b.n 8005f8c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005f76: 6878 ldr r0, [r7, #4] 8005f78: f7fa fe02 bl 8000b80 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f7c: e006 b.n 8005f8c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005f7e: 6878 ldr r0, [r7, #4] 8005f80: f7fa fdfe bl 8000b80 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005f84: 687b ldr r3, [r7, #4] 8005f86: 2200 movs r2, #0 8005f88: 645a str r2, [r3, #68] @ 0x44 } } return; 8005f8a: e18d b.n 80062a8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f8c: bf00 nop return; 8005f8e: e18b b.n 80062a8 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005f90: 687b ldr r3, [r7, #4] 8005f92: 6b1b ldr r3, [r3, #48] @ 0x30 8005f94: 2b01 cmp r3, #1 8005f96: f040 8167 bne.w 8006268 && ((isrflags & USART_SR_IDLE) != 0U) 8005f9a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005f9e: f003 0310 and.w r3, r3, #16 8005fa2: 2b00 cmp r3, #0 8005fa4: f000 8160 beq.w 8006268 && ((cr1its & USART_CR1_IDLEIE) != 0U)) 8005fa8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005fac: f003 0310 and.w r3, r3, #16 8005fb0: 2b00 cmp r3, #0 8005fb2: f000 8159 beq.w 8006268 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8005fb6: 2300 movs r3, #0 8005fb8: 60bb str r3, [r7, #8] 8005fba: 687b ldr r3, [r7, #4] 8005fbc: 681b ldr r3, [r3, #0] 8005fbe: 681b ldr r3, [r3, #0] 8005fc0: 60bb str r3, [r7, #8] 8005fc2: 687b ldr r3, [r7, #4] 8005fc4: 681b ldr r3, [r3, #0] 8005fc6: 685b ldr r3, [r3, #4] 8005fc8: 60bb str r3, [r7, #8] 8005fca: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005fcc: 687b ldr r3, [r7, #4] 8005fce: 681b ldr r3, [r3, #0] 8005fd0: 695b ldr r3, [r3, #20] 8005fd2: f003 0340 and.w r3, r3, #64 @ 0x40 8005fd6: 2b40 cmp r3, #64 @ 0x40 8005fd8: f040 80ce bne.w 8006178 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8005fdc: 687b ldr r3, [r7, #4] 8005fde: 6bdb ldr r3, [r3, #60] @ 0x3c 8005fe0: 681b ldr r3, [r3, #0] 8005fe2: 685b ldr r3, [r3, #4] 8005fe4: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8005fe8: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8005fec: 2b00 cmp r3, #0 8005fee: f000 80a9 beq.w 8006144 && (nb_remaining_rx_data < huart->RxXferSize)) 8005ff2: 687b ldr r3, [r7, #4] 8005ff4: 8d9b ldrh r3, [r3, #44] @ 0x2c 8005ff6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005ffa: 429a cmp r2, r3 8005ffc: f080 80a2 bcs.w 8006144 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8006000: 687b ldr r3, [r7, #4] 8006002: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006006: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8006008: 687b ldr r3, [r7, #4] 800600a: 6bdb ldr r3, [r3, #60] @ 0x3c 800600c: 69db ldr r3, [r3, #28] 800600e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006012: f000 8088 beq.w 8006126 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006016: 687b ldr r3, [r7, #4] 8006018: 681b ldr r3, [r3, #0] 800601a: 330c adds r3, #12 800601c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006020: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8006024: e853 3f00 ldrex r3, [r3] 8006028: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 800602c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8006030: f423 7380 bic.w r3, r3, #256 @ 0x100 8006034: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006038: 687b ldr r3, [r7, #4] 800603a: 681b ldr r3, [r3, #0] 800603c: 330c adds r3, #12 800603e: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8006042: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8006046: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800604a: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 800604e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8006052: e841 2300 strex r3, r2, [r1] 8006056: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 800605a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800605e: 2b00 cmp r3, #0 8006060: d1d9 bne.n 8006016 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006062: 687b ldr r3, [r7, #4] 8006064: 681b ldr r3, [r3, #0] 8006066: 3314 adds r3, #20 8006068: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800606a: 6f7b ldr r3, [r7, #116] @ 0x74 800606c: e853 3f00 ldrex r3, [r3] 8006070: 673b str r3, [r7, #112] @ 0x70 return(result); 8006072: 6f3b ldr r3, [r7, #112] @ 0x70 8006074: f023 0301 bic.w r3, r3, #1 8006078: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800607c: 687b ldr r3, [r7, #4] 800607e: 681b ldr r3, [r3, #0] 8006080: 3314 adds r3, #20 8006082: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8006086: f8c7 2080 str.w r2, [r7, #128] @ 0x80 800608a: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800608c: 6ff9 ldr r1, [r7, #124] @ 0x7c 800608e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8006092: e841 2300 strex r3, r2, [r1] 8006096: 67bb str r3, [r7, #120] @ 0x78 return(result); 8006098: 6fbb ldr r3, [r7, #120] @ 0x78 800609a: 2b00 cmp r3, #0 800609c: d1e1 bne.n 8006062 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800609e: 687b ldr r3, [r7, #4] 80060a0: 681b ldr r3, [r3, #0] 80060a2: 3314 adds r3, #20 80060a4: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80060a6: 6e3b ldr r3, [r7, #96] @ 0x60 80060a8: e853 3f00 ldrex r3, [r3] 80060ac: 65fb str r3, [r7, #92] @ 0x5c return(result); 80060ae: 6dfb ldr r3, [r7, #92] @ 0x5c 80060b0: f023 0340 bic.w r3, r3, #64 @ 0x40 80060b4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80060b8: 687b ldr r3, [r7, #4] 80060ba: 681b ldr r3, [r3, #0] 80060bc: 3314 adds r3, #20 80060be: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80060c2: 66fa str r2, [r7, #108] @ 0x6c 80060c4: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80060c6: 6eb9 ldr r1, [r7, #104] @ 0x68 80060c8: 6efa ldr r2, [r7, #108] @ 0x6c 80060ca: e841 2300 strex r3, r2, [r1] 80060ce: 667b str r3, [r7, #100] @ 0x64 return(result); 80060d0: 6e7b ldr r3, [r7, #100] @ 0x64 80060d2: 2b00 cmp r3, #0 80060d4: d1e3 bne.n 800609e /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80060d6: 687b ldr r3, [r7, #4] 80060d8: 2220 movs r2, #32 80060da: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80060de: 687b ldr r3, [r7, #4] 80060e0: 2200 movs r2, #0 80060e2: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80060e4: 687b ldr r3, [r7, #4] 80060e6: 681b ldr r3, [r3, #0] 80060e8: 330c adds r3, #12 80060ea: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80060ec: 6cfb ldr r3, [r7, #76] @ 0x4c 80060ee: e853 3f00 ldrex r3, [r3] 80060f2: 64bb str r3, [r7, #72] @ 0x48 return(result); 80060f4: 6cbb ldr r3, [r7, #72] @ 0x48 80060f6: f023 0310 bic.w r3, r3, #16 80060fa: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80060fe: 687b ldr r3, [r7, #4] 8006100: 681b ldr r3, [r3, #0] 8006102: 330c adds r3, #12 8006104: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8006108: 65ba str r2, [r7, #88] @ 0x58 800610a: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800610c: 6d79 ldr r1, [r7, #84] @ 0x54 800610e: 6dba ldr r2, [r7, #88] @ 0x58 8006110: e841 2300 strex r3, r2, [r1] 8006114: 653b str r3, [r7, #80] @ 0x50 return(result); 8006116: 6d3b ldr r3, [r7, #80] @ 0x50 8006118: 2b00 cmp r3, #0 800611a: d1e3 bne.n 80060e4 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 800611c: 687b ldr r3, [r7, #4] 800611e: 6bdb ldr r3, [r3, #60] @ 0x3c 8006120: 4618 mov r0, r3 8006122: f7fb ff6b bl 8001ffc } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006126: 687b ldr r3, [r7, #4] 8006128: 2202 movs r2, #2 800612a: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 800612c: 687b ldr r3, [r7, #4] 800612e: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006130: 687b ldr r3, [r7, #4] 8006132: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006134: b29b uxth r3, r3 8006136: 1ad3 subs r3, r2, r3 8006138: b29b uxth r3, r3 800613a: 4619 mov r1, r3 800613c: 6878 ldr r0, [r7, #4] 800613e: f000 f8d9 bl 80062f4 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 8006142: e0b3 b.n 80062ac if (nb_remaining_rx_data == huart->RxXferSize) 8006144: 687b ldr r3, [r7, #4] 8006146: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006148: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 800614c: 429a cmp r2, r3 800614e: f040 80ad bne.w 80062ac if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 8006152: 687b ldr r3, [r7, #4] 8006154: 6bdb ldr r3, [r3, #60] @ 0x3c 8006156: 69db ldr r3, [r3, #28] 8006158: f5b3 7f80 cmp.w r3, #256 @ 0x100 800615c: f040 80a6 bne.w 80062ac huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006160: 687b ldr r3, [r7, #4] 8006162: 2202 movs r2, #2 8006164: 635a str r2, [r3, #52] @ 0x34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006166: 687b ldr r3, [r7, #4] 8006168: 8d9b ldrh r3, [r3, #44] @ 0x2c 800616a: 4619 mov r1, r3 800616c: 6878 ldr r0, [r7, #4] 800616e: f000 f8c1 bl 80062f4 return; 8006172: e09b b.n 80062ac 8006174: 08006823 .word 0x08006823 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8006178: 687b ldr r3, [r7, #4] 800617a: 8d9a ldrh r2, [r3, #44] @ 0x2c 800617c: 687b ldr r3, [r7, #4] 800617e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006180: b29b uxth r3, r3 8006182: 1ad3 subs r3, r2, r3 8006184: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8006188: 687b ldr r3, [r7, #4] 800618a: 8ddb ldrh r3, [r3, #46] @ 0x2e 800618c: b29b uxth r3, r3 800618e: 2b00 cmp r3, #0 8006190: f000 808e beq.w 80062b0 && (nb_rx_data > 0U)) 8006194: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006198: 2b00 cmp r3, #0 800619a: f000 8089 beq.w 80062b0 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800619e: 687b ldr r3, [r7, #4] 80061a0: 681b ldr r3, [r3, #0] 80061a2: 330c adds r3, #12 80061a4: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80061a6: 6bbb ldr r3, [r7, #56] @ 0x38 80061a8: e853 3f00 ldrex r3, [r3] 80061ac: 637b str r3, [r7, #52] @ 0x34 return(result); 80061ae: 6b7b ldr r3, [r7, #52] @ 0x34 80061b0: f423 7390 bic.w r3, r3, #288 @ 0x120 80061b4: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80061b8: 687b ldr r3, [r7, #4] 80061ba: 681b ldr r3, [r3, #0] 80061bc: 330c adds r3, #12 80061be: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 80061c2: 647a str r2, [r7, #68] @ 0x44 80061c4: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80061c6: 6c39 ldr r1, [r7, #64] @ 0x40 80061c8: 6c7a ldr r2, [r7, #68] @ 0x44 80061ca: e841 2300 strex r3, r2, [r1] 80061ce: 63fb str r3, [r7, #60] @ 0x3c return(result); 80061d0: 6bfb ldr r3, [r7, #60] @ 0x3c 80061d2: 2b00 cmp r3, #0 80061d4: d1e3 bne.n 800619e /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80061d6: 687b ldr r3, [r7, #4] 80061d8: 681b ldr r3, [r3, #0] 80061da: 3314 adds r3, #20 80061dc: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80061de: 6a7b ldr r3, [r7, #36] @ 0x24 80061e0: e853 3f00 ldrex r3, [r3] 80061e4: 623b str r3, [r7, #32] return(result); 80061e6: 6a3b ldr r3, [r7, #32] 80061e8: f023 0301 bic.w r3, r3, #1 80061ec: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80061f0: 687b ldr r3, [r7, #4] 80061f2: 681b ldr r3, [r3, #0] 80061f4: 3314 adds r3, #20 80061f6: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80061fa: 633a str r2, [r7, #48] @ 0x30 80061fc: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80061fe: 6af9 ldr r1, [r7, #44] @ 0x2c 8006200: 6b3a ldr r2, [r7, #48] @ 0x30 8006202: e841 2300 strex r3, r2, [r1] 8006206: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006208: 6abb ldr r3, [r7, #40] @ 0x28 800620a: 2b00 cmp r3, #0 800620c: d1e3 bne.n 80061d6 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800620e: 687b ldr r3, [r7, #4] 8006210: 2220 movs r2, #32 8006212: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006216: 687b ldr r3, [r7, #4] 8006218: 2200 movs r2, #0 800621a: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800621c: 687b ldr r3, [r7, #4] 800621e: 681b ldr r3, [r3, #0] 8006220: 330c adds r3, #12 8006222: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006224: 693b ldr r3, [r7, #16] 8006226: e853 3f00 ldrex r3, [r3] 800622a: 60fb str r3, [r7, #12] return(result); 800622c: 68fb ldr r3, [r7, #12] 800622e: f023 0310 bic.w r3, r3, #16 8006232: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006236: 687b ldr r3, [r7, #4] 8006238: 681b ldr r3, [r3, #0] 800623a: 330c adds r3, #12 800623c: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8006240: 61fa str r2, [r7, #28] 8006242: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006244: 69b9 ldr r1, [r7, #24] 8006246: 69fa ldr r2, [r7, #28] 8006248: e841 2300 strex r3, r2, [r1] 800624c: 617b str r3, [r7, #20] return(result); 800624e: 697b ldr r3, [r7, #20] 8006250: 2b00 cmp r3, #0 8006252: d1e3 bne.n 800621c /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006254: 687b ldr r3, [r7, #4] 8006256: 2202 movs r2, #2 8006258: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 800625a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 800625e: 4619 mov r1, r3 8006260: 6878 ldr r0, [r7, #4] 8006262: f000 f847 bl 80062f4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8006266: e023 b.n 80062b0 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8006268: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800626c: f003 0380 and.w r3, r3, #128 @ 0x80 8006270: 2b00 cmp r3, #0 8006272: d009 beq.n 8006288 8006274: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006278: f003 0380 and.w r3, r3, #128 @ 0x80 800627c: 2b00 cmp r3, #0 800627e: d003 beq.n 8006288 { UART_Transmit_IT(huart); 8006280: 6878 ldr r0, [r7, #4] 8006282: f000 fadf bl 8006844 return; 8006286: e014 b.n 80062b2 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8006288: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800628c: f003 0340 and.w r3, r3, #64 @ 0x40 8006290: 2b00 cmp r3, #0 8006292: d00e beq.n 80062b2 8006294: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006298: f003 0340 and.w r3, r3, #64 @ 0x40 800629c: 2b00 cmp r3, #0 800629e: d008 beq.n 80062b2 { UART_EndTransmit_IT(huart); 80062a0: 6878 ldr r0, [r7, #4] 80062a2: f000 fb1f bl 80068e4 return; 80062a6: e004 b.n 80062b2 return; 80062a8: bf00 nop 80062aa: e002 b.n 80062b2 return; 80062ac: bf00 nop 80062ae: e000 b.n 80062b2 return; 80062b0: bf00 nop } } 80062b2: 37e8 adds r7, #232 @ 0xe8 80062b4: 46bd mov sp, r7 80062b6: bd80 pop {r7, pc} 080062b8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 80062b8: b480 push {r7} 80062ba: b083 sub sp, #12 80062bc: af00 add r7, sp, #0 80062be: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 80062c0: bf00 nop 80062c2: 370c adds r7, #12 80062c4: 46bd mov sp, r7 80062c6: f85d 7b04 ldr.w r7, [sp], #4 80062ca: 4770 bx lr 080062cc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 80062cc: b480 push {r7} 80062ce: b083 sub sp, #12 80062d0: af00 add r7, sp, #0 80062d2: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 80062d4: bf00 nop 80062d6: 370c adds r7, #12 80062d8: 46bd mov sp, r7 80062da: f85d 7b04 ldr.w r7, [sp], #4 80062de: 4770 bx lr 080062e0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 80062e0: b480 push {r7} 80062e2: b083 sub sp, #12 80062e4: af00 add r7, sp, #0 80062e6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 80062e8: bf00 nop 80062ea: 370c adds r7, #12 80062ec: 46bd mov sp, r7 80062ee: f85d 7b04 ldr.w r7, [sp], #4 80062f2: 4770 bx lr 080062f4 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 80062f4: b480 push {r7} 80062f6: b083 sub sp, #12 80062f8: af00 add r7, sp, #0 80062fa: 6078 str r0, [r7, #4] 80062fc: 460b mov r3, r1 80062fe: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8006300: bf00 nop 8006302: 370c adds r7, #12 8006304: 46bd mov sp, r7 8006306: f85d 7b04 ldr.w r7, [sp], #4 800630a: 4770 bx lr 0800630c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 800630c: b580 push {r7, lr} 800630e: b090 sub sp, #64 @ 0x40 8006310: af00 add r7, sp, #0 8006312: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006314: 687b ldr r3, [r7, #4] 8006316: 6b9b ldr r3, [r3, #56] @ 0x38 8006318: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 800631a: 687b ldr r3, [r7, #4] 800631c: 681b ldr r3, [r3, #0] 800631e: 681b ldr r3, [r3, #0] 8006320: f403 7380 and.w r3, r3, #256 @ 0x100 8006324: 2b00 cmp r3, #0 8006326: d137 bne.n 8006398 { huart->TxXferCount = 0x00U; 8006328: 6bfb ldr r3, [r7, #60] @ 0x3c 800632a: 2200 movs r2, #0 800632c: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 800632e: 6bfb ldr r3, [r7, #60] @ 0x3c 8006330: 681b ldr r3, [r3, #0] 8006332: 3314 adds r3, #20 8006334: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006336: 6a7b ldr r3, [r7, #36] @ 0x24 8006338: e853 3f00 ldrex r3, [r3] 800633c: 623b str r3, [r7, #32] return(result); 800633e: 6a3b ldr r3, [r7, #32] 8006340: f023 0380 bic.w r3, r3, #128 @ 0x80 8006344: 63bb str r3, [r7, #56] @ 0x38 8006346: 6bfb ldr r3, [r7, #60] @ 0x3c 8006348: 681b ldr r3, [r3, #0] 800634a: 3314 adds r3, #20 800634c: 6bba ldr r2, [r7, #56] @ 0x38 800634e: 633a str r2, [r7, #48] @ 0x30 8006350: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006352: 6af9 ldr r1, [r7, #44] @ 0x2c 8006354: 6b3a ldr r2, [r7, #48] @ 0x30 8006356: e841 2300 strex r3, r2, [r1] 800635a: 62bb str r3, [r7, #40] @ 0x28 return(result); 800635c: 6abb ldr r3, [r7, #40] @ 0x28 800635e: 2b00 cmp r3, #0 8006360: d1e5 bne.n 800632e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8006362: 6bfb ldr r3, [r7, #60] @ 0x3c 8006364: 681b ldr r3, [r3, #0] 8006366: 330c adds r3, #12 8006368: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800636a: 693b ldr r3, [r7, #16] 800636c: e853 3f00 ldrex r3, [r3] 8006370: 60fb str r3, [r7, #12] return(result); 8006372: 68fb ldr r3, [r7, #12] 8006374: f043 0340 orr.w r3, r3, #64 @ 0x40 8006378: 637b str r3, [r7, #52] @ 0x34 800637a: 6bfb ldr r3, [r7, #60] @ 0x3c 800637c: 681b ldr r3, [r3, #0] 800637e: 330c adds r3, #12 8006380: 6b7a ldr r2, [r7, #52] @ 0x34 8006382: 61fa str r2, [r7, #28] 8006384: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006386: 69b9 ldr r1, [r7, #24] 8006388: 69fa ldr r2, [r7, #28] 800638a: e841 2300 strex r3, r2, [r1] 800638e: 617b str r3, [r7, #20] return(result); 8006390: 697b ldr r3, [r7, #20] 8006392: 2b00 cmp r3, #0 8006394: d1e5 bne.n 8006362 #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006396: e002 b.n 800639e HAL_UART_TxCpltCallback(huart); 8006398: 6bf8 ldr r0, [r7, #60] @ 0x3c 800639a: f7ff ff8d bl 80062b8 } 800639e: bf00 nop 80063a0: 3740 adds r7, #64 @ 0x40 80063a2: 46bd mov sp, r7 80063a4: bd80 pop {r7, pc} 080063a6 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 80063a6: b580 push {r7, lr} 80063a8: b084 sub sp, #16 80063aa: af00 add r7, sp, #0 80063ac: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80063ae: 687b ldr r3, [r7, #4] 80063b0: 6b9b ldr r3, [r3, #56] @ 0x38 80063b2: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 80063b4: 68f8 ldr r0, [r7, #12] 80063b6: f7ff ff89 bl 80062cc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80063ba: bf00 nop 80063bc: 3710 adds r7, #16 80063be: 46bd mov sp, r7 80063c0: bd80 pop {r7, pc} 080063c2 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 80063c2: b580 push {r7, lr} 80063c4: b09c sub sp, #112 @ 0x70 80063c6: af00 add r7, sp, #0 80063c8: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80063ca: 687b ldr r3, [r7, #4] 80063cc: 6b9b ldr r3, [r3, #56] @ 0x38 80063ce: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 80063d0: 687b ldr r3, [r7, #4] 80063d2: 681b ldr r3, [r3, #0] 80063d4: 681b ldr r3, [r3, #0] 80063d6: f403 7380 and.w r3, r3, #256 @ 0x100 80063da: 2b00 cmp r3, #0 80063dc: d172 bne.n 80064c4 { huart->RxXferCount = 0U; 80063de: 6efb ldr r3, [r7, #108] @ 0x6c 80063e0: 2200 movs r2, #0 80063e2: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80063e4: 6efb ldr r3, [r7, #108] @ 0x6c 80063e6: 681b ldr r3, [r3, #0] 80063e8: 330c adds r3, #12 80063ea: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80063ec: 6cfb ldr r3, [r7, #76] @ 0x4c 80063ee: e853 3f00 ldrex r3, [r3] 80063f2: 64bb str r3, [r7, #72] @ 0x48 return(result); 80063f4: 6cbb ldr r3, [r7, #72] @ 0x48 80063f6: f423 7380 bic.w r3, r3, #256 @ 0x100 80063fa: 66bb str r3, [r7, #104] @ 0x68 80063fc: 6efb ldr r3, [r7, #108] @ 0x6c 80063fe: 681b ldr r3, [r3, #0] 8006400: 330c adds r3, #12 8006402: 6eba ldr r2, [r7, #104] @ 0x68 8006404: 65ba str r2, [r7, #88] @ 0x58 8006406: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006408: 6d79 ldr r1, [r7, #84] @ 0x54 800640a: 6dba ldr r2, [r7, #88] @ 0x58 800640c: e841 2300 strex r3, r2, [r1] 8006410: 653b str r3, [r7, #80] @ 0x50 return(result); 8006412: 6d3b ldr r3, [r7, #80] @ 0x50 8006414: 2b00 cmp r3, #0 8006416: d1e5 bne.n 80063e4 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006418: 6efb ldr r3, [r7, #108] @ 0x6c 800641a: 681b ldr r3, [r3, #0] 800641c: 3314 adds r3, #20 800641e: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006420: 6bbb ldr r3, [r7, #56] @ 0x38 8006422: e853 3f00 ldrex r3, [r3] 8006426: 637b str r3, [r7, #52] @ 0x34 return(result); 8006428: 6b7b ldr r3, [r7, #52] @ 0x34 800642a: f023 0301 bic.w r3, r3, #1 800642e: 667b str r3, [r7, #100] @ 0x64 8006430: 6efb ldr r3, [r7, #108] @ 0x6c 8006432: 681b ldr r3, [r3, #0] 8006434: 3314 adds r3, #20 8006436: 6e7a ldr r2, [r7, #100] @ 0x64 8006438: 647a str r2, [r7, #68] @ 0x44 800643a: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800643c: 6c39 ldr r1, [r7, #64] @ 0x40 800643e: 6c7a ldr r2, [r7, #68] @ 0x44 8006440: e841 2300 strex r3, r2, [r1] 8006444: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006446: 6bfb ldr r3, [r7, #60] @ 0x3c 8006448: 2b00 cmp r3, #0 800644a: d1e5 bne.n 8006418 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800644c: 6efb ldr r3, [r7, #108] @ 0x6c 800644e: 681b ldr r3, [r3, #0] 8006450: 3314 adds r3, #20 8006452: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006454: 6a7b ldr r3, [r7, #36] @ 0x24 8006456: e853 3f00 ldrex r3, [r3] 800645a: 623b str r3, [r7, #32] return(result); 800645c: 6a3b ldr r3, [r7, #32] 800645e: f023 0340 bic.w r3, r3, #64 @ 0x40 8006462: 663b str r3, [r7, #96] @ 0x60 8006464: 6efb ldr r3, [r7, #108] @ 0x6c 8006466: 681b ldr r3, [r3, #0] 8006468: 3314 adds r3, #20 800646a: 6e3a ldr r2, [r7, #96] @ 0x60 800646c: 633a str r2, [r7, #48] @ 0x30 800646e: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006470: 6af9 ldr r1, [r7, #44] @ 0x2c 8006472: 6b3a ldr r2, [r7, #48] @ 0x30 8006474: e841 2300 strex r3, r2, [r1] 8006478: 62bb str r3, [r7, #40] @ 0x28 return(result); 800647a: 6abb ldr r3, [r7, #40] @ 0x28 800647c: 2b00 cmp r3, #0 800647e: d1e5 bne.n 800644c /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006480: 6efb ldr r3, [r7, #108] @ 0x6c 8006482: 2220 movs r2, #32 8006484: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006488: 6efb ldr r3, [r7, #108] @ 0x6c 800648a: 6b1b ldr r3, [r3, #48] @ 0x30 800648c: 2b01 cmp r3, #1 800648e: d119 bne.n 80064c4 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006490: 6efb ldr r3, [r7, #108] @ 0x6c 8006492: 681b ldr r3, [r3, #0] 8006494: 330c adds r3, #12 8006496: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006498: 693b ldr r3, [r7, #16] 800649a: e853 3f00 ldrex r3, [r3] 800649e: 60fb str r3, [r7, #12] return(result); 80064a0: 68fb ldr r3, [r7, #12] 80064a2: f023 0310 bic.w r3, r3, #16 80064a6: 65fb str r3, [r7, #92] @ 0x5c 80064a8: 6efb ldr r3, [r7, #108] @ 0x6c 80064aa: 681b ldr r3, [r3, #0] 80064ac: 330c adds r3, #12 80064ae: 6dfa ldr r2, [r7, #92] @ 0x5c 80064b0: 61fa str r2, [r7, #28] 80064b2: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80064b4: 69b9 ldr r1, [r7, #24] 80064b6: 69fa ldr r2, [r7, #28] 80064b8: e841 2300 strex r3, r2, [r1] 80064bc: 617b str r3, [r7, #20] return(result); 80064be: 697b ldr r3, [r7, #20] 80064c0: 2b00 cmp r3, #0 80064c2: d1e5 bne.n 8006490 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80064c4: 6efb ldr r3, [r7, #108] @ 0x6c 80064c6: 2200 movs r2, #0 80064c8: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80064ca: 6efb ldr r3, [r7, #108] @ 0x6c 80064cc: 6b1b ldr r3, [r3, #48] @ 0x30 80064ce: 2b01 cmp r3, #1 80064d0: d106 bne.n 80064e0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80064d2: 6efb ldr r3, [r7, #108] @ 0x6c 80064d4: 8d9b ldrh r3, [r3, #44] @ 0x2c 80064d6: 4619 mov r1, r3 80064d8: 6ef8 ldr r0, [r7, #108] @ 0x6c 80064da: f7ff ff0b bl 80062f4 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80064de: e002 b.n 80064e6 HAL_UART_RxCpltCallback(huart); 80064e0: 6ef8 ldr r0, [r7, #108] @ 0x6c 80064e2: f7fa faf1 bl 8000ac8 } 80064e6: bf00 nop 80064e8: 3770 adds r7, #112 @ 0x70 80064ea: 46bd mov sp, r7 80064ec: bd80 pop {r7, pc} 080064ee : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 80064ee: b580 push {r7, lr} 80064f0: b084 sub sp, #16 80064f2: af00 add r7, sp, #0 80064f4: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80064f6: 687b ldr r3, [r7, #4] 80064f8: 6b9b ldr r3, [r3, #56] @ 0x38 80064fa: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 80064fc: 68fb ldr r3, [r7, #12] 80064fe: 2201 movs r2, #1 8006500: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006502: 68fb ldr r3, [r7, #12] 8006504: 6b1b ldr r3, [r3, #48] @ 0x30 8006506: 2b01 cmp r3, #1 8006508: d108 bne.n 800651c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 800650a: 68fb ldr r3, [r7, #12] 800650c: 8d9b ldrh r3, [r3, #44] @ 0x2c 800650e: 085b lsrs r3, r3, #1 8006510: b29b uxth r3, r3 8006512: 4619 mov r1, r3 8006514: 68f8 ldr r0, [r7, #12] 8006516: f7ff feed bl 80062f4 #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 800651a: e002 b.n 8006522 HAL_UART_RxHalfCpltCallback(huart); 800651c: 68f8 ldr r0, [r7, #12] 800651e: f7ff fedf bl 80062e0 } 8006522: bf00 nop 8006524: 3710 adds r7, #16 8006526: 46bd mov sp, r7 8006528: bd80 pop {r7, pc} 0800652a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 800652a: b580 push {r7, lr} 800652c: b084 sub sp, #16 800652e: af00 add r7, sp, #0 8006530: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8006532: 2300 movs r3, #0 8006534: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006536: 687b ldr r3, [r7, #4] 8006538: 6b9b ldr r3, [r3, #56] @ 0x38 800653a: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 800653c: 68bb ldr r3, [r7, #8] 800653e: 681b ldr r3, [r3, #0] 8006540: 695b ldr r3, [r3, #20] 8006542: f003 0380 and.w r3, r3, #128 @ 0x80 8006546: 2b80 cmp r3, #128 @ 0x80 8006548: bf0c ite eq 800654a: 2301 moveq r3, #1 800654c: 2300 movne r3, #0 800654e: b2db uxtb r3, r3 8006550: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8006552: 68bb ldr r3, [r7, #8] 8006554: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8006558: b2db uxtb r3, r3 800655a: 2b21 cmp r3, #33 @ 0x21 800655c: d108 bne.n 8006570 800655e: 68fb ldr r3, [r7, #12] 8006560: 2b00 cmp r3, #0 8006562: d005 beq.n 8006570 { huart->TxXferCount = 0x00U; 8006564: 68bb ldr r3, [r7, #8] 8006566: 2200 movs r2, #0 8006568: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 800656a: 68b8 ldr r0, [r7, #8] 800656c: f000 f8ce bl 800670c } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8006570: 68bb ldr r3, [r7, #8] 8006572: 681b ldr r3, [r3, #0] 8006574: 695b ldr r3, [r3, #20] 8006576: f003 0340 and.w r3, r3, #64 @ 0x40 800657a: 2b40 cmp r3, #64 @ 0x40 800657c: bf0c ite eq 800657e: 2301 moveq r3, #1 8006580: 2300 movne r3, #0 8006582: b2db uxtb r3, r3 8006584: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8006586: 68bb ldr r3, [r7, #8] 8006588: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800658c: b2db uxtb r3, r3 800658e: 2b22 cmp r3, #34 @ 0x22 8006590: d108 bne.n 80065a4 8006592: 68fb ldr r3, [r7, #12] 8006594: 2b00 cmp r3, #0 8006596: d005 beq.n 80065a4 { huart->RxXferCount = 0x00U; 8006598: 68bb ldr r3, [r7, #8] 800659a: 2200 movs r2, #0 800659c: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 800659e: 68b8 ldr r0, [r7, #8] 80065a0: f000 f8dc bl 800675c } huart->ErrorCode |= HAL_UART_ERROR_DMA; 80065a4: 68bb ldr r3, [r7, #8] 80065a6: 6c5b ldr r3, [r3, #68] @ 0x44 80065a8: f043 0210 orr.w r2, r3, #16 80065ac: 68bb ldr r3, [r7, #8] 80065ae: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80065b0: 68b8 ldr r0, [r7, #8] 80065b2: f7fa fae5 bl 8000b80 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80065b6: bf00 nop 80065b8: 3710 adds r7, #16 80065ba: 46bd mov sp, r7 80065bc: bd80 pop {r7, pc} ... 080065c0 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80065c0: b580 push {r7, lr} 80065c2: b098 sub sp, #96 @ 0x60 80065c4: af00 add r7, sp, #0 80065c6: 60f8 str r0, [r7, #12] 80065c8: 60b9 str r1, [r7, #8] 80065ca: 4613 mov r3, r2 80065cc: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 80065ce: 68ba ldr r2, [r7, #8] 80065d0: 68fb ldr r3, [r7, #12] 80065d2: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 80065d4: 68fb ldr r3, [r7, #12] 80065d6: 88fa ldrh r2, [r7, #6] 80065d8: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 80065da: 68fb ldr r3, [r7, #12] 80065dc: 2200 movs r2, #0 80065de: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 80065e0: 68fb ldr r3, [r7, #12] 80065e2: 2222 movs r2, #34 @ 0x22 80065e4: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 80065e8: 68fb ldr r3, [r7, #12] 80065ea: 6bdb ldr r3, [r3, #60] @ 0x3c 80065ec: 4a44 ldr r2, [pc, #272] @ (8006700 ) 80065ee: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 80065f0: 68fb ldr r3, [r7, #12] 80065f2: 6bdb ldr r3, [r3, #60] @ 0x3c 80065f4: 4a43 ldr r2, [pc, #268] @ (8006704 ) 80065f6: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 80065f8: 68fb ldr r3, [r7, #12] 80065fa: 6bdb ldr r3, [r3, #60] @ 0x3c 80065fc: 4a42 ldr r2, [pc, #264] @ (8006708 ) 80065fe: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 8006600: 68fb ldr r3, [r7, #12] 8006602: 6bdb ldr r3, [r3, #60] @ 0x3c 8006604: 2200 movs r2, #0 8006606: 651a str r2, [r3, #80] @ 0x50 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 8006608: f107 0308 add.w r3, r7, #8 800660c: 65fb str r3, [r7, #92] @ 0x5c if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) 800660e: 68fb ldr r3, [r7, #12] 8006610: 6bd8 ldr r0, [r3, #60] @ 0x3c 8006612: 68fb ldr r3, [r7, #12] 8006614: 681b ldr r3, [r3, #0] 8006616: 3304 adds r3, #4 8006618: 4619 mov r1, r3 800661a: 6dfb ldr r3, [r7, #92] @ 0x5c 800661c: 681a ldr r2, [r3, #0] 800661e: 88fb ldrh r3, [r7, #6] 8006620: f7fb fc94 bl 8001f4c 8006624: 4603 mov r3, r0 8006626: 2b00 cmp r3, #0 8006628: d008 beq.n 800663c { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 800662a: 68fb ldr r3, [r7, #12] 800662c: 2210 movs r2, #16 800662e: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 8006630: 68fb ldr r3, [r7, #12] 8006632: 2220 movs r2, #32 8006634: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_ERROR; 8006638: 2301 movs r3, #1 800663a: e05d b.n 80066f8 } /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 800663c: 2300 movs r3, #0 800663e: 613b str r3, [r7, #16] 8006640: 68fb ldr r3, [r7, #12] 8006642: 681b ldr r3, [r3, #0] 8006644: 681b ldr r3, [r3, #0] 8006646: 613b str r3, [r7, #16] 8006648: 68fb ldr r3, [r7, #12] 800664a: 681b ldr r3, [r3, #0] 800664c: 685b ldr r3, [r3, #4] 800664e: 613b str r3, [r7, #16] 8006650: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 8006652: 68fb ldr r3, [r7, #12] 8006654: 691b ldr r3, [r3, #16] 8006656: 2b00 cmp r3, #0 8006658: d019 beq.n 800668e { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800665a: 68fb ldr r3, [r7, #12] 800665c: 681b ldr r3, [r3, #0] 800665e: 330c adds r3, #12 8006660: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006662: 6c3b ldr r3, [r7, #64] @ 0x40 8006664: e853 3f00 ldrex r3, [r3] 8006668: 63fb str r3, [r7, #60] @ 0x3c return(result); 800666a: 6bfb ldr r3, [r7, #60] @ 0x3c 800666c: f443 7380 orr.w r3, r3, #256 @ 0x100 8006670: 65bb str r3, [r7, #88] @ 0x58 8006672: 68fb ldr r3, [r7, #12] 8006674: 681b ldr r3, [r3, #0] 8006676: 330c adds r3, #12 8006678: 6dba ldr r2, [r7, #88] @ 0x58 800667a: 64fa str r2, [r7, #76] @ 0x4c 800667c: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800667e: 6cb9 ldr r1, [r7, #72] @ 0x48 8006680: 6cfa ldr r2, [r7, #76] @ 0x4c 8006682: e841 2300 strex r3, r2, [r1] 8006686: 647b str r3, [r7, #68] @ 0x44 return(result); 8006688: 6c7b ldr r3, [r7, #68] @ 0x44 800668a: 2b00 cmp r3, #0 800668c: d1e5 bne.n 800665a } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800668e: 68fb ldr r3, [r7, #12] 8006690: 681b ldr r3, [r3, #0] 8006692: 3314 adds r3, #20 8006694: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006696: 6afb ldr r3, [r7, #44] @ 0x2c 8006698: e853 3f00 ldrex r3, [r3] 800669c: 62bb str r3, [r7, #40] @ 0x28 return(result); 800669e: 6abb ldr r3, [r7, #40] @ 0x28 80066a0: f043 0301 orr.w r3, r3, #1 80066a4: 657b str r3, [r7, #84] @ 0x54 80066a6: 68fb ldr r3, [r7, #12] 80066a8: 681b ldr r3, [r3, #0] 80066aa: 3314 adds r3, #20 80066ac: 6d7a ldr r2, [r7, #84] @ 0x54 80066ae: 63ba str r2, [r7, #56] @ 0x38 80066b0: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066b2: 6b79 ldr r1, [r7, #52] @ 0x34 80066b4: 6bba ldr r2, [r7, #56] @ 0x38 80066b6: e841 2300 strex r3, r2, [r1] 80066ba: 633b str r3, [r7, #48] @ 0x30 return(result); 80066bc: 6b3b ldr r3, [r7, #48] @ 0x30 80066be: 2b00 cmp r3, #0 80066c0: d1e5 bne.n 800668e /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80066c2: 68fb ldr r3, [r7, #12] 80066c4: 681b ldr r3, [r3, #0] 80066c6: 3314 adds r3, #20 80066c8: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80066ca: 69bb ldr r3, [r7, #24] 80066cc: e853 3f00 ldrex r3, [r3] 80066d0: 617b str r3, [r7, #20] return(result); 80066d2: 697b ldr r3, [r7, #20] 80066d4: f043 0340 orr.w r3, r3, #64 @ 0x40 80066d8: 653b str r3, [r7, #80] @ 0x50 80066da: 68fb ldr r3, [r7, #12] 80066dc: 681b ldr r3, [r3, #0] 80066de: 3314 adds r3, #20 80066e0: 6d3a ldr r2, [r7, #80] @ 0x50 80066e2: 627a str r2, [r7, #36] @ 0x24 80066e4: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066e6: 6a39 ldr r1, [r7, #32] 80066e8: 6a7a ldr r2, [r7, #36] @ 0x24 80066ea: e841 2300 strex r3, r2, [r1] 80066ee: 61fb str r3, [r7, #28] return(result); 80066f0: 69fb ldr r3, [r7, #28] 80066f2: 2b00 cmp r3, #0 80066f4: d1e5 bne.n 80066c2 return HAL_OK; 80066f6: 2300 movs r3, #0 } 80066f8: 4618 mov r0, r3 80066fa: 3760 adds r7, #96 @ 0x60 80066fc: 46bd mov sp, r7 80066fe: bd80 pop {r7, pc} 8006700: 080063c3 .word 0x080063c3 8006704: 080064ef .word 0x080064ef 8006708: 0800652b .word 0x0800652b 0800670c : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 800670c: b480 push {r7} 800670e: b089 sub sp, #36 @ 0x24 8006710: af00 add r7, sp, #0 8006712: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8006714: 687b ldr r3, [r7, #4] 8006716: 681b ldr r3, [r3, #0] 8006718: 330c adds r3, #12 800671a: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800671c: 68fb ldr r3, [r7, #12] 800671e: e853 3f00 ldrex r3, [r3] 8006722: 60bb str r3, [r7, #8] return(result); 8006724: 68bb ldr r3, [r7, #8] 8006726: f023 03c0 bic.w r3, r3, #192 @ 0xc0 800672a: 61fb str r3, [r7, #28] 800672c: 687b ldr r3, [r7, #4] 800672e: 681b ldr r3, [r3, #0] 8006730: 330c adds r3, #12 8006732: 69fa ldr r2, [r7, #28] 8006734: 61ba str r2, [r7, #24] 8006736: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006738: 6979 ldr r1, [r7, #20] 800673a: 69ba ldr r2, [r7, #24] 800673c: e841 2300 strex r3, r2, [r1] 8006740: 613b str r3, [r7, #16] return(result); 8006742: 693b ldr r3, [r7, #16] 8006744: 2b00 cmp r3, #0 8006746: d1e5 bne.n 8006714 /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006748: 687b ldr r3, [r7, #4] 800674a: 2220 movs r2, #32 800674c: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 8006750: bf00 nop 8006752: 3724 adds r7, #36 @ 0x24 8006754: 46bd mov sp, r7 8006756: f85d 7b04 ldr.w r7, [sp], #4 800675a: 4770 bx lr 0800675c : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 800675c: b480 push {r7} 800675e: b095 sub sp, #84 @ 0x54 8006760: af00 add r7, sp, #0 8006762: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006764: 687b ldr r3, [r7, #4] 8006766: 681b ldr r3, [r3, #0] 8006768: 330c adds r3, #12 800676a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800676c: 6b7b ldr r3, [r7, #52] @ 0x34 800676e: e853 3f00 ldrex r3, [r3] 8006772: 633b str r3, [r7, #48] @ 0x30 return(result); 8006774: 6b3b ldr r3, [r7, #48] @ 0x30 8006776: f423 7390 bic.w r3, r3, #288 @ 0x120 800677a: 64fb str r3, [r7, #76] @ 0x4c 800677c: 687b ldr r3, [r7, #4] 800677e: 681b ldr r3, [r3, #0] 8006780: 330c adds r3, #12 8006782: 6cfa ldr r2, [r7, #76] @ 0x4c 8006784: 643a str r2, [r7, #64] @ 0x40 8006786: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006788: 6bf9 ldr r1, [r7, #60] @ 0x3c 800678a: 6c3a ldr r2, [r7, #64] @ 0x40 800678c: e841 2300 strex r3, r2, [r1] 8006790: 63bb str r3, [r7, #56] @ 0x38 return(result); 8006792: 6bbb ldr r3, [r7, #56] @ 0x38 8006794: 2b00 cmp r3, #0 8006796: d1e5 bne.n 8006764 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006798: 687b ldr r3, [r7, #4] 800679a: 681b ldr r3, [r3, #0] 800679c: 3314 adds r3, #20 800679e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80067a0: 6a3b ldr r3, [r7, #32] 80067a2: e853 3f00 ldrex r3, [r3] 80067a6: 61fb str r3, [r7, #28] return(result); 80067a8: 69fb ldr r3, [r7, #28] 80067aa: f023 0301 bic.w r3, r3, #1 80067ae: 64bb str r3, [r7, #72] @ 0x48 80067b0: 687b ldr r3, [r7, #4] 80067b2: 681b ldr r3, [r3, #0] 80067b4: 3314 adds r3, #20 80067b6: 6cba ldr r2, [r7, #72] @ 0x48 80067b8: 62fa str r2, [r7, #44] @ 0x2c 80067ba: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067bc: 6ab9 ldr r1, [r7, #40] @ 0x28 80067be: 6afa ldr r2, [r7, #44] @ 0x2c 80067c0: e841 2300 strex r3, r2, [r1] 80067c4: 627b str r3, [r7, #36] @ 0x24 return(result); 80067c6: 6a7b ldr r3, [r7, #36] @ 0x24 80067c8: 2b00 cmp r3, #0 80067ca: d1e5 bne.n 8006798 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80067cc: 687b ldr r3, [r7, #4] 80067ce: 6b1b ldr r3, [r3, #48] @ 0x30 80067d0: 2b01 cmp r3, #1 80067d2: d119 bne.n 8006808 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80067d4: 687b ldr r3, [r7, #4] 80067d6: 681b ldr r3, [r3, #0] 80067d8: 330c adds r3, #12 80067da: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80067dc: 68fb ldr r3, [r7, #12] 80067de: e853 3f00 ldrex r3, [r3] 80067e2: 60bb str r3, [r7, #8] return(result); 80067e4: 68bb ldr r3, [r7, #8] 80067e6: f023 0310 bic.w r3, r3, #16 80067ea: 647b str r3, [r7, #68] @ 0x44 80067ec: 687b ldr r3, [r7, #4] 80067ee: 681b ldr r3, [r3, #0] 80067f0: 330c adds r3, #12 80067f2: 6c7a ldr r2, [r7, #68] @ 0x44 80067f4: 61ba str r2, [r7, #24] 80067f6: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067f8: 6979 ldr r1, [r7, #20] 80067fa: 69ba ldr r2, [r7, #24] 80067fc: e841 2300 strex r3, r2, [r1] 8006800: 613b str r3, [r7, #16] return(result); 8006802: 693b ldr r3, [r7, #16] 8006804: 2b00 cmp r3, #0 8006806: d1e5 bne.n 80067d4 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006808: 687b ldr r3, [r7, #4] 800680a: 2220 movs r2, #32 800680c: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006810: 687b ldr r3, [r7, #4] 8006812: 2200 movs r2, #0 8006814: 631a str r2, [r3, #48] @ 0x30 } 8006816: bf00 nop 8006818: 3754 adds r7, #84 @ 0x54 800681a: 46bd mov sp, r7 800681c: f85d 7b04 ldr.w r7, [sp], #4 8006820: 4770 bx lr 08006822 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8006822: b580 push {r7, lr} 8006824: b084 sub sp, #16 8006826: af00 add r7, sp, #0 8006828: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800682a: 687b ldr r3, [r7, #4] 800682c: 6b9b ldr r3, [r3, #56] @ 0x38 800682e: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8006830: 68fb ldr r3, [r7, #12] 8006832: 2200 movs r2, #0 8006834: 85da strh r2, [r3, #46] @ 0x2e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006836: 68f8 ldr r0, [r7, #12] 8006838: f7fa f9a2 bl 8000b80 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800683c: bf00 nop 800683e: 3710 adds r7, #16 8006840: 46bd mov sp, r7 8006842: bd80 pop {r7, pc} 08006844 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8006844: b480 push {r7} 8006846: b085 sub sp, #20 8006848: af00 add r7, sp, #0 800684a: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800684c: 687b ldr r3, [r7, #4] 800684e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8006852: b2db uxtb r3, r3 8006854: 2b21 cmp r3, #33 @ 0x21 8006856: d13e bne.n 80068d6 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006858: 687b ldr r3, [r7, #4] 800685a: 689b ldr r3, [r3, #8] 800685c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006860: d114 bne.n 800688c 8006862: 687b ldr r3, [r7, #4] 8006864: 691b ldr r3, [r3, #16] 8006866: 2b00 cmp r3, #0 8006868: d110 bne.n 800688c { tmp = (const uint16_t *) huart->pTxBuffPtr; 800686a: 687b ldr r3, [r7, #4] 800686c: 6a1b ldr r3, [r3, #32] 800686e: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8006870: 68fb ldr r3, [r7, #12] 8006872: 881b ldrh r3, [r3, #0] 8006874: 461a mov r2, r3 8006876: 687b ldr r3, [r7, #4] 8006878: 681b ldr r3, [r3, #0] 800687a: f3c2 0208 ubfx r2, r2, #0, #9 800687e: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8006880: 687b ldr r3, [r7, #4] 8006882: 6a1b ldr r3, [r3, #32] 8006884: 1c9a adds r2, r3, #2 8006886: 687b ldr r3, [r7, #4] 8006888: 621a str r2, [r3, #32] 800688a: e008 b.n 800689e } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 800688c: 687b ldr r3, [r7, #4] 800688e: 6a1b ldr r3, [r3, #32] 8006890: 1c59 adds r1, r3, #1 8006892: 687a ldr r2, [r7, #4] 8006894: 6211 str r1, [r2, #32] 8006896: 781a ldrb r2, [r3, #0] 8006898: 687b ldr r3, [r7, #4] 800689a: 681b ldr r3, [r3, #0] 800689c: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 800689e: 687b ldr r3, [r7, #4] 80068a0: 8cdb ldrh r3, [r3, #38] @ 0x26 80068a2: b29b uxth r3, r3 80068a4: 3b01 subs r3, #1 80068a6: b29b uxth r3, r3 80068a8: 687a ldr r2, [r7, #4] 80068aa: 4619 mov r1, r3 80068ac: 84d1 strh r1, [r2, #38] @ 0x26 80068ae: 2b00 cmp r3, #0 80068b0: d10f bne.n 80068d2 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 80068b2: 687b ldr r3, [r7, #4] 80068b4: 681b ldr r3, [r3, #0] 80068b6: 68da ldr r2, [r3, #12] 80068b8: 687b ldr r3, [r7, #4] 80068ba: 681b ldr r3, [r3, #0] 80068bc: f022 0280 bic.w r2, r2, #128 @ 0x80 80068c0: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 80068c2: 687b ldr r3, [r7, #4] 80068c4: 681b ldr r3, [r3, #0] 80068c6: 68da ldr r2, [r3, #12] 80068c8: 687b ldr r3, [r7, #4] 80068ca: 681b ldr r3, [r3, #0] 80068cc: f042 0240 orr.w r2, r2, #64 @ 0x40 80068d0: 60da str r2, [r3, #12] } return HAL_OK; 80068d2: 2300 movs r3, #0 80068d4: e000 b.n 80068d8 } else { return HAL_BUSY; 80068d6: 2302 movs r3, #2 } } 80068d8: 4618 mov r0, r3 80068da: 3714 adds r7, #20 80068dc: 46bd mov sp, r7 80068de: f85d 7b04 ldr.w r7, [sp], #4 80068e2: 4770 bx lr 080068e4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80068e4: b580 push {r7, lr} 80068e6: b082 sub sp, #8 80068e8: af00 add r7, sp, #0 80068ea: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80068ec: 687b ldr r3, [r7, #4] 80068ee: 681b ldr r3, [r3, #0] 80068f0: 68da ldr r2, [r3, #12] 80068f2: 687b ldr r3, [r7, #4] 80068f4: 681b ldr r3, [r3, #0] 80068f6: f022 0240 bic.w r2, r2, #64 @ 0x40 80068fa: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80068fc: 687b ldr r3, [r7, #4] 80068fe: 2220 movs r2, #32 8006900: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8006904: 6878 ldr r0, [r7, #4] 8006906: f7ff fcd7 bl 80062b8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 800690a: 2300 movs r3, #0 } 800690c: 4618 mov r0, r3 800690e: 3708 adds r7, #8 8006910: 46bd mov sp, r7 8006912: bd80 pop {r7, pc} 08006914 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8006914: b580 push {r7, lr} 8006916: b08c sub sp, #48 @ 0x30 8006918: af00 add r7, sp, #0 800691a: 6078 str r0, [r7, #4] uint8_t *pdata8bits = NULL; 800691c: 2300 movs r3, #0 800691e: 62fb str r3, [r7, #44] @ 0x2c uint16_t *pdata16bits = NULL; 8006920: 2300 movs r3, #0 8006922: 62bb str r3, [r7, #40] @ 0x28 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006924: 687b ldr r3, [r7, #4] 8006926: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800692a: b2db uxtb r3, r3 800692c: 2b22 cmp r3, #34 @ 0x22 800692e: f040 80aa bne.w 8006a86 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006932: 687b ldr r3, [r7, #4] 8006934: 689b ldr r3, [r3, #8] 8006936: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800693a: d115 bne.n 8006968 800693c: 687b ldr r3, [r7, #4] 800693e: 691b ldr r3, [r3, #16] 8006940: 2b00 cmp r3, #0 8006942: d111 bne.n 8006968 { /* Unused pdata8bits */ UNUSED(pdata8bits); pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8006944: 687b ldr r3, [r7, #4] 8006946: 6a9b ldr r3, [r3, #40] @ 0x28 8006948: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 800694a: 687b ldr r3, [r7, #4] 800694c: 681b ldr r3, [r3, #0] 800694e: 685b ldr r3, [r3, #4] 8006950: b29b uxth r3, r3 8006952: f3c3 0308 ubfx r3, r3, #0, #9 8006956: b29a uxth r2, r3 8006958: 6abb ldr r3, [r7, #40] @ 0x28 800695a: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 800695c: 687b ldr r3, [r7, #4] 800695e: 6a9b ldr r3, [r3, #40] @ 0x28 8006960: 1c9a adds r2, r3, #2 8006962: 687b ldr r3, [r7, #4] 8006964: 629a str r2, [r3, #40] @ 0x28 8006966: e024 b.n 80069b2 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8006968: 687b ldr r3, [r7, #4] 800696a: 6a9b ldr r3, [r3, #40] @ 0x28 800696c: 62fb str r3, [r7, #44] @ 0x2c /* Unused pdata16bits */ UNUSED(pdata16bits); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 800696e: 687b ldr r3, [r7, #4] 8006970: 689b ldr r3, [r3, #8] 8006972: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006976: d007 beq.n 8006988 8006978: 687b ldr r3, [r7, #4] 800697a: 689b ldr r3, [r3, #8] 800697c: 2b00 cmp r3, #0 800697e: d10a bne.n 8006996 8006980: 687b ldr r3, [r7, #4] 8006982: 691b ldr r3, [r3, #16] 8006984: 2b00 cmp r3, #0 8006986: d106 bne.n 8006996 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8006988: 687b ldr r3, [r7, #4] 800698a: 681b ldr r3, [r3, #0] 800698c: 685b ldr r3, [r3, #4] 800698e: b2da uxtb r2, r3 8006990: 6afb ldr r3, [r7, #44] @ 0x2c 8006992: 701a strb r2, [r3, #0] 8006994: e008 b.n 80069a8 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8006996: 687b ldr r3, [r7, #4] 8006998: 681b ldr r3, [r3, #0] 800699a: 685b ldr r3, [r3, #4] 800699c: b2db uxtb r3, r3 800699e: f003 037f and.w r3, r3, #127 @ 0x7f 80069a2: b2da uxtb r2, r3 80069a4: 6afb ldr r3, [r7, #44] @ 0x2c 80069a6: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 80069a8: 687b ldr r3, [r7, #4] 80069aa: 6a9b ldr r3, [r3, #40] @ 0x28 80069ac: 1c5a adds r2, r3, #1 80069ae: 687b ldr r3, [r7, #4] 80069b0: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 80069b2: 687b ldr r3, [r7, #4] 80069b4: 8ddb ldrh r3, [r3, #46] @ 0x2e 80069b6: b29b uxth r3, r3 80069b8: 3b01 subs r3, #1 80069ba: b29b uxth r3, r3 80069bc: 687a ldr r2, [r7, #4] 80069be: 4619 mov r1, r3 80069c0: 85d1 strh r1, [r2, #46] @ 0x2e 80069c2: 2b00 cmp r3, #0 80069c4: d15d bne.n 8006a82 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 80069c6: 687b ldr r3, [r7, #4] 80069c8: 681b ldr r3, [r3, #0] 80069ca: 68da ldr r2, [r3, #12] 80069cc: 687b ldr r3, [r7, #4] 80069ce: 681b ldr r3, [r3, #0] 80069d0: f022 0220 bic.w r2, r2, #32 80069d4: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 80069d6: 687b ldr r3, [r7, #4] 80069d8: 681b ldr r3, [r3, #0] 80069da: 68da ldr r2, [r3, #12] 80069dc: 687b ldr r3, [r7, #4] 80069de: 681b ldr r3, [r3, #0] 80069e0: f422 7280 bic.w r2, r2, #256 @ 0x100 80069e4: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 80069e6: 687b ldr r3, [r7, #4] 80069e8: 681b ldr r3, [r3, #0] 80069ea: 695a ldr r2, [r3, #20] 80069ec: 687b ldr r3, [r7, #4] 80069ee: 681b ldr r3, [r3, #0] 80069f0: f022 0201 bic.w r2, r2, #1 80069f4: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80069f6: 687b ldr r3, [r7, #4] 80069f8: 2220 movs r2, #32 80069fa: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80069fe: 687b ldr r3, [r7, #4] 8006a00: 2200 movs r2, #0 8006a02: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006a04: 687b ldr r3, [r7, #4] 8006a06: 6b1b ldr r3, [r3, #48] @ 0x30 8006a08: 2b01 cmp r3, #1 8006a0a: d135 bne.n 8006a78 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006a0c: 687b ldr r3, [r7, #4] 8006a0e: 2200 movs r2, #0 8006a10: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006a12: 687b ldr r3, [r7, #4] 8006a14: 681b ldr r3, [r3, #0] 8006a16: 330c adds r3, #12 8006a18: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006a1a: 697b ldr r3, [r7, #20] 8006a1c: e853 3f00 ldrex r3, [r3] 8006a20: 613b str r3, [r7, #16] return(result); 8006a22: 693b ldr r3, [r7, #16] 8006a24: f023 0310 bic.w r3, r3, #16 8006a28: 627b str r3, [r7, #36] @ 0x24 8006a2a: 687b ldr r3, [r7, #4] 8006a2c: 681b ldr r3, [r3, #0] 8006a2e: 330c adds r3, #12 8006a30: 6a7a ldr r2, [r7, #36] @ 0x24 8006a32: 623a str r2, [r7, #32] 8006a34: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006a36: 69f9 ldr r1, [r7, #28] 8006a38: 6a3a ldr r2, [r7, #32] 8006a3a: e841 2300 strex r3, r2, [r1] 8006a3e: 61bb str r3, [r7, #24] return(result); 8006a40: 69bb ldr r3, [r7, #24] 8006a42: 2b00 cmp r3, #0 8006a44: d1e5 bne.n 8006a12 /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8006a46: 687b ldr r3, [r7, #4] 8006a48: 681b ldr r3, [r3, #0] 8006a4a: 681b ldr r3, [r3, #0] 8006a4c: f003 0310 and.w r3, r3, #16 8006a50: 2b10 cmp r3, #16 8006a52: d10a bne.n 8006a6a { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8006a54: 2300 movs r3, #0 8006a56: 60fb str r3, [r7, #12] 8006a58: 687b ldr r3, [r7, #4] 8006a5a: 681b ldr r3, [r3, #0] 8006a5c: 681b ldr r3, [r3, #0] 8006a5e: 60fb str r3, [r7, #12] 8006a60: 687b ldr r3, [r7, #4] 8006a62: 681b ldr r3, [r3, #0] 8006a64: 685b ldr r3, [r3, #4] 8006a66: 60fb str r3, [r7, #12] 8006a68: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006a6a: 687b ldr r3, [r7, #4] 8006a6c: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006a6e: 4619 mov r1, r3 8006a70: 6878 ldr r0, [r7, #4] 8006a72: f7ff fc3f bl 80062f4 8006a76: e002 b.n 8006a7e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8006a78: 6878 ldr r0, [r7, #4] 8006a7a: f7fa f825 bl 8000ac8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8006a7e: 2300 movs r3, #0 8006a80: e002 b.n 8006a88 } return HAL_OK; 8006a82: 2300 movs r3, #0 8006a84: e000 b.n 8006a88 } else { return HAL_BUSY; 8006a86: 2302 movs r3, #2 } } 8006a88: 4618 mov r0, r3 8006a8a: 3730 adds r7, #48 @ 0x30 8006a8c: 46bd mov sp, r7 8006a8e: bd80 pop {r7, pc} 08006a90 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8006a90: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8006a94: b0c0 sub sp, #256 @ 0x100 8006a96: af00 add r7, sp, #0 8006a98: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8006a9c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006aa0: 681b ldr r3, [r3, #0] 8006aa2: 691b ldr r3, [r3, #16] 8006aa4: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8006aa8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006aac: 68d9 ldr r1, [r3, #12] 8006aae: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ab2: 681a ldr r2, [r3, #0] 8006ab4: ea40 0301 orr.w r3, r0, r1 8006ab8: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8006aba: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006abe: 689a ldr r2, [r3, #8] 8006ac0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ac4: 691b ldr r3, [r3, #16] 8006ac6: 431a orrs r2, r3 8006ac8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006acc: 695b ldr r3, [r3, #20] 8006ace: 431a orrs r2, r3 8006ad0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ad4: 69db ldr r3, [r3, #28] 8006ad6: 4313 orrs r3, r2 8006ad8: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 8006adc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ae0: 681b ldr r3, [r3, #0] 8006ae2: 68db ldr r3, [r3, #12] 8006ae4: f423 4116 bic.w r1, r3, #38400 @ 0x9600 8006ae8: f021 010c bic.w r1, r1, #12 8006aec: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006af0: 681a ldr r2, [r3, #0] 8006af2: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 8006af6: 430b orrs r3, r1 8006af8: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8006afa: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006afe: 681b ldr r3, [r3, #0] 8006b00: 695b ldr r3, [r3, #20] 8006b02: f423 7040 bic.w r0, r3, #768 @ 0x300 8006b06: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b0a: 6999 ldr r1, [r3, #24] 8006b0c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b10: 681a ldr r2, [r3, #0] 8006b12: ea40 0301 orr.w r3, r0, r1 8006b16: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 8006b18: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b1c: 681a ldr r2, [r3, #0] 8006b1e: 4b8f ldr r3, [pc, #572] @ (8006d5c ) 8006b20: 429a cmp r2, r3 8006b22: d005 beq.n 8006b30 8006b24: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b28: 681a ldr r2, [r3, #0] 8006b2a: 4b8d ldr r3, [pc, #564] @ (8006d60 ) 8006b2c: 429a cmp r2, r3 8006b2e: d104 bne.n 8006b3a { pclk = HAL_RCC_GetPCLK2Freq(); 8006b30: f7fd fbf6 bl 8004320 8006b34: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8006b38: e003 b.n 8006b42 pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8006b3a: f7fd fbdd bl 80042f8 8006b3e: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8006b42: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b46: 69db ldr r3, [r3, #28] 8006b48: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8006b4c: f040 810c bne.w 8006d68 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8006b50: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006b54: 2200 movs r2, #0 8006b56: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8006b5a: f8c7 20ec str.w r2, [r7, #236] @ 0xec 8006b5e: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 8006b62: 4622 mov r2, r4 8006b64: 462b mov r3, r5 8006b66: 1891 adds r1, r2, r2 8006b68: 65b9 str r1, [r7, #88] @ 0x58 8006b6a: 415b adcs r3, r3 8006b6c: 65fb str r3, [r7, #92] @ 0x5c 8006b6e: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8006b72: 4621 mov r1, r4 8006b74: eb12 0801 adds.w r8, r2, r1 8006b78: 4629 mov r1, r5 8006b7a: eb43 0901 adc.w r9, r3, r1 8006b7e: f04f 0200 mov.w r2, #0 8006b82: f04f 0300 mov.w r3, #0 8006b86: ea4f 03c9 mov.w r3, r9, lsl #3 8006b8a: ea43 7358 orr.w r3, r3, r8, lsr #29 8006b8e: ea4f 02c8 mov.w r2, r8, lsl #3 8006b92: 4690 mov r8, r2 8006b94: 4699 mov r9, r3 8006b96: 4623 mov r3, r4 8006b98: eb18 0303 adds.w r3, r8, r3 8006b9c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 8006ba0: 462b mov r3, r5 8006ba2: eb49 0303 adc.w r3, r9, r3 8006ba6: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8006baa: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bae: 685b ldr r3, [r3, #4] 8006bb0: 2200 movs r2, #0 8006bb2: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8006bb6: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 8006bba: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 8006bbe: 460b mov r3, r1 8006bc0: 18db adds r3, r3, r3 8006bc2: 653b str r3, [r7, #80] @ 0x50 8006bc4: 4613 mov r3, r2 8006bc6: eb42 0303 adc.w r3, r2, r3 8006bca: 657b str r3, [r7, #84] @ 0x54 8006bcc: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 8006bd0: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 8006bd4: f7f9 fb16 bl 8000204 <__aeabi_uldivmod> 8006bd8: 4602 mov r2, r0 8006bda: 460b mov r3, r1 8006bdc: 4b61 ldr r3, [pc, #388] @ (8006d64 ) 8006bde: fba3 2302 umull r2, r3, r3, r2 8006be2: 095b lsrs r3, r3, #5 8006be4: 011c lsls r4, r3, #4 8006be6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006bea: 2200 movs r2, #0 8006bec: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8006bf0: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 8006bf4: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8006bf8: 4642 mov r2, r8 8006bfa: 464b mov r3, r9 8006bfc: 1891 adds r1, r2, r2 8006bfe: 64b9 str r1, [r7, #72] @ 0x48 8006c00: 415b adcs r3, r3 8006c02: 64fb str r3, [r7, #76] @ 0x4c 8006c04: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8006c08: 4641 mov r1, r8 8006c0a: eb12 0a01 adds.w sl, r2, r1 8006c0e: 4649 mov r1, r9 8006c10: eb43 0b01 adc.w fp, r3, r1 8006c14: f04f 0200 mov.w r2, #0 8006c18: f04f 0300 mov.w r3, #0 8006c1c: ea4f 03cb mov.w r3, fp, lsl #3 8006c20: ea43 735a orr.w r3, r3, sl, lsr #29 8006c24: ea4f 02ca mov.w r2, sl, lsl #3 8006c28: 4692 mov sl, r2 8006c2a: 469b mov fp, r3 8006c2c: 4643 mov r3, r8 8006c2e: eb1a 0303 adds.w r3, sl, r3 8006c32: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006c36: 464b mov r3, r9 8006c38: eb4b 0303 adc.w r3, fp, r3 8006c3c: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8006c40: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006c44: 685b ldr r3, [r3, #4] 8006c46: 2200 movs r2, #0 8006c48: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006c4c: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 8006c50: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8006c54: 460b mov r3, r1 8006c56: 18db adds r3, r3, r3 8006c58: 643b str r3, [r7, #64] @ 0x40 8006c5a: 4613 mov r3, r2 8006c5c: eb42 0303 adc.w r3, r2, r3 8006c60: 647b str r3, [r7, #68] @ 0x44 8006c62: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 8006c66: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 8006c6a: f7f9 facb bl 8000204 <__aeabi_uldivmod> 8006c6e: 4602 mov r2, r0 8006c70: 460b mov r3, r1 8006c72: 4611 mov r1, r2 8006c74: 4b3b ldr r3, [pc, #236] @ (8006d64 ) 8006c76: fba3 2301 umull r2, r3, r3, r1 8006c7a: 095b lsrs r3, r3, #5 8006c7c: 2264 movs r2, #100 @ 0x64 8006c7e: fb02 f303 mul.w r3, r2, r3 8006c82: 1acb subs r3, r1, r3 8006c84: 00db lsls r3, r3, #3 8006c86: f103 0232 add.w r2, r3, #50 @ 0x32 8006c8a: 4b36 ldr r3, [pc, #216] @ (8006d64 ) 8006c8c: fba3 2302 umull r2, r3, r3, r2 8006c90: 095b lsrs r3, r3, #5 8006c92: 005b lsls r3, r3, #1 8006c94: f403 73f8 and.w r3, r3, #496 @ 0x1f0 8006c98: 441c add r4, r3 8006c9a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006c9e: 2200 movs r2, #0 8006ca0: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006ca4: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8006ca8: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 8006cac: 4642 mov r2, r8 8006cae: 464b mov r3, r9 8006cb0: 1891 adds r1, r2, r2 8006cb2: 63b9 str r1, [r7, #56] @ 0x38 8006cb4: 415b adcs r3, r3 8006cb6: 63fb str r3, [r7, #60] @ 0x3c 8006cb8: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 8006cbc: 4641 mov r1, r8 8006cbe: 1851 adds r1, r2, r1 8006cc0: 6339 str r1, [r7, #48] @ 0x30 8006cc2: 4649 mov r1, r9 8006cc4: 414b adcs r3, r1 8006cc6: 637b str r3, [r7, #52] @ 0x34 8006cc8: f04f 0200 mov.w r2, #0 8006ccc: f04f 0300 mov.w r3, #0 8006cd0: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 8006cd4: 4659 mov r1, fp 8006cd6: 00cb lsls r3, r1, #3 8006cd8: 4651 mov r1, sl 8006cda: ea43 7351 orr.w r3, r3, r1, lsr #29 8006cde: 4651 mov r1, sl 8006ce0: 00ca lsls r2, r1, #3 8006ce2: 4610 mov r0, r2 8006ce4: 4619 mov r1, r3 8006ce6: 4603 mov r3, r0 8006ce8: 4642 mov r2, r8 8006cea: 189b adds r3, r3, r2 8006cec: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8006cf0: 464b mov r3, r9 8006cf2: 460a mov r2, r1 8006cf4: eb42 0303 adc.w r3, r2, r3 8006cf8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006cfc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006d00: 685b ldr r3, [r3, #4] 8006d02: 2200 movs r2, #0 8006d04: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8006d08: f8c7 20ac str.w r2, [r7, #172] @ 0xac 8006d0c: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8006d10: 460b mov r3, r1 8006d12: 18db adds r3, r3, r3 8006d14: 62bb str r3, [r7, #40] @ 0x28 8006d16: 4613 mov r3, r2 8006d18: eb42 0303 adc.w r3, r2, r3 8006d1c: 62fb str r3, [r7, #44] @ 0x2c 8006d1e: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 8006d22: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 8006d26: f7f9 fa6d bl 8000204 <__aeabi_uldivmod> 8006d2a: 4602 mov r2, r0 8006d2c: 460b mov r3, r1 8006d2e: 4b0d ldr r3, [pc, #52] @ (8006d64 ) 8006d30: fba3 1302 umull r1, r3, r3, r2 8006d34: 095b lsrs r3, r3, #5 8006d36: 2164 movs r1, #100 @ 0x64 8006d38: fb01 f303 mul.w r3, r1, r3 8006d3c: 1ad3 subs r3, r2, r3 8006d3e: 00db lsls r3, r3, #3 8006d40: 3332 adds r3, #50 @ 0x32 8006d42: 4a08 ldr r2, [pc, #32] @ (8006d64 ) 8006d44: fba2 2303 umull r2, r3, r2, r3 8006d48: 095b lsrs r3, r3, #5 8006d4a: f003 0207 and.w r2, r3, #7 8006d4e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006d52: 681b ldr r3, [r3, #0] 8006d54: 4422 add r2, r4 8006d56: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8006d58: e106 b.n 8006f68 8006d5a: bf00 nop 8006d5c: 40011000 .word 0x40011000 8006d60: 40011400 .word 0x40011400 8006d64: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8006d68: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006d6c: 2200 movs r2, #0 8006d6e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8006d72: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 8006d76: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8006d7a: 4642 mov r2, r8 8006d7c: 464b mov r3, r9 8006d7e: 1891 adds r1, r2, r2 8006d80: 6239 str r1, [r7, #32] 8006d82: 415b adcs r3, r3 8006d84: 627b str r3, [r7, #36] @ 0x24 8006d86: e9d7 2308 ldrd r2, r3, [r7, #32] 8006d8a: 4641 mov r1, r8 8006d8c: 1854 adds r4, r2, r1 8006d8e: 4649 mov r1, r9 8006d90: eb43 0501 adc.w r5, r3, r1 8006d94: f04f 0200 mov.w r2, #0 8006d98: f04f 0300 mov.w r3, #0 8006d9c: 00eb lsls r3, r5, #3 8006d9e: ea43 7354 orr.w r3, r3, r4, lsr #29 8006da2: 00e2 lsls r2, r4, #3 8006da4: 4614 mov r4, r2 8006da6: 461d mov r5, r3 8006da8: 4643 mov r3, r8 8006daa: 18e3 adds r3, r4, r3 8006dac: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8006db0: 464b mov r3, r9 8006db2: eb45 0303 adc.w r3, r5, r3 8006db6: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8006dba: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006dbe: 685b ldr r3, [r3, #4] 8006dc0: 2200 movs r2, #0 8006dc2: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8006dc6: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8006dca: f04f 0200 mov.w r2, #0 8006dce: f04f 0300 mov.w r3, #0 8006dd2: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8006dd6: 4629 mov r1, r5 8006dd8: 008b lsls r3, r1, #2 8006dda: 4621 mov r1, r4 8006ddc: ea43 7391 orr.w r3, r3, r1, lsr #30 8006de0: 4621 mov r1, r4 8006de2: 008a lsls r2, r1, #2 8006de4: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 8006de8: f7f9 fa0c bl 8000204 <__aeabi_uldivmod> 8006dec: 4602 mov r2, r0 8006dee: 460b mov r3, r1 8006df0: 4b60 ldr r3, [pc, #384] @ (8006f74 ) 8006df2: fba3 2302 umull r2, r3, r3, r2 8006df6: 095b lsrs r3, r3, #5 8006df8: 011c lsls r4, r3, #4 8006dfa: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006dfe: 2200 movs r2, #0 8006e00: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8006e04: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8006e08: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 8006e0c: 4642 mov r2, r8 8006e0e: 464b mov r3, r9 8006e10: 1891 adds r1, r2, r2 8006e12: 61b9 str r1, [r7, #24] 8006e14: 415b adcs r3, r3 8006e16: 61fb str r3, [r7, #28] 8006e18: e9d7 2306 ldrd r2, r3, [r7, #24] 8006e1c: 4641 mov r1, r8 8006e1e: 1851 adds r1, r2, r1 8006e20: 6139 str r1, [r7, #16] 8006e22: 4649 mov r1, r9 8006e24: 414b adcs r3, r1 8006e26: 617b str r3, [r7, #20] 8006e28: f04f 0200 mov.w r2, #0 8006e2c: f04f 0300 mov.w r3, #0 8006e30: e9d7 ab04 ldrd sl, fp, [r7, #16] 8006e34: 4659 mov r1, fp 8006e36: 00cb lsls r3, r1, #3 8006e38: 4651 mov r1, sl 8006e3a: ea43 7351 orr.w r3, r3, r1, lsr #29 8006e3e: 4651 mov r1, sl 8006e40: 00ca lsls r2, r1, #3 8006e42: 4610 mov r0, r2 8006e44: 4619 mov r1, r3 8006e46: 4603 mov r3, r0 8006e48: 4642 mov r2, r8 8006e4a: 189b adds r3, r3, r2 8006e4c: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8006e50: 464b mov r3, r9 8006e52: 460a mov r2, r1 8006e54: eb42 0303 adc.w r3, r2, r3 8006e58: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006e5c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006e60: 685b ldr r3, [r3, #4] 8006e62: 2200 movs r2, #0 8006e64: 67bb str r3, [r7, #120] @ 0x78 8006e66: 67fa str r2, [r7, #124] @ 0x7c 8006e68: f04f 0200 mov.w r2, #0 8006e6c: f04f 0300 mov.w r3, #0 8006e70: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 8006e74: 4649 mov r1, r9 8006e76: 008b lsls r3, r1, #2 8006e78: 4641 mov r1, r8 8006e7a: ea43 7391 orr.w r3, r3, r1, lsr #30 8006e7e: 4641 mov r1, r8 8006e80: 008a lsls r2, r1, #2 8006e82: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 8006e86: f7f9 f9bd bl 8000204 <__aeabi_uldivmod> 8006e8a: 4602 mov r2, r0 8006e8c: 460b mov r3, r1 8006e8e: 4611 mov r1, r2 8006e90: 4b38 ldr r3, [pc, #224] @ (8006f74 ) 8006e92: fba3 2301 umull r2, r3, r3, r1 8006e96: 095b lsrs r3, r3, #5 8006e98: 2264 movs r2, #100 @ 0x64 8006e9a: fb02 f303 mul.w r3, r2, r3 8006e9e: 1acb subs r3, r1, r3 8006ea0: 011b lsls r3, r3, #4 8006ea2: 3332 adds r3, #50 @ 0x32 8006ea4: 4a33 ldr r2, [pc, #204] @ (8006f74 ) 8006ea6: fba2 2303 umull r2, r3, r2, r3 8006eaa: 095b lsrs r3, r3, #5 8006eac: f003 03f0 and.w r3, r3, #240 @ 0xf0 8006eb0: 441c add r4, r3 8006eb2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006eb6: 2200 movs r2, #0 8006eb8: 673b str r3, [r7, #112] @ 0x70 8006eba: 677a str r2, [r7, #116] @ 0x74 8006ebc: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 8006ec0: 4642 mov r2, r8 8006ec2: 464b mov r3, r9 8006ec4: 1891 adds r1, r2, r2 8006ec6: 60b9 str r1, [r7, #8] 8006ec8: 415b adcs r3, r3 8006eca: 60fb str r3, [r7, #12] 8006ecc: e9d7 2302 ldrd r2, r3, [r7, #8] 8006ed0: 4641 mov r1, r8 8006ed2: 1851 adds r1, r2, r1 8006ed4: 6039 str r1, [r7, #0] 8006ed6: 4649 mov r1, r9 8006ed8: 414b adcs r3, r1 8006eda: 607b str r3, [r7, #4] 8006edc: f04f 0200 mov.w r2, #0 8006ee0: f04f 0300 mov.w r3, #0 8006ee4: e9d7 ab00 ldrd sl, fp, [r7] 8006ee8: 4659 mov r1, fp 8006eea: 00cb lsls r3, r1, #3 8006eec: 4651 mov r1, sl 8006eee: ea43 7351 orr.w r3, r3, r1, lsr #29 8006ef2: 4651 mov r1, sl 8006ef4: 00ca lsls r2, r1, #3 8006ef6: 4610 mov r0, r2 8006ef8: 4619 mov r1, r3 8006efa: 4603 mov r3, r0 8006efc: 4642 mov r2, r8 8006efe: 189b adds r3, r3, r2 8006f00: 66bb str r3, [r7, #104] @ 0x68 8006f02: 464b mov r3, r9 8006f04: 460a mov r2, r1 8006f06: eb42 0303 adc.w r3, r2, r3 8006f0a: 66fb str r3, [r7, #108] @ 0x6c 8006f0c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006f10: 685b ldr r3, [r3, #4] 8006f12: 2200 movs r2, #0 8006f14: 663b str r3, [r7, #96] @ 0x60 8006f16: 667a str r2, [r7, #100] @ 0x64 8006f18: f04f 0200 mov.w r2, #0 8006f1c: f04f 0300 mov.w r3, #0 8006f20: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 8006f24: 4649 mov r1, r9 8006f26: 008b lsls r3, r1, #2 8006f28: 4641 mov r1, r8 8006f2a: ea43 7391 orr.w r3, r3, r1, lsr #30 8006f2e: 4641 mov r1, r8 8006f30: 008a lsls r2, r1, #2 8006f32: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 8006f36: f7f9 f965 bl 8000204 <__aeabi_uldivmod> 8006f3a: 4602 mov r2, r0 8006f3c: 460b mov r3, r1 8006f3e: 4b0d ldr r3, [pc, #52] @ (8006f74 ) 8006f40: fba3 1302 umull r1, r3, r3, r2 8006f44: 095b lsrs r3, r3, #5 8006f46: 2164 movs r1, #100 @ 0x64 8006f48: fb01 f303 mul.w r3, r1, r3 8006f4c: 1ad3 subs r3, r2, r3 8006f4e: 011b lsls r3, r3, #4 8006f50: 3332 adds r3, #50 @ 0x32 8006f52: 4a08 ldr r2, [pc, #32] @ (8006f74 ) 8006f54: fba2 2303 umull r2, r3, r2, r3 8006f58: 095b lsrs r3, r3, #5 8006f5a: f003 020f and.w r2, r3, #15 8006f5e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006f62: 681b ldr r3, [r3, #0] 8006f64: 4422 add r2, r4 8006f66: 609a str r2, [r3, #8] } 8006f68: bf00 nop 8006f6a: f507 7780 add.w r7, r7, #256 @ 0x100 8006f6e: 46bd mov sp, r7 8006f70: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8006f74: 51eb851f .word 0x51eb851f 08006f78 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8006f78: b084 sub sp, #16 8006f7a: b580 push {r7, lr} 8006f7c: b084 sub sp, #16 8006f7e: af00 add r7, sp, #0 8006f80: 6078 str r0, [r7, #4] 8006f82: f107 001c add.w r0, r7, #28 8006f86: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8006f8a: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 8006f8e: 2b01 cmp r3, #1 8006f90: d123 bne.n 8006fda { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8006f92: 687b ldr r3, [r7, #4] 8006f94: 6b9b ldr r3, [r3, #56] @ 0x38 8006f96: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8006f9a: 687b ldr r3, [r7, #4] 8006f9c: 639a str r2, [r3, #56] @ 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 8006f9e: 687b ldr r3, [r7, #4] 8006fa0: 68db ldr r3, [r3, #12] 8006fa2: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 8006fa6: f023 0340 bic.w r3, r3, #64 @ 0x40 8006faa: 687a ldr r2, [r7, #4] 8006fac: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 8006fae: 687b ldr r3, [r7, #4] 8006fb0: 68db ldr r3, [r3, #12] 8006fb2: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8006fb6: 687b ldr r3, [r7, #4] 8006fb8: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8006fba: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8006fbe: 2b01 cmp r3, #1 8006fc0: d105 bne.n 8006fce { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 8006fc2: 687b ldr r3, [r7, #4] 8006fc4: 68db ldr r3, [r3, #12] 8006fc6: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8006fca: 687b ldr r3, [r7, #4] 8006fcc: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8006fce: 6878 ldr r0, [r7, #4] 8006fd0: f001 fae2 bl 8008598 8006fd4: 4603 mov r3, r0 8006fd6: 73fb strb r3, [r7, #15] 8006fd8: e01b b.n 8007012 } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8006fda: 687b ldr r3, [r7, #4] 8006fdc: 68db ldr r3, [r3, #12] 8006fde: f043 0240 orr.w r2, r3, #64 @ 0x40 8006fe2: 687b ldr r3, [r7, #4] 8006fe4: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8006fe6: 6878 ldr r0, [r7, #4] 8006fe8: f001 fad6 bl 8008598 8006fec: 4603 mov r3, r0 8006fee: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 8006ff0: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 8006ff4: 2b00 cmp r3, #0 8006ff6: d106 bne.n 8007006 { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8006ff8: 687b ldr r3, [r7, #4] 8006ffa: 6b9b ldr r3, [r3, #56] @ 0x38 8006ffc: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8007000: 687b ldr r3, [r7, #4] 8007002: 639a str r2, [r3, #56] @ 0x38 8007004: e005 b.n 8007012 } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8007006: 687b ldr r3, [r7, #4] 8007008: 6b9b ldr r3, [r3, #56] @ 0x38 800700a: f423 3280 bic.w r2, r3, #65536 @ 0x10000 800700e: 687b ldr r3, [r7, #4] 8007010: 639a str r2, [r3, #56] @ 0x38 } } if (cfg.dma_enable == 1U) 8007012: 7fbb ldrb r3, [r7, #30] 8007014: 2b01 cmp r3, #1 8007016: d10b bne.n 8007030 { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8007018: 687b ldr r3, [r7, #4] 800701a: 689b ldr r3, [r3, #8] 800701c: f043 0206 orr.w r2, r3, #6 8007020: 687b ldr r3, [r7, #4] 8007022: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 8007024: 687b ldr r3, [r7, #4] 8007026: 689b ldr r3, [r3, #8] 8007028: f043 0220 orr.w r2, r3, #32 800702c: 687b ldr r3, [r7, #4] 800702e: 609a str r2, [r3, #8] } return ret; 8007030: 7bfb ldrb r3, [r7, #15] } 8007032: 4618 mov r0, r3 8007034: 3710 adds r7, #16 8007036: 46bd mov sp, r7 8007038: e8bd 4080 ldmia.w sp!, {r7, lr} 800703c: b004 add sp, #16 800703e: 4770 bx lr 08007040 : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8007040: b480 push {r7} 8007042: b087 sub sp, #28 8007044: af00 add r7, sp, #0 8007046: 60f8 str r0, [r7, #12] 8007048: 60b9 str r1, [r7, #8] 800704a: 4613 mov r3, r2 800704c: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 800704e: 79fb ldrb r3, [r7, #7] 8007050: 2b02 cmp r3, #2 8007052: d165 bne.n 8007120 { if ((hclk >= 14200000U) && (hclk < 15000000U)) 8007054: 68bb ldr r3, [r7, #8] 8007056: 4a41 ldr r2, [pc, #260] @ (800715c ) 8007058: 4293 cmp r3, r2 800705a: d906 bls.n 800706a 800705c: 68bb ldr r3, [r7, #8] 800705e: 4a40 ldr r2, [pc, #256] @ (8007160 ) 8007060: 4293 cmp r3, r2 8007062: d202 bcs.n 800706a { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 8007064: 230f movs r3, #15 8007066: 617b str r3, [r7, #20] 8007068: e062 b.n 8007130 } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 800706a: 68bb ldr r3, [r7, #8] 800706c: 4a3c ldr r2, [pc, #240] @ (8007160 ) 800706e: 4293 cmp r3, r2 8007070: d306 bcc.n 8007080 8007072: 68bb ldr r3, [r7, #8] 8007074: 4a3b ldr r2, [pc, #236] @ (8007164 ) 8007076: 4293 cmp r3, r2 8007078: d202 bcs.n 8007080 { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 800707a: 230e movs r3, #14 800707c: 617b str r3, [r7, #20] 800707e: e057 b.n 8007130 } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 8007080: 68bb ldr r3, [r7, #8] 8007082: 4a38 ldr r2, [pc, #224] @ (8007164 ) 8007084: 4293 cmp r3, r2 8007086: d306 bcc.n 8007096 8007088: 68bb ldr r3, [r7, #8] 800708a: 4a37 ldr r2, [pc, #220] @ (8007168 ) 800708c: 4293 cmp r3, r2 800708e: d202 bcs.n 8007096 { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 8007090: 230d movs r3, #13 8007092: 617b str r3, [r7, #20] 8007094: e04c b.n 8007130 } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 8007096: 68bb ldr r3, [r7, #8] 8007098: 4a33 ldr r2, [pc, #204] @ (8007168 ) 800709a: 4293 cmp r3, r2 800709c: d306 bcc.n 80070ac 800709e: 68bb ldr r3, [r7, #8] 80070a0: 4a32 ldr r2, [pc, #200] @ (800716c ) 80070a2: 4293 cmp r3, r2 80070a4: d802 bhi.n 80070ac { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 80070a6: 230c movs r3, #12 80070a8: 617b str r3, [r7, #20] 80070aa: e041 b.n 8007130 } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 80070ac: 68bb ldr r3, [r7, #8] 80070ae: 4a2f ldr r2, [pc, #188] @ (800716c ) 80070b0: 4293 cmp r3, r2 80070b2: d906 bls.n 80070c2 80070b4: 68bb ldr r3, [r7, #8] 80070b6: 4a2e ldr r2, [pc, #184] @ (8007170 ) 80070b8: 4293 cmp r3, r2 80070ba: d802 bhi.n 80070c2 { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 80070bc: 230b movs r3, #11 80070be: 617b str r3, [r7, #20] 80070c0: e036 b.n 8007130 } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 80070c2: 68bb ldr r3, [r7, #8] 80070c4: 4a2a ldr r2, [pc, #168] @ (8007170 ) 80070c6: 4293 cmp r3, r2 80070c8: d906 bls.n 80070d8 80070ca: 68bb ldr r3, [r7, #8] 80070cc: 4a29 ldr r2, [pc, #164] @ (8007174 ) 80070ce: 4293 cmp r3, r2 80070d0: d802 bhi.n 80070d8 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 80070d2: 230a movs r3, #10 80070d4: 617b str r3, [r7, #20] 80070d6: e02b b.n 8007130 } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 80070d8: 68bb ldr r3, [r7, #8] 80070da: 4a26 ldr r2, [pc, #152] @ (8007174 ) 80070dc: 4293 cmp r3, r2 80070de: d906 bls.n 80070ee 80070e0: 68bb ldr r3, [r7, #8] 80070e2: 4a25 ldr r2, [pc, #148] @ (8007178 ) 80070e4: 4293 cmp r3, r2 80070e6: d202 bcs.n 80070ee { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 80070e8: 2309 movs r3, #9 80070ea: 617b str r3, [r7, #20] 80070ec: e020 b.n 8007130 } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 80070ee: 68bb ldr r3, [r7, #8] 80070f0: 4a21 ldr r2, [pc, #132] @ (8007178 ) 80070f2: 4293 cmp r3, r2 80070f4: d306 bcc.n 8007104 80070f6: 68bb ldr r3, [r7, #8] 80070f8: 4a20 ldr r2, [pc, #128] @ (800717c ) 80070fa: 4293 cmp r3, r2 80070fc: d802 bhi.n 8007104 { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 80070fe: 2308 movs r3, #8 8007100: 617b str r3, [r7, #20] 8007102: e015 b.n 8007130 } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8007104: 68bb ldr r3, [r7, #8] 8007106: 4a1d ldr r2, [pc, #116] @ (800717c ) 8007108: 4293 cmp r3, r2 800710a: d906 bls.n 800711a 800710c: 68bb ldr r3, [r7, #8] 800710e: 4a1c ldr r2, [pc, #112] @ (8007180 ) 8007110: 4293 cmp r3, r2 8007112: d202 bcs.n 800711a { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 8007114: 2307 movs r3, #7 8007116: 617b str r3, [r7, #20] 8007118: e00a b.n 8007130 } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 800711a: 2306 movs r3, #6 800711c: 617b str r3, [r7, #20] 800711e: e007 b.n 8007130 } } else if (speed == USBD_HS_SPEED) 8007120: 79fb ldrb r3, [r7, #7] 8007122: 2b00 cmp r3, #0 8007124: d102 bne.n 800712c { UsbTrd = USBD_HS_TRDT_VALUE; 8007126: 2309 movs r3, #9 8007128: 617b str r3, [r7, #20] 800712a: e001 b.n 8007130 } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 800712c: 2309 movs r3, #9 800712e: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 8007130: 68fb ldr r3, [r7, #12] 8007132: 68db ldr r3, [r3, #12] 8007134: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 8007138: 68fb ldr r3, [r7, #12] 800713a: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 800713c: 68fb ldr r3, [r7, #12] 800713e: 68da ldr r2, [r3, #12] 8007140: 697b ldr r3, [r7, #20] 8007142: 029b lsls r3, r3, #10 8007144: f403 5370 and.w r3, r3, #15360 @ 0x3c00 8007148: 431a orrs r2, r3 800714a: 68fb ldr r3, [r7, #12] 800714c: 60da str r2, [r3, #12] return HAL_OK; 800714e: 2300 movs r3, #0 } 8007150: 4618 mov r0, r3 8007152: 371c adds r7, #28 8007154: 46bd mov sp, r7 8007156: f85d 7b04 ldr.w r7, [sp], #4 800715a: 4770 bx lr 800715c: 00d8acbf .word 0x00d8acbf 8007160: 00e4e1c0 .word 0x00e4e1c0 8007164: 00f42400 .word 0x00f42400 8007168: 01067380 .word 0x01067380 800716c: 011a499f .word 0x011a499f 8007170: 01312cff .word 0x01312cff 8007174: 014ca43f .word 0x014ca43f 8007178: 016e3600 .word 0x016e3600 800717c: 01a6ab1f .word 0x01a6ab1f 8007180: 01e84800 .word 0x01e84800 08007184 : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007184: b480 push {r7} 8007186: b083 sub sp, #12 8007188: af00 add r7, sp, #0 800718a: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 800718c: 687b ldr r3, [r7, #4] 800718e: 689b ldr r3, [r3, #8] 8007190: f043 0201 orr.w r2, r3, #1 8007194: 687b ldr r3, [r7, #4] 8007196: 609a str r2, [r3, #8] return HAL_OK; 8007198: 2300 movs r3, #0 } 800719a: 4618 mov r0, r3 800719c: 370c adds r7, #12 800719e: 46bd mov sp, r7 80071a0: f85d 7b04 ldr.w r7, [sp], #4 80071a4: 4770 bx lr 080071a6 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 80071a6: b480 push {r7} 80071a8: b083 sub sp, #12 80071aa: af00 add r7, sp, #0 80071ac: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 80071ae: 687b ldr r3, [r7, #4] 80071b0: 689b ldr r3, [r3, #8] 80071b2: f023 0201 bic.w r2, r3, #1 80071b6: 687b ldr r3, [r7, #4] 80071b8: 609a str r2, [r3, #8] return HAL_OK; 80071ba: 2300 movs r3, #0 } 80071bc: 4618 mov r0, r3 80071be: 370c adds r7, #12 80071c0: 46bd mov sp, r7 80071c2: f85d 7b04 ldr.w r7, [sp], #4 80071c6: 4770 bx lr 080071c8 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 80071c8: b580 push {r7, lr} 80071ca: b084 sub sp, #16 80071cc: af00 add r7, sp, #0 80071ce: 6078 str r0, [r7, #4] 80071d0: 460b mov r3, r1 80071d2: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 80071d4: 2300 movs r3, #0 80071d6: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 80071d8: 687b ldr r3, [r7, #4] 80071da: 68db ldr r3, [r3, #12] 80071dc: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 80071e0: 687b ldr r3, [r7, #4] 80071e2: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 80071e4: 78fb ldrb r3, [r7, #3] 80071e6: 2b01 cmp r3, #1 80071e8: d115 bne.n 8007216 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 80071ea: 687b ldr r3, [r7, #4] 80071ec: 68db ldr r3, [r3, #12] 80071ee: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 80071f2: 687b ldr r3, [r7, #4] 80071f4: 60da str r2, [r3, #12] do { HAL_Delay(10U); 80071f6: 200a movs r0, #10 80071f8: f7fa fcc4 bl 8001b84 ms += 10U; 80071fc: 68fb ldr r3, [r7, #12] 80071fe: 330a adds r3, #10 8007200: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007202: 6878 ldr r0, [r7, #4] 8007204: f001 f939 bl 800847a 8007208: 4603 mov r3, r0 800720a: 2b01 cmp r3, #1 800720c: d01e beq.n 800724c 800720e: 68fb ldr r3, [r7, #12] 8007210: 2bc7 cmp r3, #199 @ 0xc7 8007212: d9f0 bls.n 80071f6 8007214: e01a b.n 800724c } else if (mode == USB_DEVICE_MODE) 8007216: 78fb ldrb r3, [r7, #3] 8007218: 2b00 cmp r3, #0 800721a: d115 bne.n 8007248 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 800721c: 687b ldr r3, [r7, #4] 800721e: 68db ldr r3, [r3, #12] 8007220: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 8007224: 687b ldr r3, [r7, #4] 8007226: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8007228: 200a movs r0, #10 800722a: f7fa fcab bl 8001b84 ms += 10U; 800722e: 68fb ldr r3, [r7, #12] 8007230: 330a adds r3, #10 8007232: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007234: 6878 ldr r0, [r7, #4] 8007236: f001 f920 bl 800847a 800723a: 4603 mov r3, r0 800723c: 2b00 cmp r3, #0 800723e: d005 beq.n 800724c 8007240: 68fb ldr r3, [r7, #12] 8007242: 2bc7 cmp r3, #199 @ 0xc7 8007244: d9f0 bls.n 8007228 8007246: e001 b.n 800724c } else { return HAL_ERROR; 8007248: 2301 movs r3, #1 800724a: e005 b.n 8007258 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 800724c: 68fb ldr r3, [r7, #12] 800724e: 2bc8 cmp r3, #200 @ 0xc8 8007250: d101 bne.n 8007256 { return HAL_ERROR; 8007252: 2301 movs r3, #1 8007254: e000 b.n 8007258 } return HAL_OK; 8007256: 2300 movs r3, #0 } 8007258: 4618 mov r0, r3 800725a: 3710 adds r7, #16 800725c: 46bd mov sp, r7 800725e: bd80 pop {r7, pc} 08007260 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007260: b084 sub sp, #16 8007262: b580 push {r7, lr} 8007264: b086 sub sp, #24 8007266: af00 add r7, sp, #0 8007268: 6078 str r0, [r7, #4] 800726a: f107 0024 add.w r0, r7, #36 @ 0x24 800726e: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 8007272: 2300 movs r3, #0 8007274: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007276: 687b ldr r3, [r7, #4] 8007278: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 800727a: 2300 movs r3, #0 800727c: 613b str r3, [r7, #16] 800727e: e009 b.n 8007294 { USBx->DIEPTXF[i] = 0U; 8007280: 687a ldr r2, [r7, #4] 8007282: 693b ldr r3, [r7, #16] 8007284: 3340 adds r3, #64 @ 0x40 8007286: 009b lsls r3, r3, #2 8007288: 4413 add r3, r2 800728a: 2200 movs r2, #0 800728c: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 800728e: 693b ldr r3, [r7, #16] 8007290: 3301 adds r3, #1 8007292: 613b str r3, [r7, #16] 8007294: 693b ldr r3, [r7, #16] 8007296: 2b0e cmp r3, #14 8007298: d9f2 bls.n 8007280 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 800729a: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800729e: 2b00 cmp r3, #0 80072a0: d11c bne.n 80072dc { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 80072a2: 68fb ldr r3, [r7, #12] 80072a4: f503 6300 add.w r3, r3, #2048 @ 0x800 80072a8: 685b ldr r3, [r3, #4] 80072aa: 68fa ldr r2, [r7, #12] 80072ac: f502 6200 add.w r2, r2, #2048 @ 0x800 80072b0: f043 0302 orr.w r3, r3, #2 80072b4: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 80072b6: 687b ldr r3, [r7, #4] 80072b8: 6b9b ldr r3, [r3, #56] @ 0x38 80072ba: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 80072be: 687b ldr r3, [r7, #4] 80072c0: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 80072c2: 687b ldr r3, [r7, #4] 80072c4: 681b ldr r3, [r3, #0] 80072c6: f043 0240 orr.w r2, r3, #64 @ 0x40 80072ca: 687b ldr r3, [r7, #4] 80072cc: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 80072ce: 687b ldr r3, [r7, #4] 80072d0: 681b ldr r3, [r3, #0] 80072d2: f043 0280 orr.w r2, r3, #128 @ 0x80 80072d6: 687b ldr r3, [r7, #4] 80072d8: 601a str r2, [r3, #0] 80072da: e005 b.n 80072e8 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 80072dc: 687b ldr r3, [r7, #4] 80072de: 6b9b ldr r3, [r3, #56] @ 0x38 80072e0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 80072e4: 687b ldr r3, [r7, #4] 80072e6: 639a str r2, [r3, #56] @ 0x38 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 80072e8: 68fb ldr r3, [r7, #12] 80072ea: f503 6360 add.w r3, r3, #3584 @ 0xe00 80072ee: 461a mov r2, r3 80072f0: 2300 movs r3, #0 80072f2: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 80072f4: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 80072f8: 2b01 cmp r3, #1 80072fa: d10d bne.n 8007318 { if (cfg.speed == USBD_HS_SPEED) 80072fc: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007300: 2b00 cmp r3, #0 8007302: d104 bne.n 800730e { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 8007304: 2100 movs r1, #0 8007306: 6878 ldr r0, [r7, #4] 8007308: f000 f968 bl 80075dc 800730c: e008 b.n 8007320 } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 800730e: 2101 movs r1, #1 8007310: 6878 ldr r0, [r7, #4] 8007312: f000 f963 bl 80075dc 8007316: e003 b.n 8007320 } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 8007318: 2103 movs r1, #3 800731a: 6878 ldr r0, [r7, #4] 800731c: f000 f95e bl 80075dc } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 8007320: 2110 movs r1, #16 8007322: 6878 ldr r0, [r7, #4] 8007324: f000 f8fa bl 800751c 8007328: 4603 mov r3, r0 800732a: 2b00 cmp r3, #0 800732c: d001 beq.n 8007332 { ret = HAL_ERROR; 800732e: 2301 movs r3, #1 8007330: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 8007332: 6878 ldr r0, [r7, #4] 8007334: f000 f924 bl 8007580 8007338: 4603 mov r3, r0 800733a: 2b00 cmp r3, #0 800733c: d001 beq.n 8007342 { ret = HAL_ERROR; 800733e: 2301 movs r3, #1 8007340: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 8007342: 68fb ldr r3, [r7, #12] 8007344: f503 6300 add.w r3, r3, #2048 @ 0x800 8007348: 461a mov r2, r3 800734a: 2300 movs r3, #0 800734c: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 800734e: 68fb ldr r3, [r7, #12] 8007350: f503 6300 add.w r3, r3, #2048 @ 0x800 8007354: 461a mov r2, r3 8007356: 2300 movs r3, #0 8007358: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 800735a: 68fb ldr r3, [r7, #12] 800735c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007360: 461a mov r2, r3 8007362: 2300 movs r3, #0 8007364: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 8007366: 2300 movs r3, #0 8007368: 613b str r3, [r7, #16] 800736a: e043 b.n 80073f4 { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 800736c: 693b ldr r3, [r7, #16] 800736e: 015a lsls r2, r3, #5 8007370: 68fb ldr r3, [r7, #12] 8007372: 4413 add r3, r2 8007374: f503 6310 add.w r3, r3, #2304 @ 0x900 8007378: 681b ldr r3, [r3, #0] 800737a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800737e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007382: d118 bne.n 80073b6 { if (i == 0U) 8007384: 693b ldr r3, [r7, #16] 8007386: 2b00 cmp r3, #0 8007388: d10a bne.n 80073a0 { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 800738a: 693b ldr r3, [r7, #16] 800738c: 015a lsls r2, r3, #5 800738e: 68fb ldr r3, [r7, #12] 8007390: 4413 add r3, r2 8007392: f503 6310 add.w r3, r3, #2304 @ 0x900 8007396: 461a mov r2, r3 8007398: f04f 6300 mov.w r3, #134217728 @ 0x8000000 800739c: 6013 str r3, [r2, #0] 800739e: e013 b.n 80073c8 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 80073a0: 693b ldr r3, [r7, #16] 80073a2: 015a lsls r2, r3, #5 80073a4: 68fb ldr r3, [r7, #12] 80073a6: 4413 add r3, r2 80073a8: f503 6310 add.w r3, r3, #2304 @ 0x900 80073ac: 461a mov r2, r3 80073ae: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 80073b2: 6013 str r3, [r2, #0] 80073b4: e008 b.n 80073c8 } } else { USBx_INEP(i)->DIEPCTL = 0U; 80073b6: 693b ldr r3, [r7, #16] 80073b8: 015a lsls r2, r3, #5 80073ba: 68fb ldr r3, [r7, #12] 80073bc: 4413 add r3, r2 80073be: f503 6310 add.w r3, r3, #2304 @ 0x900 80073c2: 461a mov r2, r3 80073c4: 2300 movs r3, #0 80073c6: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 80073c8: 693b ldr r3, [r7, #16] 80073ca: 015a lsls r2, r3, #5 80073cc: 68fb ldr r3, [r7, #12] 80073ce: 4413 add r3, r2 80073d0: f503 6310 add.w r3, r3, #2304 @ 0x900 80073d4: 461a mov r2, r3 80073d6: 2300 movs r3, #0 80073d8: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 80073da: 693b ldr r3, [r7, #16] 80073dc: 015a lsls r2, r3, #5 80073de: 68fb ldr r3, [r7, #12] 80073e0: 4413 add r3, r2 80073e2: f503 6310 add.w r3, r3, #2304 @ 0x900 80073e6: 461a mov r2, r3 80073e8: f64f 337f movw r3, #64383 @ 0xfb7f 80073ec: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 80073ee: 693b ldr r3, [r7, #16] 80073f0: 3301 adds r3, #1 80073f2: 613b str r3, [r7, #16] 80073f4: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 80073f8: 461a mov r2, r3 80073fa: 693b ldr r3, [r7, #16] 80073fc: 4293 cmp r3, r2 80073fe: d3b5 bcc.n 800736c } for (i = 0U; i < cfg.dev_endpoints; i++) 8007400: 2300 movs r3, #0 8007402: 613b str r3, [r7, #16] 8007404: e043 b.n 800748e { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007406: 693b ldr r3, [r7, #16] 8007408: 015a lsls r2, r3, #5 800740a: 68fb ldr r3, [r7, #12] 800740c: 4413 add r3, r2 800740e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007412: 681b ldr r3, [r3, #0] 8007414: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007418: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800741c: d118 bne.n 8007450 { if (i == 0U) 800741e: 693b ldr r3, [r7, #16] 8007420: 2b00 cmp r3, #0 8007422: d10a bne.n 800743a { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 8007424: 693b ldr r3, [r7, #16] 8007426: 015a lsls r2, r3, #5 8007428: 68fb ldr r3, [r7, #12] 800742a: 4413 add r3, r2 800742c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007430: 461a mov r2, r3 8007432: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007436: 6013 str r3, [r2, #0] 8007438: e013 b.n 8007462 } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 800743a: 693b ldr r3, [r7, #16] 800743c: 015a lsls r2, r3, #5 800743e: 68fb ldr r3, [r7, #12] 8007440: 4413 add r3, r2 8007442: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007446: 461a mov r2, r3 8007448: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 800744c: 6013 str r3, [r2, #0] 800744e: e008 b.n 8007462 } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 8007450: 693b ldr r3, [r7, #16] 8007452: 015a lsls r2, r3, #5 8007454: 68fb ldr r3, [r7, #12] 8007456: 4413 add r3, r2 8007458: f503 6330 add.w r3, r3, #2816 @ 0xb00 800745c: 461a mov r2, r3 800745e: 2300 movs r3, #0 8007460: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 8007462: 693b ldr r3, [r7, #16] 8007464: 015a lsls r2, r3, #5 8007466: 68fb ldr r3, [r7, #12] 8007468: 4413 add r3, r2 800746a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800746e: 461a mov r2, r3 8007470: 2300 movs r3, #0 8007472: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8007474: 693b ldr r3, [r7, #16] 8007476: 015a lsls r2, r3, #5 8007478: 68fb ldr r3, [r7, #12] 800747a: 4413 add r3, r2 800747c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007480: 461a mov r2, r3 8007482: f64f 337f movw r3, #64383 @ 0xfb7f 8007486: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8007488: 693b ldr r3, [r7, #16] 800748a: 3301 adds r3, #1 800748c: 613b str r3, [r7, #16] 800748e: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8007492: 461a mov r2, r3 8007494: 693b ldr r3, [r7, #16] 8007496: 4293 cmp r3, r2 8007498: d3b5 bcc.n 8007406 } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 800749a: 68fb ldr r3, [r7, #12] 800749c: f503 6300 add.w r3, r3, #2048 @ 0x800 80074a0: 691b ldr r3, [r3, #16] 80074a2: 68fa ldr r2, [r7, #12] 80074a4: f502 6200 add.w r2, r2, #2048 @ 0x800 80074a8: f423 7380 bic.w r3, r3, #256 @ 0x100 80074ac: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 80074ae: 687b ldr r3, [r7, #4] 80074b0: 2200 movs r2, #0 80074b2: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 80074b4: 687b ldr r3, [r7, #4] 80074b6: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 80074ba: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 80074bc: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 80074c0: 2b00 cmp r3, #0 80074c2: d105 bne.n 80074d0 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 80074c4: 687b ldr r3, [r7, #4] 80074c6: 699b ldr r3, [r3, #24] 80074c8: f043 0210 orr.w r2, r3, #16 80074cc: 687b ldr r3, [r7, #4] 80074ce: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 80074d0: 687b ldr r3, [r7, #4] 80074d2: 699a ldr r2, [r3, #24] 80074d4: 4b10 ldr r3, [pc, #64] @ (8007518 ) 80074d6: 4313 orrs r3, r2 80074d8: 687a ldr r2, [r7, #4] 80074da: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 80074dc: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 80074e0: 2b00 cmp r3, #0 80074e2: d005 beq.n 80074f0 { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 80074e4: 687b ldr r3, [r7, #4] 80074e6: 699b ldr r3, [r3, #24] 80074e8: f043 0208 orr.w r2, r3, #8 80074ec: 687b ldr r3, [r7, #4] 80074ee: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 80074f0: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 80074f4: 2b01 cmp r3, #1 80074f6: d107 bne.n 8007508 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 80074f8: 687b ldr r3, [r7, #4] 80074fa: 699b ldr r3, [r3, #24] 80074fc: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007500: f043 0304 orr.w r3, r3, #4 8007504: 687a ldr r2, [r7, #4] 8007506: 6193 str r3, [r2, #24] } return ret; 8007508: 7dfb ldrb r3, [r7, #23] } 800750a: 4618 mov r0, r3 800750c: 3718 adds r7, #24 800750e: 46bd mov sp, r7 8007510: e8bd 4080 ldmia.w sp!, {r7, lr} 8007514: b004 add sp, #16 8007516: 4770 bx lr 8007518: 803c3800 .word 0x803c3800 0800751c : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 800751c: b480 push {r7} 800751e: b085 sub sp, #20 8007520: af00 add r7, sp, #0 8007522: 6078 str r0, [r7, #4] 8007524: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8007526: 2300 movs r3, #0 8007528: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 800752a: 68fb ldr r3, [r7, #12] 800752c: 3301 adds r3, #1 800752e: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007530: 68fb ldr r3, [r7, #12] 8007532: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007536: d901 bls.n 800753c { return HAL_TIMEOUT; 8007538: 2303 movs r3, #3 800753a: e01b b.n 8007574 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 800753c: 687b ldr r3, [r7, #4] 800753e: 691b ldr r3, [r3, #16] 8007540: 2b00 cmp r3, #0 8007542: daf2 bge.n 800752a /* Flush TX Fifo */ count = 0U; 8007544: 2300 movs r3, #0 8007546: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 8007548: 683b ldr r3, [r7, #0] 800754a: 019b lsls r3, r3, #6 800754c: f043 0220 orr.w r2, r3, #32 8007550: 687b ldr r3, [r7, #4] 8007552: 611a str r2, [r3, #16] do { count++; 8007554: 68fb ldr r3, [r7, #12] 8007556: 3301 adds r3, #1 8007558: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800755a: 68fb ldr r3, [r7, #12] 800755c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007560: d901 bls.n 8007566 { return HAL_TIMEOUT; 8007562: 2303 movs r3, #3 8007564: e006 b.n 8007574 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 8007566: 687b ldr r3, [r7, #4] 8007568: 691b ldr r3, [r3, #16] 800756a: f003 0320 and.w r3, r3, #32 800756e: 2b20 cmp r3, #32 8007570: d0f0 beq.n 8007554 return HAL_OK; 8007572: 2300 movs r3, #0 } 8007574: 4618 mov r0, r3 8007576: 3714 adds r7, #20 8007578: 46bd mov sp, r7 800757a: f85d 7b04 ldr.w r7, [sp], #4 800757e: 4770 bx lr 08007580 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 8007580: b480 push {r7} 8007582: b085 sub sp, #20 8007584: af00 add r7, sp, #0 8007586: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8007588: 2300 movs r3, #0 800758a: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 800758c: 68fb ldr r3, [r7, #12] 800758e: 3301 adds r3, #1 8007590: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007592: 68fb ldr r3, [r7, #12] 8007594: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007598: d901 bls.n 800759e { return HAL_TIMEOUT; 800759a: 2303 movs r3, #3 800759c: e018 b.n 80075d0 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 800759e: 687b ldr r3, [r7, #4] 80075a0: 691b ldr r3, [r3, #16] 80075a2: 2b00 cmp r3, #0 80075a4: daf2 bge.n 800758c /* Flush RX Fifo */ count = 0U; 80075a6: 2300 movs r3, #0 80075a8: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 80075aa: 687b ldr r3, [r7, #4] 80075ac: 2210 movs r2, #16 80075ae: 611a str r2, [r3, #16] do { count++; 80075b0: 68fb ldr r3, [r7, #12] 80075b2: 3301 adds r3, #1 80075b4: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80075b6: 68fb ldr r3, [r7, #12] 80075b8: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80075bc: d901 bls.n 80075c2 { return HAL_TIMEOUT; 80075be: 2303 movs r3, #3 80075c0: e006 b.n 80075d0 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 80075c2: 687b ldr r3, [r7, #4] 80075c4: 691b ldr r3, [r3, #16] 80075c6: f003 0310 and.w r3, r3, #16 80075ca: 2b10 cmp r3, #16 80075cc: d0f0 beq.n 80075b0 return HAL_OK; 80075ce: 2300 movs r3, #0 } 80075d0: 4618 mov r0, r3 80075d2: 3714 adds r7, #20 80075d4: 46bd mov sp, r7 80075d6: f85d 7b04 ldr.w r7, [sp], #4 80075da: 4770 bx lr 080075dc : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 80075dc: b480 push {r7} 80075de: b085 sub sp, #20 80075e0: af00 add r7, sp, #0 80075e2: 6078 str r0, [r7, #4] 80075e4: 460b mov r3, r1 80075e6: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80075e8: 687b ldr r3, [r7, #4] 80075ea: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 80075ec: 68fb ldr r3, [r7, #12] 80075ee: f503 6300 add.w r3, r3, #2048 @ 0x800 80075f2: 681a ldr r2, [r3, #0] 80075f4: 78fb ldrb r3, [r7, #3] 80075f6: 68f9 ldr r1, [r7, #12] 80075f8: f501 6100 add.w r1, r1, #2048 @ 0x800 80075fc: 4313 orrs r3, r2 80075fe: 600b str r3, [r1, #0] return HAL_OK; 8007600: 2300 movs r3, #0 } 8007602: 4618 mov r0, r3 8007604: 3714 adds r7, #20 8007606: 46bd mov sp, r7 8007608: f85d 7b04 ldr.w r7, [sp], #4 800760c: 4770 bx lr 0800760e : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { 800760e: b480 push {r7} 8007610: b087 sub sp, #28 8007612: af00 add r7, sp, #0 8007614: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007616: 687b ldr r3, [r7, #4] 8007618: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 800761a: 693b ldr r3, [r7, #16] 800761c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007620: 689b ldr r3, [r3, #8] 8007622: f003 0306 and.w r3, r3, #6 8007626: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 8007628: 68fb ldr r3, [r7, #12] 800762a: 2b00 cmp r3, #0 800762c: d102 bne.n 8007634 { speed = USBD_HS_SPEED; 800762e: 2300 movs r3, #0 8007630: 75fb strb r3, [r7, #23] 8007632: e00a b.n 800764a } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 8007634: 68fb ldr r3, [r7, #12] 8007636: 2b02 cmp r3, #2 8007638: d002 beq.n 8007640 800763a: 68fb ldr r3, [r7, #12] 800763c: 2b06 cmp r3, #6 800763e: d102 bne.n 8007646 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 8007640: 2302 movs r3, #2 8007642: 75fb strb r3, [r7, #23] 8007644: e001 b.n 800764a } else { speed = 0xFU; 8007646: 230f movs r3, #15 8007648: 75fb strb r3, [r7, #23] } return speed; 800764a: 7dfb ldrb r3, [r7, #23] } 800764c: 4618 mov r0, r3 800764e: 371c adds r7, #28 8007650: 46bd mov sp, r7 8007652: f85d 7b04 ldr.w r7, [sp], #4 8007656: 4770 bx lr 08007658 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007658: b480 push {r7} 800765a: b085 sub sp, #20 800765c: af00 add r7, sp, #0 800765e: 6078 str r0, [r7, #4] 8007660: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8007662: 687b ldr r3, [r7, #4] 8007664: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007666: 683b ldr r3, [r7, #0] 8007668: 781b ldrb r3, [r3, #0] 800766a: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 800766c: 683b ldr r3, [r7, #0] 800766e: 785b ldrb r3, [r3, #1] 8007670: 2b01 cmp r3, #1 8007672: d13a bne.n 80076ea { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 8007674: 68fb ldr r3, [r7, #12] 8007676: f503 6300 add.w r3, r3, #2048 @ 0x800 800767a: 69da ldr r2, [r3, #28] 800767c: 683b ldr r3, [r7, #0] 800767e: 781b ldrb r3, [r3, #0] 8007680: f003 030f and.w r3, r3, #15 8007684: 2101 movs r1, #1 8007686: fa01 f303 lsl.w r3, r1, r3 800768a: b29b uxth r3, r3 800768c: 68f9 ldr r1, [r7, #12] 800768e: f501 6100 add.w r1, r1, #2048 @ 0x800 8007692: 4313 orrs r3, r2 8007694: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 8007696: 68bb ldr r3, [r7, #8] 8007698: 015a lsls r2, r3, #5 800769a: 68fb ldr r3, [r7, #12] 800769c: 4413 add r3, r2 800769e: f503 6310 add.w r3, r3, #2304 @ 0x900 80076a2: 681b ldr r3, [r3, #0] 80076a4: f403 4300 and.w r3, r3, #32768 @ 0x8000 80076a8: 2b00 cmp r3, #0 80076aa: d155 bne.n 8007758 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 80076ac: 68bb ldr r3, [r7, #8] 80076ae: 015a lsls r2, r3, #5 80076b0: 68fb ldr r3, [r7, #12] 80076b2: 4413 add r3, r2 80076b4: f503 6310 add.w r3, r3, #2304 @ 0x900 80076b8: 681a ldr r2, [r3, #0] 80076ba: 683b ldr r3, [r7, #0] 80076bc: 689b ldr r3, [r3, #8] 80076be: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 80076c2: 683b ldr r3, [r7, #0] 80076c4: 791b ldrb r3, [r3, #4] 80076c6: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 80076c8: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 80076ca: 68bb ldr r3, [r7, #8] 80076cc: 059b lsls r3, r3, #22 80076ce: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 80076d0: 4313 orrs r3, r2 80076d2: 68ba ldr r2, [r7, #8] 80076d4: 0151 lsls r1, r2, #5 80076d6: 68fa ldr r2, [r7, #12] 80076d8: 440a add r2, r1 80076da: f502 6210 add.w r2, r2, #2304 @ 0x900 80076de: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80076e2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80076e6: 6013 str r3, [r2, #0] 80076e8: e036 b.n 8007758 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 80076ea: 68fb ldr r3, [r7, #12] 80076ec: f503 6300 add.w r3, r3, #2048 @ 0x800 80076f0: 69da ldr r2, [r3, #28] 80076f2: 683b ldr r3, [r7, #0] 80076f4: 781b ldrb r3, [r3, #0] 80076f6: f003 030f and.w r3, r3, #15 80076fa: 2101 movs r1, #1 80076fc: fa01 f303 lsl.w r3, r1, r3 8007700: 041b lsls r3, r3, #16 8007702: 68f9 ldr r1, [r7, #12] 8007704: f501 6100 add.w r1, r1, #2048 @ 0x800 8007708: 4313 orrs r3, r2 800770a: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 800770c: 68bb ldr r3, [r7, #8] 800770e: 015a lsls r2, r3, #5 8007710: 68fb ldr r3, [r7, #12] 8007712: 4413 add r3, r2 8007714: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007718: 681b ldr r3, [r3, #0] 800771a: f403 4300 and.w r3, r3, #32768 @ 0x8000 800771e: 2b00 cmp r3, #0 8007720: d11a bne.n 8007758 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 8007722: 68bb ldr r3, [r7, #8] 8007724: 015a lsls r2, r3, #5 8007726: 68fb ldr r3, [r7, #12] 8007728: 4413 add r3, r2 800772a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800772e: 681a ldr r2, [r3, #0] 8007730: 683b ldr r3, [r7, #0] 8007732: 689b ldr r3, [r3, #8] 8007734: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 8007738: 683b ldr r3, [r7, #0] 800773a: 791b ldrb r3, [r3, #4] 800773c: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 800773e: 430b orrs r3, r1 8007740: 4313 orrs r3, r2 8007742: 68ba ldr r2, [r7, #8] 8007744: 0151 lsls r1, r2, #5 8007746: 68fa ldr r2, [r7, #12] 8007748: 440a add r2, r1 800774a: f502 6230 add.w r2, r2, #2816 @ 0xb00 800774e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007752: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8007756: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 8007758: 2300 movs r3, #0 } 800775a: 4618 mov r0, r3 800775c: 3714 adds r7, #20 800775e: 46bd mov sp, r7 8007760: f85d 7b04 ldr.w r7, [sp], #4 8007764: 4770 bx lr ... 08007768 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007768: b480 push {r7} 800776a: b085 sub sp, #20 800776c: af00 add r7, sp, #0 800776e: 6078 str r0, [r7, #4] 8007770: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8007772: 687b ldr r3, [r7, #4] 8007774: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007776: 683b ldr r3, [r7, #0] 8007778: 781b ldrb r3, [r3, #0] 800777a: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 800777c: 683b ldr r3, [r7, #0] 800777e: 785b ldrb r3, [r3, #1] 8007780: 2b01 cmp r3, #1 8007782: d161 bne.n 8007848 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007784: 68bb ldr r3, [r7, #8] 8007786: 015a lsls r2, r3, #5 8007788: 68fb ldr r3, [r7, #12] 800778a: 4413 add r3, r2 800778c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007790: 681b ldr r3, [r3, #0] 8007792: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007796: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800779a: d11f bne.n 80077dc { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 800779c: 68bb ldr r3, [r7, #8] 800779e: 015a lsls r2, r3, #5 80077a0: 68fb ldr r3, [r7, #12] 80077a2: 4413 add r3, r2 80077a4: f503 6310 add.w r3, r3, #2304 @ 0x900 80077a8: 681b ldr r3, [r3, #0] 80077aa: 68ba ldr r2, [r7, #8] 80077ac: 0151 lsls r1, r2, #5 80077ae: 68fa ldr r2, [r7, #12] 80077b0: 440a add r2, r1 80077b2: f502 6210 add.w r2, r2, #2304 @ 0x900 80077b6: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80077ba: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 80077bc: 68bb ldr r3, [r7, #8] 80077be: 015a lsls r2, r3, #5 80077c0: 68fb ldr r3, [r7, #12] 80077c2: 4413 add r3, r2 80077c4: f503 6310 add.w r3, r3, #2304 @ 0x900 80077c8: 681b ldr r3, [r3, #0] 80077ca: 68ba ldr r2, [r7, #8] 80077cc: 0151 lsls r1, r2, #5 80077ce: 68fa ldr r2, [r7, #12] 80077d0: 440a add r2, r1 80077d2: f502 6210 add.w r2, r2, #2304 @ 0x900 80077d6: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80077da: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80077dc: 68fb ldr r3, [r7, #12] 80077de: f503 6300 add.w r3, r3, #2048 @ 0x800 80077e2: 6bda ldr r2, [r3, #60] @ 0x3c 80077e4: 683b ldr r3, [r7, #0] 80077e6: 781b ldrb r3, [r3, #0] 80077e8: f003 030f and.w r3, r3, #15 80077ec: 2101 movs r1, #1 80077ee: fa01 f303 lsl.w r3, r1, r3 80077f2: b29b uxth r3, r3 80077f4: 43db mvns r3, r3 80077f6: 68f9 ldr r1, [r7, #12] 80077f8: f501 6100 add.w r1, r1, #2048 @ 0x800 80077fc: 4013 ands r3, r2 80077fe: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8007800: 68fb ldr r3, [r7, #12] 8007802: f503 6300 add.w r3, r3, #2048 @ 0x800 8007806: 69da ldr r2, [r3, #28] 8007808: 683b ldr r3, [r7, #0] 800780a: 781b ldrb r3, [r3, #0] 800780c: f003 030f and.w r3, r3, #15 8007810: 2101 movs r1, #1 8007812: fa01 f303 lsl.w r3, r1, r3 8007816: b29b uxth r3, r3 8007818: 43db mvns r3, r3 800781a: 68f9 ldr r1, [r7, #12] 800781c: f501 6100 add.w r1, r1, #2048 @ 0x800 8007820: 4013 ands r3, r2 8007822: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 8007824: 68bb ldr r3, [r7, #8] 8007826: 015a lsls r2, r3, #5 8007828: 68fb ldr r3, [r7, #12] 800782a: 4413 add r3, r2 800782c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007830: 681a ldr r2, [r3, #0] 8007832: 68bb ldr r3, [r7, #8] 8007834: 0159 lsls r1, r3, #5 8007836: 68fb ldr r3, [r7, #12] 8007838: 440b add r3, r1 800783a: f503 6310 add.w r3, r3, #2304 @ 0x900 800783e: 4619 mov r1, r3 8007840: 4b35 ldr r3, [pc, #212] @ (8007918 ) 8007842: 4013 ands r3, r2 8007844: 600b str r3, [r1, #0] 8007846: e060 b.n 800790a USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007848: 68bb ldr r3, [r7, #8] 800784a: 015a lsls r2, r3, #5 800784c: 68fb ldr r3, [r7, #12] 800784e: 4413 add r3, r2 8007850: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007854: 681b ldr r3, [r3, #0] 8007856: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800785a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800785e: d11f bne.n 80078a0 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8007860: 68bb ldr r3, [r7, #8] 8007862: 015a lsls r2, r3, #5 8007864: 68fb ldr r3, [r7, #12] 8007866: 4413 add r3, r2 8007868: f503 6330 add.w r3, r3, #2816 @ 0xb00 800786c: 681b ldr r3, [r3, #0] 800786e: 68ba ldr r2, [r7, #8] 8007870: 0151 lsls r1, r2, #5 8007872: 68fa ldr r2, [r7, #12] 8007874: 440a add r2, r1 8007876: f502 6230 add.w r2, r2, #2816 @ 0xb00 800787a: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800787e: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 8007880: 68bb ldr r3, [r7, #8] 8007882: 015a lsls r2, r3, #5 8007884: 68fb ldr r3, [r7, #12] 8007886: 4413 add r3, r2 8007888: f503 6330 add.w r3, r3, #2816 @ 0xb00 800788c: 681b ldr r3, [r3, #0] 800788e: 68ba ldr r2, [r7, #8] 8007890: 0151 lsls r1, r2, #5 8007892: 68fa ldr r2, [r7, #12] 8007894: 440a add r2, r1 8007896: f502 6230 add.w r2, r2, #2816 @ 0xb00 800789a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800789e: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 80078a0: 68fb ldr r3, [r7, #12] 80078a2: f503 6300 add.w r3, r3, #2048 @ 0x800 80078a6: 6bda ldr r2, [r3, #60] @ 0x3c 80078a8: 683b ldr r3, [r7, #0] 80078aa: 781b ldrb r3, [r3, #0] 80078ac: f003 030f and.w r3, r3, #15 80078b0: 2101 movs r1, #1 80078b2: fa01 f303 lsl.w r3, r1, r3 80078b6: 041b lsls r3, r3, #16 80078b8: 43db mvns r3, r3 80078ba: 68f9 ldr r1, [r7, #12] 80078bc: f501 6100 add.w r1, r1, #2048 @ 0x800 80078c0: 4013 ands r3, r2 80078c2: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 80078c4: 68fb ldr r3, [r7, #12] 80078c6: f503 6300 add.w r3, r3, #2048 @ 0x800 80078ca: 69da ldr r2, [r3, #28] 80078cc: 683b ldr r3, [r7, #0] 80078ce: 781b ldrb r3, [r3, #0] 80078d0: f003 030f and.w r3, r3, #15 80078d4: 2101 movs r1, #1 80078d6: fa01 f303 lsl.w r3, r1, r3 80078da: 041b lsls r3, r3, #16 80078dc: 43db mvns r3, r3 80078de: 68f9 ldr r1, [r7, #12] 80078e0: f501 6100 add.w r1, r1, #2048 @ 0x800 80078e4: 4013 ands r3, r2 80078e6: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 80078e8: 68bb ldr r3, [r7, #8] 80078ea: 015a lsls r2, r3, #5 80078ec: 68fb ldr r3, [r7, #12] 80078ee: 4413 add r3, r2 80078f0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80078f4: 681a ldr r2, [r3, #0] 80078f6: 68bb ldr r3, [r7, #8] 80078f8: 0159 lsls r1, r3, #5 80078fa: 68fb ldr r3, [r7, #12] 80078fc: 440b add r3, r1 80078fe: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007902: 4619 mov r1, r3 8007904: 4b05 ldr r3, [pc, #20] @ (800791c ) 8007906: 4013 ands r3, r2 8007908: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 800790a: 2300 movs r3, #0 } 800790c: 4618 mov r0, r3 800790e: 3714 adds r7, #20 8007910: 46bd mov sp, r7 8007912: f85d 7b04 ldr.w r7, [sp], #4 8007916: 4770 bx lr 8007918: ec337800 .word 0xec337800 800791c: eff37800 .word 0xeff37800 08007920 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 8007920: b580 push {r7, lr} 8007922: b08a sub sp, #40 @ 0x28 8007924: af02 add r7, sp, #8 8007926: 60f8 str r0, [r7, #12] 8007928: 60b9 str r1, [r7, #8] 800792a: 4613 mov r3, r2 800792c: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 800792e: 68fb ldr r3, [r7, #12] 8007930: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 8007932: 68bb ldr r3, [r7, #8] 8007934: 781b ldrb r3, [r3, #0] 8007936: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 8007938: 68bb ldr r3, [r7, #8] 800793a: 785b ldrb r3, [r3, #1] 800793c: 2b01 cmp r3, #1 800793e: f040 817f bne.w 8007c40 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 8007942: 68bb ldr r3, [r7, #8] 8007944: 691b ldr r3, [r3, #16] 8007946: 2b00 cmp r3, #0 8007948: d132 bne.n 80079b0 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 800794a: 69bb ldr r3, [r7, #24] 800794c: 015a lsls r2, r3, #5 800794e: 69fb ldr r3, [r7, #28] 8007950: 4413 add r3, r2 8007952: f503 6310 add.w r3, r3, #2304 @ 0x900 8007956: 691b ldr r3, [r3, #16] 8007958: 69ba ldr r2, [r7, #24] 800795a: 0151 lsls r1, r2, #5 800795c: 69fa ldr r2, [r7, #28] 800795e: 440a add r2, r1 8007960: f502 6210 add.w r2, r2, #2304 @ 0x900 8007964: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007968: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 800796c: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 800796e: 69bb ldr r3, [r7, #24] 8007970: 015a lsls r2, r3, #5 8007972: 69fb ldr r3, [r7, #28] 8007974: 4413 add r3, r2 8007976: f503 6310 add.w r3, r3, #2304 @ 0x900 800797a: 691b ldr r3, [r3, #16] 800797c: 69ba ldr r2, [r7, #24] 800797e: 0151 lsls r1, r2, #5 8007980: 69fa ldr r2, [r7, #28] 8007982: 440a add r2, r1 8007984: f502 6210 add.w r2, r2, #2304 @ 0x900 8007988: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800798c: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 800798e: 69bb ldr r3, [r7, #24] 8007990: 015a lsls r2, r3, #5 8007992: 69fb ldr r3, [r7, #28] 8007994: 4413 add r3, r2 8007996: f503 6310 add.w r3, r3, #2304 @ 0x900 800799a: 691b ldr r3, [r3, #16] 800799c: 69ba ldr r2, [r7, #24] 800799e: 0151 lsls r1, r2, #5 80079a0: 69fa ldr r2, [r7, #28] 80079a2: 440a add r2, r1 80079a4: f502 6210 add.w r2, r2, #2304 @ 0x900 80079a8: 0cdb lsrs r3, r3, #19 80079aa: 04db lsls r3, r3, #19 80079ac: 6113 str r3, [r2, #16] 80079ae: e097 b.n 8007ae0 /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 80079b0: 69bb ldr r3, [r7, #24] 80079b2: 015a lsls r2, r3, #5 80079b4: 69fb ldr r3, [r7, #28] 80079b6: 4413 add r3, r2 80079b8: f503 6310 add.w r3, r3, #2304 @ 0x900 80079bc: 691b ldr r3, [r3, #16] 80079be: 69ba ldr r2, [r7, #24] 80079c0: 0151 lsls r1, r2, #5 80079c2: 69fa ldr r2, [r7, #28] 80079c4: 440a add r2, r1 80079c6: f502 6210 add.w r2, r2, #2304 @ 0x900 80079ca: 0cdb lsrs r3, r3, #19 80079cc: 04db lsls r3, r3, #19 80079ce: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 80079d0: 69bb ldr r3, [r7, #24] 80079d2: 015a lsls r2, r3, #5 80079d4: 69fb ldr r3, [r7, #28] 80079d6: 4413 add r3, r2 80079d8: f503 6310 add.w r3, r3, #2304 @ 0x900 80079dc: 691b ldr r3, [r3, #16] 80079de: 69ba ldr r2, [r7, #24] 80079e0: 0151 lsls r1, r2, #5 80079e2: 69fa ldr r2, [r7, #28] 80079e4: 440a add r2, r1 80079e6: f502 6210 add.w r2, r2, #2304 @ 0x900 80079ea: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 80079ee: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 80079f2: 6113 str r3, [r2, #16] if (epnum == 0U) 80079f4: 69bb ldr r3, [r7, #24] 80079f6: 2b00 cmp r3, #0 80079f8: d11a bne.n 8007a30 { if (ep->xfer_len > ep->maxpacket) 80079fa: 68bb ldr r3, [r7, #8] 80079fc: 691a ldr r2, [r3, #16] 80079fe: 68bb ldr r3, [r7, #8] 8007a00: 689b ldr r3, [r3, #8] 8007a02: 429a cmp r2, r3 8007a04: d903 bls.n 8007a0e { ep->xfer_len = ep->maxpacket; 8007a06: 68bb ldr r3, [r7, #8] 8007a08: 689a ldr r2, [r3, #8] 8007a0a: 68bb ldr r3, [r7, #8] 8007a0c: 611a str r2, [r3, #16] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8007a0e: 69bb ldr r3, [r7, #24] 8007a10: 015a lsls r2, r3, #5 8007a12: 69fb ldr r3, [r7, #28] 8007a14: 4413 add r3, r2 8007a16: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a1a: 691b ldr r3, [r3, #16] 8007a1c: 69ba ldr r2, [r7, #24] 8007a1e: 0151 lsls r1, r2, #5 8007a20: 69fa ldr r2, [r7, #28] 8007a22: 440a add r2, r1 8007a24: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a28: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007a2c: 6113 str r3, [r2, #16] 8007a2e: e044 b.n 8007aba } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8007a30: 68bb ldr r3, [r7, #8] 8007a32: 691a ldr r2, [r3, #16] 8007a34: 68bb ldr r3, [r7, #8] 8007a36: 689b ldr r3, [r3, #8] 8007a38: 4413 add r3, r2 8007a3a: 1e5a subs r2, r3, #1 8007a3c: 68bb ldr r3, [r7, #8] 8007a3e: 689b ldr r3, [r3, #8] 8007a40: fbb2 f3f3 udiv r3, r2, r3 8007a44: 82fb strh r3, [r7, #22] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); 8007a46: 69bb ldr r3, [r7, #24] 8007a48: 015a lsls r2, r3, #5 8007a4a: 69fb ldr r3, [r7, #28] 8007a4c: 4413 add r3, r2 8007a4e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a52: 691a ldr r2, [r3, #16] 8007a54: 8afb ldrh r3, [r7, #22] 8007a56: 04d9 lsls r1, r3, #19 8007a58: 4ba4 ldr r3, [pc, #656] @ (8007cec ) 8007a5a: 400b ands r3, r1 8007a5c: 69b9 ldr r1, [r7, #24] 8007a5e: 0148 lsls r0, r1, #5 8007a60: 69f9 ldr r1, [r7, #28] 8007a62: 4401 add r1, r0 8007a64: f501 6110 add.w r1, r1, #2304 @ 0x900 8007a68: 4313 orrs r3, r2 8007a6a: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 8007a6c: 68bb ldr r3, [r7, #8] 8007a6e: 791b ldrb r3, [r3, #4] 8007a70: 2b01 cmp r3, #1 8007a72: d122 bne.n 8007aba { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 8007a74: 69bb ldr r3, [r7, #24] 8007a76: 015a lsls r2, r3, #5 8007a78: 69fb ldr r3, [r7, #28] 8007a7a: 4413 add r3, r2 8007a7c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a80: 691b ldr r3, [r3, #16] 8007a82: 69ba ldr r2, [r7, #24] 8007a84: 0151 lsls r1, r2, #5 8007a86: 69fa ldr r2, [r7, #28] 8007a88: 440a add r2, r1 8007a8a: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a8e: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 8007a92: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); 8007a94: 69bb ldr r3, [r7, #24] 8007a96: 015a lsls r2, r3, #5 8007a98: 69fb ldr r3, [r7, #28] 8007a9a: 4413 add r3, r2 8007a9c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007aa0: 691a ldr r2, [r3, #16] 8007aa2: 8afb ldrh r3, [r7, #22] 8007aa4: 075b lsls r3, r3, #29 8007aa6: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 8007aaa: 69b9 ldr r1, [r7, #24] 8007aac: 0148 lsls r0, r1, #5 8007aae: 69f9 ldr r1, [r7, #28] 8007ab0: 4401 add r1, r0 8007ab2: f501 6110 add.w r1, r1, #2304 @ 0x900 8007ab6: 4313 orrs r3, r2 8007ab8: 610b str r3, [r1, #16] } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8007aba: 69bb ldr r3, [r7, #24] 8007abc: 015a lsls r2, r3, #5 8007abe: 69fb ldr r3, [r7, #28] 8007ac0: 4413 add r3, r2 8007ac2: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ac6: 691a ldr r2, [r3, #16] 8007ac8: 68bb ldr r3, [r7, #8] 8007aca: 691b ldr r3, [r3, #16] 8007acc: f3c3 0312 ubfx r3, r3, #0, #19 8007ad0: 69b9 ldr r1, [r7, #24] 8007ad2: 0148 lsls r0, r1, #5 8007ad4: 69f9 ldr r1, [r7, #28] 8007ad6: 4401 add r1, r0 8007ad8: f501 6110 add.w r1, r1, #2304 @ 0x900 8007adc: 4313 orrs r3, r2 8007ade: 610b str r3, [r1, #16] } if (dma == 1U) 8007ae0: 79fb ldrb r3, [r7, #7] 8007ae2: 2b01 cmp r3, #1 8007ae4: d14b bne.n 8007b7e { if ((uint32_t)ep->dma_addr != 0U) 8007ae6: 68bb ldr r3, [r7, #8] 8007ae8: 69db ldr r3, [r3, #28] 8007aea: 2b00 cmp r3, #0 8007aec: d009 beq.n 8007b02 { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8007aee: 69bb ldr r3, [r7, #24] 8007af0: 015a lsls r2, r3, #5 8007af2: 69fb ldr r3, [r7, #28] 8007af4: 4413 add r3, r2 8007af6: f503 6310 add.w r3, r3, #2304 @ 0x900 8007afa: 461a mov r2, r3 8007afc: 68bb ldr r3, [r7, #8] 8007afe: 69db ldr r3, [r3, #28] 8007b00: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 8007b02: 68bb ldr r3, [r7, #8] 8007b04: 791b ldrb r3, [r3, #4] 8007b06: 2b01 cmp r3, #1 8007b08: d128 bne.n 8007b5c { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007b0a: 69fb ldr r3, [r7, #28] 8007b0c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007b10: 689b ldr r3, [r3, #8] 8007b12: f403 7380 and.w r3, r3, #256 @ 0x100 8007b16: 2b00 cmp r3, #0 8007b18: d110 bne.n 8007b3c { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8007b1a: 69bb ldr r3, [r7, #24] 8007b1c: 015a lsls r2, r3, #5 8007b1e: 69fb ldr r3, [r7, #28] 8007b20: 4413 add r3, r2 8007b22: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b26: 681b ldr r3, [r3, #0] 8007b28: 69ba ldr r2, [r7, #24] 8007b2a: 0151 lsls r1, r2, #5 8007b2c: 69fa ldr r2, [r7, #28] 8007b2e: 440a add r2, r1 8007b30: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b34: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007b38: 6013 str r3, [r2, #0] 8007b3a: e00f b.n 8007b5c } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007b3c: 69bb ldr r3, [r7, #24] 8007b3e: 015a lsls r2, r3, #5 8007b40: 69fb ldr r3, [r7, #28] 8007b42: 4413 add r3, r2 8007b44: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b48: 681b ldr r3, [r3, #0] 8007b4a: 69ba ldr r2, [r7, #24] 8007b4c: 0151 lsls r1, r2, #5 8007b4e: 69fa ldr r2, [r7, #28] 8007b50: 440a add r2, r1 8007b52: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b56: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007b5a: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007b5c: 69bb ldr r3, [r7, #24] 8007b5e: 015a lsls r2, r3, #5 8007b60: 69fb ldr r3, [r7, #28] 8007b62: 4413 add r3, r2 8007b64: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b68: 681b ldr r3, [r3, #0] 8007b6a: 69ba ldr r2, [r7, #24] 8007b6c: 0151 lsls r1, r2, #5 8007b6e: 69fa ldr r2, [r7, #28] 8007b70: 440a add r2, r1 8007b72: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b76: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007b7a: 6013 str r3, [r2, #0] 8007b7c: e166 b.n 8007e4c } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007b7e: 69bb ldr r3, [r7, #24] 8007b80: 015a lsls r2, r3, #5 8007b82: 69fb ldr r3, [r7, #28] 8007b84: 4413 add r3, r2 8007b86: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b8a: 681b ldr r3, [r3, #0] 8007b8c: 69ba ldr r2, [r7, #24] 8007b8e: 0151 lsls r1, r2, #5 8007b90: 69fa ldr r2, [r7, #28] 8007b92: 440a add r2, r1 8007b94: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b98: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007b9c: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 8007b9e: 68bb ldr r3, [r7, #8] 8007ba0: 791b ldrb r3, [r3, #4] 8007ba2: 2b01 cmp r3, #1 8007ba4: d015 beq.n 8007bd2 { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8007ba6: 68bb ldr r3, [r7, #8] 8007ba8: 691b ldr r3, [r3, #16] 8007baa: 2b00 cmp r3, #0 8007bac: f000 814e beq.w 8007e4c { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8007bb0: 69fb ldr r3, [r7, #28] 8007bb2: f503 6300 add.w r3, r3, #2048 @ 0x800 8007bb6: 6b5a ldr r2, [r3, #52] @ 0x34 8007bb8: 68bb ldr r3, [r7, #8] 8007bba: 781b ldrb r3, [r3, #0] 8007bbc: f003 030f and.w r3, r3, #15 8007bc0: 2101 movs r1, #1 8007bc2: fa01 f303 lsl.w r3, r1, r3 8007bc6: 69f9 ldr r1, [r7, #28] 8007bc8: f501 6100 add.w r1, r1, #2048 @ 0x800 8007bcc: 4313 orrs r3, r2 8007bce: 634b str r3, [r1, #52] @ 0x34 8007bd0: e13c b.n 8007e4c } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007bd2: 69fb ldr r3, [r7, #28] 8007bd4: f503 6300 add.w r3, r3, #2048 @ 0x800 8007bd8: 689b ldr r3, [r3, #8] 8007bda: f403 7380 and.w r3, r3, #256 @ 0x100 8007bde: 2b00 cmp r3, #0 8007be0: d110 bne.n 8007c04 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8007be2: 69bb ldr r3, [r7, #24] 8007be4: 015a lsls r2, r3, #5 8007be6: 69fb ldr r3, [r7, #28] 8007be8: 4413 add r3, r2 8007bea: f503 6310 add.w r3, r3, #2304 @ 0x900 8007bee: 681b ldr r3, [r3, #0] 8007bf0: 69ba ldr r2, [r7, #24] 8007bf2: 0151 lsls r1, r2, #5 8007bf4: 69fa ldr r2, [r7, #28] 8007bf6: 440a add r2, r1 8007bf8: f502 6210 add.w r2, r2, #2304 @ 0x900 8007bfc: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007c00: 6013 str r3, [r2, #0] 8007c02: e00f b.n 8007c24 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007c04: 69bb ldr r3, [r7, #24] 8007c06: 015a lsls r2, r3, #5 8007c08: 69fb ldr r3, [r7, #28] 8007c0a: 4413 add r3, r2 8007c0c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007c10: 681b ldr r3, [r3, #0] 8007c12: 69ba ldr r2, [r7, #24] 8007c14: 0151 lsls r1, r2, #5 8007c16: 69fa ldr r2, [r7, #28] 8007c18: 440a add r2, r1 8007c1a: f502 6210 add.w r2, r2, #2304 @ 0x900 8007c1e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007c22: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 8007c24: 68bb ldr r3, [r7, #8] 8007c26: 68d9 ldr r1, [r3, #12] 8007c28: 68bb ldr r3, [r7, #8] 8007c2a: 781a ldrb r2, [r3, #0] 8007c2c: 68bb ldr r3, [r7, #8] 8007c2e: 691b ldr r3, [r3, #16] 8007c30: b298 uxth r0, r3 8007c32: 79fb ldrb r3, [r7, #7] 8007c34: 9300 str r3, [sp, #0] 8007c36: 4603 mov r3, r0 8007c38: 68f8 ldr r0, [r7, #12] 8007c3a: f000 f9b9 bl 8007fb0 8007c3e: e105 b.n 8007e4c { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8007c40: 69bb ldr r3, [r7, #24] 8007c42: 015a lsls r2, r3, #5 8007c44: 69fb ldr r3, [r7, #28] 8007c46: 4413 add r3, r2 8007c48: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c4c: 691b ldr r3, [r3, #16] 8007c4e: 69ba ldr r2, [r7, #24] 8007c50: 0151 lsls r1, r2, #5 8007c52: 69fa ldr r2, [r7, #28] 8007c54: 440a add r2, r1 8007c56: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007c5a: 0cdb lsrs r3, r3, #19 8007c5c: 04db lsls r3, r3, #19 8007c5e: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8007c60: 69bb ldr r3, [r7, #24] 8007c62: 015a lsls r2, r3, #5 8007c64: 69fb ldr r3, [r7, #28] 8007c66: 4413 add r3, r2 8007c68: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c6c: 691b ldr r3, [r3, #16] 8007c6e: 69ba ldr r2, [r7, #24] 8007c70: 0151 lsls r1, r2, #5 8007c72: 69fa ldr r2, [r7, #28] 8007c74: 440a add r2, r1 8007c76: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007c7a: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007c7e: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007c82: 6113 str r3, [r2, #16] if (epnum == 0U) 8007c84: 69bb ldr r3, [r7, #24] 8007c86: 2b00 cmp r3, #0 8007c88: d132 bne.n 8007cf0 { if (ep->xfer_len > 0U) 8007c8a: 68bb ldr r3, [r7, #8] 8007c8c: 691b ldr r3, [r3, #16] 8007c8e: 2b00 cmp r3, #0 8007c90: d003 beq.n 8007c9a { ep->xfer_len = ep->maxpacket; 8007c92: 68bb ldr r3, [r7, #8] 8007c94: 689a ldr r2, [r3, #8] 8007c96: 68bb ldr r3, [r7, #8] 8007c98: 611a str r2, [r3, #16] } /* Store transfer size, for EP0 this is equal to endpoint max packet size */ ep->xfer_size = ep->maxpacket; 8007c9a: 68bb ldr r3, [r7, #8] 8007c9c: 689a ldr r2, [r3, #8] 8007c9e: 68bb ldr r3, [r7, #8] 8007ca0: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); 8007ca2: 69bb ldr r3, [r7, #24] 8007ca4: 015a lsls r2, r3, #5 8007ca6: 69fb ldr r3, [r7, #28] 8007ca8: 4413 add r3, r2 8007caa: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007cae: 691a ldr r2, [r3, #16] 8007cb0: 68bb ldr r3, [r7, #8] 8007cb2: 6a1b ldr r3, [r3, #32] 8007cb4: f3c3 0312 ubfx r3, r3, #0, #19 8007cb8: 69b9 ldr r1, [r7, #24] 8007cba: 0148 lsls r0, r1, #5 8007cbc: 69f9 ldr r1, [r7, #28] 8007cbe: 4401 add r1, r0 8007cc0: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007cc4: 4313 orrs r3, r2 8007cc6: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007cc8: 69bb ldr r3, [r7, #24] 8007cca: 015a lsls r2, r3, #5 8007ccc: 69fb ldr r3, [r7, #28] 8007cce: 4413 add r3, r2 8007cd0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007cd4: 691b ldr r3, [r3, #16] 8007cd6: 69ba ldr r2, [r7, #24] 8007cd8: 0151 lsls r1, r2, #5 8007cda: 69fa ldr r2, [r7, #28] 8007cdc: 440a add r2, r1 8007cde: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007ce2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007ce6: 6113 str r3, [r2, #16] 8007ce8: e062 b.n 8007db0 8007cea: bf00 nop 8007cec: 1ff80000 .word 0x1ff80000 } else { if (ep->xfer_len == 0U) 8007cf0: 68bb ldr r3, [r7, #8] 8007cf2: 691b ldr r3, [r3, #16] 8007cf4: 2b00 cmp r3, #0 8007cf6: d123 bne.n 8007d40 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8007cf8: 69bb ldr r3, [r7, #24] 8007cfa: 015a lsls r2, r3, #5 8007cfc: 69fb ldr r3, [r7, #28] 8007cfe: 4413 add r3, r2 8007d00: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d04: 691a ldr r2, [r3, #16] 8007d06: 68bb ldr r3, [r7, #8] 8007d08: 689b ldr r3, [r3, #8] 8007d0a: f3c3 0312 ubfx r3, r3, #0, #19 8007d0e: 69b9 ldr r1, [r7, #24] 8007d10: 0148 lsls r0, r1, #5 8007d12: 69f9 ldr r1, [r7, #28] 8007d14: 4401 add r1, r0 8007d16: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007d1a: 4313 orrs r3, r2 8007d1c: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007d1e: 69bb ldr r3, [r7, #24] 8007d20: 015a lsls r2, r3, #5 8007d22: 69fb ldr r3, [r7, #28] 8007d24: 4413 add r3, r2 8007d26: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d2a: 691b ldr r3, [r3, #16] 8007d2c: 69ba ldr r2, [r7, #24] 8007d2e: 0151 lsls r1, r2, #5 8007d30: 69fa ldr r2, [r7, #28] 8007d32: 440a add r2, r1 8007d34: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007d38: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007d3c: 6113 str r3, [r2, #16] 8007d3e: e037 b.n 8007db0 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8007d40: 68bb ldr r3, [r7, #8] 8007d42: 691a ldr r2, [r3, #16] 8007d44: 68bb ldr r3, [r7, #8] 8007d46: 689b ldr r3, [r3, #8] 8007d48: 4413 add r3, r2 8007d4a: 1e5a subs r2, r3, #1 8007d4c: 68bb ldr r3, [r7, #8] 8007d4e: 689b ldr r3, [r3, #8] 8007d50: fbb2 f3f3 udiv r3, r2, r3 8007d54: 82fb strh r3, [r7, #22] ep->xfer_size = ep->maxpacket * pktcnt; 8007d56: 68bb ldr r3, [r7, #8] 8007d58: 689b ldr r3, [r3, #8] 8007d5a: 8afa ldrh r2, [r7, #22] 8007d5c: fb03 f202 mul.w r2, r3, r2 8007d60: 68bb ldr r3, [r7, #8] 8007d62: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8007d64: 69bb ldr r3, [r7, #24] 8007d66: 015a lsls r2, r3, #5 8007d68: 69fb ldr r3, [r7, #28] 8007d6a: 4413 add r3, r2 8007d6c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d70: 691a ldr r2, [r3, #16] 8007d72: 8afb ldrh r3, [r7, #22] 8007d74: 04d9 lsls r1, r3, #19 8007d76: 4b38 ldr r3, [pc, #224] @ (8007e58 ) 8007d78: 400b ands r3, r1 8007d7a: 69b9 ldr r1, [r7, #24] 8007d7c: 0148 lsls r0, r1, #5 8007d7e: 69f9 ldr r1, [r7, #28] 8007d80: 4401 add r1, r0 8007d82: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007d86: 4313 orrs r3, r2 8007d88: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; 8007d8a: 69bb ldr r3, [r7, #24] 8007d8c: 015a lsls r2, r3, #5 8007d8e: 69fb ldr r3, [r7, #28] 8007d90: 4413 add r3, r2 8007d92: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d96: 691a ldr r2, [r3, #16] 8007d98: 68bb ldr r3, [r7, #8] 8007d9a: 6a1b ldr r3, [r3, #32] 8007d9c: f3c3 0312 ubfx r3, r3, #0, #19 8007da0: 69b9 ldr r1, [r7, #24] 8007da2: 0148 lsls r0, r1, #5 8007da4: 69f9 ldr r1, [r7, #28] 8007da6: 4401 add r1, r0 8007da8: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007dac: 4313 orrs r3, r2 8007dae: 610b str r3, [r1, #16] } } if (dma == 1U) 8007db0: 79fb ldrb r3, [r7, #7] 8007db2: 2b01 cmp r3, #1 8007db4: d10d bne.n 8007dd2 { if ((uint32_t)ep->xfer_buff != 0U) 8007db6: 68bb ldr r3, [r7, #8] 8007db8: 68db ldr r3, [r3, #12] 8007dba: 2b00 cmp r3, #0 8007dbc: d009 beq.n 8007dd2 { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8007dbe: 68bb ldr r3, [r7, #8] 8007dc0: 68d9 ldr r1, [r3, #12] 8007dc2: 69bb ldr r3, [r7, #24] 8007dc4: 015a lsls r2, r3, #5 8007dc6: 69fb ldr r3, [r7, #28] 8007dc8: 4413 add r3, r2 8007dca: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007dce: 460a mov r2, r1 8007dd0: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8007dd2: 68bb ldr r3, [r7, #8] 8007dd4: 791b ldrb r3, [r3, #4] 8007dd6: 2b01 cmp r3, #1 8007dd8: d128 bne.n 8007e2c { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007dda: 69fb ldr r3, [r7, #28] 8007ddc: f503 6300 add.w r3, r3, #2048 @ 0x800 8007de0: 689b ldr r3, [r3, #8] 8007de2: f403 7380 and.w r3, r3, #256 @ 0x100 8007de6: 2b00 cmp r3, #0 8007de8: d110 bne.n 8007e0c { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 8007dea: 69bb ldr r3, [r7, #24] 8007dec: 015a lsls r2, r3, #5 8007dee: 69fb ldr r3, [r7, #28] 8007df0: 4413 add r3, r2 8007df2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007df6: 681b ldr r3, [r3, #0] 8007df8: 69ba ldr r2, [r7, #24] 8007dfa: 0151 lsls r1, r2, #5 8007dfc: 69fa ldr r2, [r7, #28] 8007dfe: 440a add r2, r1 8007e00: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007e04: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007e08: 6013 str r3, [r2, #0] 8007e0a: e00f b.n 8007e2c } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8007e0c: 69bb ldr r3, [r7, #24] 8007e0e: 015a lsls r2, r3, #5 8007e10: 69fb ldr r3, [r7, #28] 8007e12: 4413 add r3, r2 8007e14: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e18: 681b ldr r3, [r3, #0] 8007e1a: 69ba ldr r2, [r7, #24] 8007e1c: 0151 lsls r1, r2, #5 8007e1e: 69fa ldr r2, [r7, #28] 8007e20: 440a add r2, r1 8007e22: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007e26: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007e2a: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8007e2c: 69bb ldr r3, [r7, #24] 8007e2e: 015a lsls r2, r3, #5 8007e30: 69fb ldr r3, [r7, #28] 8007e32: 4413 add r3, r2 8007e34: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e38: 681b ldr r3, [r3, #0] 8007e3a: 69ba ldr r2, [r7, #24] 8007e3c: 0151 lsls r1, r2, #5 8007e3e: 69fa ldr r2, [r7, #28] 8007e40: 440a add r2, r1 8007e42: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007e46: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007e4a: 6013 str r3, [r2, #0] } return HAL_OK; 8007e4c: 2300 movs r3, #0 } 8007e4e: 4618 mov r0, r3 8007e50: 3720 adds r7, #32 8007e52: 46bd mov sp, r7 8007e54: bd80 pop {r7, pc} 8007e56: bf00 nop 8007e58: 1ff80000 .word 0x1ff80000 08007e5c : * @param USBx usb device instance * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8007e5c: b480 push {r7} 8007e5e: b087 sub sp, #28 8007e60: af00 add r7, sp, #0 8007e62: 6078 str r0, [r7, #4] 8007e64: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8007e66: 2300 movs r3, #0 8007e68: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; 8007e6a: 2300 movs r3, #0 8007e6c: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007e6e: 687b ldr r3, [r7, #4] 8007e70: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8007e72: 683b ldr r3, [r7, #0] 8007e74: 785b ldrb r3, [r3, #1] 8007e76: 2b01 cmp r3, #1 8007e78: d14a bne.n 8007f10 { /* EP enable, IN data in FIFO */ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007e7a: 683b ldr r3, [r7, #0] 8007e7c: 781b ldrb r3, [r3, #0] 8007e7e: 015a lsls r2, r3, #5 8007e80: 693b ldr r3, [r7, #16] 8007e82: 4413 add r3, r2 8007e84: f503 6310 add.w r3, r3, #2304 @ 0x900 8007e88: 681b ldr r3, [r3, #0] 8007e8a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007e8e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007e92: f040 8086 bne.w 8007fa2 { USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); 8007e96: 683b ldr r3, [r7, #0] 8007e98: 781b ldrb r3, [r3, #0] 8007e9a: 015a lsls r2, r3, #5 8007e9c: 693b ldr r3, [r7, #16] 8007e9e: 4413 add r3, r2 8007ea0: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ea4: 681b ldr r3, [r3, #0] 8007ea6: 683a ldr r2, [r7, #0] 8007ea8: 7812 ldrb r2, [r2, #0] 8007eaa: 0151 lsls r1, r2, #5 8007eac: 693a ldr r2, [r7, #16] 8007eae: 440a add r2, r1 8007eb0: f502 6210 add.w r2, r2, #2304 @ 0x900 8007eb4: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007eb8: 6013 str r3, [r2, #0] USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); 8007eba: 683b ldr r3, [r7, #0] 8007ebc: 781b ldrb r3, [r3, #0] 8007ebe: 015a lsls r2, r3, #5 8007ec0: 693b ldr r3, [r7, #16] 8007ec2: 4413 add r3, r2 8007ec4: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ec8: 681b ldr r3, [r3, #0] 8007eca: 683a ldr r2, [r7, #0] 8007ecc: 7812 ldrb r2, [r2, #0] 8007ece: 0151 lsls r1, r2, #5 8007ed0: 693a ldr r2, [r7, #16] 8007ed2: 440a add r2, r1 8007ed4: f502 6210 add.w r2, r2, #2304 @ 0x900 8007ed8: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007edc: 6013 str r3, [r2, #0] do { count++; 8007ede: 68fb ldr r3, [r7, #12] 8007ee0: 3301 adds r3, #1 8007ee2: 60fb str r3, [r7, #12] if (count > 10000U) 8007ee4: 68fb ldr r3, [r7, #12] 8007ee6: f242 7210 movw r2, #10000 @ 0x2710 8007eea: 4293 cmp r3, r2 8007eec: d902 bls.n 8007ef4 { ret = HAL_ERROR; 8007eee: 2301 movs r3, #1 8007ef0: 75fb strb r3, [r7, #23] break; 8007ef2: e056 b.n 8007fa2 } } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); 8007ef4: 683b ldr r3, [r7, #0] 8007ef6: 781b ldrb r3, [r3, #0] 8007ef8: 015a lsls r2, r3, #5 8007efa: 693b ldr r3, [r7, #16] 8007efc: 4413 add r3, r2 8007efe: f503 6310 add.w r3, r3, #2304 @ 0x900 8007f02: 681b ldr r3, [r3, #0] 8007f04: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007f08: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007f0c: d0e7 beq.n 8007ede 8007f0e: e048 b.n 8007fa2 } } else /* OUT endpoint */ { if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007f10: 683b ldr r3, [r7, #0] 8007f12: 781b ldrb r3, [r3, #0] 8007f14: 015a lsls r2, r3, #5 8007f16: 693b ldr r3, [r7, #16] 8007f18: 4413 add r3, r2 8007f1a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f1e: 681b ldr r3, [r3, #0] 8007f20: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007f24: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007f28: d13b bne.n 8007fa2 { USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); 8007f2a: 683b ldr r3, [r7, #0] 8007f2c: 781b ldrb r3, [r3, #0] 8007f2e: 015a lsls r2, r3, #5 8007f30: 693b ldr r3, [r7, #16] 8007f32: 4413 add r3, r2 8007f34: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f38: 681b ldr r3, [r3, #0] 8007f3a: 683a ldr r2, [r7, #0] 8007f3c: 7812 ldrb r2, [r2, #0] 8007f3e: 0151 lsls r1, r2, #5 8007f40: 693a ldr r2, [r7, #16] 8007f42: 440a add r2, r1 8007f44: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f48: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007f4c: 6013 str r3, [r2, #0] USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); 8007f4e: 683b ldr r3, [r7, #0] 8007f50: 781b ldrb r3, [r3, #0] 8007f52: 015a lsls r2, r3, #5 8007f54: 693b ldr r3, [r7, #16] 8007f56: 4413 add r3, r2 8007f58: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f5c: 681b ldr r3, [r3, #0] 8007f5e: 683a ldr r2, [r7, #0] 8007f60: 7812 ldrb r2, [r2, #0] 8007f62: 0151 lsls r1, r2, #5 8007f64: 693a ldr r2, [r7, #16] 8007f66: 440a add r2, r1 8007f68: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f6c: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007f70: 6013 str r3, [r2, #0] do { count++; 8007f72: 68fb ldr r3, [r7, #12] 8007f74: 3301 adds r3, #1 8007f76: 60fb str r3, [r7, #12] if (count > 10000U) 8007f78: 68fb ldr r3, [r7, #12] 8007f7a: f242 7210 movw r2, #10000 @ 0x2710 8007f7e: 4293 cmp r3, r2 8007f80: d902 bls.n 8007f88 { ret = HAL_ERROR; 8007f82: 2301 movs r3, #1 8007f84: 75fb strb r3, [r7, #23] break; 8007f86: e00c b.n 8007fa2 } } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); 8007f88: 683b ldr r3, [r7, #0] 8007f8a: 781b ldrb r3, [r3, #0] 8007f8c: 015a lsls r2, r3, #5 8007f8e: 693b ldr r3, [r7, #16] 8007f90: 4413 add r3, r2 8007f92: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f96: 681b ldr r3, [r3, #0] 8007f98: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007f9c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007fa0: d0e7 beq.n 8007f72 } } return ret; 8007fa2: 7dfb ldrb r3, [r7, #23] } 8007fa4: 4618 mov r0, r3 8007fa6: 371c adds r7, #28 8007fa8: 46bd mov sp, r7 8007faa: f85d 7b04 ldr.w r7, [sp], #4 8007fae: 4770 bx lr 08007fb0 : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 8007fb0: b480 push {r7} 8007fb2: b089 sub sp, #36 @ 0x24 8007fb4: af00 add r7, sp, #0 8007fb6: 60f8 str r0, [r7, #12] 8007fb8: 60b9 str r1, [r7, #8] 8007fba: 4611 mov r1, r2 8007fbc: 461a mov r2, r3 8007fbe: 460b mov r3, r1 8007fc0: 71fb strb r3, [r7, #7] 8007fc2: 4613 mov r3, r2 8007fc4: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007fc6: 68fb ldr r3, [r7, #12] 8007fc8: 617b str r3, [r7, #20] uint8_t *pSrc = src; 8007fca: 68bb ldr r3, [r7, #8] 8007fcc: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 8007fce: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8007fd2: 2b00 cmp r3, #0 8007fd4: d123 bne.n 800801e { count32b = ((uint32_t)len + 3U) / 4U; 8007fd6: 88bb ldrh r3, [r7, #4] 8007fd8: 3303 adds r3, #3 8007fda: 089b lsrs r3, r3, #2 8007fdc: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 8007fde: 2300 movs r3, #0 8007fe0: 61bb str r3, [r7, #24] 8007fe2: e018 b.n 8008016 { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 8007fe4: 79fb ldrb r3, [r7, #7] 8007fe6: 031a lsls r2, r3, #12 8007fe8: 697b ldr r3, [r7, #20] 8007fea: 4413 add r3, r2 8007fec: f503 5380 add.w r3, r3, #4096 @ 0x1000 8007ff0: 461a mov r2, r3 8007ff2: 69fb ldr r3, [r7, #28] 8007ff4: 681b ldr r3, [r3, #0] 8007ff6: 6013 str r3, [r2, #0] pSrc++; 8007ff8: 69fb ldr r3, [r7, #28] 8007ffa: 3301 adds r3, #1 8007ffc: 61fb str r3, [r7, #28] pSrc++; 8007ffe: 69fb ldr r3, [r7, #28] 8008000: 3301 adds r3, #1 8008002: 61fb str r3, [r7, #28] pSrc++; 8008004: 69fb ldr r3, [r7, #28] 8008006: 3301 adds r3, #1 8008008: 61fb str r3, [r7, #28] pSrc++; 800800a: 69fb ldr r3, [r7, #28] 800800c: 3301 adds r3, #1 800800e: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8008010: 69bb ldr r3, [r7, #24] 8008012: 3301 adds r3, #1 8008014: 61bb str r3, [r7, #24] 8008016: 69ba ldr r2, [r7, #24] 8008018: 693b ldr r3, [r7, #16] 800801a: 429a cmp r2, r3 800801c: d3e2 bcc.n 8007fe4 } } return HAL_OK; 800801e: 2300 movs r3, #0 } 8008020: 4618 mov r0, r3 8008022: 3724 adds r7, #36 @ 0x24 8008024: 46bd mov sp, r7 8008026: f85d 7b04 ldr.w r7, [sp], #4 800802a: 4770 bx lr 0800802c : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 800802c: b480 push {r7} 800802e: b08b sub sp, #44 @ 0x2c 8008030: af00 add r7, sp, #0 8008032: 60f8 str r0, [r7, #12] 8008034: 60b9 str r1, [r7, #8] 8008036: 4613 mov r3, r2 8008038: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 800803a: 68fb ldr r3, [r7, #12] 800803c: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 800803e: 68bb ldr r3, [r7, #8] 8008040: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8008042: 88fb ldrh r3, [r7, #6] 8008044: 089b lsrs r3, r3, #2 8008046: b29b uxth r3, r3 8008048: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 800804a: 88fb ldrh r3, [r7, #6] 800804c: f003 0303 and.w r3, r3, #3 8008050: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8008052: 2300 movs r3, #0 8008054: 623b str r3, [r7, #32] 8008056: e014 b.n 8008082 { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8008058: 69bb ldr r3, [r7, #24] 800805a: f503 5380 add.w r3, r3, #4096 @ 0x1000 800805e: 681a ldr r2, [r3, #0] 8008060: 6a7b ldr r3, [r7, #36] @ 0x24 8008062: 601a str r2, [r3, #0] pDest++; 8008064: 6a7b ldr r3, [r7, #36] @ 0x24 8008066: 3301 adds r3, #1 8008068: 627b str r3, [r7, #36] @ 0x24 pDest++; 800806a: 6a7b ldr r3, [r7, #36] @ 0x24 800806c: 3301 adds r3, #1 800806e: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008070: 6a7b ldr r3, [r7, #36] @ 0x24 8008072: 3301 adds r3, #1 8008074: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008076: 6a7b ldr r3, [r7, #36] @ 0x24 8008078: 3301 adds r3, #1 800807a: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 800807c: 6a3b ldr r3, [r7, #32] 800807e: 3301 adds r3, #1 8008080: 623b str r3, [r7, #32] 8008082: 6a3a ldr r2, [r7, #32] 8008084: 697b ldr r3, [r7, #20] 8008086: 429a cmp r2, r3 8008088: d3e6 bcc.n 8008058 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 800808a: 8bfb ldrh r3, [r7, #30] 800808c: 2b00 cmp r3, #0 800808e: d01e beq.n 80080ce { i = 0U; 8008090: 2300 movs r3, #0 8008092: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8008094: 69bb ldr r3, [r7, #24] 8008096: f503 5380 add.w r3, r3, #4096 @ 0x1000 800809a: 461a mov r2, r3 800809c: f107 0310 add.w r3, r7, #16 80080a0: 6812 ldr r2, [r2, #0] 80080a2: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 80080a4: 693a ldr r2, [r7, #16] 80080a6: 6a3b ldr r3, [r7, #32] 80080a8: b2db uxtb r3, r3 80080aa: 00db lsls r3, r3, #3 80080ac: fa22 f303 lsr.w r3, r2, r3 80080b0: b2da uxtb r2, r3 80080b2: 6a7b ldr r3, [r7, #36] @ 0x24 80080b4: 701a strb r2, [r3, #0] i++; 80080b6: 6a3b ldr r3, [r7, #32] 80080b8: 3301 adds r3, #1 80080ba: 623b str r3, [r7, #32] pDest++; 80080bc: 6a7b ldr r3, [r7, #36] @ 0x24 80080be: 3301 adds r3, #1 80080c0: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 80080c2: 8bfb ldrh r3, [r7, #30] 80080c4: 3b01 subs r3, #1 80080c6: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 80080c8: 8bfb ldrh r3, [r7, #30] 80080ca: 2b00 cmp r3, #0 80080cc: d1ea bne.n 80080a4 } return ((void *)pDest); 80080ce: 6a7b ldr r3, [r7, #36] @ 0x24 } 80080d0: 4618 mov r0, r3 80080d2: 372c adds r7, #44 @ 0x2c 80080d4: 46bd mov sp, r7 80080d6: f85d 7b04 ldr.w r7, [sp], #4 80080da: 4770 bx lr 080080dc : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80080dc: b480 push {r7} 80080de: b085 sub sp, #20 80080e0: af00 add r7, sp, #0 80080e2: 6078 str r0, [r7, #4] 80080e4: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80080e6: 687b ldr r3, [r7, #4] 80080e8: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80080ea: 683b ldr r3, [r7, #0] 80080ec: 781b ldrb r3, [r3, #0] 80080ee: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80080f0: 683b ldr r3, [r7, #0] 80080f2: 785b ldrb r3, [r3, #1] 80080f4: 2b01 cmp r3, #1 80080f6: d12c bne.n 8008152 { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 80080f8: 68bb ldr r3, [r7, #8] 80080fa: 015a lsls r2, r3, #5 80080fc: 68fb ldr r3, [r7, #12] 80080fe: 4413 add r3, r2 8008100: f503 6310 add.w r3, r3, #2304 @ 0x900 8008104: 681b ldr r3, [r3, #0] 8008106: 2b00 cmp r3, #0 8008108: db12 blt.n 8008130 800810a: 68bb ldr r3, [r7, #8] 800810c: 2b00 cmp r3, #0 800810e: d00f beq.n 8008130 { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8008110: 68bb ldr r3, [r7, #8] 8008112: 015a lsls r2, r3, #5 8008114: 68fb ldr r3, [r7, #12] 8008116: 4413 add r3, r2 8008118: f503 6310 add.w r3, r3, #2304 @ 0x900 800811c: 681b ldr r3, [r3, #0] 800811e: 68ba ldr r2, [r7, #8] 8008120: 0151 lsls r1, r2, #5 8008122: 68fa ldr r2, [r7, #12] 8008124: 440a add r2, r1 8008126: f502 6210 add.w r2, r2, #2304 @ 0x900 800812a: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 800812e: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8008130: 68bb ldr r3, [r7, #8] 8008132: 015a lsls r2, r3, #5 8008134: 68fb ldr r3, [r7, #12] 8008136: 4413 add r3, r2 8008138: f503 6310 add.w r3, r3, #2304 @ 0x900 800813c: 681b ldr r3, [r3, #0] 800813e: 68ba ldr r2, [r7, #8] 8008140: 0151 lsls r1, r2, #5 8008142: 68fa ldr r2, [r7, #12] 8008144: 440a add r2, r1 8008146: f502 6210 add.w r2, r2, #2304 @ 0x900 800814a: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800814e: 6013 str r3, [r2, #0] 8008150: e02b b.n 80081aa } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 8008152: 68bb ldr r3, [r7, #8] 8008154: 015a lsls r2, r3, #5 8008156: 68fb ldr r3, [r7, #12] 8008158: 4413 add r3, r2 800815a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800815e: 681b ldr r3, [r3, #0] 8008160: 2b00 cmp r3, #0 8008162: db12 blt.n 800818a 8008164: 68bb ldr r3, [r7, #8] 8008166: 2b00 cmp r3, #0 8008168: d00f beq.n 800818a { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 800816a: 68bb ldr r3, [r7, #8] 800816c: 015a lsls r2, r3, #5 800816e: 68fb ldr r3, [r7, #12] 8008170: 4413 add r3, r2 8008172: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008176: 681b ldr r3, [r3, #0] 8008178: 68ba ldr r2, [r7, #8] 800817a: 0151 lsls r1, r2, #5 800817c: 68fa ldr r2, [r7, #12] 800817e: 440a add r2, r1 8008180: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008184: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008188: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 800818a: 68bb ldr r3, [r7, #8] 800818c: 015a lsls r2, r3, #5 800818e: 68fb ldr r3, [r7, #12] 8008190: 4413 add r3, r2 8008192: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008196: 681b ldr r3, [r3, #0] 8008198: 68ba ldr r2, [r7, #8] 800819a: 0151 lsls r1, r2, #5 800819c: 68fa ldr r2, [r7, #12] 800819e: 440a add r2, r1 80081a0: f502 6230 add.w r2, r2, #2816 @ 0xb00 80081a4: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 80081a8: 6013 str r3, [r2, #0] } return HAL_OK; 80081aa: 2300 movs r3, #0 } 80081ac: 4618 mov r0, r3 80081ae: 3714 adds r7, #20 80081b0: 46bd mov sp, r7 80081b2: f85d 7b04 ldr.w r7, [sp], #4 80081b6: 4770 bx lr 080081b8 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80081b8: b480 push {r7} 80081ba: b085 sub sp, #20 80081bc: af00 add r7, sp, #0 80081be: 6078 str r0, [r7, #4] 80081c0: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80081c2: 687b ldr r3, [r7, #4] 80081c4: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80081c6: 683b ldr r3, [r7, #0] 80081c8: 781b ldrb r3, [r3, #0] 80081ca: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80081cc: 683b ldr r3, [r7, #0] 80081ce: 785b ldrb r3, [r3, #1] 80081d0: 2b01 cmp r3, #1 80081d2: d128 bne.n 8008226 { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 80081d4: 68bb ldr r3, [r7, #8] 80081d6: 015a lsls r2, r3, #5 80081d8: 68fb ldr r3, [r7, #12] 80081da: 4413 add r3, r2 80081dc: f503 6310 add.w r3, r3, #2304 @ 0x900 80081e0: 681b ldr r3, [r3, #0] 80081e2: 68ba ldr r2, [r7, #8] 80081e4: 0151 lsls r1, r2, #5 80081e6: 68fa ldr r2, [r7, #12] 80081e8: 440a add r2, r1 80081ea: f502 6210 add.w r2, r2, #2304 @ 0x900 80081ee: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80081f2: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 80081f4: 683b ldr r3, [r7, #0] 80081f6: 791b ldrb r3, [r3, #4] 80081f8: 2b03 cmp r3, #3 80081fa: d003 beq.n 8008204 80081fc: 683b ldr r3, [r7, #0] 80081fe: 791b ldrb r3, [r3, #4] 8008200: 2b02 cmp r3, #2 8008202: d138 bne.n 8008276 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008204: 68bb ldr r3, [r7, #8] 8008206: 015a lsls r2, r3, #5 8008208: 68fb ldr r3, [r7, #12] 800820a: 4413 add r3, r2 800820c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008210: 681b ldr r3, [r3, #0] 8008212: 68ba ldr r2, [r7, #8] 8008214: 0151 lsls r1, r2, #5 8008216: 68fa ldr r2, [r7, #12] 8008218: 440a add r2, r1 800821a: f502 6210 add.w r2, r2, #2304 @ 0x900 800821e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008222: 6013 str r3, [r2, #0] 8008224: e027 b.n 8008276 } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8008226: 68bb ldr r3, [r7, #8] 8008228: 015a lsls r2, r3, #5 800822a: 68fb ldr r3, [r7, #12] 800822c: 4413 add r3, r2 800822e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008232: 681b ldr r3, [r3, #0] 8008234: 68ba ldr r2, [r7, #8] 8008236: 0151 lsls r1, r2, #5 8008238: 68fa ldr r2, [r7, #12] 800823a: 440a add r2, r1 800823c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008240: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8008244: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8008246: 683b ldr r3, [r7, #0] 8008248: 791b ldrb r3, [r3, #4] 800824a: 2b03 cmp r3, #3 800824c: d003 beq.n 8008256 800824e: 683b ldr r3, [r7, #0] 8008250: 791b ldrb r3, [r3, #4] 8008252: 2b02 cmp r3, #2 8008254: d10f bne.n 8008276 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008256: 68bb ldr r3, [r7, #8] 8008258: 015a lsls r2, r3, #5 800825a: 68fb ldr r3, [r7, #12] 800825c: 4413 add r3, r2 800825e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008262: 681b ldr r3, [r3, #0] 8008264: 68ba ldr r2, [r7, #8] 8008266: 0151 lsls r1, r2, #5 8008268: 68fa ldr r2, [r7, #12] 800826a: 440a add r2, r1 800826c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008270: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008274: 6013 str r3, [r2, #0] } } return HAL_OK; 8008276: 2300 movs r3, #0 } 8008278: 4618 mov r0, r3 800827a: 3714 adds r7, #20 800827c: 46bd mov sp, r7 800827e: f85d 7b04 ldr.w r7, [sp], #4 8008282: 4770 bx lr 08008284 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 8008284: b480 push {r7} 8008286: b085 sub sp, #20 8008288: af00 add r7, sp, #0 800828a: 6078 str r0, [r7, #4] 800828c: 460b mov r3, r1 800828e: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008290: 687b ldr r3, [r7, #4] 8008292: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 8008294: 68fb ldr r3, [r7, #12] 8008296: f503 6300 add.w r3, r3, #2048 @ 0x800 800829a: 681b ldr r3, [r3, #0] 800829c: 68fa ldr r2, [r7, #12] 800829e: f502 6200 add.w r2, r2, #2048 @ 0x800 80082a2: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 80082a6: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 80082a8: 68fb ldr r3, [r7, #12] 80082aa: f503 6300 add.w r3, r3, #2048 @ 0x800 80082ae: 681a ldr r2, [r3, #0] 80082b0: 78fb ldrb r3, [r7, #3] 80082b2: 011b lsls r3, r3, #4 80082b4: f403 63fe and.w r3, r3, #2032 @ 0x7f0 80082b8: 68f9 ldr r1, [r7, #12] 80082ba: f501 6100 add.w r1, r1, #2048 @ 0x800 80082be: 4313 orrs r3, r2 80082c0: 600b str r3, [r1, #0] return HAL_OK; 80082c2: 2300 movs r3, #0 } 80082c4: 4618 mov r0, r3 80082c6: 3714 adds r7, #20 80082c8: 46bd mov sp, r7 80082ca: f85d 7b04 ldr.w r7, [sp], #4 80082ce: 4770 bx lr 080082d0 : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { 80082d0: b480 push {r7} 80082d2: b085 sub sp, #20 80082d4: af00 add r7, sp, #0 80082d6: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80082d8: 687b ldr r3, [r7, #4] 80082da: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 80082dc: 68fb ldr r3, [r7, #12] 80082de: f503 6360 add.w r3, r3, #3584 @ 0xe00 80082e2: 681b ldr r3, [r3, #0] 80082e4: 68fa ldr r2, [r7, #12] 80082e6: f502 6260 add.w r2, r2, #3584 @ 0xe00 80082ea: f023 0303 bic.w r3, r3, #3 80082ee: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 80082f0: 68fb ldr r3, [r7, #12] 80082f2: f503 6300 add.w r3, r3, #2048 @ 0x800 80082f6: 685b ldr r3, [r3, #4] 80082f8: 68fa ldr r2, [r7, #12] 80082fa: f502 6200 add.w r2, r2, #2048 @ 0x800 80082fe: f023 0302 bic.w r3, r3, #2 8008302: 6053 str r3, [r2, #4] return HAL_OK; 8008304: 2300 movs r3, #0 } 8008306: 4618 mov r0, r3 8008308: 3714 adds r7, #20 800830a: 46bd mov sp, r7 800830c: f85d 7b04 ldr.w r7, [sp], #4 8008310: 4770 bx lr 08008312 : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 8008312: b480 push {r7} 8008314: b085 sub sp, #20 8008316: af00 add r7, sp, #0 8008318: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800831a: 687b ldr r3, [r7, #4] 800831c: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 800831e: 68fb ldr r3, [r7, #12] 8008320: f503 6360 add.w r3, r3, #3584 @ 0xe00 8008324: 681b ldr r3, [r3, #0] 8008326: 68fa ldr r2, [r7, #12] 8008328: f502 6260 add.w r2, r2, #3584 @ 0xe00 800832c: f023 0303 bic.w r3, r3, #3 8008330: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8008332: 68fb ldr r3, [r7, #12] 8008334: f503 6300 add.w r3, r3, #2048 @ 0x800 8008338: 685b ldr r3, [r3, #4] 800833a: 68fa ldr r2, [r7, #12] 800833c: f502 6200 add.w r2, r2, #2048 @ 0x800 8008340: f043 0302 orr.w r3, r3, #2 8008344: 6053 str r3, [r2, #4] return HAL_OK; 8008346: 2300 movs r3, #0 } 8008348: 4618 mov r0, r3 800834a: 3714 adds r7, #20 800834c: 46bd mov sp, r7 800834e: f85d 7b04 ldr.w r7, [sp], #4 8008352: 4770 bx lr 08008354 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 8008354: b480 push {r7} 8008356: b085 sub sp, #20 8008358: af00 add r7, sp, #0 800835a: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 800835c: 687b ldr r3, [r7, #4] 800835e: 695b ldr r3, [r3, #20] 8008360: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 8008362: 687b ldr r3, [r7, #4] 8008364: 699b ldr r3, [r3, #24] 8008366: 68fa ldr r2, [r7, #12] 8008368: 4013 ands r3, r2 800836a: 60fb str r3, [r7, #12] return tmpreg; 800836c: 68fb ldr r3, [r7, #12] } 800836e: 4618 mov r0, r3 8008370: 3714 adds r7, #20 8008372: 46bd mov sp, r7 8008374: f85d 7b04 ldr.w r7, [sp], #4 8008378: 4770 bx lr 0800837a : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 800837a: b480 push {r7} 800837c: b085 sub sp, #20 800837e: af00 add r7, sp, #0 8008380: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008382: 687b ldr r3, [r7, #4] 8008384: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8008386: 68fb ldr r3, [r7, #12] 8008388: f503 6300 add.w r3, r3, #2048 @ 0x800 800838c: 699b ldr r3, [r3, #24] 800838e: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8008390: 68fb ldr r3, [r7, #12] 8008392: f503 6300 add.w r3, r3, #2048 @ 0x800 8008396: 69db ldr r3, [r3, #28] 8008398: 68ba ldr r2, [r7, #8] 800839a: 4013 ands r3, r2 800839c: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 800839e: 68bb ldr r3, [r7, #8] 80083a0: 0c1b lsrs r3, r3, #16 } 80083a2: 4618 mov r0, r3 80083a4: 3714 adds r7, #20 80083a6: 46bd mov sp, r7 80083a8: f85d 7b04 ldr.w r7, [sp], #4 80083ac: 4770 bx lr 080083ae : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 80083ae: b480 push {r7} 80083b0: b085 sub sp, #20 80083b2: af00 add r7, sp, #0 80083b4: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80083b6: 687b ldr r3, [r7, #4] 80083b8: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 80083ba: 68fb ldr r3, [r7, #12] 80083bc: f503 6300 add.w r3, r3, #2048 @ 0x800 80083c0: 699b ldr r3, [r3, #24] 80083c2: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 80083c4: 68fb ldr r3, [r7, #12] 80083c6: f503 6300 add.w r3, r3, #2048 @ 0x800 80083ca: 69db ldr r3, [r3, #28] 80083cc: 68ba ldr r2, [r7, #8] 80083ce: 4013 ands r3, r2 80083d0: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 80083d2: 68bb ldr r3, [r7, #8] 80083d4: b29b uxth r3, r3 } 80083d6: 4618 mov r0, r3 80083d8: 3714 adds r7, #20 80083da: 46bd mov sp, r7 80083dc: f85d 7b04 ldr.w r7, [sp], #4 80083e0: 4770 bx lr 080083e2 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 80083e2: b480 push {r7} 80083e4: b085 sub sp, #20 80083e6: af00 add r7, sp, #0 80083e8: 6078 str r0, [r7, #4] 80083ea: 460b mov r3, r1 80083ec: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80083ee: 687b ldr r3, [r7, #4] 80083f0: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 80083f2: 78fb ldrb r3, [r7, #3] 80083f4: 015a lsls r2, r3, #5 80083f6: 68fb ldr r3, [r7, #12] 80083f8: 4413 add r3, r2 80083fa: f503 6330 add.w r3, r3, #2816 @ 0xb00 80083fe: 689b ldr r3, [r3, #8] 8008400: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 8008402: 68fb ldr r3, [r7, #12] 8008404: f503 6300 add.w r3, r3, #2048 @ 0x800 8008408: 695b ldr r3, [r3, #20] 800840a: 68ba ldr r2, [r7, #8] 800840c: 4013 ands r3, r2 800840e: 60bb str r3, [r7, #8] return tmpreg; 8008410: 68bb ldr r3, [r7, #8] } 8008412: 4618 mov r0, r3 8008414: 3714 adds r7, #20 8008416: 46bd mov sp, r7 8008418: f85d 7b04 ldr.w r7, [sp], #4 800841c: 4770 bx lr 0800841e : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 800841e: b480 push {r7} 8008420: b087 sub sp, #28 8008422: af00 add r7, sp, #0 8008424: 6078 str r0, [r7, #4] 8008426: 460b mov r3, r1 8008428: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 800842a: 687b ldr r3, [r7, #4] 800842c: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 800842e: 697b ldr r3, [r7, #20] 8008430: f503 6300 add.w r3, r3, #2048 @ 0x800 8008434: 691b ldr r3, [r3, #16] 8008436: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 8008438: 697b ldr r3, [r7, #20] 800843a: f503 6300 add.w r3, r3, #2048 @ 0x800 800843e: 6b5b ldr r3, [r3, #52] @ 0x34 8008440: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 8008442: 78fb ldrb r3, [r7, #3] 8008444: f003 030f and.w r3, r3, #15 8008448: 68fa ldr r2, [r7, #12] 800844a: fa22 f303 lsr.w r3, r2, r3 800844e: 01db lsls r3, r3, #7 8008450: b2db uxtb r3, r3 8008452: 693a ldr r2, [r7, #16] 8008454: 4313 orrs r3, r2 8008456: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 8008458: 78fb ldrb r3, [r7, #3] 800845a: 015a lsls r2, r3, #5 800845c: 697b ldr r3, [r7, #20] 800845e: 4413 add r3, r2 8008460: f503 6310 add.w r3, r3, #2304 @ 0x900 8008464: 689b ldr r3, [r3, #8] 8008466: 693a ldr r2, [r7, #16] 8008468: 4013 ands r3, r2 800846a: 60bb str r3, [r7, #8] return tmpreg; 800846c: 68bb ldr r3, [r7, #8] } 800846e: 4618 mov r0, r3 8008470: 371c adds r7, #28 8008472: 46bd mov sp, r7 8008474: f85d 7b04 ldr.w r7, [sp], #4 8008478: 4770 bx lr 0800847a : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 800847a: b480 push {r7} 800847c: b083 sub sp, #12 800847e: af00 add r7, sp, #0 8008480: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 8008482: 687b ldr r3, [r7, #4] 8008484: 695b ldr r3, [r3, #20] 8008486: f003 0301 and.w r3, r3, #1 } 800848a: 4618 mov r0, r3 800848c: 370c adds r7, #12 800848e: 46bd mov sp, r7 8008490: f85d 7b04 ldr.w r7, [sp], #4 8008494: 4770 bx lr 08008496 : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { 8008496: b480 push {r7} 8008498: b085 sub sp, #20 800849a: af00 add r7, sp, #0 800849c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800849e: 687b ldr r3, [r7, #4] 80084a0: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 80084a2: 68fb ldr r3, [r7, #12] 80084a4: f503 6310 add.w r3, r3, #2304 @ 0x900 80084a8: 681b ldr r3, [r3, #0] 80084aa: 68fa ldr r2, [r7, #12] 80084ac: f502 6210 add.w r2, r2, #2304 @ 0x900 80084b0: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 80084b4: f023 0307 bic.w r3, r3, #7 80084b8: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 80084ba: 68fb ldr r3, [r7, #12] 80084bc: f503 6300 add.w r3, r3, #2048 @ 0x800 80084c0: 685b ldr r3, [r3, #4] 80084c2: 68fa ldr r2, [r7, #12] 80084c4: f502 6200 add.w r2, r2, #2048 @ 0x800 80084c8: f443 7380 orr.w r3, r3, #256 @ 0x100 80084cc: 6053 str r3, [r2, #4] return HAL_OK; 80084ce: 2300 movs r3, #0 } 80084d0: 4618 mov r0, r3 80084d2: 3714 adds r7, #20 80084d4: 46bd mov sp, r7 80084d6: f85d 7b04 ldr.w r7, [sp], #4 80084da: 4770 bx lr 080084dc : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { 80084dc: b480 push {r7} 80084de: b087 sub sp, #28 80084e0: af00 add r7, sp, #0 80084e2: 60f8 str r0, [r7, #12] 80084e4: 460b mov r3, r1 80084e6: 607a str r2, [r7, #4] 80084e8: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 80084ea: 68fb ldr r3, [r7, #12] 80084ec: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 80084ee: 68fb ldr r3, [r7, #12] 80084f0: 333c adds r3, #60 @ 0x3c 80084f2: 3304 adds r3, #4 80084f4: 681b ldr r3, [r3, #0] 80084f6: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 80084f8: 693b ldr r3, [r7, #16] 80084fa: 4a26 ldr r2, [pc, #152] @ (8008594 ) 80084fc: 4293 cmp r3, r2 80084fe: d90a bls.n 8008516 { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8008500: 697b ldr r3, [r7, #20] 8008502: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008506: 681b ldr r3, [r3, #0] 8008508: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800850c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008510: d101 bne.n 8008516 { return HAL_OK; 8008512: 2300 movs r3, #0 8008514: e037 b.n 8008586 } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 8008516: 697b ldr r3, [r7, #20] 8008518: f503 6330 add.w r3, r3, #2816 @ 0xb00 800851c: 461a mov r2, r3 800851e: 2300 movs r3, #0 8008520: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8008522: 697b ldr r3, [r7, #20] 8008524: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008528: 691b ldr r3, [r3, #16] 800852a: 697a ldr r2, [r7, #20] 800852c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008530: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008534: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 8008536: 697b ldr r3, [r7, #20] 8008538: f503 6330 add.w r3, r3, #2816 @ 0xb00 800853c: 691b ldr r3, [r3, #16] 800853e: 697a ldr r2, [r7, #20] 8008540: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008544: f043 0318 orr.w r3, r3, #24 8008548: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 800854a: 697b ldr r3, [r7, #20] 800854c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008550: 691b ldr r3, [r3, #16] 8008552: 697a ldr r2, [r7, #20] 8008554: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008558: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 800855c: 6113 str r3, [r2, #16] if (dma == 1U) 800855e: 7afb ldrb r3, [r7, #11] 8008560: 2b01 cmp r3, #1 8008562: d10f bne.n 8008584 { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 8008564: 697b ldr r3, [r7, #20] 8008566: f503 6330 add.w r3, r3, #2816 @ 0xb00 800856a: 461a mov r2, r3 800856c: 687b ldr r3, [r7, #4] 800856e: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 8008570: 697b ldr r3, [r7, #20] 8008572: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008576: 681b ldr r3, [r3, #0] 8008578: 697a ldr r2, [r7, #20] 800857a: f502 6230 add.w r2, r2, #2816 @ 0xb00 800857e: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 8008582: 6013 str r3, [r2, #0] } return HAL_OK; 8008584: 2300 movs r3, #0 } 8008586: 4618 mov r0, r3 8008588: 371c adds r7, #28 800858a: 46bd mov sp, r7 800858c: f85d 7b04 ldr.w r7, [sp], #4 8008590: 4770 bx lr 8008592: bf00 nop 8008594: 4f54300a .word 0x4f54300a 08008598 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 8008598: b480 push {r7} 800859a: b085 sub sp, #20 800859c: af00 add r7, sp, #0 800859e: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80085a0: 2300 movs r3, #0 80085a2: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80085a4: 68fb ldr r3, [r7, #12] 80085a6: 3301 adds r3, #1 80085a8: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80085aa: 68fb ldr r3, [r7, #12] 80085ac: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80085b0: d901 bls.n 80085b6 { return HAL_TIMEOUT; 80085b2: 2303 movs r3, #3 80085b4: e022 b.n 80085fc } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80085b6: 687b ldr r3, [r7, #4] 80085b8: 691b ldr r3, [r3, #16] 80085ba: 2b00 cmp r3, #0 80085bc: daf2 bge.n 80085a4 count = 10U; 80085be: 230a movs r3, #10 80085c0: 60fb str r3, [r7, #12] /* few cycles before setting core reset */ while (count > 0U) 80085c2: e002 b.n 80085ca { count--; 80085c4: 68fb ldr r3, [r7, #12] 80085c6: 3b01 subs r3, #1 80085c8: 60fb str r3, [r7, #12] while (count > 0U) 80085ca: 68fb ldr r3, [r7, #12] 80085cc: 2b00 cmp r3, #0 80085ce: d1f9 bne.n 80085c4 } /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 80085d0: 687b ldr r3, [r7, #4] 80085d2: 691b ldr r3, [r3, #16] 80085d4: f043 0201 orr.w r2, r3, #1 80085d8: 687b ldr r3, [r7, #4] 80085da: 611a str r2, [r3, #16] do { count++; 80085dc: 68fb ldr r3, [r7, #12] 80085de: 3301 adds r3, #1 80085e0: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80085e2: 68fb ldr r3, [r7, #12] 80085e4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80085e8: d901 bls.n 80085ee { return HAL_TIMEOUT; 80085ea: 2303 movs r3, #3 80085ec: e006 b.n 80085fc } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 80085ee: 687b ldr r3, [r7, #4] 80085f0: 691b ldr r3, [r3, #16] 80085f2: f003 0301 and.w r3, r3, #1 80085f6: 2b01 cmp r3, #1 80085f8: d0f0 beq.n 80085dc return HAL_OK; 80085fa: 2300 movs r3, #0 } 80085fc: 4618 mov r0, r3 80085fe: 3714 adds r7, #20 8008600: 46bd mov sp, r7 8008602: f85d 7b04 ldr.w r7, [sp], #4 8008606: 4770 bx lr 08008608 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008608: b580 push {r7, lr} 800860a: b084 sub sp, #16 800860c: af00 add r7, sp, #0 800860e: 6078 str r0, [r7, #4] 8008610: 460b mov r3, r1 8008612: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_HID_HandleTypeDef *hhid; hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); 8008614: 2010 movs r0, #16 8008616: f002 f9e3 bl 800a9e0 800861a: 60f8 str r0, [r7, #12] if (hhid == NULL) 800861c: 68fb ldr r3, [r7, #12] 800861e: 2b00 cmp r3, #0 8008620: d109 bne.n 8008636 { pdev->pClassDataCmsit[pdev->classId] = NULL; 8008622: 687b ldr r3, [r7, #4] 8008624: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008628: 687b ldr r3, [r7, #4] 800862a: 32b0 adds r2, #176 @ 0xb0 800862c: 2100 movs r1, #0 800862e: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 8008632: 2302 movs r3, #2 8008634: e048 b.n 80086c8 } pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; 8008636: 687b ldr r3, [r7, #4] 8008638: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800863c: 687b ldr r3, [r7, #4] 800863e: 32b0 adds r2, #176 @ 0xb0 8008640: 68f9 ldr r1, [r7, #12] 8008642: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 8008646: 687b ldr r3, [r7, #4] 8008648: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800864c: 687b ldr r3, [r7, #4] 800864e: 32b0 adds r2, #176 @ 0xb0 8008650: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8008654: 687b ldr r3, [r7, #4] 8008656: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 800865a: 687b ldr r3, [r7, #4] 800865c: 7c1b ldrb r3, [r3, #16] 800865e: 2b00 cmp r3, #0 8008660: d10d bne.n 800867e { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; 8008662: 4b1b ldr r3, [pc, #108] @ (80086d0 ) 8008664: 781b ldrb r3, [r3, #0] 8008666: f003 020f and.w r2, r3, #15 800866a: 6879 ldr r1, [r7, #4] 800866c: 4613 mov r3, r2 800866e: 009b lsls r3, r3, #2 8008670: 4413 add r3, r2 8008672: 009b lsls r3, r3, #2 8008674: 440b add r3, r1 8008676: 331c adds r3, #28 8008678: 2207 movs r2, #7 800867a: 601a str r2, [r3, #0] 800867c: e00c b.n 8008698 } else /* LOW and FULL-speed endpoints */ { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; 800867e: 4b14 ldr r3, [pc, #80] @ (80086d0 ) 8008680: 781b ldrb r3, [r3, #0] 8008682: f003 020f and.w r2, r3, #15 8008686: 6879 ldr r1, [r7, #4] 8008688: 4613 mov r3, r2 800868a: 009b lsls r3, r3, #2 800868c: 4413 add r3, r2 800868e: 009b lsls r3, r3, #2 8008690: 440b add r3, r1 8008692: 331c adds r3, #28 8008694: 220a movs r2, #10 8008696: 601a str r2, [r3, #0] } /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); 8008698: 4b0d ldr r3, [pc, #52] @ (80086d0 ) 800869a: 7819 ldrb r1, [r3, #0] 800869c: 230e movs r3, #14 800869e: 2203 movs r2, #3 80086a0: 6878 ldr r0, [r7, #4] 80086a2: f002 f83e bl 800a722 pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; 80086a6: 4b0a ldr r3, [pc, #40] @ (80086d0 ) 80086a8: 781b ldrb r3, [r3, #0] 80086aa: f003 020f and.w r2, r3, #15 80086ae: 6879 ldr r1, [r7, #4] 80086b0: 4613 mov r3, r2 80086b2: 009b lsls r3, r3, #2 80086b4: 4413 add r3, r2 80086b6: 009b lsls r3, r3, #2 80086b8: 440b add r3, r1 80086ba: 3323 adds r3, #35 @ 0x23 80086bc: 2201 movs r2, #1 80086be: 701a strb r2, [r3, #0] hhid->state = USBD_HID_IDLE; 80086c0: 68fb ldr r3, [r7, #12] 80086c2: 2200 movs r2, #0 80086c4: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 80086c6: 2300 movs r3, #0 } 80086c8: 4618 mov r0, r3 80086ca: 3710 adds r7, #16 80086cc: 46bd mov sp, r7 80086ce: bd80 pop {r7, pc} 80086d0: 2000013d .word 0x2000013d 080086d4 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80086d4: b580 push {r7, lr} 80086d6: b082 sub sp, #8 80086d8: af00 add r7, sp, #0 80086da: 6078 str r0, [r7, #4] 80086dc: 460b mov r3, r1 80086de: 70fb strb r3, [r7, #3] /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close HID EPs */ (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); 80086e0: 4b1f ldr r3, [pc, #124] @ (8008760 ) 80086e2: 781b ldrb r3, [r3, #0] 80086e4: 4619 mov r1, r3 80086e6: 6878 ldr r0, [r7, #4] 80086e8: f002 f841 bl 800a76e pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; 80086ec: 4b1c ldr r3, [pc, #112] @ (8008760 ) 80086ee: 781b ldrb r3, [r3, #0] 80086f0: f003 020f and.w r2, r3, #15 80086f4: 6879 ldr r1, [r7, #4] 80086f6: 4613 mov r3, r2 80086f8: 009b lsls r3, r3, #2 80086fa: 4413 add r3, r2 80086fc: 009b lsls r3, r3, #2 80086fe: 440b add r3, r1 8008700: 3323 adds r3, #35 @ 0x23 8008702: 2200 movs r2, #0 8008704: 701a strb r2, [r3, #0] pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; 8008706: 4b16 ldr r3, [pc, #88] @ (8008760 ) 8008708: 781b ldrb r3, [r3, #0] 800870a: f003 020f and.w r2, r3, #15 800870e: 6879 ldr r1, [r7, #4] 8008710: 4613 mov r3, r2 8008712: 009b lsls r3, r3, #2 8008714: 4413 add r3, r2 8008716: 009b lsls r3, r3, #2 8008718: 440b add r3, r1 800871a: 331c adds r3, #28 800871c: 2200 movs r2, #0 800871e: 601a str r2, [r3, #0] /* Free allocated memory */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 8008720: 687b ldr r3, [r7, #4] 8008722: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008726: 687b ldr r3, [r7, #4] 8008728: 32b0 adds r2, #176 @ 0xb0 800872a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800872e: 2b00 cmp r3, #0 8008730: d011 beq.n 8008756 { (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 8008732: 687b ldr r3, [r7, #4] 8008734: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008738: 687b ldr r3, [r7, #4] 800873a: 32b0 adds r2, #176 @ 0xb0 800873c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008740: 4618 mov r0, r3 8008742: f002 f95b bl 800a9fc pdev->pClassDataCmsit[pdev->classId] = NULL; 8008746: 687b ldr r3, [r7, #4] 8008748: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800874c: 687b ldr r3, [r7, #4] 800874e: 32b0 adds r2, #176 @ 0xb0 8008750: 2100 movs r1, #0 8008752: f843 1022 str.w r1, [r3, r2, lsl #2] } return (uint8_t)USBD_OK; 8008756: 2300 movs r3, #0 } 8008758: 4618 mov r0, r3 800875a: 3708 adds r7, #8 800875c: 46bd mov sp, r7 800875e: bd80 pop {r7, pc} 8008760: 2000013d .word 0x2000013d 08008764 : * @param pdev: instance * @param req: usb requests * @retval status */ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008764: b580 push {r7, lr} 8008766: b086 sub sp, #24 8008768: af00 add r7, sp, #0 800876a: 6078 str r0, [r7, #4] 800876c: 6039 str r1, [r7, #0] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 800876e: 687b ldr r3, [r7, #4] 8008770: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008774: 687b ldr r3, [r7, #4] 8008776: 32b0 adds r2, #176 @ 0xb0 8008778: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800877c: 60fb str r3, [r7, #12] USBD_StatusTypeDef ret = USBD_OK; 800877e: 2300 movs r3, #0 8008780: 75fb strb r3, [r7, #23] uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; 8008782: 2300 movs r3, #0 8008784: 817b strh r3, [r7, #10] if (hhid == NULL) 8008786: 68fb ldr r3, [r7, #12] 8008788: 2b00 cmp r3, #0 800878a: d101 bne.n 8008790 { return (uint8_t)USBD_FAIL; 800878c: 2303 movs r3, #3 800878e: e0e8 b.n 8008962 } switch (req->bmRequest & USB_REQ_TYPE_MASK) 8008790: 683b ldr r3, [r7, #0] 8008792: 781b ldrb r3, [r3, #0] 8008794: f003 0360 and.w r3, r3, #96 @ 0x60 8008798: 2b00 cmp r3, #0 800879a: d046 beq.n 800882a 800879c: 2b20 cmp r3, #32 800879e: f040 80d8 bne.w 8008952 { case USB_REQ_TYPE_CLASS : switch (req->bRequest) 80087a2: 683b ldr r3, [r7, #0] 80087a4: 785b ldrb r3, [r3, #1] 80087a6: 3b02 subs r3, #2 80087a8: 2b09 cmp r3, #9 80087aa: d836 bhi.n 800881a 80087ac: a201 add r2, pc, #4 @ (adr r2, 80087b4 ) 80087ae: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80087b2: bf00 nop 80087b4: 0800880b .word 0x0800880b 80087b8: 080087eb .word 0x080087eb 80087bc: 0800881b .word 0x0800881b 80087c0: 0800881b .word 0x0800881b 80087c4: 0800881b .word 0x0800881b 80087c8: 0800881b .word 0x0800881b 80087cc: 0800881b .word 0x0800881b 80087d0: 0800881b .word 0x0800881b 80087d4: 080087f9 .word 0x080087f9 80087d8: 080087dd .word 0x080087dd { case USBD_HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); 80087dc: 683b ldr r3, [r7, #0] 80087de: 885b ldrh r3, [r3, #2] 80087e0: b2db uxtb r3, r3 80087e2: 461a mov r2, r3 80087e4: 68fb ldr r3, [r7, #12] 80087e6: 601a str r2, [r3, #0] break; 80087e8: e01e b.n 8008828 case USBD_HID_REQ_GET_PROTOCOL: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); 80087ea: 68fb ldr r3, [r7, #12] 80087ec: 2201 movs r2, #1 80087ee: 4619 mov r1, r3 80087f0: 6878 ldr r0, [r7, #4] 80087f2: f001 fc25 bl 800a040 break; 80087f6: e017 b.n 8008828 case USBD_HID_REQ_SET_IDLE: hhid->IdleState = (uint8_t)(req->wValue >> 8); 80087f8: 683b ldr r3, [r7, #0] 80087fa: 885b ldrh r3, [r3, #2] 80087fc: 0a1b lsrs r3, r3, #8 80087fe: b29b uxth r3, r3 8008800: b2db uxtb r3, r3 8008802: 461a mov r2, r3 8008804: 68fb ldr r3, [r7, #12] 8008806: 605a str r2, [r3, #4] break; 8008808: e00e b.n 8008828 case USBD_HID_REQ_GET_IDLE: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); 800880a: 68fb ldr r3, [r7, #12] 800880c: 3304 adds r3, #4 800880e: 2201 movs r2, #1 8008810: 4619 mov r1, r3 8008812: 6878 ldr r0, [r7, #4] 8008814: f001 fc14 bl 800a040 break; 8008818: e006 b.n 8008828 default: USBD_CtlError(pdev, req); 800881a: 6839 ldr r1, [r7, #0] 800881c: 6878 ldr r0, [r7, #4] 800881e: f001 fb92 bl 8009f46 ret = USBD_FAIL; 8008822: 2303 movs r3, #3 8008824: 75fb strb r3, [r7, #23] break; 8008826: bf00 nop } break; 8008828: e09a b.n 8008960 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800882a: 683b ldr r3, [r7, #0] 800882c: 785b ldrb r3, [r3, #1] 800882e: 2b0b cmp r3, #11 8008830: f200 8086 bhi.w 8008940 8008834: a201 add r2, pc, #4 @ (adr r2, 800883c ) 8008836: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800883a: bf00 nop 800883c: 0800886d .word 0x0800886d 8008840: 0800894f .word 0x0800894f 8008844: 08008941 .word 0x08008941 8008848: 08008941 .word 0x08008941 800884c: 08008941 .word 0x08008941 8008850: 08008941 .word 0x08008941 8008854: 08008897 .word 0x08008897 8008858: 08008941 .word 0x08008941 800885c: 08008941 .word 0x08008941 8008860: 08008941 .word 0x08008941 8008864: 080088ef .word 0x080088ef 8008868: 08008919 .word 0x08008919 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 800886c: 687b ldr r3, [r7, #4] 800886e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008872: b2db uxtb r3, r3 8008874: 2b03 cmp r3, #3 8008876: d107 bne.n 8008888 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 8008878: f107 030a add.w r3, r7, #10 800887c: 2202 movs r2, #2 800887e: 4619 mov r1, r3 8008880: 6878 ldr r0, [r7, #4] 8008882: f001 fbdd bl 800a040 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008886: e063 b.n 8008950 USBD_CtlError(pdev, req); 8008888: 6839 ldr r1, [r7, #0] 800888a: 6878 ldr r0, [r7, #4] 800888c: f001 fb5b bl 8009f46 ret = USBD_FAIL; 8008890: 2303 movs r3, #3 8008892: 75fb strb r3, [r7, #23] break; 8008894: e05c b.n 8008950 case USB_REQ_GET_DESCRIPTOR: if ((req->wValue >> 8) == HID_REPORT_DESC) 8008896: 683b ldr r3, [r7, #0] 8008898: 885b ldrh r3, [r3, #2] 800889a: 0a1b lsrs r3, r3, #8 800889c: b29b uxth r3, r3 800889e: 2b22 cmp r3, #34 @ 0x22 80088a0: d108 bne.n 80088b4 { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); 80088a2: 683b ldr r3, [r7, #0] 80088a4: 88db ldrh r3, [r3, #6] 80088a6: 2b2d cmp r3, #45 @ 0x2d 80088a8: bf28 it cs 80088aa: 232d movcs r3, #45 @ 0x2d 80088ac: 82bb strh r3, [r7, #20] pbuf = HID_MOUSE_ReportDesc; 80088ae: 4b2f ldr r3, [pc, #188] @ (800896c ) 80088b0: 613b str r3, [r7, #16] 80088b2: e015 b.n 80088e0 } else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) 80088b4: 683b ldr r3, [r7, #0] 80088b6: 885b ldrh r3, [r3, #2] 80088b8: 0a1b lsrs r3, r3, #8 80088ba: b29b uxth r3, r3 80088bc: 2b21 cmp r3, #33 @ 0x21 80088be: d108 bne.n 80088d2 { pbuf = USBD_HID_Desc; 80088c0: 4b2b ldr r3, [pc, #172] @ (8008970 ) 80088c2: 613b str r3, [r7, #16] len = MIN(USB_HID_DESC_SIZ, req->wLength); 80088c4: 683b ldr r3, [r7, #0] 80088c6: 88db ldrh r3, [r3, #6] 80088c8: 2b09 cmp r3, #9 80088ca: bf28 it cs 80088cc: 2309 movcs r3, #9 80088ce: 82bb strh r3, [r7, #20] 80088d0: e006 b.n 80088e0 } else { USBD_CtlError(pdev, req); 80088d2: 6839 ldr r1, [r7, #0] 80088d4: 6878 ldr r0, [r7, #4] 80088d6: f001 fb36 bl 8009f46 ret = USBD_FAIL; 80088da: 2303 movs r3, #3 80088dc: 75fb strb r3, [r7, #23] break; 80088de: e037 b.n 8008950 } (void)USBD_CtlSendData(pdev, pbuf, len); 80088e0: 8abb ldrh r3, [r7, #20] 80088e2: 461a mov r2, r3 80088e4: 6939 ldr r1, [r7, #16] 80088e6: 6878 ldr r0, [r7, #4] 80088e8: f001 fbaa bl 800a040 break; 80088ec: e030 b.n 8008950 case USB_REQ_GET_INTERFACE : if (pdev->dev_state == USBD_STATE_CONFIGURED) 80088ee: 687b ldr r3, [r7, #4] 80088f0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80088f4: b2db uxtb r3, r3 80088f6: 2b03 cmp r3, #3 80088f8: d107 bne.n 800890a { (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); 80088fa: 68fb ldr r3, [r7, #12] 80088fc: 3308 adds r3, #8 80088fe: 2201 movs r2, #1 8008900: 4619 mov r1, r3 8008902: 6878 ldr r0, [r7, #4] 8008904: f001 fb9c bl 800a040 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008908: e022 b.n 8008950 USBD_CtlError(pdev, req); 800890a: 6839 ldr r1, [r7, #0] 800890c: 6878 ldr r0, [r7, #4] 800890e: f001 fb1a bl 8009f46 ret = USBD_FAIL; 8008912: 2303 movs r3, #3 8008914: 75fb strb r3, [r7, #23] break; 8008916: e01b b.n 8008950 case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008918: 687b ldr r3, [r7, #4] 800891a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800891e: b2db uxtb r3, r3 8008920: 2b03 cmp r3, #3 8008922: d106 bne.n 8008932 { hhid->AltSetting = (uint8_t)(req->wValue); 8008924: 683b ldr r3, [r7, #0] 8008926: 885b ldrh r3, [r3, #2] 8008928: b2db uxtb r3, r3 800892a: 461a mov r2, r3 800892c: 68fb ldr r3, [r7, #12] 800892e: 609a str r2, [r3, #8] else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008930: e00e b.n 8008950 USBD_CtlError(pdev, req); 8008932: 6839 ldr r1, [r7, #0] 8008934: 6878 ldr r0, [r7, #4] 8008936: f001 fb06 bl 8009f46 ret = USBD_FAIL; 800893a: 2303 movs r3, #3 800893c: 75fb strb r3, [r7, #23] break; 800893e: e007 b.n 8008950 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 8008940: 6839 ldr r1, [r7, #0] 8008942: 6878 ldr r0, [r7, #4] 8008944: f001 faff bl 8009f46 ret = USBD_FAIL; 8008948: 2303 movs r3, #3 800894a: 75fb strb r3, [r7, #23] break; 800894c: e000 b.n 8008950 break; 800894e: bf00 nop } break; 8008950: e006 b.n 8008960 default: USBD_CtlError(pdev, req); 8008952: 6839 ldr r1, [r7, #0] 8008954: 6878 ldr r0, [r7, #4] 8008956: f001 faf6 bl 8009f46 ret = USBD_FAIL; 800895a: 2303 movs r3, #3 800895c: 75fb strb r3, [r7, #23] break; 800895e: bf00 nop } return (uint8_t)ret; 8008960: 7dfb ldrb r3, [r7, #23] } 8008962: 4618 mov r0, r3 8008964: 3718 adds r7, #24 8008966: 46bd mov sp, r7 8008968: bd80 pop {r7, pc} 800896a: bf00 nop 800896c: 20000110 .word 0x20000110 8008970: 200000f8 .word 0x200000f8 08008974 : uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) { USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { 8008974: b580 push {r7, lr} 8008976: b086 sub sp, #24 8008978: af00 add r7, sp, #0 800897a: 60f8 str r0, [r7, #12] 800897c: 60b9 str r1, [r7, #8] 800897e: 4613 mov r3, r2 8008980: 80fb strh r3, [r7, #6] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8008982: 68fb ldr r3, [r7, #12] 8008984: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008988: 68fb ldr r3, [r7, #12] 800898a: 32b0 adds r2, #176 @ 0xb0 800898c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008990: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hhid == NULL) 8008992: 697b ldr r3, [r7, #20] 8008994: 2b00 cmp r3, #0 8008996: d101 bne.n 800899c { return (uint8_t)USBD_FAIL; 8008998: 2303 movs r3, #3 800899a: e014 b.n 80089c6 #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 800899c: 68fb ldr r3, [r7, #12] 800899e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80089a2: b2db uxtb r3, r3 80089a4: 2b03 cmp r3, #3 80089a6: d10d bne.n 80089c4 { if (hhid->state == USBD_HID_IDLE) 80089a8: 697b ldr r3, [r7, #20] 80089aa: 7b1b ldrb r3, [r3, #12] 80089ac: 2b00 cmp r3, #0 80089ae: d109 bne.n 80089c4 { hhid->state = USBD_HID_BUSY; 80089b0: 697b ldr r3, [r7, #20] 80089b2: 2201 movs r2, #1 80089b4: 731a strb r2, [r3, #12] (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); 80089b6: 4b06 ldr r3, [pc, #24] @ (80089d0 ) 80089b8: 7819 ldrb r1, [r3, #0] 80089ba: 88fb ldrh r3, [r7, #6] 80089bc: 68ba ldr r2, [r7, #8] 80089be: 68f8 ldr r0, [r7, #12] 80089c0: f001 ff7d bl 800a8be } } return (uint8_t)USBD_OK; 80089c4: 2300 movs r3, #0 } 80089c6: 4618 mov r0, r3 80089c8: 3718 adds r7, #24 80089ca: 46bd mov sp, r7 80089cc: bd80 pop {r7, pc} 80089ce: bf00 nop 80089d0: 2000013d .word 0x2000013d 080089d4 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { 80089d4: b580 push {r7, lr} 80089d6: b084 sub sp, #16 80089d8: af00 add r7, sp, #0 80089da: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80089dc: 2181 movs r1, #129 @ 0x81 80089de: 4809 ldr r0, [pc, #36] @ (8008a04 ) 80089e0: f000 fc4e bl 8009280 80089e4: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80089e6: 68fb ldr r3, [r7, #12] 80089e8: 2b00 cmp r3, #0 80089ea: d002 beq.n 80089f2 { pEpDesc->bInterval = HID_FS_BINTERVAL; 80089ec: 68fb ldr r3, [r7, #12] 80089ee: 220a movs r2, #10 80089f0: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80089f2: 687b ldr r3, [r7, #4] 80089f4: 2222 movs r2, #34 @ 0x22 80089f6: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 80089f8: 4b02 ldr r3, [pc, #8] @ (8008a04 ) } 80089fa: 4618 mov r0, r3 80089fc: 3710 adds r7, #16 80089fe: 46bd mov sp, r7 8008a00: bd80 pop {r7, pc} 8008a02: bf00 nop 8008a04: 200000d4 .word 0x200000d4 08008a08 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { 8008a08: b580 push {r7, lr} 8008a0a: b084 sub sp, #16 8008a0c: af00 add r7, sp, #0 8008a0e: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008a10: 2181 movs r1, #129 @ 0x81 8008a12: 4809 ldr r0, [pc, #36] @ (8008a38 ) 8008a14: f000 fc34 bl 8009280 8008a18: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8008a1a: 68fb ldr r3, [r7, #12] 8008a1c: 2b00 cmp r3, #0 8008a1e: d002 beq.n 8008a26 { pEpDesc->bInterval = HID_HS_BINTERVAL; 8008a20: 68fb ldr r3, [r7, #12] 8008a22: 2207 movs r2, #7 8008a24: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008a26: 687b ldr r3, [r7, #4] 8008a28: 2222 movs r2, #34 @ 0x22 8008a2a: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008a2c: 4b02 ldr r3, [pc, #8] @ (8008a38 ) } 8008a2e: 4618 mov r0, r3 8008a30: 3710 adds r7, #16 8008a32: 46bd mov sp, r7 8008a34: bd80 pop {r7, pc} 8008a36: bf00 nop 8008a38: 200000d4 .word 0x200000d4 08008a3c : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { 8008a3c: b580 push {r7, lr} 8008a3e: b084 sub sp, #16 8008a40: af00 add r7, sp, #0 8008a42: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008a44: 2181 movs r1, #129 @ 0x81 8008a46: 4809 ldr r0, [pc, #36] @ (8008a6c ) 8008a48: f000 fc1a bl 8009280 8008a4c: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8008a4e: 68fb ldr r3, [r7, #12] 8008a50: 2b00 cmp r3, #0 8008a52: d002 beq.n 8008a5a { pEpDesc->bInterval = HID_FS_BINTERVAL; 8008a54: 68fb ldr r3, [r7, #12] 8008a56: 220a movs r2, #10 8008a58: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008a5a: 687b ldr r3, [r7, #4] 8008a5c: 2222 movs r2, #34 @ 0x22 8008a5e: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008a60: 4b02 ldr r3, [pc, #8] @ (8008a6c ) } 8008a62: 4618 mov r0, r3 8008a64: 3710 adds r7, #16 8008a66: 46bd mov sp, r7 8008a68: bd80 pop {r7, pc} 8008a6a: bf00 nop 8008a6c: 200000d4 .word 0x200000d4 08008a70 : * @param pdev: device instance * @param epnum: endpoint index * @retval status */ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008a70: b480 push {r7} 8008a72: b083 sub sp, #12 8008a74: af00 add r7, sp, #0 8008a76: 6078 str r0, [r7, #4] 8008a78: 460b mov r3, r1 8008a7a: 70fb strb r3, [r7, #3] UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; 8008a7c: 687b ldr r3, [r7, #4] 8008a7e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008a82: 687b ldr r3, [r7, #4] 8008a84: 32b0 adds r2, #176 @ 0xb0 8008a86: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008a8a: 2200 movs r2, #0 8008a8c: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 8008a8e: 2300 movs r3, #0 } 8008a90: 4618 mov r0, r3 8008a92: 370c adds r7, #12 8008a94: 46bd mov sp, r7 8008a96: f85d 7b04 ldr.w r7, [sp], #4 8008a9a: 4770 bx lr 08008a9c : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { 8008a9c: b480 push {r7} 8008a9e: b083 sub sp, #12 8008aa0: af00 add r7, sp, #0 8008aa2: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); 8008aa4: 687b ldr r3, [r7, #4] 8008aa6: 220a movs r2, #10 8008aa8: 801a strh r2, [r3, #0] return USBD_HID_DeviceQualifierDesc; 8008aaa: 4b03 ldr r3, [pc, #12] @ (8008ab8 ) } 8008aac: 4618 mov r0, r3 8008aae: 370c adds r7, #12 8008ab0: 46bd mov sp, r7 8008ab2: f85d 7b04 ldr.w r7, [sp], #4 8008ab6: 4770 bx lr 8008ab8: 20000104 .word 0x20000104 08008abc : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 8008abc: b580 push {r7, lr} 8008abe: b086 sub sp, #24 8008ac0: af00 add r7, sp, #0 8008ac2: 60f8 str r0, [r7, #12] 8008ac4: 60b9 str r1, [r7, #8] 8008ac6: 4613 mov r3, r2 8008ac8: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 8008aca: 68fb ldr r3, [r7, #12] 8008acc: 2b00 cmp r3, #0 8008ace: d101 bne.n 8008ad4 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8008ad0: 2303 movs r3, #3 8008ad2: e01f b.n 8008b14 pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 8008ad4: 68fb ldr r3, [r7, #12] 8008ad6: 2200 movs r2, #0 8008ad8: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 8008adc: 68fb ldr r3, [r7, #12] 8008ade: 2200 movs r2, #0 8008ae0: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 8008ae4: 68fb ldr r3, [r7, #12] 8008ae6: 2200 movs r2, #0 8008ae8: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 8008aec: 68bb ldr r3, [r7, #8] 8008aee: 2b00 cmp r3, #0 8008af0: d003 beq.n 8008afa { pdev->pDesc = pdesc; 8008af2: 68fb ldr r3, [r7, #12] 8008af4: 68ba ldr r2, [r7, #8] 8008af6: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 8008afa: 68fb ldr r3, [r7, #12] 8008afc: 2201 movs r2, #1 8008afe: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 8008b02: 68fb ldr r3, [r7, #12] 8008b04: 79fa ldrb r2, [r7, #7] 8008b06: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8008b08: 68f8 ldr r0, [r7, #12] 8008b0a: f001 fda3 bl 800a654 8008b0e: 4603 mov r3, r0 8008b10: 75fb strb r3, [r7, #23] return ret; 8008b12: 7dfb ldrb r3, [r7, #23] } 8008b14: 4618 mov r0, r3 8008b16: 3718 adds r7, #24 8008b18: 46bd mov sp, r7 8008b1a: bd80 pop {r7, pc} 08008b1c : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 8008b1c: b580 push {r7, lr} 8008b1e: b084 sub sp, #16 8008b20: af00 add r7, sp, #0 8008b22: 6078 str r0, [r7, #4] 8008b24: 6039 str r1, [r7, #0] uint16_t len = 0U; 8008b26: 2300 movs r3, #0 8008b28: 81fb strh r3, [r7, #14] if (pclass == NULL) 8008b2a: 683b ldr r3, [r7, #0] 8008b2c: 2b00 cmp r3, #0 8008b2e: d101 bne.n 8008b34 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8008b30: 2303 movs r3, #3 8008b32: e025 b.n 8008b80 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 8008b34: 687b ldr r3, [r7, #4] 8008b36: 683a ldr r2, [r7, #0] 8008b38: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 8008b3c: 687b ldr r3, [r7, #4] 8008b3e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b42: 687b ldr r3, [r7, #4] 8008b44: 32ae adds r2, #174 @ 0xae 8008b46: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b4a: 6adb ldr r3, [r3, #44] @ 0x2c 8008b4c: 2b00 cmp r3, #0 8008b4e: d00f beq.n 8008b70 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 8008b50: 687b ldr r3, [r7, #4] 8008b52: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b56: 687b ldr r3, [r7, #4] 8008b58: 32ae adds r2, #174 @ 0xae 8008b5a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b5e: 6adb ldr r3, [r3, #44] @ 0x2c 8008b60: f107 020e add.w r2, r7, #14 8008b64: 4610 mov r0, r2 8008b66: 4798 blx r3 8008b68: 4602 mov r2, r0 8008b6a: 687b ldr r3, [r7, #4] 8008b6c: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 8008b70: 687b ldr r3, [r7, #4] 8008b72: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8008b76: 1c5a adds r2, r3, #1 8008b78: 687b ldr r3, [r7, #4] 8008b7a: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 8008b7e: 2300 movs r3, #0 } 8008b80: 4618 mov r0, r3 8008b82: 3710 adds r7, #16 8008b84: 46bd mov sp, r7 8008b86: bd80 pop {r7, pc} 08008b88 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8008b88: b580 push {r7, lr} 8008b8a: b082 sub sp, #8 8008b8c: af00 add r7, sp, #0 8008b8e: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 8008b90: 6878 ldr r0, [r7, #4] 8008b92: f001 fdab bl 800a6ec 8008b96: 4603 mov r3, r0 } 8008b98: 4618 mov r0, r3 8008b9a: 3708 adds r7, #8 8008b9c: 46bd mov sp, r7 8008b9e: bd80 pop {r7, pc} 08008ba0 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8008ba0: b480 push {r7} 8008ba2: b083 sub sp, #12 8008ba4: af00 add r7, sp, #0 8008ba6: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8008ba8: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 8008baa: 4618 mov r0, r3 8008bac: 370c adds r7, #12 8008bae: 46bd mov sp, r7 8008bb0: f85d 7b04 ldr.w r7, [sp], #4 8008bb4: 4770 bx lr 08008bb6 : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008bb6: b580 push {r7, lr} 8008bb8: b084 sub sp, #16 8008bba: af00 add r7, sp, #0 8008bbc: 6078 str r0, [r7, #4] 8008bbe: 460b mov r3, r1 8008bc0: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008bc2: 2300 movs r3, #0 8008bc4: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 8008bc6: 687b ldr r3, [r7, #4] 8008bc8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008bcc: 2b00 cmp r3, #0 8008bce: d009 beq.n 8008be4 { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 8008bd0: 687b ldr r3, [r7, #4] 8008bd2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008bd6: 681b ldr r3, [r3, #0] 8008bd8: 78fa ldrb r2, [r7, #3] 8008bda: 4611 mov r1, r2 8008bdc: 6878 ldr r0, [r7, #4] 8008bde: 4798 blx r3 8008be0: 4603 mov r3, r0 8008be2: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008be4: 7bfb ldrb r3, [r7, #15] } 8008be6: 4618 mov r0, r3 8008be8: 3710 adds r7, #16 8008bea: 46bd mov sp, r7 8008bec: bd80 pop {r7, pc} 08008bee : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008bee: b580 push {r7, lr} 8008bf0: b084 sub sp, #16 8008bf2: af00 add r7, sp, #0 8008bf4: 6078 str r0, [r7, #4] 8008bf6: 460b mov r3, r1 8008bf8: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008bfa: 2300 movs r3, #0 8008bfc: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 8008bfe: 687b ldr r3, [r7, #4] 8008c00: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008c04: 685b ldr r3, [r3, #4] 8008c06: 78fa ldrb r2, [r7, #3] 8008c08: 4611 mov r1, r2 8008c0a: 6878 ldr r0, [r7, #4] 8008c0c: 4798 blx r3 8008c0e: 4603 mov r3, r0 8008c10: 2b00 cmp r3, #0 8008c12: d001 beq.n 8008c18 { ret = USBD_FAIL; 8008c14: 2303 movs r3, #3 8008c16: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008c18: 7bfb ldrb r3, [r7, #15] } 8008c1a: 4618 mov r0, r3 8008c1c: 3710 adds r7, #16 8008c1e: 46bd mov sp, r7 8008c20: bd80 pop {r7, pc} 08008c22 : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 8008c22: b580 push {r7, lr} 8008c24: b084 sub sp, #16 8008c26: af00 add r7, sp, #0 8008c28: 6078 str r0, [r7, #4] 8008c2a: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 8008c2c: 687b ldr r3, [r7, #4] 8008c2e: f203 23aa addw r3, r3, #682 @ 0x2aa 8008c32: 6839 ldr r1, [r7, #0] 8008c34: 4618 mov r0, r3 8008c36: f001 f94c bl 8009ed2 pdev->ep0_state = USBD_EP0_SETUP; 8008c3a: 687b ldr r3, [r7, #4] 8008c3c: 2201 movs r2, #1 8008c3e: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 8008c42: 687b ldr r3, [r7, #4] 8008c44: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 8008c48: 461a mov r2, r3 8008c4a: 687b ldr r3, [r7, #4] 8008c4c: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 8008c50: 687b ldr r3, [r7, #4] 8008c52: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008c56: f003 031f and.w r3, r3, #31 8008c5a: 2b02 cmp r3, #2 8008c5c: d01a beq.n 8008c94 8008c5e: 2b02 cmp r3, #2 8008c60: d822 bhi.n 8008ca8 8008c62: 2b00 cmp r3, #0 8008c64: d002 beq.n 8008c6c 8008c66: 2b01 cmp r3, #1 8008c68: d00a beq.n 8008c80 8008c6a: e01d b.n 8008ca8 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8008c6c: 687b ldr r3, [r7, #4] 8008c6e: f203 23aa addw r3, r3, #682 @ 0x2aa 8008c72: 4619 mov r1, r3 8008c74: 6878 ldr r0, [r7, #4] 8008c76: f000 fb77 bl 8009368 8008c7a: 4603 mov r3, r0 8008c7c: 73fb strb r3, [r7, #15] break; 8008c7e: e020 b.n 8008cc2 case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8008c80: 687b ldr r3, [r7, #4] 8008c82: f203 23aa addw r3, r3, #682 @ 0x2aa 8008c86: 4619 mov r1, r3 8008c88: 6878 ldr r0, [r7, #4] 8008c8a: f000 fbdf bl 800944c 8008c8e: 4603 mov r3, r0 8008c90: 73fb strb r3, [r7, #15] break; 8008c92: e016 b.n 8008cc2 case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8008c94: 687b ldr r3, [r7, #4] 8008c96: f203 23aa addw r3, r3, #682 @ 0x2aa 8008c9a: 4619 mov r1, r3 8008c9c: 6878 ldr r0, [r7, #4] 8008c9e: f000 fc41 bl 8009524 8008ca2: 4603 mov r3, r0 8008ca4: 73fb strb r3, [r7, #15] break; 8008ca6: e00c b.n 8008cc2 default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8008ca8: 687b ldr r3, [r7, #4] 8008caa: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008cae: f023 037f bic.w r3, r3, #127 @ 0x7f 8008cb2: b2db uxtb r3, r3 8008cb4: 4619 mov r1, r3 8008cb6: 6878 ldr r0, [r7, #4] 8008cb8: f001 fd78 bl 800a7ac 8008cbc: 4603 mov r3, r0 8008cbe: 73fb strb r3, [r7, #15] break; 8008cc0: bf00 nop } return ret; 8008cc2: 7bfb ldrb r3, [r7, #15] } 8008cc4: 4618 mov r0, r3 8008cc6: 3710 adds r7, #16 8008cc8: 46bd mov sp, r7 8008cca: bd80 pop {r7, pc} 08008ccc : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008ccc: b580 push {r7, lr} 8008cce: b086 sub sp, #24 8008cd0: af00 add r7, sp, #0 8008cd2: 60f8 str r0, [r7, #12] 8008cd4: 460b mov r3, r1 8008cd6: 607a str r2, [r7, #4] 8008cd8: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 8008cda: 2300 movs r3, #0 8008cdc: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008cde: 7afb ldrb r3, [r7, #11] 8008ce0: 2b00 cmp r3, #0 8008ce2: d177 bne.n 8008dd4 { pep = &pdev->ep_out[0]; 8008ce4: 68fb ldr r3, [r7, #12] 8008ce6: f503 73aa add.w r3, r3, #340 @ 0x154 8008cea: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 8008cec: 68fb ldr r3, [r7, #12] 8008cee: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008cf2: 2b03 cmp r3, #3 8008cf4: f040 80a1 bne.w 8008e3a { if (pep->rem_length > pep->maxpacket) 8008cf8: 693b ldr r3, [r7, #16] 8008cfa: 685b ldr r3, [r3, #4] 8008cfc: 693a ldr r2, [r7, #16] 8008cfe: 8992 ldrh r2, [r2, #12] 8008d00: 4293 cmp r3, r2 8008d02: d91c bls.n 8008d3e { pep->rem_length -= pep->maxpacket; 8008d04: 693b ldr r3, [r7, #16] 8008d06: 685b ldr r3, [r3, #4] 8008d08: 693a ldr r2, [r7, #16] 8008d0a: 8992 ldrh r2, [r2, #12] 8008d0c: 1a9a subs r2, r3, r2 8008d0e: 693b ldr r3, [r7, #16] 8008d10: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008d12: 693b ldr r3, [r7, #16] 8008d14: 691b ldr r3, [r3, #16] 8008d16: 693a ldr r2, [r7, #16] 8008d18: 8992 ldrh r2, [r2, #12] 8008d1a: 441a add r2, r3 8008d1c: 693b ldr r3, [r7, #16] 8008d1e: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 8008d20: 693b ldr r3, [r7, #16] 8008d22: 6919 ldr r1, [r3, #16] 8008d24: 693b ldr r3, [r7, #16] 8008d26: 899b ldrh r3, [r3, #12] 8008d28: 461a mov r2, r3 8008d2a: 693b ldr r3, [r7, #16] 8008d2c: 685b ldr r3, [r3, #4] 8008d2e: 4293 cmp r3, r2 8008d30: bf38 it cc 8008d32: 4613 movcc r3, r2 8008d34: 461a mov r2, r3 8008d36: 68f8 ldr r0, [r7, #12] 8008d38: f001 f9b1 bl 800a09e 8008d3c: e07d b.n 8008e3a } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 8008d3e: 68fb ldr r3, [r7, #12] 8008d40: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008d44: f003 031f and.w r3, r3, #31 8008d48: 2b02 cmp r3, #2 8008d4a: d014 beq.n 8008d76 8008d4c: 2b02 cmp r3, #2 8008d4e: d81d bhi.n 8008d8c 8008d50: 2b00 cmp r3, #0 8008d52: d002 beq.n 8008d5a 8008d54: 2b01 cmp r3, #1 8008d56: d003 beq.n 8008d60 8008d58: e018 b.n 8008d8c { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 8008d5a: 2300 movs r3, #0 8008d5c: 75bb strb r3, [r7, #22] break; 8008d5e: e018 b.n 8008d92 case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8008d60: 68fb ldr r3, [r7, #12] 8008d62: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008d66: b2db uxtb r3, r3 8008d68: 4619 mov r1, r3 8008d6a: 68f8 ldr r0, [r7, #12] 8008d6c: f000 fa6e bl 800924c 8008d70: 4603 mov r3, r0 8008d72: 75bb strb r3, [r7, #22] break; 8008d74: e00d b.n 8008d92 case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8008d76: 68fb ldr r3, [r7, #12] 8008d78: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008d7c: b2db uxtb r3, r3 8008d7e: 4619 mov r1, r3 8008d80: 68f8 ldr r0, [r7, #12] 8008d82: f000 fa70 bl 8009266 8008d86: 4603 mov r3, r0 8008d88: 75bb strb r3, [r7, #22] break; 8008d8a: e002 b.n 8008d92 default: /* Back to the first class in case of doubt */ idx = 0U; 8008d8c: 2300 movs r3, #0 8008d8e: 75bb strb r3, [r7, #22] break; 8008d90: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 8008d92: 7dbb ldrb r3, [r7, #22] 8008d94: 2b00 cmp r3, #0 8008d96: d119 bne.n 8008dcc { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008d98: 68fb ldr r3, [r7, #12] 8008d9a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008d9e: b2db uxtb r3, r3 8008da0: 2b03 cmp r3, #3 8008da2: d113 bne.n 8008dcc { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8008da4: 7dba ldrb r2, [r7, #22] 8008da6: 68fb ldr r3, [r7, #12] 8008da8: 32ae adds r2, #174 @ 0xae 8008daa: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008dae: 691b ldr r3, [r3, #16] 8008db0: 2b00 cmp r3, #0 8008db2: d00b beq.n 8008dcc { pdev->classId = idx; 8008db4: 7dba ldrb r2, [r7, #22] 8008db6: 68fb ldr r3, [r7, #12] 8008db8: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 8008dbc: 7dba ldrb r2, [r7, #22] 8008dbe: 68fb ldr r3, [r7, #12] 8008dc0: 32ae adds r2, #174 @ 0xae 8008dc2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008dc6: 691b ldr r3, [r3, #16] 8008dc8: 68f8 ldr r0, [r7, #12] 8008dca: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 8008dcc: 68f8 ldr r0, [r7, #12] 8008dce: f001 f977 bl 800a0c0 8008dd2: e032 b.n 8008e3a } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 8008dd4: 7afb ldrb r3, [r7, #11] 8008dd6: f003 037f and.w r3, r3, #127 @ 0x7f 8008dda: b2db uxtb r3, r3 8008ddc: 4619 mov r1, r3 8008dde: 68f8 ldr r0, [r7, #12] 8008de0: f000 fa41 bl 8009266 8008de4: 4603 mov r3, r0 8008de6: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008de8: 7dbb ldrb r3, [r7, #22] 8008dea: 2bff cmp r3, #255 @ 0xff 8008dec: d025 beq.n 8008e3a 8008dee: 7dbb ldrb r3, [r7, #22] 8008df0: 2b00 cmp r3, #0 8008df2: d122 bne.n 8008e3a { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008df4: 68fb ldr r3, [r7, #12] 8008df6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008dfa: b2db uxtb r3, r3 8008dfc: 2b03 cmp r3, #3 8008dfe: d117 bne.n 8008e30 { if (pdev->pClass[idx]->DataOut != NULL) 8008e00: 7dba ldrb r2, [r7, #22] 8008e02: 68fb ldr r3, [r7, #12] 8008e04: 32ae adds r2, #174 @ 0xae 8008e06: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008e0a: 699b ldr r3, [r3, #24] 8008e0c: 2b00 cmp r3, #0 8008e0e: d00f beq.n 8008e30 { pdev->classId = idx; 8008e10: 7dba ldrb r2, [r7, #22] 8008e12: 68fb ldr r3, [r7, #12] 8008e14: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 8008e18: 7dba ldrb r2, [r7, #22] 8008e1a: 68fb ldr r3, [r7, #12] 8008e1c: 32ae adds r2, #174 @ 0xae 8008e1e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008e22: 699b ldr r3, [r3, #24] 8008e24: 7afa ldrb r2, [r7, #11] 8008e26: 4611 mov r1, r2 8008e28: 68f8 ldr r0, [r7, #12] 8008e2a: 4798 blx r3 8008e2c: 4603 mov r3, r0 8008e2e: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8008e30: 7dfb ldrb r3, [r7, #23] 8008e32: 2b00 cmp r3, #0 8008e34: d001 beq.n 8008e3a { return ret; 8008e36: 7dfb ldrb r3, [r7, #23] 8008e38: e000 b.n 8008e3c } } } return USBD_OK; 8008e3a: 2300 movs r3, #0 } 8008e3c: 4618 mov r0, r3 8008e3e: 3718 adds r7, #24 8008e40: 46bd mov sp, r7 8008e42: bd80 pop {r7, pc} 08008e44 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008e44: b580 push {r7, lr} 8008e46: b086 sub sp, #24 8008e48: af00 add r7, sp, #0 8008e4a: 60f8 str r0, [r7, #12] 8008e4c: 460b mov r3, r1 8008e4e: 607a str r2, [r7, #4] 8008e50: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008e52: 7afb ldrb r3, [r7, #11] 8008e54: 2b00 cmp r3, #0 8008e56: d178 bne.n 8008f4a { pep = &pdev->ep_in[0]; 8008e58: 68fb ldr r3, [r7, #12] 8008e5a: 3314 adds r3, #20 8008e5c: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8008e5e: 68fb ldr r3, [r7, #12] 8008e60: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008e64: 2b02 cmp r3, #2 8008e66: d163 bne.n 8008f30 { if (pep->rem_length > pep->maxpacket) 8008e68: 693b ldr r3, [r7, #16] 8008e6a: 685b ldr r3, [r3, #4] 8008e6c: 693a ldr r2, [r7, #16] 8008e6e: 8992 ldrh r2, [r2, #12] 8008e70: 4293 cmp r3, r2 8008e72: d91c bls.n 8008eae { pep->rem_length -= pep->maxpacket; 8008e74: 693b ldr r3, [r7, #16] 8008e76: 685b ldr r3, [r3, #4] 8008e78: 693a ldr r2, [r7, #16] 8008e7a: 8992 ldrh r2, [r2, #12] 8008e7c: 1a9a subs r2, r3, r2 8008e7e: 693b ldr r3, [r7, #16] 8008e80: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008e82: 693b ldr r3, [r7, #16] 8008e84: 691b ldr r3, [r3, #16] 8008e86: 693a ldr r2, [r7, #16] 8008e88: 8992 ldrh r2, [r2, #12] 8008e8a: 441a add r2, r3 8008e8c: 693b ldr r3, [r7, #16] 8008e8e: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8008e90: 693b ldr r3, [r7, #16] 8008e92: 6919 ldr r1, [r3, #16] 8008e94: 693b ldr r3, [r7, #16] 8008e96: 685b ldr r3, [r3, #4] 8008e98: 461a mov r2, r3 8008e9a: 68f8 ldr r0, [r7, #12] 8008e9c: f001 f8ee bl 800a07c /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008ea0: 2300 movs r3, #0 8008ea2: 2200 movs r2, #0 8008ea4: 2100 movs r1, #0 8008ea6: 68f8 ldr r0, [r7, #12] 8008ea8: f001 fd2a bl 800a900 8008eac: e040 b.n 8008f30 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8008eae: 693b ldr r3, [r7, #16] 8008eb0: 899b ldrh r3, [r3, #12] 8008eb2: 461a mov r2, r3 8008eb4: 693b ldr r3, [r7, #16] 8008eb6: 685b ldr r3, [r3, #4] 8008eb8: 429a cmp r2, r3 8008eba: d11c bne.n 8008ef6 (pep->total_length >= pep->maxpacket) && 8008ebc: 693b ldr r3, [r7, #16] 8008ebe: 681b ldr r3, [r3, #0] 8008ec0: 693a ldr r2, [r7, #16] 8008ec2: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 8008ec4: 4293 cmp r3, r2 8008ec6: d316 bcc.n 8008ef6 (pep->total_length < pdev->ep0_data_len)) 8008ec8: 693b ldr r3, [r7, #16] 8008eca: 681a ldr r2, [r3, #0] 8008ecc: 68fb ldr r3, [r7, #12] 8008ece: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 8008ed2: 429a cmp r2, r3 8008ed4: d20f bcs.n 8008ef6 { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8008ed6: 2200 movs r2, #0 8008ed8: 2100 movs r1, #0 8008eda: 68f8 ldr r0, [r7, #12] 8008edc: f001 f8ce bl 800a07c pdev->ep0_data_len = 0U; 8008ee0: 68fb ldr r3, [r7, #12] 8008ee2: 2200 movs r2, #0 8008ee4: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008ee8: 2300 movs r3, #0 8008eea: 2200 movs r2, #0 8008eec: 2100 movs r1, #0 8008eee: 68f8 ldr r0, [r7, #12] 8008ef0: f001 fd06 bl 800a900 8008ef4: e01c b.n 8008f30 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008ef6: 68fb ldr r3, [r7, #12] 8008ef8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008efc: b2db uxtb r3, r3 8008efe: 2b03 cmp r3, #3 8008f00: d10f bne.n 8008f22 { if (pdev->pClass[0]->EP0_TxSent != NULL) 8008f02: 68fb ldr r3, [r7, #12] 8008f04: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008f08: 68db ldr r3, [r3, #12] 8008f0a: 2b00 cmp r3, #0 8008f0c: d009 beq.n 8008f22 { pdev->classId = 0U; 8008f0e: 68fb ldr r3, [r7, #12] 8008f10: 2200 movs r2, #0 8008f12: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 8008f16: 68fb ldr r3, [r7, #12] 8008f18: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008f1c: 68db ldr r3, [r3, #12] 8008f1e: 68f8 ldr r0, [r7, #12] 8008f20: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8008f22: 2180 movs r1, #128 @ 0x80 8008f24: 68f8 ldr r0, [r7, #12] 8008f26: f001 fc41 bl 800a7ac (void)USBD_CtlReceiveStatus(pdev); 8008f2a: 68f8 ldr r0, [r7, #12] 8008f2c: f001 f8db bl 800a0e6 } } } if (pdev->dev_test_mode != 0U) 8008f30: 68fb ldr r3, [r7, #12] 8008f32: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8008f36: 2b00 cmp r3, #0 8008f38: d03a beq.n 8008fb0 { (void)USBD_RunTestMode(pdev); 8008f3a: 68f8 ldr r0, [r7, #12] 8008f3c: f7ff fe30 bl 8008ba0 pdev->dev_test_mode = 0U; 8008f40: 68fb ldr r3, [r7, #12] 8008f42: 2200 movs r2, #0 8008f44: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8008f48: e032 b.n 8008fb0 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8008f4a: 7afb ldrb r3, [r7, #11] 8008f4c: f063 037f orn r3, r3, #127 @ 0x7f 8008f50: b2db uxtb r3, r3 8008f52: 4619 mov r1, r3 8008f54: 68f8 ldr r0, [r7, #12] 8008f56: f000 f986 bl 8009266 8008f5a: 4603 mov r3, r0 8008f5c: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008f5e: 7dfb ldrb r3, [r7, #23] 8008f60: 2bff cmp r3, #255 @ 0xff 8008f62: d025 beq.n 8008fb0 8008f64: 7dfb ldrb r3, [r7, #23] 8008f66: 2b00 cmp r3, #0 8008f68: d122 bne.n 8008fb0 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008f6a: 68fb ldr r3, [r7, #12] 8008f6c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008f70: b2db uxtb r3, r3 8008f72: 2b03 cmp r3, #3 8008f74: d11c bne.n 8008fb0 { if (pdev->pClass[idx]->DataIn != NULL) 8008f76: 7dfa ldrb r2, [r7, #23] 8008f78: 68fb ldr r3, [r7, #12] 8008f7a: 32ae adds r2, #174 @ 0xae 8008f7c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008f80: 695b ldr r3, [r3, #20] 8008f82: 2b00 cmp r3, #0 8008f84: d014 beq.n 8008fb0 { pdev->classId = idx; 8008f86: 7dfa ldrb r2, [r7, #23] 8008f88: 68fb ldr r3, [r7, #12] 8008f8a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 8008f8e: 7dfa ldrb r2, [r7, #23] 8008f90: 68fb ldr r3, [r7, #12] 8008f92: 32ae adds r2, #174 @ 0xae 8008f94: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008f98: 695b ldr r3, [r3, #20] 8008f9a: 7afa ldrb r2, [r7, #11] 8008f9c: 4611 mov r1, r2 8008f9e: 68f8 ldr r0, [r7, #12] 8008fa0: 4798 blx r3 8008fa2: 4603 mov r3, r0 8008fa4: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 8008fa6: 7dbb ldrb r3, [r7, #22] 8008fa8: 2b00 cmp r3, #0 8008faa: d001 beq.n 8008fb0 { return ret; 8008fac: 7dbb ldrb r3, [r7, #22] 8008fae: e000 b.n 8008fb2 } } } } return USBD_OK; 8008fb0: 2300 movs r3, #0 } 8008fb2: 4618 mov r0, r3 8008fb4: 3718 adds r7, #24 8008fb6: 46bd mov sp, r7 8008fb8: bd80 pop {r7, pc} 08008fba : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8008fba: b580 push {r7, lr} 8008fbc: b084 sub sp, #16 8008fbe: af00 add r7, sp, #0 8008fc0: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8008fc2: 2300 movs r3, #0 8008fc4: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8008fc6: 687b ldr r3, [r7, #4] 8008fc8: 2201 movs r2, #1 8008fca: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 8008fce: 687b ldr r3, [r7, #4] 8008fd0: 2200 movs r2, #0 8008fd2: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 8008fd6: 687b ldr r3, [r7, #4] 8008fd8: 2200 movs r2, #0 8008fda: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 8008fdc: 687b ldr r3, [r7, #4] 8008fde: 2200 movs r2, #0 8008fe0: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 8008fe4: 687b ldr r3, [r7, #4] 8008fe6: 2200 movs r2, #0 8008fe8: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 8008fec: 687b ldr r3, [r7, #4] 8008fee: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ff2: 2b00 cmp r3, #0 8008ff4: d014 beq.n 8009020 { if (pdev->pClass[0]->DeInit != NULL) 8008ff6: 687b ldr r3, [r7, #4] 8008ff8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ffc: 685b ldr r3, [r3, #4] 8008ffe: 2b00 cmp r3, #0 8009000: d00e beq.n 8009020 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 8009002: 687b ldr r3, [r7, #4] 8009004: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009008: 685b ldr r3, [r3, #4] 800900a: 687a ldr r2, [r7, #4] 800900c: 6852 ldr r2, [r2, #4] 800900e: b2d2 uxtb r2, r2 8009010: 4611 mov r1, r2 8009012: 6878 ldr r0, [r7, #4] 8009014: 4798 blx r3 8009016: 4603 mov r3, r0 8009018: 2b00 cmp r3, #0 800901a: d001 beq.n 8009020 { ret = USBD_FAIL; 800901c: 2303 movs r3, #3 800901e: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009020: 2340 movs r3, #64 @ 0x40 8009022: 2200 movs r2, #0 8009024: 2100 movs r1, #0 8009026: 6878 ldr r0, [r7, #4] 8009028: f001 fb7b bl 800a722 pdev->ep_out[0x00U & 0xFU].is_used = 1U; 800902c: 687b ldr r3, [r7, #4] 800902e: 2201 movs r2, #1 8009030: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8009034: 687b ldr r3, [r7, #4] 8009036: 2240 movs r2, #64 @ 0x40 8009038: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 800903c: 2340 movs r3, #64 @ 0x40 800903e: 2200 movs r2, #0 8009040: 2180 movs r1, #128 @ 0x80 8009042: 6878 ldr r0, [r7, #4] 8009044: f001 fb6d bl 800a722 pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8009048: 687b ldr r3, [r7, #4] 800904a: 2201 movs r2, #1 800904c: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8009050: 687b ldr r3, [r7, #4] 8009052: 2240 movs r2, #64 @ 0x40 8009054: 841a strh r2, [r3, #32] return ret; 8009056: 7bfb ldrb r3, [r7, #15] } 8009058: 4618 mov r0, r3 800905a: 3710 adds r7, #16 800905c: 46bd mov sp, r7 800905e: bd80 pop {r7, pc} 08009060 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8009060: b480 push {r7} 8009062: b083 sub sp, #12 8009064: af00 add r7, sp, #0 8009066: 6078 str r0, [r7, #4] 8009068: 460b mov r3, r1 800906a: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 800906c: 687b ldr r3, [r7, #4] 800906e: 78fa ldrb r2, [r7, #3] 8009070: 741a strb r2, [r3, #16] return USBD_OK; 8009072: 2300 movs r3, #0 } 8009074: 4618 mov r0, r3 8009076: 370c adds r7, #12 8009078: 46bd mov sp, r7 800907a: f85d 7b04 ldr.w r7, [sp], #4 800907e: 4770 bx lr 08009080 : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8009080: b480 push {r7} 8009082: b083 sub sp, #12 8009084: af00 add r7, sp, #0 8009086: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8009088: 687b ldr r3, [r7, #4] 800908a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800908e: b2db uxtb r3, r3 8009090: 2b04 cmp r3, #4 8009092: d006 beq.n 80090a2 { pdev->dev_old_state = pdev->dev_state; 8009094: 687b ldr r3, [r7, #4] 8009096: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800909a: b2da uxtb r2, r3 800909c: 687b ldr r3, [r7, #4] 800909e: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 80090a2: 687b ldr r3, [r7, #4] 80090a4: 2204 movs r2, #4 80090a6: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 80090aa: 2300 movs r3, #0 } 80090ac: 4618 mov r0, r3 80090ae: 370c adds r7, #12 80090b0: 46bd mov sp, r7 80090b2: f85d 7b04 ldr.w r7, [sp], #4 80090b6: 4770 bx lr 080090b8 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 80090b8: b480 push {r7} 80090ba: b083 sub sp, #12 80090bc: af00 add r7, sp, #0 80090be: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 80090c0: 687b ldr r3, [r7, #4] 80090c2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80090c6: b2db uxtb r3, r3 80090c8: 2b04 cmp r3, #4 80090ca: d106 bne.n 80090da { pdev->dev_state = pdev->dev_old_state; 80090cc: 687b ldr r3, [r7, #4] 80090ce: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 80090d2: b2da uxtb r2, r3 80090d4: 687b ldr r3, [r7, #4] 80090d6: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 80090da: 2300 movs r3, #0 } 80090dc: 4618 mov r0, r3 80090de: 370c adds r7, #12 80090e0: 46bd mov sp, r7 80090e2: f85d 7b04 ldr.w r7, [sp], #4 80090e6: 4770 bx lr 080090e8 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 80090e8: b580 push {r7, lr} 80090ea: b082 sub sp, #8 80090ec: af00 add r7, sp, #0 80090ee: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80090f0: 687b ldr r3, [r7, #4] 80090f2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80090f6: b2db uxtb r3, r3 80090f8: 2b03 cmp r3, #3 80090fa: d110 bne.n 800911e } } } } #else if (pdev->pClass[0] != NULL) 80090fc: 687b ldr r3, [r7, #4] 80090fe: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009102: 2b00 cmp r3, #0 8009104: d00b beq.n 800911e { if (pdev->pClass[0]->SOF != NULL) 8009106: 687b ldr r3, [r7, #4] 8009108: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800910c: 69db ldr r3, [r3, #28] 800910e: 2b00 cmp r3, #0 8009110: d005 beq.n 800911e { (void)pdev->pClass[0]->SOF(pdev); 8009112: 687b ldr r3, [r7, #4] 8009114: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009118: 69db ldr r3, [r3, #28] 800911a: 6878 ldr r0, [r7, #4] 800911c: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 800911e: 2300 movs r3, #0 } 8009120: 4618 mov r0, r3 8009122: 3708 adds r7, #8 8009124: 46bd mov sp, r7 8009126: bd80 pop {r7, pc} 08009128 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009128: b580 push {r7, lr} 800912a: b082 sub sp, #8 800912c: af00 add r7, sp, #0 800912e: 6078 str r0, [r7, #4] 8009130: 460b mov r3, r1 8009132: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009134: 687b ldr r3, [r7, #4] 8009136: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800913a: 687b ldr r3, [r7, #4] 800913c: 32ae adds r2, #174 @ 0xae 800913e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009142: 2b00 cmp r3, #0 8009144: d101 bne.n 800914a { return USBD_FAIL; 8009146: 2303 movs r3, #3 8009148: e01c b.n 8009184 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 800914a: 687b ldr r3, [r7, #4] 800914c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009150: b2db uxtb r3, r3 8009152: 2b03 cmp r3, #3 8009154: d115 bne.n 8009182 { if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) 8009156: 687b ldr r3, [r7, #4] 8009158: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800915c: 687b ldr r3, [r7, #4] 800915e: 32ae adds r2, #174 @ 0xae 8009160: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009164: 6a1b ldr r3, [r3, #32] 8009166: 2b00 cmp r3, #0 8009168: d00b beq.n 8009182 { (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); 800916a: 687b ldr r3, [r7, #4] 800916c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009170: 687b ldr r3, [r7, #4] 8009172: 32ae adds r2, #174 @ 0xae 8009174: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009178: 6a1b ldr r3, [r3, #32] 800917a: 78fa ldrb r2, [r7, #3] 800917c: 4611 mov r1, r2 800917e: 6878 ldr r0, [r7, #4] 8009180: 4798 blx r3 } } return USBD_OK; 8009182: 2300 movs r3, #0 } 8009184: 4618 mov r0, r3 8009186: 3708 adds r7, #8 8009188: 46bd mov sp, r7 800918a: bd80 pop {r7, pc} 0800918c : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 800918c: b580 push {r7, lr} 800918e: b082 sub sp, #8 8009190: af00 add r7, sp, #0 8009192: 6078 str r0, [r7, #4] 8009194: 460b mov r3, r1 8009196: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009198: 687b ldr r3, [r7, #4] 800919a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800919e: 687b ldr r3, [r7, #4] 80091a0: 32ae adds r2, #174 @ 0xae 80091a2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80091a6: 2b00 cmp r3, #0 80091a8: d101 bne.n 80091ae { return USBD_FAIL; 80091aa: 2303 movs r3, #3 80091ac: e01c b.n 80091e8 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 80091ae: 687b ldr r3, [r7, #4] 80091b0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80091b4: b2db uxtb r3, r3 80091b6: 2b03 cmp r3, #3 80091b8: d115 bne.n 80091e6 { if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) 80091ba: 687b ldr r3, [r7, #4] 80091bc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80091c0: 687b ldr r3, [r7, #4] 80091c2: 32ae adds r2, #174 @ 0xae 80091c4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80091c8: 6a5b ldr r3, [r3, #36] @ 0x24 80091ca: 2b00 cmp r3, #0 80091cc: d00b beq.n 80091e6 { (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); 80091ce: 687b ldr r3, [r7, #4] 80091d0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80091d4: 687b ldr r3, [r7, #4] 80091d6: 32ae adds r2, #174 @ 0xae 80091d8: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80091dc: 6a5b ldr r3, [r3, #36] @ 0x24 80091de: 78fa ldrb r2, [r7, #3] 80091e0: 4611 mov r1, r2 80091e2: 6878 ldr r0, [r7, #4] 80091e4: 4798 blx r3 } } return USBD_OK; 80091e6: 2300 movs r3, #0 } 80091e8: 4618 mov r0, r3 80091ea: 3708 adds r7, #8 80091ec: 46bd mov sp, r7 80091ee: bd80 pop {r7, pc} 080091f0 : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 80091f0: b480 push {r7} 80091f2: b083 sub sp, #12 80091f4: af00 add r7, sp, #0 80091f6: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 80091f8: 2300 movs r3, #0 } 80091fa: 4618 mov r0, r3 80091fc: 370c adds r7, #12 80091fe: 46bd mov sp, r7 8009200: f85d 7b04 ldr.w r7, [sp], #4 8009204: 4770 bx lr 08009206 : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 8009206: b580 push {r7, lr} 8009208: b084 sub sp, #16 800920a: af00 add r7, sp, #0 800920c: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 800920e: 2300 movs r3, #0 8009210: 73fb strb r3, [r7, #15] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 8009212: 687b ldr r3, [r7, #4] 8009214: 2201 movs r2, #1 8009216: f883 229c strb.w r2, [r3, #668] @ 0x29c } } } } #else if (pdev->pClass[0] != NULL) 800921a: 687b ldr r3, [r7, #4] 800921c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009220: 2b00 cmp r3, #0 8009222: d00e beq.n 8009242 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) 8009224: 687b ldr r3, [r7, #4] 8009226: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800922a: 685b ldr r3, [r3, #4] 800922c: 687a ldr r2, [r7, #4] 800922e: 6852 ldr r2, [r2, #4] 8009230: b2d2 uxtb r2, r2 8009232: 4611 mov r1, r2 8009234: 6878 ldr r0, [r7, #4] 8009236: 4798 blx r3 8009238: 4603 mov r3, r0 800923a: 2b00 cmp r3, #0 800923c: d001 beq.n 8009242 { ret = USBD_FAIL; 800923e: 2303 movs r3, #3 8009240: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ return ret; 8009242: 7bfb ldrb r3, [r7, #15] } 8009244: 4618 mov r0, r3 8009246: 3710 adds r7, #16 8009248: 46bd mov sp, r7 800924a: bd80 pop {r7, pc} 0800924c : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 800924c: b480 push {r7} 800924e: b083 sub sp, #12 8009250: af00 add r7, sp, #0 8009252: 6078 str r0, [r7, #4] 8009254: 460b mov r3, r1 8009256: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009258: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 800925a: 4618 mov r0, r3 800925c: 370c adds r7, #12 800925e: 46bd mov sp, r7 8009260: f85d 7b04 ldr.w r7, [sp], #4 8009264: 4770 bx lr 08009266 : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 8009266: b480 push {r7} 8009268: b083 sub sp, #12 800926a: af00 add r7, sp, #0 800926c: 6078 str r0, [r7, #4] 800926e: 460b mov r3, r1 8009270: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009272: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009274: 4618 mov r0, r3 8009276: 370c adds r7, #12 8009278: 46bd mov sp, r7 800927a: f85d 7b04 ldr.w r7, [sp], #4 800927e: 4770 bx lr 08009280 : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 8009280: b580 push {r7, lr} 8009282: b086 sub sp, #24 8009284: af00 add r7, sp, #0 8009286: 6078 str r0, [r7, #4] 8009288: 460b mov r3, r1 800928a: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 800928c: 687b ldr r3, [r7, #4] 800928e: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 8009290: 687b ldr r3, [r7, #4] 8009292: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 8009294: 2300 movs r3, #0 8009296: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8009298: 68fb ldr r3, [r7, #12] 800929a: 885b ldrh r3, [r3, #2] 800929c: b29b uxth r3, r3 800929e: 68fa ldr r2, [r7, #12] 80092a0: 7812 ldrb r2, [r2, #0] 80092a2: 4293 cmp r3, r2 80092a4: d91f bls.n 80092e6 { ptr = desc->bLength; 80092a6: 68fb ldr r3, [r7, #12] 80092a8: 781b ldrb r3, [r3, #0] 80092aa: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 80092ac: e013 b.n 80092d6 { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 80092ae: f107 030a add.w r3, r7, #10 80092b2: 4619 mov r1, r3 80092b4: 6978 ldr r0, [r7, #20] 80092b6: f000 f81b bl 80092f0 80092ba: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 80092bc: 697b ldr r3, [r7, #20] 80092be: 785b ldrb r3, [r3, #1] 80092c0: 2b05 cmp r3, #5 80092c2: d108 bne.n 80092d6 { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 80092c4: 697b ldr r3, [r7, #20] 80092c6: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 80092c8: 693b ldr r3, [r7, #16] 80092ca: 789b ldrb r3, [r3, #2] 80092cc: 78fa ldrb r2, [r7, #3] 80092ce: 429a cmp r2, r3 80092d0: d008 beq.n 80092e4 { break; } else { pEpDesc = NULL; 80092d2: 2300 movs r3, #0 80092d4: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 80092d6: 68fb ldr r3, [r7, #12] 80092d8: 885b ldrh r3, [r3, #2] 80092da: b29a uxth r2, r3 80092dc: 897b ldrh r3, [r7, #10] 80092de: 429a cmp r2, r3 80092e0: d8e5 bhi.n 80092ae 80092e2: e000 b.n 80092e6 break; 80092e4: bf00 nop } } } } return (void *)pEpDesc; 80092e6: 693b ldr r3, [r7, #16] } 80092e8: 4618 mov r0, r3 80092ea: 3718 adds r7, #24 80092ec: 46bd mov sp, r7 80092ee: bd80 pop {r7, pc} 080092f0 : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 80092f0: b480 push {r7} 80092f2: b085 sub sp, #20 80092f4: af00 add r7, sp, #0 80092f6: 6078 str r0, [r7, #4] 80092f8: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 80092fa: 687b ldr r3, [r7, #4] 80092fc: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 80092fe: 683b ldr r3, [r7, #0] 8009300: 881b ldrh r3, [r3, #0] 8009302: 68fa ldr r2, [r7, #12] 8009304: 7812 ldrb r2, [r2, #0] 8009306: 4413 add r3, r2 8009308: b29a uxth r2, r3 800930a: 683b ldr r3, [r7, #0] 800930c: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 800930e: 68fb ldr r3, [r7, #12] 8009310: 781b ldrb r3, [r3, #0] 8009312: 461a mov r2, r3 8009314: 687b ldr r3, [r7, #4] 8009316: 4413 add r3, r2 8009318: 60fb str r3, [r7, #12] return (pnext); 800931a: 68fb ldr r3, [r7, #12] } 800931c: 4618 mov r0, r3 800931e: 3714 adds r7, #20 8009320: 46bd mov sp, r7 8009322: f85d 7b04 ldr.w r7, [sp], #4 8009326: 4770 bx lr 08009328 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 8009328: b480 push {r7} 800932a: b087 sub sp, #28 800932c: af00 add r7, sp, #0 800932e: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 8009330: 687b ldr r3, [r7, #4] 8009332: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 8009334: 697b ldr r3, [r7, #20] 8009336: 781b ldrb r3, [r3, #0] 8009338: 827b strh r3, [r7, #18] _pbuff++; 800933a: 697b ldr r3, [r7, #20] 800933c: 3301 adds r3, #1 800933e: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 8009340: 697b ldr r3, [r7, #20] 8009342: 781b ldrb r3, [r3, #0] 8009344: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 8009346: f9b7 3010 ldrsh.w r3, [r7, #16] 800934a: 021b lsls r3, r3, #8 800934c: b21a sxth r2, r3 800934e: f9b7 3012 ldrsh.w r3, [r7, #18] 8009352: 4313 orrs r3, r2 8009354: b21b sxth r3, r3 8009356: 81fb strh r3, [r7, #14] return _SwapVal; 8009358: 89fb ldrh r3, [r7, #14] } 800935a: 4618 mov r0, r3 800935c: 371c adds r7, #28 800935e: 46bd mov sp, r7 8009360: f85d 7b04 ldr.w r7, [sp], #4 8009364: 4770 bx lr ... 08009368 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009368: b580 push {r7, lr} 800936a: b084 sub sp, #16 800936c: af00 add r7, sp, #0 800936e: 6078 str r0, [r7, #4] 8009370: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009372: 2300 movs r3, #0 8009374: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009376: 683b ldr r3, [r7, #0] 8009378: 781b ldrb r3, [r3, #0] 800937a: f003 0360 and.w r3, r3, #96 @ 0x60 800937e: 2b40 cmp r3, #64 @ 0x40 8009380: d005 beq.n 800938e 8009382: 2b40 cmp r3, #64 @ 0x40 8009384: d857 bhi.n 8009436 8009386: 2b00 cmp r3, #0 8009388: d00f beq.n 80093aa 800938a: 2b20 cmp r3, #32 800938c: d153 bne.n 8009436 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 800938e: 687b ldr r3, [r7, #4] 8009390: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009394: 687b ldr r3, [r7, #4] 8009396: 32ae adds r2, #174 @ 0xae 8009398: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800939c: 689b ldr r3, [r3, #8] 800939e: 6839 ldr r1, [r7, #0] 80093a0: 6878 ldr r0, [r7, #4] 80093a2: 4798 blx r3 80093a4: 4603 mov r3, r0 80093a6: 73fb strb r3, [r7, #15] break; 80093a8: e04a b.n 8009440 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80093aa: 683b ldr r3, [r7, #0] 80093ac: 785b ldrb r3, [r3, #1] 80093ae: 2b09 cmp r3, #9 80093b0: d83b bhi.n 800942a 80093b2: a201 add r2, pc, #4 @ (adr r2, 80093b8 ) 80093b4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80093b8: 0800940d .word 0x0800940d 80093bc: 08009421 .word 0x08009421 80093c0: 0800942b .word 0x0800942b 80093c4: 08009417 .word 0x08009417 80093c8: 0800942b .word 0x0800942b 80093cc: 080093eb .word 0x080093eb 80093d0: 080093e1 .word 0x080093e1 80093d4: 0800942b .word 0x0800942b 80093d8: 08009403 .word 0x08009403 80093dc: 080093f5 .word 0x080093f5 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 80093e0: 6839 ldr r1, [r7, #0] 80093e2: 6878 ldr r0, [r7, #4] 80093e4: f000 fa3e bl 8009864 break; 80093e8: e024 b.n 8009434 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 80093ea: 6839 ldr r1, [r7, #0] 80093ec: 6878 ldr r0, [r7, #4] 80093ee: f000 fbcd bl 8009b8c break; 80093f2: e01f b.n 8009434 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 80093f4: 6839 ldr r1, [r7, #0] 80093f6: 6878 ldr r0, [r7, #4] 80093f8: f000 fc0c bl 8009c14 80093fc: 4603 mov r3, r0 80093fe: 73fb strb r3, [r7, #15] break; 8009400: e018 b.n 8009434 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 8009402: 6839 ldr r1, [r7, #0] 8009404: 6878 ldr r0, [r7, #4] 8009406: f000 fcaf bl 8009d68 break; 800940a: e013 b.n 8009434 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 800940c: 6839 ldr r1, [r7, #0] 800940e: 6878 ldr r0, [r7, #4] 8009410: f000 fce0 bl 8009dd4 break; 8009414: e00e b.n 8009434 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 8009416: 6839 ldr r1, [r7, #0] 8009418: 6878 ldr r0, [r7, #4] 800941a: f000 fd0f bl 8009e3c break; 800941e: e009 b.n 8009434 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 8009420: 6839 ldr r1, [r7, #0] 8009422: 6878 ldr r0, [r7, #4] 8009424: f000 fd33 bl 8009e8e break; 8009428: e004 b.n 8009434 default: USBD_CtlError(pdev, req); 800942a: 6839 ldr r1, [r7, #0] 800942c: 6878 ldr r0, [r7, #4] 800942e: f000 fd8a bl 8009f46 break; 8009432: bf00 nop } break; 8009434: e004 b.n 8009440 default: USBD_CtlError(pdev, req); 8009436: 6839 ldr r1, [r7, #0] 8009438: 6878 ldr r0, [r7, #4] 800943a: f000 fd84 bl 8009f46 break; 800943e: bf00 nop } return ret; 8009440: 7bfb ldrb r3, [r7, #15] } 8009442: 4618 mov r0, r3 8009444: 3710 adds r7, #16 8009446: 46bd mov sp, r7 8009448: bd80 pop {r7, pc} 800944a: bf00 nop 0800944c : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800944c: b580 push {r7, lr} 800944e: b084 sub sp, #16 8009450: af00 add r7, sp, #0 8009452: 6078 str r0, [r7, #4] 8009454: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009456: 2300 movs r3, #0 8009458: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 800945a: 683b ldr r3, [r7, #0] 800945c: 781b ldrb r3, [r3, #0] 800945e: f003 0360 and.w r3, r3, #96 @ 0x60 8009462: 2b40 cmp r3, #64 @ 0x40 8009464: d005 beq.n 8009472 8009466: 2b40 cmp r3, #64 @ 0x40 8009468: d852 bhi.n 8009510 800946a: 2b00 cmp r3, #0 800946c: d001 beq.n 8009472 800946e: 2b20 cmp r3, #32 8009470: d14e bne.n 8009510 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 8009472: 687b ldr r3, [r7, #4] 8009474: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009478: b2db uxtb r3, r3 800947a: 3b01 subs r3, #1 800947c: 2b02 cmp r3, #2 800947e: d840 bhi.n 8009502 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 8009480: 683b ldr r3, [r7, #0] 8009482: 889b ldrh r3, [r3, #4] 8009484: b2db uxtb r3, r3 8009486: 2b01 cmp r3, #1 8009488: d836 bhi.n 80094f8 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 800948a: 683b ldr r3, [r7, #0] 800948c: 889b ldrh r3, [r3, #4] 800948e: b2db uxtb r3, r3 8009490: 4619 mov r1, r3 8009492: 6878 ldr r0, [r7, #4] 8009494: f7ff feda bl 800924c 8009498: 4603 mov r3, r0 800949a: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800949c: 7bbb ldrb r3, [r7, #14] 800949e: 2bff cmp r3, #255 @ 0xff 80094a0: d01d beq.n 80094de 80094a2: 7bbb ldrb r3, [r7, #14] 80094a4: 2b00 cmp r3, #0 80094a6: d11a bne.n 80094de { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 80094a8: 7bba ldrb r2, [r7, #14] 80094aa: 687b ldr r3, [r7, #4] 80094ac: 32ae adds r2, #174 @ 0xae 80094ae: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80094b2: 689b ldr r3, [r3, #8] 80094b4: 2b00 cmp r3, #0 80094b6: d00f beq.n 80094d8 { pdev->classId = idx; 80094b8: 7bba ldrb r2, [r7, #14] 80094ba: 687b ldr r3, [r7, #4] 80094bc: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 80094c0: 7bba ldrb r2, [r7, #14] 80094c2: 687b ldr r3, [r7, #4] 80094c4: 32ae adds r2, #174 @ 0xae 80094c6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80094ca: 689b ldr r3, [r3, #8] 80094cc: 6839 ldr r1, [r7, #0] 80094ce: 6878 ldr r0, [r7, #4] 80094d0: 4798 blx r3 80094d2: 4603 mov r3, r0 80094d4: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 80094d6: e004 b.n 80094e2 } else { /* should never reach this condition */ ret = USBD_FAIL; 80094d8: 2303 movs r3, #3 80094da: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 80094dc: e001 b.n 80094e2 } } else { /* No relative interface found */ ret = USBD_FAIL; 80094de: 2303 movs r3, #3 80094e0: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 80094e2: 683b ldr r3, [r7, #0] 80094e4: 88db ldrh r3, [r3, #6] 80094e6: 2b00 cmp r3, #0 80094e8: d110 bne.n 800950c 80094ea: 7bfb ldrb r3, [r7, #15] 80094ec: 2b00 cmp r3, #0 80094ee: d10d bne.n 800950c { (void)USBD_CtlSendStatus(pdev); 80094f0: 6878 ldr r0, [r7, #4] 80094f2: f000 fde5 bl 800a0c0 } else { USBD_CtlError(pdev, req); } break; 80094f6: e009 b.n 800950c USBD_CtlError(pdev, req); 80094f8: 6839 ldr r1, [r7, #0] 80094fa: 6878 ldr r0, [r7, #4] 80094fc: f000 fd23 bl 8009f46 break; 8009500: e004 b.n 800950c default: USBD_CtlError(pdev, req); 8009502: 6839 ldr r1, [r7, #0] 8009504: 6878 ldr r0, [r7, #4] 8009506: f000 fd1e bl 8009f46 break; 800950a: e000 b.n 800950e break; 800950c: bf00 nop } break; 800950e: e004 b.n 800951a default: USBD_CtlError(pdev, req); 8009510: 6839 ldr r1, [r7, #0] 8009512: 6878 ldr r0, [r7, #4] 8009514: f000 fd17 bl 8009f46 break; 8009518: bf00 nop } return ret; 800951a: 7bfb ldrb r3, [r7, #15] } 800951c: 4618 mov r0, r3 800951e: 3710 adds r7, #16 8009520: 46bd mov sp, r7 8009522: bd80 pop {r7, pc} 08009524 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009524: b580 push {r7, lr} 8009526: b084 sub sp, #16 8009528: af00 add r7, sp, #0 800952a: 6078 str r0, [r7, #4] 800952c: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 800952e: 2300 movs r3, #0 8009530: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 8009532: 683b ldr r3, [r7, #0] 8009534: 889b ldrh r3, [r3, #4] 8009536: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009538: 683b ldr r3, [r7, #0] 800953a: 781b ldrb r3, [r3, #0] 800953c: f003 0360 and.w r3, r3, #96 @ 0x60 8009540: 2b40 cmp r3, #64 @ 0x40 8009542: d007 beq.n 8009554 8009544: 2b40 cmp r3, #64 @ 0x40 8009546: f200 8181 bhi.w 800984c 800954a: 2b00 cmp r3, #0 800954c: d02a beq.n 80095a4 800954e: 2b20 cmp r3, #32 8009550: f040 817c bne.w 800984c { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 8009554: 7bbb ldrb r3, [r7, #14] 8009556: 4619 mov r1, r3 8009558: 6878 ldr r0, [r7, #4] 800955a: f7ff fe84 bl 8009266 800955e: 4603 mov r3, r0 8009560: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009562: 7b7b ldrb r3, [r7, #13] 8009564: 2bff cmp r3, #255 @ 0xff 8009566: f000 8176 beq.w 8009856 800956a: 7b7b ldrb r3, [r7, #13] 800956c: 2b00 cmp r3, #0 800956e: f040 8172 bne.w 8009856 { pdev->classId = idx; 8009572: 7b7a ldrb r2, [r7, #13] 8009574: 687b ldr r3, [r7, #4] 8009576: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 800957a: 7b7a ldrb r2, [r7, #13] 800957c: 687b ldr r3, [r7, #4] 800957e: 32ae adds r2, #174 @ 0xae 8009580: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009584: 689b ldr r3, [r3, #8] 8009586: 2b00 cmp r3, #0 8009588: f000 8165 beq.w 8009856 { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 800958c: 7b7a ldrb r2, [r7, #13] 800958e: 687b ldr r3, [r7, #4] 8009590: 32ae adds r2, #174 @ 0xae 8009592: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009596: 689b ldr r3, [r3, #8] 8009598: 6839 ldr r1, [r7, #0] 800959a: 6878 ldr r0, [r7, #4] 800959c: 4798 blx r3 800959e: 4603 mov r3, r0 80095a0: 73fb strb r3, [r7, #15] } } break; 80095a2: e158 b.n 8009856 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80095a4: 683b ldr r3, [r7, #0] 80095a6: 785b ldrb r3, [r3, #1] 80095a8: 2b03 cmp r3, #3 80095aa: d008 beq.n 80095be 80095ac: 2b03 cmp r3, #3 80095ae: f300 8147 bgt.w 8009840 80095b2: 2b00 cmp r3, #0 80095b4: f000 809b beq.w 80096ee 80095b8: 2b01 cmp r3, #1 80095ba: d03c beq.n 8009636 80095bc: e140 b.n 8009840 { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 80095be: 687b ldr r3, [r7, #4] 80095c0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80095c4: b2db uxtb r3, r3 80095c6: 2b02 cmp r3, #2 80095c8: d002 beq.n 80095d0 80095ca: 2b03 cmp r3, #3 80095cc: d016 beq.n 80095fc 80095ce: e02c b.n 800962a { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80095d0: 7bbb ldrb r3, [r7, #14] 80095d2: 2b00 cmp r3, #0 80095d4: d00d beq.n 80095f2 80095d6: 7bbb ldrb r3, [r7, #14] 80095d8: 2b80 cmp r3, #128 @ 0x80 80095da: d00a beq.n 80095f2 { (void)USBD_LL_StallEP(pdev, ep_addr); 80095dc: 7bbb ldrb r3, [r7, #14] 80095de: 4619 mov r1, r3 80095e0: 6878 ldr r0, [r7, #4] 80095e2: f001 f8e3 bl 800a7ac (void)USBD_LL_StallEP(pdev, 0x80U); 80095e6: 2180 movs r1, #128 @ 0x80 80095e8: 6878 ldr r0, [r7, #4] 80095ea: f001 f8df bl 800a7ac 80095ee: bf00 nop } else { USBD_CtlError(pdev, req); } break; 80095f0: e020 b.n 8009634 USBD_CtlError(pdev, req); 80095f2: 6839 ldr r1, [r7, #0] 80095f4: 6878 ldr r0, [r7, #4] 80095f6: f000 fca6 bl 8009f46 break; 80095fa: e01b b.n 8009634 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 80095fc: 683b ldr r3, [r7, #0] 80095fe: 885b ldrh r3, [r3, #2] 8009600: 2b00 cmp r3, #0 8009602: d10e bne.n 8009622 { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 8009604: 7bbb ldrb r3, [r7, #14] 8009606: 2b00 cmp r3, #0 8009608: d00b beq.n 8009622 800960a: 7bbb ldrb r3, [r7, #14] 800960c: 2b80 cmp r3, #128 @ 0x80 800960e: d008 beq.n 8009622 8009610: 683b ldr r3, [r7, #0] 8009612: 88db ldrh r3, [r3, #6] 8009614: 2b00 cmp r3, #0 8009616: d104 bne.n 8009622 { (void)USBD_LL_StallEP(pdev, ep_addr); 8009618: 7bbb ldrb r3, [r7, #14] 800961a: 4619 mov r1, r3 800961c: 6878 ldr r0, [r7, #4] 800961e: f001 f8c5 bl 800a7ac } } (void)USBD_CtlSendStatus(pdev); 8009622: 6878 ldr r0, [r7, #4] 8009624: f000 fd4c bl 800a0c0 break; 8009628: e004 b.n 8009634 default: USBD_CtlError(pdev, req); 800962a: 6839 ldr r1, [r7, #0] 800962c: 6878 ldr r0, [r7, #4] 800962e: f000 fc8a bl 8009f46 break; 8009632: bf00 nop } break; 8009634: e109 b.n 800984a case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 8009636: 687b ldr r3, [r7, #4] 8009638: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800963c: b2db uxtb r3, r3 800963e: 2b02 cmp r3, #2 8009640: d002 beq.n 8009648 8009642: 2b03 cmp r3, #3 8009644: d016 beq.n 8009674 8009646: e04b b.n 80096e0 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009648: 7bbb ldrb r3, [r7, #14] 800964a: 2b00 cmp r3, #0 800964c: d00d beq.n 800966a 800964e: 7bbb ldrb r3, [r7, #14] 8009650: 2b80 cmp r3, #128 @ 0x80 8009652: d00a beq.n 800966a { (void)USBD_LL_StallEP(pdev, ep_addr); 8009654: 7bbb ldrb r3, [r7, #14] 8009656: 4619 mov r1, r3 8009658: 6878 ldr r0, [r7, #4] 800965a: f001 f8a7 bl 800a7ac (void)USBD_LL_StallEP(pdev, 0x80U); 800965e: 2180 movs r1, #128 @ 0x80 8009660: 6878 ldr r0, [r7, #4] 8009662: f001 f8a3 bl 800a7ac 8009666: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8009668: e040 b.n 80096ec USBD_CtlError(pdev, req); 800966a: 6839 ldr r1, [r7, #0] 800966c: 6878 ldr r0, [r7, #4] 800966e: f000 fc6a bl 8009f46 break; 8009672: e03b b.n 80096ec case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8009674: 683b ldr r3, [r7, #0] 8009676: 885b ldrh r3, [r3, #2] 8009678: 2b00 cmp r3, #0 800967a: d136 bne.n 80096ea { if ((ep_addr & 0x7FU) != 0x00U) 800967c: 7bbb ldrb r3, [r7, #14] 800967e: f003 037f and.w r3, r3, #127 @ 0x7f 8009682: 2b00 cmp r3, #0 8009684: d004 beq.n 8009690 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 8009686: 7bbb ldrb r3, [r7, #14] 8009688: 4619 mov r1, r3 800968a: 6878 ldr r0, [r7, #4] 800968c: f001 f8ad bl 800a7ea } (void)USBD_CtlSendStatus(pdev); 8009690: 6878 ldr r0, [r7, #4] 8009692: f000 fd15 bl 800a0c0 /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 8009696: 7bbb ldrb r3, [r7, #14] 8009698: 4619 mov r1, r3 800969a: 6878 ldr r0, [r7, #4] 800969c: f7ff fde3 bl 8009266 80096a0: 4603 mov r3, r0 80096a2: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 80096a4: 7b7b ldrb r3, [r7, #13] 80096a6: 2bff cmp r3, #255 @ 0xff 80096a8: d01f beq.n 80096ea 80096aa: 7b7b ldrb r3, [r7, #13] 80096ac: 2b00 cmp r3, #0 80096ae: d11c bne.n 80096ea { pdev->classId = idx; 80096b0: 7b7a ldrb r2, [r7, #13] 80096b2: 687b ldr r3, [r7, #4] 80096b4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 80096b8: 7b7a ldrb r2, [r7, #13] 80096ba: 687b ldr r3, [r7, #4] 80096bc: 32ae adds r2, #174 @ 0xae 80096be: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80096c2: 689b ldr r3, [r3, #8] 80096c4: 2b00 cmp r3, #0 80096c6: d010 beq.n 80096ea { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 80096c8: 7b7a ldrb r2, [r7, #13] 80096ca: 687b ldr r3, [r7, #4] 80096cc: 32ae adds r2, #174 @ 0xae 80096ce: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80096d2: 689b ldr r3, [r3, #8] 80096d4: 6839 ldr r1, [r7, #0] 80096d6: 6878 ldr r0, [r7, #4] 80096d8: 4798 blx r3 80096da: 4603 mov r3, r0 80096dc: 73fb strb r3, [r7, #15] } } } break; 80096de: e004 b.n 80096ea default: USBD_CtlError(pdev, req); 80096e0: 6839 ldr r1, [r7, #0] 80096e2: 6878 ldr r0, [r7, #4] 80096e4: f000 fc2f bl 8009f46 break; 80096e8: e000 b.n 80096ec break; 80096ea: bf00 nop } break; 80096ec: e0ad b.n 800984a case USB_REQ_GET_STATUS: switch (pdev->dev_state) 80096ee: 687b ldr r3, [r7, #4] 80096f0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80096f4: b2db uxtb r3, r3 80096f6: 2b02 cmp r3, #2 80096f8: d002 beq.n 8009700 80096fa: 2b03 cmp r3, #3 80096fc: d033 beq.n 8009766 80096fe: e099 b.n 8009834 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009700: 7bbb ldrb r3, [r7, #14] 8009702: 2b00 cmp r3, #0 8009704: d007 beq.n 8009716 8009706: 7bbb ldrb r3, [r7, #14] 8009708: 2b80 cmp r3, #128 @ 0x80 800970a: d004 beq.n 8009716 { USBD_CtlError(pdev, req); 800970c: 6839 ldr r1, [r7, #0] 800970e: 6878 ldr r0, [r7, #4] 8009710: f000 fc19 bl 8009f46 break; 8009714: e093 b.n 800983e } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009716: f997 300e ldrsb.w r3, [r7, #14] 800971a: 2b00 cmp r3, #0 800971c: da0b bge.n 8009736 800971e: 7bbb ldrb r3, [r7, #14] 8009720: f003 027f and.w r2, r3, #127 @ 0x7f 8009724: 4613 mov r3, r2 8009726: 009b lsls r3, r3, #2 8009728: 4413 add r3, r2 800972a: 009b lsls r3, r3, #2 800972c: 3310 adds r3, #16 800972e: 687a ldr r2, [r7, #4] 8009730: 4413 add r3, r2 8009732: 3304 adds r3, #4 8009734: e00b b.n 800974e &pdev->ep_out[ep_addr & 0x7FU]; 8009736: 7bbb ldrb r3, [r7, #14] 8009738: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800973c: 4613 mov r3, r2 800973e: 009b lsls r3, r3, #2 8009740: 4413 add r3, r2 8009742: 009b lsls r3, r3, #2 8009744: f503 73a8 add.w r3, r3, #336 @ 0x150 8009748: 687a ldr r2, [r7, #4] 800974a: 4413 add r3, r2 800974c: 3304 adds r3, #4 800974e: 60bb str r3, [r7, #8] pep->status = 0x0000U; 8009750: 68bb ldr r3, [r7, #8] 8009752: 2200 movs r2, #0 8009754: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8009756: 68bb ldr r3, [r7, #8] 8009758: 330e adds r3, #14 800975a: 2202 movs r2, #2 800975c: 4619 mov r1, r3 800975e: 6878 ldr r0, [r7, #4] 8009760: f000 fc6e bl 800a040 break; 8009764: e06b b.n 800983e case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 8009766: f997 300e ldrsb.w r3, [r7, #14] 800976a: 2b00 cmp r3, #0 800976c: da11 bge.n 8009792 { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 800976e: 7bbb ldrb r3, [r7, #14] 8009770: f003 020f and.w r2, r3, #15 8009774: 6879 ldr r1, [r7, #4] 8009776: 4613 mov r3, r2 8009778: 009b lsls r3, r3, #2 800977a: 4413 add r3, r2 800977c: 009b lsls r3, r3, #2 800977e: 440b add r3, r1 8009780: 3323 adds r3, #35 @ 0x23 8009782: 781b ldrb r3, [r3, #0] 8009784: 2b00 cmp r3, #0 8009786: d117 bne.n 80097b8 { USBD_CtlError(pdev, req); 8009788: 6839 ldr r1, [r7, #0] 800978a: 6878 ldr r0, [r7, #4] 800978c: f000 fbdb bl 8009f46 break; 8009790: e055 b.n 800983e } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 8009792: 7bbb ldrb r3, [r7, #14] 8009794: f003 020f and.w r2, r3, #15 8009798: 6879 ldr r1, [r7, #4] 800979a: 4613 mov r3, r2 800979c: 009b lsls r3, r3, #2 800979e: 4413 add r3, r2 80097a0: 009b lsls r3, r3, #2 80097a2: 440b add r3, r1 80097a4: f203 1363 addw r3, r3, #355 @ 0x163 80097a8: 781b ldrb r3, [r3, #0] 80097aa: 2b00 cmp r3, #0 80097ac: d104 bne.n 80097b8 { USBD_CtlError(pdev, req); 80097ae: 6839 ldr r1, [r7, #0] 80097b0: 6878 ldr r0, [r7, #4] 80097b2: f000 fbc8 bl 8009f46 break; 80097b6: e042 b.n 800983e } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80097b8: f997 300e ldrsb.w r3, [r7, #14] 80097bc: 2b00 cmp r3, #0 80097be: da0b bge.n 80097d8 80097c0: 7bbb ldrb r3, [r7, #14] 80097c2: f003 027f and.w r2, r3, #127 @ 0x7f 80097c6: 4613 mov r3, r2 80097c8: 009b lsls r3, r3, #2 80097ca: 4413 add r3, r2 80097cc: 009b lsls r3, r3, #2 80097ce: 3310 adds r3, #16 80097d0: 687a ldr r2, [r7, #4] 80097d2: 4413 add r3, r2 80097d4: 3304 adds r3, #4 80097d6: e00b b.n 80097f0 &pdev->ep_out[ep_addr & 0x7FU]; 80097d8: 7bbb ldrb r3, [r7, #14] 80097da: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80097de: 4613 mov r3, r2 80097e0: 009b lsls r3, r3, #2 80097e2: 4413 add r3, r2 80097e4: 009b lsls r3, r3, #2 80097e6: f503 73a8 add.w r3, r3, #336 @ 0x150 80097ea: 687a ldr r2, [r7, #4] 80097ec: 4413 add r3, r2 80097ee: 3304 adds r3, #4 80097f0: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 80097f2: 7bbb ldrb r3, [r7, #14] 80097f4: 2b00 cmp r3, #0 80097f6: d002 beq.n 80097fe 80097f8: 7bbb ldrb r3, [r7, #14] 80097fa: 2b80 cmp r3, #128 @ 0x80 80097fc: d103 bne.n 8009806 { pep->status = 0x0000U; 80097fe: 68bb ldr r3, [r7, #8] 8009800: 2200 movs r2, #0 8009802: 739a strb r2, [r3, #14] 8009804: e00e b.n 8009824 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 8009806: 7bbb ldrb r3, [r7, #14] 8009808: 4619 mov r1, r3 800980a: 6878 ldr r0, [r7, #4] 800980c: f001 f80c bl 800a828 8009810: 4603 mov r3, r0 8009812: 2b00 cmp r3, #0 8009814: d003 beq.n 800981e { pep->status = 0x0001U; 8009816: 68bb ldr r3, [r7, #8] 8009818: 2201 movs r2, #1 800981a: 739a strb r2, [r3, #14] 800981c: e002 b.n 8009824 } else { pep->status = 0x0000U; 800981e: 68bb ldr r3, [r7, #8] 8009820: 2200 movs r2, #0 8009822: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8009824: 68bb ldr r3, [r7, #8] 8009826: 330e adds r3, #14 8009828: 2202 movs r2, #2 800982a: 4619 mov r1, r3 800982c: 6878 ldr r0, [r7, #4] 800982e: f000 fc07 bl 800a040 break; 8009832: e004 b.n 800983e default: USBD_CtlError(pdev, req); 8009834: 6839 ldr r1, [r7, #0] 8009836: 6878 ldr r0, [r7, #4] 8009838: f000 fb85 bl 8009f46 break; 800983c: bf00 nop } break; 800983e: e004 b.n 800984a default: USBD_CtlError(pdev, req); 8009840: 6839 ldr r1, [r7, #0] 8009842: 6878 ldr r0, [r7, #4] 8009844: f000 fb7f bl 8009f46 break; 8009848: bf00 nop } break; 800984a: e005 b.n 8009858 default: USBD_CtlError(pdev, req); 800984c: 6839 ldr r1, [r7, #0] 800984e: 6878 ldr r0, [r7, #4] 8009850: f000 fb79 bl 8009f46 break; 8009854: e000 b.n 8009858 break; 8009856: bf00 nop } return ret; 8009858: 7bfb ldrb r3, [r7, #15] } 800985a: 4618 mov r0, r3 800985c: 3710 adds r7, #16 800985e: 46bd mov sp, r7 8009860: bd80 pop {r7, pc} ... 08009864 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009864: b580 push {r7, lr} 8009866: b084 sub sp, #16 8009868: af00 add r7, sp, #0 800986a: 6078 str r0, [r7, #4] 800986c: 6039 str r1, [r7, #0] uint16_t len = 0U; 800986e: 2300 movs r3, #0 8009870: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 8009872: 2300 movs r3, #0 8009874: 60fb str r3, [r7, #12] uint8_t err = 0U; 8009876: 2300 movs r3, #0 8009878: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 800987a: 683b ldr r3, [r7, #0] 800987c: 885b ldrh r3, [r3, #2] 800987e: 0a1b lsrs r3, r3, #8 8009880: b29b uxth r3, r3 8009882: 3b01 subs r3, #1 8009884: 2b0e cmp r3, #14 8009886: f200 8152 bhi.w 8009b2e 800988a: a201 add r2, pc, #4 @ (adr r2, 8009890 ) 800988c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009890: 08009901 .word 0x08009901 8009894: 08009919 .word 0x08009919 8009898: 08009959 .word 0x08009959 800989c: 08009b2f .word 0x08009b2f 80098a0: 08009b2f .word 0x08009b2f 80098a4: 08009acf .word 0x08009acf 80098a8: 08009afb .word 0x08009afb 80098ac: 08009b2f .word 0x08009b2f 80098b0: 08009b2f .word 0x08009b2f 80098b4: 08009b2f .word 0x08009b2f 80098b8: 08009b2f .word 0x08009b2f 80098bc: 08009b2f .word 0x08009b2f 80098c0: 08009b2f .word 0x08009b2f 80098c4: 08009b2f .word 0x08009b2f 80098c8: 080098cd .word 0x080098cd { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 80098cc: 687b ldr r3, [r7, #4] 80098ce: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80098d2: 69db ldr r3, [r3, #28] 80098d4: 2b00 cmp r3, #0 80098d6: d00b beq.n 80098f0 { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 80098d8: 687b ldr r3, [r7, #4] 80098da: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80098de: 69db ldr r3, [r3, #28] 80098e0: 687a ldr r2, [r7, #4] 80098e2: 7c12 ldrb r2, [r2, #16] 80098e4: f107 0108 add.w r1, r7, #8 80098e8: 4610 mov r0, r2 80098ea: 4798 blx r3 80098ec: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80098ee: e126 b.n 8009b3e USBD_CtlError(pdev, req); 80098f0: 6839 ldr r1, [r7, #0] 80098f2: 6878 ldr r0, [r7, #4] 80098f4: f000 fb27 bl 8009f46 err++; 80098f8: 7afb ldrb r3, [r7, #11] 80098fa: 3301 adds r3, #1 80098fc: 72fb strb r3, [r7, #11] break; 80098fe: e11e b.n 8009b3e #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 8009900: 687b ldr r3, [r7, #4] 8009902: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009906: 681b ldr r3, [r3, #0] 8009908: 687a ldr r2, [r7, #4] 800990a: 7c12 ldrb r2, [r2, #16] 800990c: f107 0108 add.w r1, r7, #8 8009910: 4610 mov r0, r2 8009912: 4798 blx r3 8009914: 60f8 str r0, [r7, #12] break; 8009916: e112 b.n 8009b3e case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009918: 687b ldr r3, [r7, #4] 800991a: 7c1b ldrb r3, [r3, #16] 800991c: 2b00 cmp r3, #0 800991e: d10d bne.n 800993c pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 8009920: 687b ldr r3, [r7, #4] 8009922: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009926: 6a9b ldr r3, [r3, #40] @ 0x28 8009928: f107 0208 add.w r2, r7, #8 800992c: 4610 mov r0, r2 800992e: 4798 blx r3 8009930: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 8009932: 68fb ldr r3, [r7, #12] 8009934: 3301 adds r3, #1 8009936: 2202 movs r2, #2 8009938: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 800993a: e100 b.n 8009b3e pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 800993c: 687b ldr r3, [r7, #4] 800993e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009942: 6adb ldr r3, [r3, #44] @ 0x2c 8009944: f107 0208 add.w r2, r7, #8 8009948: 4610 mov r0, r2 800994a: 4798 blx r3 800994c: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800994e: 68fb ldr r3, [r7, #12] 8009950: 3301 adds r3, #1 8009952: 2202 movs r2, #2 8009954: 701a strb r2, [r3, #0] break; 8009956: e0f2 b.n 8009b3e case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 8009958: 683b ldr r3, [r7, #0] 800995a: 885b ldrh r3, [r3, #2] 800995c: b2db uxtb r3, r3 800995e: 2b05 cmp r3, #5 8009960: f200 80ac bhi.w 8009abc 8009964: a201 add r2, pc, #4 @ (adr r2, 800996c ) 8009966: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800996a: bf00 nop 800996c: 08009985 .word 0x08009985 8009970: 080099b9 .word 0x080099b9 8009974: 080099ed .word 0x080099ed 8009978: 08009a21 .word 0x08009a21 800997c: 08009a55 .word 0x08009a55 8009980: 08009a89 .word 0x08009a89 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 8009984: 687b ldr r3, [r7, #4] 8009986: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800998a: 685b ldr r3, [r3, #4] 800998c: 2b00 cmp r3, #0 800998e: d00b beq.n 80099a8 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 8009990: 687b ldr r3, [r7, #4] 8009992: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009996: 685b ldr r3, [r3, #4] 8009998: 687a ldr r2, [r7, #4] 800999a: 7c12 ldrb r2, [r2, #16] 800999c: f107 0108 add.w r1, r7, #8 80099a0: 4610 mov r0, r2 80099a2: 4798 blx r3 80099a4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80099a6: e091 b.n 8009acc USBD_CtlError(pdev, req); 80099a8: 6839 ldr r1, [r7, #0] 80099aa: 6878 ldr r0, [r7, #4] 80099ac: f000 facb bl 8009f46 err++; 80099b0: 7afb ldrb r3, [r7, #11] 80099b2: 3301 adds r3, #1 80099b4: 72fb strb r3, [r7, #11] break; 80099b6: e089 b.n 8009acc case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 80099b8: 687b ldr r3, [r7, #4] 80099ba: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099be: 689b ldr r3, [r3, #8] 80099c0: 2b00 cmp r3, #0 80099c2: d00b beq.n 80099dc { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 80099c4: 687b ldr r3, [r7, #4] 80099c6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099ca: 689b ldr r3, [r3, #8] 80099cc: 687a ldr r2, [r7, #4] 80099ce: 7c12 ldrb r2, [r2, #16] 80099d0: f107 0108 add.w r1, r7, #8 80099d4: 4610 mov r0, r2 80099d6: 4798 blx r3 80099d8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80099da: e077 b.n 8009acc USBD_CtlError(pdev, req); 80099dc: 6839 ldr r1, [r7, #0] 80099de: 6878 ldr r0, [r7, #4] 80099e0: f000 fab1 bl 8009f46 err++; 80099e4: 7afb ldrb r3, [r7, #11] 80099e6: 3301 adds r3, #1 80099e8: 72fb strb r3, [r7, #11] break; 80099ea: e06f b.n 8009acc case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 80099ec: 687b ldr r3, [r7, #4] 80099ee: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099f2: 68db ldr r3, [r3, #12] 80099f4: 2b00 cmp r3, #0 80099f6: d00b beq.n 8009a10 { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 80099f8: 687b ldr r3, [r7, #4] 80099fa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099fe: 68db ldr r3, [r3, #12] 8009a00: 687a ldr r2, [r7, #4] 8009a02: 7c12 ldrb r2, [r2, #16] 8009a04: f107 0108 add.w r1, r7, #8 8009a08: 4610 mov r0, r2 8009a0a: 4798 blx r3 8009a0c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009a0e: e05d b.n 8009acc USBD_CtlError(pdev, req); 8009a10: 6839 ldr r1, [r7, #0] 8009a12: 6878 ldr r0, [r7, #4] 8009a14: f000 fa97 bl 8009f46 err++; 8009a18: 7afb ldrb r3, [r7, #11] 8009a1a: 3301 adds r3, #1 8009a1c: 72fb strb r3, [r7, #11] break; 8009a1e: e055 b.n 8009acc case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 8009a20: 687b ldr r3, [r7, #4] 8009a22: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a26: 691b ldr r3, [r3, #16] 8009a28: 2b00 cmp r3, #0 8009a2a: d00b beq.n 8009a44 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 8009a2c: 687b ldr r3, [r7, #4] 8009a2e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a32: 691b ldr r3, [r3, #16] 8009a34: 687a ldr r2, [r7, #4] 8009a36: 7c12 ldrb r2, [r2, #16] 8009a38: f107 0108 add.w r1, r7, #8 8009a3c: 4610 mov r0, r2 8009a3e: 4798 blx r3 8009a40: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009a42: e043 b.n 8009acc USBD_CtlError(pdev, req); 8009a44: 6839 ldr r1, [r7, #0] 8009a46: 6878 ldr r0, [r7, #4] 8009a48: f000 fa7d bl 8009f46 err++; 8009a4c: 7afb ldrb r3, [r7, #11] 8009a4e: 3301 adds r3, #1 8009a50: 72fb strb r3, [r7, #11] break; 8009a52: e03b b.n 8009acc case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 8009a54: 687b ldr r3, [r7, #4] 8009a56: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a5a: 695b ldr r3, [r3, #20] 8009a5c: 2b00 cmp r3, #0 8009a5e: d00b beq.n 8009a78 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 8009a60: 687b ldr r3, [r7, #4] 8009a62: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a66: 695b ldr r3, [r3, #20] 8009a68: 687a ldr r2, [r7, #4] 8009a6a: 7c12 ldrb r2, [r2, #16] 8009a6c: f107 0108 add.w r1, r7, #8 8009a70: 4610 mov r0, r2 8009a72: 4798 blx r3 8009a74: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009a76: e029 b.n 8009acc USBD_CtlError(pdev, req); 8009a78: 6839 ldr r1, [r7, #0] 8009a7a: 6878 ldr r0, [r7, #4] 8009a7c: f000 fa63 bl 8009f46 err++; 8009a80: 7afb ldrb r3, [r7, #11] 8009a82: 3301 adds r3, #1 8009a84: 72fb strb r3, [r7, #11] break; 8009a86: e021 b.n 8009acc case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 8009a88: 687b ldr r3, [r7, #4] 8009a8a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a8e: 699b ldr r3, [r3, #24] 8009a90: 2b00 cmp r3, #0 8009a92: d00b beq.n 8009aac { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8009a94: 687b ldr r3, [r7, #4] 8009a96: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a9a: 699b ldr r3, [r3, #24] 8009a9c: 687a ldr r2, [r7, #4] 8009a9e: 7c12 ldrb r2, [r2, #16] 8009aa0: f107 0108 add.w r1, r7, #8 8009aa4: 4610 mov r0, r2 8009aa6: 4798 blx r3 8009aa8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009aaa: e00f b.n 8009acc USBD_CtlError(pdev, req); 8009aac: 6839 ldr r1, [r7, #0] 8009aae: 6878 ldr r0, [r7, #4] 8009ab0: f000 fa49 bl 8009f46 err++; 8009ab4: 7afb ldrb r3, [r7, #11] 8009ab6: 3301 adds r3, #1 8009ab8: 72fb strb r3, [r7, #11] break; 8009aba: e007 b.n 8009acc err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8009abc: 6839 ldr r1, [r7, #0] 8009abe: 6878 ldr r0, [r7, #4] 8009ac0: f000 fa41 bl 8009f46 err++; 8009ac4: 7afb ldrb r3, [r7, #11] 8009ac6: 3301 adds r3, #1 8009ac8: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 8009aca: bf00 nop } break; 8009acc: e037 b.n 8009b3e case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009ace: 687b ldr r3, [r7, #4] 8009ad0: 7c1b ldrb r3, [r3, #16] 8009ad2: 2b00 cmp r3, #0 8009ad4: d109 bne.n 8009aea pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 8009ad6: 687b ldr r3, [r7, #4] 8009ad8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009adc: 6b5b ldr r3, [r3, #52] @ 0x34 8009ade: f107 0208 add.w r2, r7, #8 8009ae2: 4610 mov r0, r2 8009ae4: 4798 blx r3 8009ae6: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009ae8: e029 b.n 8009b3e USBD_CtlError(pdev, req); 8009aea: 6839 ldr r1, [r7, #0] 8009aec: 6878 ldr r0, [r7, #4] 8009aee: f000 fa2a bl 8009f46 err++; 8009af2: 7afb ldrb r3, [r7, #11] 8009af4: 3301 adds r3, #1 8009af6: 72fb strb r3, [r7, #11] break; 8009af8: e021 b.n 8009b3e case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009afa: 687b ldr r3, [r7, #4] 8009afc: 7c1b ldrb r3, [r3, #16] 8009afe: 2b00 cmp r3, #0 8009b00: d10d bne.n 8009b1e pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 8009b02: 687b ldr r3, [r7, #4] 8009b04: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009b08: 6b1b ldr r3, [r3, #48] @ 0x30 8009b0a: f107 0208 add.w r2, r7, #8 8009b0e: 4610 mov r0, r2 8009b10: 4798 blx r3 8009b12: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 8009b14: 68fb ldr r3, [r7, #12] 8009b16: 3301 adds r3, #1 8009b18: 2207 movs r2, #7 8009b1a: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 8009b1c: e00f b.n 8009b3e USBD_CtlError(pdev, req); 8009b1e: 6839 ldr r1, [r7, #0] 8009b20: 6878 ldr r0, [r7, #4] 8009b22: f000 fa10 bl 8009f46 err++; 8009b26: 7afb ldrb r3, [r7, #11] 8009b28: 3301 adds r3, #1 8009b2a: 72fb strb r3, [r7, #11] break; 8009b2c: e007 b.n 8009b3e default: USBD_CtlError(pdev, req); 8009b2e: 6839 ldr r1, [r7, #0] 8009b30: 6878 ldr r0, [r7, #4] 8009b32: f000 fa08 bl 8009f46 err++; 8009b36: 7afb ldrb r3, [r7, #11] 8009b38: 3301 adds r3, #1 8009b3a: 72fb strb r3, [r7, #11] break; 8009b3c: bf00 nop } if (err != 0U) 8009b3e: 7afb ldrb r3, [r7, #11] 8009b40: 2b00 cmp r3, #0 8009b42: d11e bne.n 8009b82 { return; } if (req->wLength != 0U) 8009b44: 683b ldr r3, [r7, #0] 8009b46: 88db ldrh r3, [r3, #6] 8009b48: 2b00 cmp r3, #0 8009b4a: d016 beq.n 8009b7a { if (len != 0U) 8009b4c: 893b ldrh r3, [r7, #8] 8009b4e: 2b00 cmp r3, #0 8009b50: d00e beq.n 8009b70 { len = MIN(len, req->wLength); 8009b52: 683b ldr r3, [r7, #0] 8009b54: 88da ldrh r2, [r3, #6] 8009b56: 893b ldrh r3, [r7, #8] 8009b58: 4293 cmp r3, r2 8009b5a: bf28 it cs 8009b5c: 4613 movcs r3, r2 8009b5e: b29b uxth r3, r3 8009b60: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 8009b62: 893b ldrh r3, [r7, #8] 8009b64: 461a mov r2, r3 8009b66: 68f9 ldr r1, [r7, #12] 8009b68: 6878 ldr r0, [r7, #4] 8009b6a: f000 fa69 bl 800a040 8009b6e: e009 b.n 8009b84 } else { USBD_CtlError(pdev, req); 8009b70: 6839 ldr r1, [r7, #0] 8009b72: 6878 ldr r0, [r7, #4] 8009b74: f000 f9e7 bl 8009f46 8009b78: e004 b.n 8009b84 } } else { (void)USBD_CtlSendStatus(pdev); 8009b7a: 6878 ldr r0, [r7, #4] 8009b7c: f000 faa0 bl 800a0c0 8009b80: e000 b.n 8009b84 return; 8009b82: bf00 nop } } 8009b84: 3710 adds r7, #16 8009b86: 46bd mov sp, r7 8009b88: bd80 pop {r7, pc} 8009b8a: bf00 nop 08009b8c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009b8c: b580 push {r7, lr} 8009b8e: b084 sub sp, #16 8009b90: af00 add r7, sp, #0 8009b92: 6078 str r0, [r7, #4] 8009b94: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 8009b96: 683b ldr r3, [r7, #0] 8009b98: 889b ldrh r3, [r3, #4] 8009b9a: 2b00 cmp r3, #0 8009b9c: d131 bne.n 8009c02 8009b9e: 683b ldr r3, [r7, #0] 8009ba0: 88db ldrh r3, [r3, #6] 8009ba2: 2b00 cmp r3, #0 8009ba4: d12d bne.n 8009c02 8009ba6: 683b ldr r3, [r7, #0] 8009ba8: 885b ldrh r3, [r3, #2] 8009baa: 2b7f cmp r3, #127 @ 0x7f 8009bac: d829 bhi.n 8009c02 { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 8009bae: 683b ldr r3, [r7, #0] 8009bb0: 885b ldrh r3, [r3, #2] 8009bb2: b2db uxtb r3, r3 8009bb4: f003 037f and.w r3, r3, #127 @ 0x7f 8009bb8: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009bba: 687b ldr r3, [r7, #4] 8009bbc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009bc0: b2db uxtb r3, r3 8009bc2: 2b03 cmp r3, #3 8009bc4: d104 bne.n 8009bd0 { USBD_CtlError(pdev, req); 8009bc6: 6839 ldr r1, [r7, #0] 8009bc8: 6878 ldr r0, [r7, #4] 8009bca: f000 f9bc bl 8009f46 if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009bce: e01d b.n 8009c0c } else { pdev->dev_address = dev_addr; 8009bd0: 687b ldr r3, [r7, #4] 8009bd2: 7bfa ldrb r2, [r7, #15] 8009bd4: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 8009bd8: 7bfb ldrb r3, [r7, #15] 8009bda: 4619 mov r1, r3 8009bdc: 6878 ldr r0, [r7, #4] 8009bde: f000 fe4f bl 800a880 (void)USBD_CtlSendStatus(pdev); 8009be2: 6878 ldr r0, [r7, #4] 8009be4: f000 fa6c bl 800a0c0 if (dev_addr != 0U) 8009be8: 7bfb ldrb r3, [r7, #15] 8009bea: 2b00 cmp r3, #0 8009bec: d004 beq.n 8009bf8 { pdev->dev_state = USBD_STATE_ADDRESSED; 8009bee: 687b ldr r3, [r7, #4] 8009bf0: 2202 movs r2, #2 8009bf2: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009bf6: e009 b.n 8009c0c } else { pdev->dev_state = USBD_STATE_DEFAULT; 8009bf8: 687b ldr r3, [r7, #4] 8009bfa: 2201 movs r2, #1 8009bfc: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009c00: e004 b.n 8009c0c } } } else { USBD_CtlError(pdev, req); 8009c02: 6839 ldr r1, [r7, #0] 8009c04: 6878 ldr r0, [r7, #4] 8009c06: f000 f99e bl 8009f46 } } 8009c0a: bf00 nop 8009c0c: bf00 nop 8009c0e: 3710 adds r7, #16 8009c10: 46bd mov sp, r7 8009c12: bd80 pop {r7, pc} 08009c14 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009c14: b580 push {r7, lr} 8009c16: b084 sub sp, #16 8009c18: af00 add r7, sp, #0 8009c1a: 6078 str r0, [r7, #4] 8009c1c: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009c1e: 2300 movs r3, #0 8009c20: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 8009c22: 683b ldr r3, [r7, #0] 8009c24: 885b ldrh r3, [r3, #2] 8009c26: b2da uxtb r2, r3 8009c28: 4b4e ldr r3, [pc, #312] @ (8009d64 ) 8009c2a: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 8009c2c: 4b4d ldr r3, [pc, #308] @ (8009d64 ) 8009c2e: 781b ldrb r3, [r3, #0] 8009c30: 2b01 cmp r3, #1 8009c32: d905 bls.n 8009c40 { USBD_CtlError(pdev, req); 8009c34: 6839 ldr r1, [r7, #0] 8009c36: 6878 ldr r0, [r7, #4] 8009c38: f000 f985 bl 8009f46 return USBD_FAIL; 8009c3c: 2303 movs r3, #3 8009c3e: e08c b.n 8009d5a } switch (pdev->dev_state) 8009c40: 687b ldr r3, [r7, #4] 8009c42: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009c46: b2db uxtb r3, r3 8009c48: 2b02 cmp r3, #2 8009c4a: d002 beq.n 8009c52 8009c4c: 2b03 cmp r3, #3 8009c4e: d029 beq.n 8009ca4 8009c50: e075 b.n 8009d3e { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 8009c52: 4b44 ldr r3, [pc, #272] @ (8009d64 ) 8009c54: 781b ldrb r3, [r3, #0] 8009c56: 2b00 cmp r3, #0 8009c58: d020 beq.n 8009c9c { pdev->dev_config = cfgidx; 8009c5a: 4b42 ldr r3, [pc, #264] @ (8009d64 ) 8009c5c: 781b ldrb r3, [r3, #0] 8009c5e: 461a mov r2, r3 8009c60: 687b ldr r3, [r7, #4] 8009c62: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009c64: 4b3f ldr r3, [pc, #252] @ (8009d64 ) 8009c66: 781b ldrb r3, [r3, #0] 8009c68: 4619 mov r1, r3 8009c6a: 6878 ldr r0, [r7, #4] 8009c6c: f7fe ffa3 bl 8008bb6 8009c70: 4603 mov r3, r0 8009c72: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009c74: 7bfb ldrb r3, [r7, #15] 8009c76: 2b00 cmp r3, #0 8009c78: d008 beq.n 8009c8c { USBD_CtlError(pdev, req); 8009c7a: 6839 ldr r1, [r7, #0] 8009c7c: 6878 ldr r0, [r7, #4] 8009c7e: f000 f962 bl 8009f46 pdev->dev_state = USBD_STATE_ADDRESSED; 8009c82: 687b ldr r3, [r7, #4] 8009c84: 2202 movs r2, #2 8009c86: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 8009c8a: e065 b.n 8009d58 (void)USBD_CtlSendStatus(pdev); 8009c8c: 6878 ldr r0, [r7, #4] 8009c8e: f000 fa17 bl 800a0c0 pdev->dev_state = USBD_STATE_CONFIGURED; 8009c92: 687b ldr r3, [r7, #4] 8009c94: 2203 movs r2, #3 8009c96: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009c9a: e05d b.n 8009d58 (void)USBD_CtlSendStatus(pdev); 8009c9c: 6878 ldr r0, [r7, #4] 8009c9e: f000 fa0f bl 800a0c0 break; 8009ca2: e059 b.n 8009d58 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8009ca4: 4b2f ldr r3, [pc, #188] @ (8009d64 ) 8009ca6: 781b ldrb r3, [r3, #0] 8009ca8: 2b00 cmp r3, #0 8009caa: d112 bne.n 8009cd2 { pdev->dev_state = USBD_STATE_ADDRESSED; 8009cac: 687b ldr r3, [r7, #4] 8009cae: 2202 movs r2, #2 8009cb0: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 8009cb4: 4b2b ldr r3, [pc, #172] @ (8009d64 ) 8009cb6: 781b ldrb r3, [r3, #0] 8009cb8: 461a mov r2, r3 8009cba: 687b ldr r3, [r7, #4] 8009cbc: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 8009cbe: 4b29 ldr r3, [pc, #164] @ (8009d64 ) 8009cc0: 781b ldrb r3, [r3, #0] 8009cc2: 4619 mov r1, r3 8009cc4: 6878 ldr r0, [r7, #4] 8009cc6: f7fe ff92 bl 8008bee (void)USBD_CtlSendStatus(pdev); 8009cca: 6878 ldr r0, [r7, #4] 8009ccc: f000 f9f8 bl 800a0c0 } else { (void)USBD_CtlSendStatus(pdev); } break; 8009cd0: e042 b.n 8009d58 else if (cfgidx != pdev->dev_config) 8009cd2: 4b24 ldr r3, [pc, #144] @ (8009d64 ) 8009cd4: 781b ldrb r3, [r3, #0] 8009cd6: 461a mov r2, r3 8009cd8: 687b ldr r3, [r7, #4] 8009cda: 685b ldr r3, [r3, #4] 8009cdc: 429a cmp r2, r3 8009cde: d02a beq.n 8009d36 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009ce0: 687b ldr r3, [r7, #4] 8009ce2: 685b ldr r3, [r3, #4] 8009ce4: b2db uxtb r3, r3 8009ce6: 4619 mov r1, r3 8009ce8: 6878 ldr r0, [r7, #4] 8009cea: f7fe ff80 bl 8008bee pdev->dev_config = cfgidx; 8009cee: 4b1d ldr r3, [pc, #116] @ (8009d64 ) 8009cf0: 781b ldrb r3, [r3, #0] 8009cf2: 461a mov r2, r3 8009cf4: 687b ldr r3, [r7, #4] 8009cf6: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009cf8: 4b1a ldr r3, [pc, #104] @ (8009d64 ) 8009cfa: 781b ldrb r3, [r3, #0] 8009cfc: 4619 mov r1, r3 8009cfe: 6878 ldr r0, [r7, #4] 8009d00: f7fe ff59 bl 8008bb6 8009d04: 4603 mov r3, r0 8009d06: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009d08: 7bfb ldrb r3, [r7, #15] 8009d0a: 2b00 cmp r3, #0 8009d0c: d00f beq.n 8009d2e USBD_CtlError(pdev, req); 8009d0e: 6839 ldr r1, [r7, #0] 8009d10: 6878 ldr r0, [r7, #4] 8009d12: f000 f918 bl 8009f46 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009d16: 687b ldr r3, [r7, #4] 8009d18: 685b ldr r3, [r3, #4] 8009d1a: b2db uxtb r3, r3 8009d1c: 4619 mov r1, r3 8009d1e: 6878 ldr r0, [r7, #4] 8009d20: f7fe ff65 bl 8008bee pdev->dev_state = USBD_STATE_ADDRESSED; 8009d24: 687b ldr r3, [r7, #4] 8009d26: 2202 movs r2, #2 8009d28: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009d2c: e014 b.n 8009d58 (void)USBD_CtlSendStatus(pdev); 8009d2e: 6878 ldr r0, [r7, #4] 8009d30: f000 f9c6 bl 800a0c0 break; 8009d34: e010 b.n 8009d58 (void)USBD_CtlSendStatus(pdev); 8009d36: 6878 ldr r0, [r7, #4] 8009d38: f000 f9c2 bl 800a0c0 break; 8009d3c: e00c b.n 8009d58 default: USBD_CtlError(pdev, req); 8009d3e: 6839 ldr r1, [r7, #0] 8009d40: 6878 ldr r0, [r7, #4] 8009d42: f000 f900 bl 8009f46 (void)USBD_ClrClassConfig(pdev, cfgidx); 8009d46: 4b07 ldr r3, [pc, #28] @ (8009d64 ) 8009d48: 781b ldrb r3, [r3, #0] 8009d4a: 4619 mov r1, r3 8009d4c: 6878 ldr r0, [r7, #4] 8009d4e: f7fe ff4e bl 8008bee ret = USBD_FAIL; 8009d52: 2303 movs r3, #3 8009d54: 73fb strb r3, [r7, #15] break; 8009d56: bf00 nop } return ret; 8009d58: 7bfb ldrb r3, [r7, #15] } 8009d5a: 4618 mov r0, r3 8009d5c: 3710 adds r7, #16 8009d5e: 46bd mov sp, r7 8009d60: bd80 pop {r7, pc} 8009d62: bf00 nop 8009d64: 20000734 .word 0x20000734 08009d68 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009d68: b580 push {r7, lr} 8009d6a: b082 sub sp, #8 8009d6c: af00 add r7, sp, #0 8009d6e: 6078 str r0, [r7, #4] 8009d70: 6039 str r1, [r7, #0] if (req->wLength != 1U) 8009d72: 683b ldr r3, [r7, #0] 8009d74: 88db ldrh r3, [r3, #6] 8009d76: 2b01 cmp r3, #1 8009d78: d004 beq.n 8009d84 { USBD_CtlError(pdev, req); 8009d7a: 6839 ldr r1, [r7, #0] 8009d7c: 6878 ldr r0, [r7, #4] 8009d7e: f000 f8e2 bl 8009f46 default: USBD_CtlError(pdev, req); break; } } } 8009d82: e023 b.n 8009dcc switch (pdev->dev_state) 8009d84: 687b ldr r3, [r7, #4] 8009d86: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d8a: b2db uxtb r3, r3 8009d8c: 2b02 cmp r3, #2 8009d8e: dc02 bgt.n 8009d96 8009d90: 2b00 cmp r3, #0 8009d92: dc03 bgt.n 8009d9c 8009d94: e015 b.n 8009dc2 8009d96: 2b03 cmp r3, #3 8009d98: d00b beq.n 8009db2 8009d9a: e012 b.n 8009dc2 pdev->dev_default_config = 0U; 8009d9c: 687b ldr r3, [r7, #4] 8009d9e: 2200 movs r2, #0 8009da0: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 8009da2: 687b ldr r3, [r7, #4] 8009da4: 3308 adds r3, #8 8009da6: 2201 movs r2, #1 8009da8: 4619 mov r1, r3 8009daa: 6878 ldr r0, [r7, #4] 8009dac: f000 f948 bl 800a040 break; 8009db0: e00c b.n 8009dcc (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 8009db2: 687b ldr r3, [r7, #4] 8009db4: 3304 adds r3, #4 8009db6: 2201 movs r2, #1 8009db8: 4619 mov r1, r3 8009dba: 6878 ldr r0, [r7, #4] 8009dbc: f000 f940 bl 800a040 break; 8009dc0: e004 b.n 8009dcc USBD_CtlError(pdev, req); 8009dc2: 6839 ldr r1, [r7, #0] 8009dc4: 6878 ldr r0, [r7, #4] 8009dc6: f000 f8be bl 8009f46 break; 8009dca: bf00 nop } 8009dcc: bf00 nop 8009dce: 3708 adds r7, #8 8009dd0: 46bd mov sp, r7 8009dd2: bd80 pop {r7, pc} 08009dd4 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009dd4: b580 push {r7, lr} 8009dd6: b082 sub sp, #8 8009dd8: af00 add r7, sp, #0 8009dda: 6078 str r0, [r7, #4] 8009ddc: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009dde: 687b ldr r3, [r7, #4] 8009de0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009de4: b2db uxtb r3, r3 8009de6: 3b01 subs r3, #1 8009de8: 2b02 cmp r3, #2 8009dea: d81e bhi.n 8009e2a { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 8009dec: 683b ldr r3, [r7, #0] 8009dee: 88db ldrh r3, [r3, #6] 8009df0: 2b02 cmp r3, #2 8009df2: d004 beq.n 8009dfe { USBD_CtlError(pdev, req); 8009df4: 6839 ldr r1, [r7, #0] 8009df6: 6878 ldr r0, [r7, #4] 8009df8: f000 f8a5 bl 8009f46 break; 8009dfc: e01a b.n 8009e34 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 8009dfe: 687b ldr r3, [r7, #4] 8009e00: 2201 movs r2, #1 8009e02: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 8009e04: 687b ldr r3, [r7, #4] 8009e06: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 8009e0a: 2b00 cmp r3, #0 8009e0c: d005 beq.n 8009e1a { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 8009e0e: 687b ldr r3, [r7, #4] 8009e10: 68db ldr r3, [r3, #12] 8009e12: f043 0202 orr.w r2, r3, #2 8009e16: 687b ldr r3, [r7, #4] 8009e18: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 8009e1a: 687b ldr r3, [r7, #4] 8009e1c: 330c adds r3, #12 8009e1e: 2202 movs r2, #2 8009e20: 4619 mov r1, r3 8009e22: 6878 ldr r0, [r7, #4] 8009e24: f000 f90c bl 800a040 break; 8009e28: e004 b.n 8009e34 default: USBD_CtlError(pdev, req); 8009e2a: 6839 ldr r1, [r7, #0] 8009e2c: 6878 ldr r0, [r7, #4] 8009e2e: f000 f88a bl 8009f46 break; 8009e32: bf00 nop } } 8009e34: bf00 nop 8009e36: 3708 adds r7, #8 8009e38: 46bd mov sp, r7 8009e3a: bd80 pop {r7, pc} 08009e3c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009e3c: b580 push {r7, lr} 8009e3e: b082 sub sp, #8 8009e40: af00 add r7, sp, #0 8009e42: 6078 str r0, [r7, #4] 8009e44: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009e46: 683b ldr r3, [r7, #0] 8009e48: 885b ldrh r3, [r3, #2] 8009e4a: 2b01 cmp r3, #1 8009e4c: d107 bne.n 8009e5e { pdev->dev_remote_wakeup = 1U; 8009e4e: 687b ldr r3, [r7, #4] 8009e50: 2201 movs r2, #1 8009e52: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009e56: 6878 ldr r0, [r7, #4] 8009e58: f000 f932 bl 800a0c0 } else { USBD_CtlError(pdev, req); } } 8009e5c: e013 b.n 8009e86 else if (req->wValue == USB_FEATURE_TEST_MODE) 8009e5e: 683b ldr r3, [r7, #0] 8009e60: 885b ldrh r3, [r3, #2] 8009e62: 2b02 cmp r3, #2 8009e64: d10b bne.n 8009e7e pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 8009e66: 683b ldr r3, [r7, #0] 8009e68: 889b ldrh r3, [r3, #4] 8009e6a: 0a1b lsrs r3, r3, #8 8009e6c: b29b uxth r3, r3 8009e6e: b2da uxtb r2, r3 8009e70: 687b ldr r3, [r7, #4] 8009e72: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 8009e76: 6878 ldr r0, [r7, #4] 8009e78: f000 f922 bl 800a0c0 } 8009e7c: e003 b.n 8009e86 USBD_CtlError(pdev, req); 8009e7e: 6839 ldr r1, [r7, #0] 8009e80: 6878 ldr r0, [r7, #4] 8009e82: f000 f860 bl 8009f46 } 8009e86: bf00 nop 8009e88: 3708 adds r7, #8 8009e8a: 46bd mov sp, r7 8009e8c: bd80 pop {r7, pc} 08009e8e : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009e8e: b580 push {r7, lr} 8009e90: b082 sub sp, #8 8009e92: af00 add r7, sp, #0 8009e94: 6078 str r0, [r7, #4] 8009e96: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009e98: 687b ldr r3, [r7, #4] 8009e9a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009e9e: b2db uxtb r3, r3 8009ea0: 3b01 subs r3, #1 8009ea2: 2b02 cmp r3, #2 8009ea4: d80b bhi.n 8009ebe { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009ea6: 683b ldr r3, [r7, #0] 8009ea8: 885b ldrh r3, [r3, #2] 8009eaa: 2b01 cmp r3, #1 8009eac: d10c bne.n 8009ec8 { pdev->dev_remote_wakeup = 0U; 8009eae: 687b ldr r3, [r7, #4] 8009eb0: 2200 movs r2, #0 8009eb2: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009eb6: 6878 ldr r0, [r7, #4] 8009eb8: f000 f902 bl 800a0c0 } break; 8009ebc: e004 b.n 8009ec8 default: USBD_CtlError(pdev, req); 8009ebe: 6839 ldr r1, [r7, #0] 8009ec0: 6878 ldr r0, [r7, #4] 8009ec2: f000 f840 bl 8009f46 break; 8009ec6: e000 b.n 8009eca break; 8009ec8: bf00 nop } } 8009eca: bf00 nop 8009ecc: 3708 adds r7, #8 8009ece: 46bd mov sp, r7 8009ed0: bd80 pop {r7, pc} 08009ed2 : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 8009ed2: b580 push {r7, lr} 8009ed4: b084 sub sp, #16 8009ed6: af00 add r7, sp, #0 8009ed8: 6078 str r0, [r7, #4] 8009eda: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 8009edc: 683b ldr r3, [r7, #0] 8009ede: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 8009ee0: 68fb ldr r3, [r7, #12] 8009ee2: 781a ldrb r2, [r3, #0] 8009ee4: 687b ldr r3, [r7, #4] 8009ee6: 701a strb r2, [r3, #0] pbuff++; 8009ee8: 68fb ldr r3, [r7, #12] 8009eea: 3301 adds r3, #1 8009eec: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 8009eee: 68fb ldr r3, [r7, #12] 8009ef0: 781a ldrb r2, [r3, #0] 8009ef2: 687b ldr r3, [r7, #4] 8009ef4: 705a strb r2, [r3, #1] pbuff++; 8009ef6: 68fb ldr r3, [r7, #12] 8009ef8: 3301 adds r3, #1 8009efa: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 8009efc: 68f8 ldr r0, [r7, #12] 8009efe: f7ff fa13 bl 8009328 8009f02: 4603 mov r3, r0 8009f04: 461a mov r2, r3 8009f06: 687b ldr r3, [r7, #4] 8009f08: 805a strh r2, [r3, #2] pbuff++; 8009f0a: 68fb ldr r3, [r7, #12] 8009f0c: 3301 adds r3, #1 8009f0e: 60fb str r3, [r7, #12] pbuff++; 8009f10: 68fb ldr r3, [r7, #12] 8009f12: 3301 adds r3, #1 8009f14: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 8009f16: 68f8 ldr r0, [r7, #12] 8009f18: f7ff fa06 bl 8009328 8009f1c: 4603 mov r3, r0 8009f1e: 461a mov r2, r3 8009f20: 687b ldr r3, [r7, #4] 8009f22: 809a strh r2, [r3, #4] pbuff++; 8009f24: 68fb ldr r3, [r7, #12] 8009f26: 3301 adds r3, #1 8009f28: 60fb str r3, [r7, #12] pbuff++; 8009f2a: 68fb ldr r3, [r7, #12] 8009f2c: 3301 adds r3, #1 8009f2e: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 8009f30: 68f8 ldr r0, [r7, #12] 8009f32: f7ff f9f9 bl 8009328 8009f36: 4603 mov r3, r0 8009f38: 461a mov r2, r3 8009f3a: 687b ldr r3, [r7, #4] 8009f3c: 80da strh r2, [r3, #6] } 8009f3e: bf00 nop 8009f40: 3710 adds r7, #16 8009f42: 46bd mov sp, r7 8009f44: bd80 pop {r7, pc} 08009f46 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009f46: b580 push {r7, lr} 8009f48: b082 sub sp, #8 8009f4a: af00 add r7, sp, #0 8009f4c: 6078 str r0, [r7, #4] 8009f4e: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 8009f50: 2180 movs r1, #128 @ 0x80 8009f52: 6878 ldr r0, [r7, #4] 8009f54: f000 fc2a bl 800a7ac (void)USBD_LL_StallEP(pdev, 0U); 8009f58: 2100 movs r1, #0 8009f5a: 6878 ldr r0, [r7, #4] 8009f5c: f000 fc26 bl 800a7ac } 8009f60: bf00 nop 8009f62: 3708 adds r7, #8 8009f64: 46bd mov sp, r7 8009f66: bd80 pop {r7, pc} 08009f68 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8009f68: b580 push {r7, lr} 8009f6a: b086 sub sp, #24 8009f6c: af00 add r7, sp, #0 8009f6e: 60f8 str r0, [r7, #12] 8009f70: 60b9 str r1, [r7, #8] 8009f72: 607a str r2, [r7, #4] uint8_t idx = 0U; 8009f74: 2300 movs r3, #0 8009f76: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8009f78: 68fb ldr r3, [r7, #12] 8009f7a: 2b00 cmp r3, #0 8009f7c: d042 beq.n 800a004 { return; } pdesc = desc; 8009f7e: 68fb ldr r3, [r7, #12] 8009f80: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 8009f82: 6938 ldr r0, [r7, #16] 8009f84: f000 f842 bl 800a00c 8009f88: 4603 mov r3, r0 8009f8a: 3301 adds r3, #1 8009f8c: 005b lsls r3, r3, #1 8009f8e: f5b3 7f00 cmp.w r3, #512 @ 0x200 8009f92: d808 bhi.n 8009fa6 8009f94: 6938 ldr r0, [r7, #16] 8009f96: f000 f839 bl 800a00c 8009f9a: 4603 mov r3, r0 8009f9c: 3301 adds r3, #1 8009f9e: b29b uxth r3, r3 8009fa0: 005b lsls r3, r3, #1 8009fa2: b29a uxth r2, r3 8009fa4: e001 b.n 8009faa 8009fa6: f44f 7200 mov.w r2, #512 @ 0x200 8009faa: 687b ldr r3, [r7, #4] 8009fac: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 8009fae: 7dfb ldrb r3, [r7, #23] 8009fb0: 68ba ldr r2, [r7, #8] 8009fb2: 4413 add r3, r2 8009fb4: 687a ldr r2, [r7, #4] 8009fb6: 7812 ldrb r2, [r2, #0] 8009fb8: 701a strb r2, [r3, #0] idx++; 8009fba: 7dfb ldrb r3, [r7, #23] 8009fbc: 3301 adds r3, #1 8009fbe: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 8009fc0: 7dfb ldrb r3, [r7, #23] 8009fc2: 68ba ldr r2, [r7, #8] 8009fc4: 4413 add r3, r2 8009fc6: 2203 movs r2, #3 8009fc8: 701a strb r2, [r3, #0] idx++; 8009fca: 7dfb ldrb r3, [r7, #23] 8009fcc: 3301 adds r3, #1 8009fce: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8009fd0: e013 b.n 8009ffa { unicode[idx] = *pdesc; 8009fd2: 7dfb ldrb r3, [r7, #23] 8009fd4: 68ba ldr r2, [r7, #8] 8009fd6: 4413 add r3, r2 8009fd8: 693a ldr r2, [r7, #16] 8009fda: 7812 ldrb r2, [r2, #0] 8009fdc: 701a strb r2, [r3, #0] pdesc++; 8009fde: 693b ldr r3, [r7, #16] 8009fe0: 3301 adds r3, #1 8009fe2: 613b str r3, [r7, #16] idx++; 8009fe4: 7dfb ldrb r3, [r7, #23] 8009fe6: 3301 adds r3, #1 8009fe8: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 8009fea: 7dfb ldrb r3, [r7, #23] 8009fec: 68ba ldr r2, [r7, #8] 8009fee: 4413 add r3, r2 8009ff0: 2200 movs r2, #0 8009ff2: 701a strb r2, [r3, #0] idx++; 8009ff4: 7dfb ldrb r3, [r7, #23] 8009ff6: 3301 adds r3, #1 8009ff8: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8009ffa: 693b ldr r3, [r7, #16] 8009ffc: 781b ldrb r3, [r3, #0] 8009ffe: 2b00 cmp r3, #0 800a000: d1e7 bne.n 8009fd2 800a002: e000 b.n 800a006 return; 800a004: bf00 nop } } 800a006: 3718 adds r7, #24 800a008: 46bd mov sp, r7 800a00a: bd80 pop {r7, pc} 0800a00c : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 800a00c: b480 push {r7} 800a00e: b085 sub sp, #20 800a010: af00 add r7, sp, #0 800a012: 6078 str r0, [r7, #4] uint8_t len = 0U; 800a014: 2300 movs r3, #0 800a016: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 800a018: 687b ldr r3, [r7, #4] 800a01a: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800a01c: e005 b.n 800a02a { len++; 800a01e: 7bfb ldrb r3, [r7, #15] 800a020: 3301 adds r3, #1 800a022: 73fb strb r3, [r7, #15] pbuff++; 800a024: 68bb ldr r3, [r7, #8] 800a026: 3301 adds r3, #1 800a028: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800a02a: 68bb ldr r3, [r7, #8] 800a02c: 781b ldrb r3, [r3, #0] 800a02e: 2b00 cmp r3, #0 800a030: d1f5 bne.n 800a01e } return len; 800a032: 7bfb ldrb r3, [r7, #15] } 800a034: 4618 mov r0, r3 800a036: 3714 adds r7, #20 800a038: 46bd mov sp, r7 800a03a: f85d 7b04 ldr.w r7, [sp], #4 800a03e: 4770 bx lr 0800a040 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a040: b580 push {r7, lr} 800a042: b084 sub sp, #16 800a044: af00 add r7, sp, #0 800a046: 60f8 str r0, [r7, #12] 800a048: 60b9 str r1, [r7, #8] 800a04a: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 800a04c: 68fb ldr r3, [r7, #12] 800a04e: 2202 movs r2, #2 800a050: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 800a054: 68fb ldr r3, [r7, #12] 800a056: 687a ldr r2, [r7, #4] 800a058: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 800a05a: 68fb ldr r3, [r7, #12] 800a05c: 68ba ldr r2, [r7, #8] 800a05e: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 800a060: 68fb ldr r3, [r7, #12] 800a062: 687a ldr r2, [r7, #4] 800a064: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a066: 687b ldr r3, [r7, #4] 800a068: 68ba ldr r2, [r7, #8] 800a06a: 2100 movs r1, #0 800a06c: 68f8 ldr r0, [r7, #12] 800a06e: f000 fc26 bl 800a8be return USBD_OK; 800a072: 2300 movs r3, #0 } 800a074: 4618 mov r0, r3 800a076: 3710 adds r7, #16 800a078: 46bd mov sp, r7 800a07a: bd80 pop {r7, pc} 0800a07c : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a07c: b580 push {r7, lr} 800a07e: b084 sub sp, #16 800a080: af00 add r7, sp, #0 800a082: 60f8 str r0, [r7, #12] 800a084: 60b9 str r1, [r7, #8] 800a086: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a088: 687b ldr r3, [r7, #4] 800a08a: 68ba ldr r2, [r7, #8] 800a08c: 2100 movs r1, #0 800a08e: 68f8 ldr r0, [r7, #12] 800a090: f000 fc15 bl 800a8be return USBD_OK; 800a094: 2300 movs r3, #0 } 800a096: 4618 mov r0, r3 800a098: 3710 adds r7, #16 800a09a: 46bd mov sp, r7 800a09c: bd80 pop {r7, pc} 0800a09e : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a09e: b580 push {r7, lr} 800a0a0: b084 sub sp, #16 800a0a2: af00 add r7, sp, #0 800a0a4: 60f8 str r0, [r7, #12] 800a0a6: 60b9 str r1, [r7, #8] 800a0a8: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800a0aa: 687b ldr r3, [r7, #4] 800a0ac: 68ba ldr r2, [r7, #8] 800a0ae: 2100 movs r1, #0 800a0b0: 68f8 ldr r0, [r7, #12] 800a0b2: f000 fc25 bl 800a900 return USBD_OK; 800a0b6: 2300 movs r3, #0 } 800a0b8: 4618 mov r0, r3 800a0ba: 3710 adds r7, #16 800a0bc: 46bd mov sp, r7 800a0be: bd80 pop {r7, pc} 0800a0c0 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 800a0c0: b580 push {r7, lr} 800a0c2: b082 sub sp, #8 800a0c4: af00 add r7, sp, #0 800a0c6: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 800a0c8: 687b ldr r3, [r7, #4] 800a0ca: 2204 movs r2, #4 800a0cc: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 800a0d0: 2300 movs r3, #0 800a0d2: 2200 movs r2, #0 800a0d4: 2100 movs r1, #0 800a0d6: 6878 ldr r0, [r7, #4] 800a0d8: f000 fbf1 bl 800a8be return USBD_OK; 800a0dc: 2300 movs r3, #0 } 800a0de: 4618 mov r0, r3 800a0e0: 3708 adds r7, #8 800a0e2: 46bd mov sp, r7 800a0e4: bd80 pop {r7, pc} 0800a0e6 : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 800a0e6: b580 push {r7, lr} 800a0e8: b082 sub sp, #8 800a0ea: af00 add r7, sp, #0 800a0ec: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 800a0ee: 687b ldr r3, [r7, #4] 800a0f0: 2205 movs r2, #5 800a0f2: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800a0f6: 2300 movs r3, #0 800a0f8: 2200 movs r2, #0 800a0fa: 2100 movs r1, #0 800a0fc: 6878 ldr r0, [r7, #4] 800a0fe: f000 fbff bl 800a900 return USBD_OK; 800a102: 2300 movs r3, #0 } 800a104: 4618 mov r0, r3 800a106: 3708 adds r7, #8 800a108: 46bd mov sp, r7 800a10a: bd80 pop {r7, pc} 0800a10c : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 800a10c: b580 push {r7, lr} 800a10e: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 800a110: 2200 movs r2, #0 800a112: 490e ldr r1, [pc, #56] @ (800a14c ) 800a114: 480e ldr r0, [pc, #56] @ (800a150 ) 800a116: f7fe fcd1 bl 8008abc 800a11a: 4603 mov r3, r0 800a11c: 2b00 cmp r3, #0 800a11e: d001 beq.n 800a124 { Error_Handler(); 800a120: f7f6 feec bl 8000efc } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) 800a124: 490b ldr r1, [pc, #44] @ (800a154 ) 800a126: 480a ldr r0, [pc, #40] @ (800a150 ) 800a128: f7fe fcf8 bl 8008b1c 800a12c: 4603 mov r3, r0 800a12e: 2b00 cmp r3, #0 800a130: d001 beq.n 800a136 { Error_Handler(); 800a132: f7f6 fee3 bl 8000efc } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 800a136: 4806 ldr r0, [pc, #24] @ (800a150 ) 800a138: f7fe fd26 bl 8008b88 800a13c: 4603 mov r3, r0 800a13e: 2b00 cmp r3, #0 800a140: d001 beq.n 800a146 { Error_Handler(); 800a142: f7f6 fedb bl 8000efc } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 800a146: bf00 nop 800a148: bd80 pop {r7, pc} 800a14a: bf00 nop 800a14c: 20000140 .word 0x20000140 800a150: 20000738 .word 0x20000738 800a154: 2000009c .word 0x2000009c 0800a158 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a158: b480 push {r7} 800a15a: b083 sub sp, #12 800a15c: af00 add r7, sp, #0 800a15e: 4603 mov r3, r0 800a160: 6039 str r1, [r7, #0] 800a162: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 800a164: 683b ldr r3, [r7, #0] 800a166: 2212 movs r2, #18 800a168: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 800a16a: 4b03 ldr r3, [pc, #12] @ (800a178 ) } 800a16c: 4618 mov r0, r3 800a16e: 370c adds r7, #12 800a170: 46bd mov sp, r7 800a172: f85d 7b04 ldr.w r7, [sp], #4 800a176: 4770 bx lr 800a178: 20000160 .word 0x20000160 0800a17c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a17c: b480 push {r7} 800a17e: b083 sub sp, #12 800a180: af00 add r7, sp, #0 800a182: 4603 mov r3, r0 800a184: 6039 str r1, [r7, #0] 800a186: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 800a188: 683b ldr r3, [r7, #0] 800a18a: 2204 movs r2, #4 800a18c: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800a18e: 4b03 ldr r3, [pc, #12] @ (800a19c ) } 800a190: 4618 mov r0, r3 800a192: 370c adds r7, #12 800a194: 46bd mov sp, r7 800a196: f85d 7b04 ldr.w r7, [sp], #4 800a19a: 4770 bx lr 800a19c: 20000180 .word 0x20000180 0800a1a0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a1a0: b580 push {r7, lr} 800a1a2: b082 sub sp, #8 800a1a4: af00 add r7, sp, #0 800a1a6: 4603 mov r3, r0 800a1a8: 6039 str r1, [r7, #0] 800a1aa: 71fb strb r3, [r7, #7] if(speed == 0) 800a1ac: 79fb ldrb r3, [r7, #7] 800a1ae: 2b00 cmp r3, #0 800a1b0: d105 bne.n 800a1be { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a1b2: 683a ldr r2, [r7, #0] 800a1b4: 4907 ldr r1, [pc, #28] @ (800a1d4 ) 800a1b6: 4808 ldr r0, [pc, #32] @ (800a1d8 ) 800a1b8: f7ff fed6 bl 8009f68 800a1bc: e004 b.n 800a1c8 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a1be: 683a ldr r2, [r7, #0] 800a1c0: 4904 ldr r1, [pc, #16] @ (800a1d4 ) 800a1c2: 4805 ldr r0, [pc, #20] @ (800a1d8 ) 800a1c4: f7ff fed0 bl 8009f68 } return USBD_StrDesc; 800a1c8: 4b02 ldr r3, [pc, #8] @ (800a1d4 ) } 800a1ca: 4618 mov r0, r3 800a1cc: 3708 adds r7, #8 800a1ce: 46bd mov sp, r7 800a1d0: bd80 pop {r7, pc} 800a1d2: bf00 nop 800a1d4: 20000a14 .word 0x20000a14 800a1d8: 0800aad8 .word 0x0800aad8 0800a1dc : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a1dc: b580 push {r7, lr} 800a1de: b082 sub sp, #8 800a1e0: af00 add r7, sp, #0 800a1e2: 4603 mov r3, r0 800a1e4: 6039 str r1, [r7, #0] 800a1e6: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800a1e8: 683a ldr r2, [r7, #0] 800a1ea: 4904 ldr r1, [pc, #16] @ (800a1fc ) 800a1ec: 4804 ldr r0, [pc, #16] @ (800a200 ) 800a1ee: f7ff febb bl 8009f68 return USBD_StrDesc; 800a1f2: 4b02 ldr r3, [pc, #8] @ (800a1fc ) } 800a1f4: 4618 mov r0, r3 800a1f6: 3708 adds r7, #8 800a1f8: 46bd mov sp, r7 800a1fa: bd80 pop {r7, pc} 800a1fc: 20000a14 .word 0x20000a14 800a200: 0800aaec .word 0x0800aaec 0800a204 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a204: b580 push {r7, lr} 800a206: b082 sub sp, #8 800a208: af00 add r7, sp, #0 800a20a: 4603 mov r3, r0 800a20c: 6039 str r1, [r7, #0] 800a20e: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800a210: 683b ldr r3, [r7, #0] 800a212: 221a movs r2, #26 800a214: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800a216: f000 f855 bl 800a2c4 /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800a21a: 4b02 ldr r3, [pc, #8] @ (800a224 ) } 800a21c: 4618 mov r0, r3 800a21e: 3708 adds r7, #8 800a220: 46bd mov sp, r7 800a222: bd80 pop {r7, pc} 800a224: 20000184 .word 0x20000184 0800a228 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a228: b580 push {r7, lr} 800a22a: b082 sub sp, #8 800a22c: af00 add r7, sp, #0 800a22e: 4603 mov r3, r0 800a230: 6039 str r1, [r7, #0] 800a232: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 800a234: 79fb ldrb r3, [r7, #7] 800a236: 2b00 cmp r3, #0 800a238: d105 bne.n 800a246 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a23a: 683a ldr r2, [r7, #0] 800a23c: 4907 ldr r1, [pc, #28] @ (800a25c ) 800a23e: 4808 ldr r0, [pc, #32] @ (800a260 ) 800a240: f7ff fe92 bl 8009f68 800a244: e004 b.n 800a250 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a246: 683a ldr r2, [r7, #0] 800a248: 4904 ldr r1, [pc, #16] @ (800a25c ) 800a24a: 4805 ldr r0, [pc, #20] @ (800a260 ) 800a24c: f7ff fe8c bl 8009f68 } return USBD_StrDesc; 800a250: 4b02 ldr r3, [pc, #8] @ (800a25c ) } 800a252: 4618 mov r0, r3 800a254: 3708 adds r7, #8 800a256: 46bd mov sp, r7 800a258: bd80 pop {r7, pc} 800a25a: bf00 nop 800a25c: 20000a14 .word 0x20000a14 800a260: 0800aaf8 .word 0x0800aaf8 0800a264 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a264: b580 push {r7, lr} 800a266: b082 sub sp, #8 800a268: af00 add r7, sp, #0 800a26a: 4603 mov r3, r0 800a26c: 6039 str r1, [r7, #0] 800a26e: 71fb strb r3, [r7, #7] if(speed == 0) 800a270: 79fb ldrb r3, [r7, #7] 800a272: 2b00 cmp r3, #0 800a274: d105 bne.n 800a282 { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a276: 683a ldr r2, [r7, #0] 800a278: 4907 ldr r1, [pc, #28] @ (800a298 ) 800a27a: 4808 ldr r0, [pc, #32] @ (800a29c ) 800a27c: f7ff fe74 bl 8009f68 800a280: e004 b.n 800a28c } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a282: 683a ldr r2, [r7, #0] 800a284: 4904 ldr r1, [pc, #16] @ (800a298 ) 800a286: 4805 ldr r0, [pc, #20] @ (800a29c ) 800a288: f7ff fe6e bl 8009f68 } return USBD_StrDesc; 800a28c: 4b02 ldr r3, [pc, #8] @ (800a298 ) } 800a28e: 4618 mov r0, r3 800a290: 3708 adds r7, #8 800a292: 46bd mov sp, r7 800a294: bd80 pop {r7, pc} 800a296: bf00 nop 800a298: 20000a14 .word 0x20000a14 800a29c: 0800ab04 .word 0x0800ab04 0800a2a0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a2a0: b480 push {r7} 800a2a2: b083 sub sp, #12 800a2a4: af00 add r7, sp, #0 800a2a6: 4603 mov r3, r0 800a2a8: 6039 str r1, [r7, #0] 800a2aa: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 800a2ac: 683b ldr r3, [r7, #0] 800a2ae: 220c movs r2, #12 800a2b0: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 800a2b2: 4b03 ldr r3, [pc, #12] @ (800a2c0 ) } 800a2b4: 4618 mov r0, r3 800a2b6: 370c adds r7, #12 800a2b8: 46bd mov sp, r7 800a2ba: f85d 7b04 ldr.w r7, [sp], #4 800a2be: 4770 bx lr 800a2c0: 20000174 .word 0x20000174 0800a2c4 : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800a2c4: b580 push {r7, lr} 800a2c6: b084 sub sp, #16 800a2c8: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 800a2ca: 4b0f ldr r3, [pc, #60] @ (800a308 ) 800a2cc: 681b ldr r3, [r3, #0] 800a2ce: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800a2d0: 4b0e ldr r3, [pc, #56] @ (800a30c ) 800a2d2: 681b ldr r3, [r3, #0] 800a2d4: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800a2d6: 4b0e ldr r3, [pc, #56] @ (800a310 ) 800a2d8: 681b ldr r3, [r3, #0] 800a2da: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 800a2dc: 68fa ldr r2, [r7, #12] 800a2de: 687b ldr r3, [r7, #4] 800a2e0: 4413 add r3, r2 800a2e2: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 800a2e4: 68fb ldr r3, [r7, #12] 800a2e6: 2b00 cmp r3, #0 800a2e8: d009 beq.n 800a2fe { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 800a2ea: 2208 movs r2, #8 800a2ec: 4909 ldr r1, [pc, #36] @ (800a314 ) 800a2ee: 68f8 ldr r0, [r7, #12] 800a2f0: f000 f814 bl 800a31c IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 800a2f4: 2204 movs r2, #4 800a2f6: 4908 ldr r1, [pc, #32] @ (800a318 ) 800a2f8: 68b8 ldr r0, [r7, #8] 800a2fa: f000 f80f bl 800a31c } } 800a2fe: bf00 nop 800a300: 3710 adds r7, #16 800a302: 46bd mov sp, r7 800a304: bd80 pop {r7, pc} 800a306: bf00 nop 800a308: 1fff7a10 .word 0x1fff7a10 800a30c: 1fff7a14 .word 0x1fff7a14 800a310: 1fff7a18 .word 0x1fff7a18 800a314: 20000186 .word 0x20000186 800a318: 20000196 .word 0x20000196 0800a31c : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800a31c: b480 push {r7} 800a31e: b087 sub sp, #28 800a320: af00 add r7, sp, #0 800a322: 60f8 str r0, [r7, #12] 800a324: 60b9 str r1, [r7, #8] 800a326: 4613 mov r3, r2 800a328: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800a32a: 2300 movs r3, #0 800a32c: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800a32e: 2300 movs r3, #0 800a330: 75fb strb r3, [r7, #23] 800a332: e027 b.n 800a384 { if (((value >> 28)) < 0xA) 800a334: 68fb ldr r3, [r7, #12] 800a336: 0f1b lsrs r3, r3, #28 800a338: 2b09 cmp r3, #9 800a33a: d80b bhi.n 800a354 { pbuf[2 * idx] = (value >> 28) + '0'; 800a33c: 68fb ldr r3, [r7, #12] 800a33e: 0f1b lsrs r3, r3, #28 800a340: b2da uxtb r2, r3 800a342: 7dfb ldrb r3, [r7, #23] 800a344: 005b lsls r3, r3, #1 800a346: 4619 mov r1, r3 800a348: 68bb ldr r3, [r7, #8] 800a34a: 440b add r3, r1 800a34c: 3230 adds r2, #48 @ 0x30 800a34e: b2d2 uxtb r2, r2 800a350: 701a strb r2, [r3, #0] 800a352: e00a b.n 800a36a } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800a354: 68fb ldr r3, [r7, #12] 800a356: 0f1b lsrs r3, r3, #28 800a358: b2da uxtb r2, r3 800a35a: 7dfb ldrb r3, [r7, #23] 800a35c: 005b lsls r3, r3, #1 800a35e: 4619 mov r1, r3 800a360: 68bb ldr r3, [r7, #8] 800a362: 440b add r3, r1 800a364: 3237 adds r2, #55 @ 0x37 800a366: b2d2 uxtb r2, r2 800a368: 701a strb r2, [r3, #0] } value = value << 4; 800a36a: 68fb ldr r3, [r7, #12] 800a36c: 011b lsls r3, r3, #4 800a36e: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 800a370: 7dfb ldrb r3, [r7, #23] 800a372: 005b lsls r3, r3, #1 800a374: 3301 adds r3, #1 800a376: 68ba ldr r2, [r7, #8] 800a378: 4413 add r3, r2 800a37a: 2200 movs r2, #0 800a37c: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800a37e: 7dfb ldrb r3, [r7, #23] 800a380: 3301 adds r3, #1 800a382: 75fb strb r3, [r7, #23] 800a384: 7dfa ldrb r2, [r7, #23] 800a386: 79fb ldrb r3, [r7, #7] 800a388: 429a cmp r2, r3 800a38a: d3d3 bcc.n 800a334 } } 800a38c: bf00 nop 800a38e: bf00 nop 800a390: 371c adds r7, #28 800a392: 46bd mov sp, r7 800a394: f85d 7b04 ldr.w r7, [sp], #4 800a398: 4770 bx lr ... 0800a39c : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 800a39c: b580 push {r7, lr} 800a39e: b0a0 sub sp, #128 @ 0x80 800a3a0: af00 add r7, sp, #0 800a3a2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a3a4: f107 036c add.w r3, r7, #108 @ 0x6c 800a3a8: 2200 movs r2, #0 800a3aa: 601a str r2, [r3, #0] 800a3ac: 605a str r2, [r3, #4] 800a3ae: 609a str r2, [r3, #8] 800a3b0: 60da str r2, [r3, #12] 800a3b2: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800a3b4: f107 0310 add.w r3, r7, #16 800a3b8: 225c movs r2, #92 @ 0x5c 800a3ba: 2100 movs r1, #0 800a3bc: 4618 mov r0, r3 800a3be: f000 fb53 bl 800aa68 if(pcdHandle->Instance==USB_OTG_FS) 800a3c2: 687b ldr r3, [r7, #4] 800a3c4: 681b ldr r3, [r3, #0] 800a3c6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800a3ca: d149 bne.n 800a460 /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 800a3cc: f44f 7380 mov.w r3, #256 @ 0x100 800a3d0: 613b str r3, [r7, #16] PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; 800a3d2: 2300 movs r3, #0 800a3d4: 667b str r3, [r7, #100] @ 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800a3d6: f107 0310 add.w r3, r7, #16 800a3da: 4618 mov r0, r3 800a3dc: f7f9 ffb4 bl 8004348 800a3e0: 4603 mov r3, r0 800a3e2: 2b00 cmp r3, #0 800a3e4: d001 beq.n 800a3ea { Error_Handler(); 800a3e6: f7f6 fd89 bl 8000efc } __HAL_RCC_GPIOA_CLK_ENABLE(); 800a3ea: 2300 movs r3, #0 800a3ec: 60fb str r3, [r7, #12] 800a3ee: 4b1e ldr r3, [pc, #120] @ (800a468 ) 800a3f0: 6b1b ldr r3, [r3, #48] @ 0x30 800a3f2: 4a1d ldr r2, [pc, #116] @ (800a468 ) 800a3f4: f043 0301 orr.w r3, r3, #1 800a3f8: 6313 str r3, [r2, #48] @ 0x30 800a3fa: 4b1b ldr r3, [pc, #108] @ (800a468 ) 800a3fc: 6b1b ldr r3, [r3, #48] @ 0x30 800a3fe: f003 0301 and.w r3, r3, #1 800a402: 60fb str r3, [r7, #12] 800a404: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 800a406: f44f 53c0 mov.w r3, #6144 @ 0x1800 800a40a: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800a40c: 2302 movs r3, #2 800a40e: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 800a410: 2300 movs r3, #0 800a412: 677b str r3, [r7, #116] @ 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800a414: 2303 movs r3, #3 800a416: 67bb str r3, [r7, #120] @ 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 800a418: 230a movs r3, #10 800a41a: 67fb str r3, [r7, #124] @ 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a41c: f107 036c add.w r3, r7, #108 @ 0x6c 800a420: 4619 mov r1, r3 800a422: 4812 ldr r0, [pc, #72] @ (800a46c ) 800a424: f7f8 f8e6 bl 80025f4 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800a428: 4b0f ldr r3, [pc, #60] @ (800a468 ) 800a42a: 6b5b ldr r3, [r3, #52] @ 0x34 800a42c: 4a0e ldr r2, [pc, #56] @ (800a468 ) 800a42e: f043 0380 orr.w r3, r3, #128 @ 0x80 800a432: 6353 str r3, [r2, #52] @ 0x34 800a434: 2300 movs r3, #0 800a436: 60bb str r3, [r7, #8] 800a438: 4b0b ldr r3, [pc, #44] @ (800a468 ) 800a43a: 6c5b ldr r3, [r3, #68] @ 0x44 800a43c: 4a0a ldr r2, [pc, #40] @ (800a468 ) 800a43e: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800a442: 6453 str r3, [r2, #68] @ 0x44 800a444: 4b08 ldr r3, [pc, #32] @ (800a468 ) 800a446: 6c5b ldr r3, [r3, #68] @ 0x44 800a448: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a44c: 60bb str r3, [r7, #8] 800a44e: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 800a450: 2200 movs r2, #0 800a452: 2100 movs r1, #0 800a454: 2043 movs r0, #67 @ 0x43 800a456: f7f7 fc94 bl 8001d82 HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 800a45a: 2043 movs r0, #67 @ 0x43 800a45c: f7f7 fcad bl 8001dba /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 800a460: bf00 nop 800a462: 3780 adds r7, #128 @ 0x80 800a464: 46bd mov sp, r7 800a466: bd80 pop {r7, pc} 800a468: 40023800 .word 0x40023800 800a46c: 40020000 .word 0x40020000 0800a470 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a470: b580 push {r7, lr} 800a472: b082 sub sp, #8 800a474: af00 add r7, sp, #0 800a476: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 800a478: 687b ldr r3, [r7, #4] 800a47a: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 800a47e: 687b ldr r3, [r7, #4] 800a480: f203 439c addw r3, r3, #1180 @ 0x49c 800a484: 4619 mov r1, r3 800a486: 4610 mov r0, r2 800a488: f7fe fbcb bl 8008c22 } 800a48c: bf00 nop 800a48e: 3708 adds r7, #8 800a490: 46bd mov sp, r7 800a492: bd80 pop {r7, pc} 0800a494 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a494: b580 push {r7, lr} 800a496: b082 sub sp, #8 800a498: af00 add r7, sp, #0 800a49a: 6078 str r0, [r7, #4] 800a49c: 460b mov r3, r1 800a49e: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 800a4a0: 687b ldr r3, [r7, #4] 800a4a2: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a4a6: 78fa ldrb r2, [r7, #3] 800a4a8: 6879 ldr r1, [r7, #4] 800a4aa: 4613 mov r3, r2 800a4ac: 00db lsls r3, r3, #3 800a4ae: 4413 add r3, r2 800a4b0: 009b lsls r3, r3, #2 800a4b2: 440b add r3, r1 800a4b4: f503 7318 add.w r3, r3, #608 @ 0x260 800a4b8: 681a ldr r2, [r3, #0] 800a4ba: 78fb ldrb r3, [r7, #3] 800a4bc: 4619 mov r1, r3 800a4be: f7fe fc05 bl 8008ccc } 800a4c2: bf00 nop 800a4c4: 3708 adds r7, #8 800a4c6: 46bd mov sp, r7 800a4c8: bd80 pop {r7, pc} 0800a4ca : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a4ca: b580 push {r7, lr} 800a4cc: b082 sub sp, #8 800a4ce: af00 add r7, sp, #0 800a4d0: 6078 str r0, [r7, #4] 800a4d2: 460b mov r3, r1 800a4d4: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800a4d6: 687b ldr r3, [r7, #4] 800a4d8: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a4dc: 78fa ldrb r2, [r7, #3] 800a4de: 6879 ldr r1, [r7, #4] 800a4e0: 4613 mov r3, r2 800a4e2: 00db lsls r3, r3, #3 800a4e4: 4413 add r3, r2 800a4e6: 009b lsls r3, r3, #2 800a4e8: 440b add r3, r1 800a4ea: 3320 adds r3, #32 800a4ec: 681a ldr r2, [r3, #0] 800a4ee: 78fb ldrb r3, [r7, #3] 800a4f0: 4619 mov r1, r3 800a4f2: f7fe fca7 bl 8008e44 } 800a4f6: bf00 nop 800a4f8: 3708 adds r7, #8 800a4fa: 46bd mov sp, r7 800a4fc: bd80 pop {r7, pc} 0800a4fe : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a4fe: b580 push {r7, lr} 800a500: b082 sub sp, #8 800a502: af00 add r7, sp, #0 800a504: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800a506: 687b ldr r3, [r7, #4] 800a508: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a50c: 4618 mov r0, r3 800a50e: f7fe fdeb bl 80090e8 } 800a512: bf00 nop 800a514: 3708 adds r7, #8 800a516: 46bd mov sp, r7 800a518: bd80 pop {r7, pc} 0800a51a : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a51a: b580 push {r7, lr} 800a51c: b084 sub sp, #16 800a51e: af00 add r7, sp, #0 800a520: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 800a522: 2301 movs r3, #1 800a524: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 800a526: 687b ldr r3, [r7, #4] 800a528: 79db ldrb r3, [r3, #7] 800a52a: 2b00 cmp r3, #0 800a52c: d102 bne.n 800a534 { speed = USBD_SPEED_HIGH; 800a52e: 2300 movs r3, #0 800a530: 73fb strb r3, [r7, #15] 800a532: e008 b.n 800a546 } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 800a534: 687b ldr r3, [r7, #4] 800a536: 79db ldrb r3, [r3, #7] 800a538: 2b02 cmp r3, #2 800a53a: d102 bne.n 800a542 { speed = USBD_SPEED_FULL; 800a53c: 2301 movs r3, #1 800a53e: 73fb strb r3, [r7, #15] 800a540: e001 b.n 800a546 } else { Error_Handler(); 800a542: f7f6 fcdb bl 8000efc } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800a546: 687b ldr r3, [r7, #4] 800a548: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a54c: 7bfa ldrb r2, [r7, #15] 800a54e: 4611 mov r1, r2 800a550: 4618 mov r0, r3 800a552: f7fe fd85 bl 8009060 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800a556: 687b ldr r3, [r7, #4] 800a558: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a55c: 4618 mov r0, r3 800a55e: f7fe fd2c bl 8008fba } 800a562: bf00 nop 800a564: 3710 adds r7, #16 800a566: 46bd mov sp, r7 800a568: bd80 pop {r7, pc} ... 0800a56c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a56c: b580 push {r7, lr} 800a56e: b082 sub sp, #8 800a570: af00 add r7, sp, #0 800a572: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800a574: 687b ldr r3, [r7, #4] 800a576: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a57a: 4618 mov r0, r3 800a57c: f7fe fd80 bl 8009080 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a580: 687b ldr r3, [r7, #4] 800a582: 681b ldr r3, [r3, #0] 800a584: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a588: 681b ldr r3, [r3, #0] 800a58a: 687a ldr r2, [r7, #4] 800a58c: 6812 ldr r2, [r2, #0] 800a58e: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a592: f043 0301 orr.w r3, r3, #1 800a596: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 800a598: 687b ldr r3, [r7, #4] 800a59a: 7adb ldrb r3, [r3, #11] 800a59c: 2b00 cmp r3, #0 800a59e: d005 beq.n 800a5ac { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a5a0: 4b04 ldr r3, [pc, #16] @ (800a5b4 ) 800a5a2: 691b ldr r3, [r3, #16] 800a5a4: 4a03 ldr r2, [pc, #12] @ (800a5b4 ) 800a5a6: f043 0306 orr.w r3, r3, #6 800a5aa: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 800a5ac: bf00 nop 800a5ae: 3708 adds r7, #8 800a5b0: 46bd mov sp, r7 800a5b2: bd80 pop {r7, pc} 800a5b4: e000ed00 .word 0xe000ed00 0800a5b8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5b8: b580 push {r7, lr} 800a5ba: b082 sub sp, #8 800a5bc: af00 add r7, sp, #0 800a5be: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 800a5c0: 687b ldr r3, [r7, #4] 800a5c2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a5c6: 4618 mov r0, r3 800a5c8: f7fe fd76 bl 80090b8 } 800a5cc: bf00 nop 800a5ce: 3708 adds r7, #8 800a5d0: 46bd mov sp, r7 800a5d2: bd80 pop {r7, pc} 0800a5d4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5d4: b580 push {r7, lr} 800a5d6: b082 sub sp, #8 800a5d8: af00 add r7, sp, #0 800a5da: 6078 str r0, [r7, #4] 800a5dc: 460b mov r3, r1 800a5de: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a5e0: 687b ldr r3, [r7, #4] 800a5e2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a5e6: 78fa ldrb r2, [r7, #3] 800a5e8: 4611 mov r1, r2 800a5ea: 4618 mov r0, r3 800a5ec: f7fe fdce bl 800918c } 800a5f0: bf00 nop 800a5f2: 3708 adds r7, #8 800a5f4: 46bd mov sp, r7 800a5f6: bd80 pop {r7, pc} 0800a5f8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5f8: b580 push {r7, lr} 800a5fa: b082 sub sp, #8 800a5fc: af00 add r7, sp, #0 800a5fe: 6078 str r0, [r7, #4] 800a600: 460b mov r3, r1 800a602: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a604: 687b ldr r3, [r7, #4] 800a606: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a60a: 78fa ldrb r2, [r7, #3] 800a60c: 4611 mov r1, r2 800a60e: 4618 mov r0, r3 800a610: f7fe fd8a bl 8009128 } 800a614: bf00 nop 800a616: 3708 adds r7, #8 800a618: 46bd mov sp, r7 800a61a: bd80 pop {r7, pc} 0800a61c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a61c: b580 push {r7, lr} 800a61e: b082 sub sp, #8 800a620: af00 add r7, sp, #0 800a622: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 800a624: 687b ldr r3, [r7, #4] 800a626: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a62a: 4618 mov r0, r3 800a62c: f7fe fde0 bl 80091f0 } 800a630: bf00 nop 800a632: 3708 adds r7, #8 800a634: 46bd mov sp, r7 800a636: bd80 pop {r7, pc} 0800a638 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a638: b580 push {r7, lr} 800a63a: b082 sub sp, #8 800a63c: af00 add r7, sp, #0 800a63e: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 800a640: 687b ldr r3, [r7, #4] 800a642: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a646: 4618 mov r0, r3 800a648: f7fe fddd bl 8009206 } 800a64c: bf00 nop 800a64e: 3708 adds r7, #8 800a650: 46bd mov sp, r7 800a652: bd80 pop {r7, pc} 0800a654 : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800a654: b580 push {r7, lr} 800a656: b082 sub sp, #8 800a658: af00 add r7, sp, #0 800a65a: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 800a65c: 687b ldr r3, [r7, #4] 800a65e: 781b ldrb r3, [r3, #0] 800a660: 2b00 cmp r3, #0 800a662: d13c bne.n 800a6de /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 800a664: 4a20 ldr r2, [pc, #128] @ (800a6e8 ) 800a666: 687b ldr r3, [r7, #4] 800a668: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 pdev->pData = &hpcd_USB_OTG_FS; 800a66c: 687b ldr r3, [r7, #4] 800a66e: 4a1e ldr r2, [pc, #120] @ (800a6e8 ) 800a670: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800a674: 4b1c ldr r3, [pc, #112] @ (800a6e8 ) 800a676: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 800a67a: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 800a67c: 4b1a ldr r3, [pc, #104] @ (800a6e8 ) 800a67e: 2206 movs r2, #6 800a680: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800a682: 4b19 ldr r3, [pc, #100] @ (800a6e8 ) 800a684: 2202 movs r2, #2 800a686: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 800a688: 4b17 ldr r3, [pc, #92] @ (800a6e8 ) 800a68a: 2200 movs r2, #0 800a68c: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 800a68e: 4b16 ldr r3, [pc, #88] @ (800a6e8 ) 800a690: 2202 movs r2, #2 800a692: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 800a694: 4b14 ldr r3, [pc, #80] @ (800a6e8 ) 800a696: 2200 movs r2, #0 800a698: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800a69a: 4b13 ldr r3, [pc, #76] @ (800a6e8 ) 800a69c: 2200 movs r2, #0 800a69e: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 800a6a0: 4b11 ldr r3, [pc, #68] @ (800a6e8 ) 800a6a2: 2200 movs r2, #0 800a6a4: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 800a6a6: 4b10 ldr r3, [pc, #64] @ (800a6e8 ) 800a6a8: 2200 movs r2, #0 800a6aa: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 800a6ac: 4b0e ldr r3, [pc, #56] @ (800a6e8 ) 800a6ae: 2200 movs r2, #0 800a6b0: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 800a6b2: 480d ldr r0, [pc, #52] @ (800a6e8 ) 800a6b4: f7f8 faa8 bl 8002c08 800a6b8: 4603 mov r3, r0 800a6ba: 2b00 cmp r3, #0 800a6bc: d001 beq.n 800a6c2 { Error_Handler( ); 800a6be: f7f6 fc1d bl 8000efc HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 800a6c2: 2180 movs r1, #128 @ 0x80 800a6c4: 4808 ldr r0, [pc, #32] @ (800a6e8 ) 800a6c6: f7f9 fcf0 bl 80040aa HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 800a6ca: 2240 movs r2, #64 @ 0x40 800a6cc: 2100 movs r1, #0 800a6ce: 4806 ldr r0, [pc, #24] @ (800a6e8 ) 800a6d0: f7f9 fca4 bl 800401c HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 800a6d4: 2280 movs r2, #128 @ 0x80 800a6d6: 2101 movs r1, #1 800a6d8: 4803 ldr r0, [pc, #12] @ (800a6e8 ) 800a6da: f7f9 fc9f bl 800401c } return USBD_OK; 800a6de: 2300 movs r3, #0 } 800a6e0: 4618 mov r0, r3 800a6e2: 3708 adds r7, #8 800a6e4: 46bd mov sp, r7 800a6e6: bd80 pop {r7, pc} 800a6e8: 20000c14 .word 0x20000c14 0800a6ec : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800a6ec: b580 push {r7, lr} 800a6ee: b084 sub sp, #16 800a6f0: af00 add r7, sp, #0 800a6f2: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800a6f4: 2300 movs r3, #0 800a6f6: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a6f8: 2300 movs r3, #0 800a6fa: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800a6fc: 687b ldr r3, [r7, #4] 800a6fe: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a702: 4618 mov r0, r3 800a704: f7f8 fb96 bl 8002e34 800a708: 4603 mov r3, r0 800a70a: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a70c: 7bfb ldrb r3, [r7, #15] 800a70e: 4618 mov r0, r3 800a710: f000 f97e bl 800aa10 800a714: 4603 mov r3, r0 800a716: 73bb strb r3, [r7, #14] return usb_status; 800a718: 7bbb ldrb r3, [r7, #14] } 800a71a: 4618 mov r0, r3 800a71c: 3710 adds r7, #16 800a71e: 46bd mov sp, r7 800a720: bd80 pop {r7, pc} 0800a722 : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800a722: b580 push {r7, lr} 800a724: b084 sub sp, #16 800a726: af00 add r7, sp, #0 800a728: 6078 str r0, [r7, #4] 800a72a: 4608 mov r0, r1 800a72c: 4611 mov r1, r2 800a72e: 461a mov r2, r3 800a730: 4603 mov r3, r0 800a732: 70fb strb r3, [r7, #3] 800a734: 460b mov r3, r1 800a736: 70bb strb r3, [r7, #2] 800a738: 4613 mov r3, r2 800a73a: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800a73c: 2300 movs r3, #0 800a73e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a740: 2300 movs r3, #0 800a742: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800a744: 687b ldr r3, [r7, #4] 800a746: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a74a: 78bb ldrb r3, [r7, #2] 800a74c: 883a ldrh r2, [r7, #0] 800a74e: 78f9 ldrb r1, [r7, #3] 800a750: f7f9 f897 bl 8003882 800a754: 4603 mov r3, r0 800a756: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a758: 7bfb ldrb r3, [r7, #15] 800a75a: 4618 mov r0, r3 800a75c: f000 f958 bl 800aa10 800a760: 4603 mov r3, r0 800a762: 73bb strb r3, [r7, #14] return usb_status; 800a764: 7bbb ldrb r3, [r7, #14] } 800a766: 4618 mov r0, r3 800a768: 3710 adds r7, #16 800a76a: 46bd mov sp, r7 800a76c: bd80 pop {r7, pc} 0800a76e : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a76e: b580 push {r7, lr} 800a770: b084 sub sp, #16 800a772: af00 add r7, sp, #0 800a774: 6078 str r0, [r7, #4] 800a776: 460b mov r3, r1 800a778: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a77a: 2300 movs r3, #0 800a77c: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a77e: 2300 movs r3, #0 800a780: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800a782: 687b ldr r3, [r7, #4] 800a784: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a788: 78fa ldrb r2, [r7, #3] 800a78a: 4611 mov r1, r2 800a78c: 4618 mov r0, r3 800a78e: f7f9 f8e2 bl 8003956 800a792: 4603 mov r3, r0 800a794: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a796: 7bfb ldrb r3, [r7, #15] 800a798: 4618 mov r0, r3 800a79a: f000 f939 bl 800aa10 800a79e: 4603 mov r3, r0 800a7a0: 73bb strb r3, [r7, #14] return usb_status; 800a7a2: 7bbb ldrb r3, [r7, #14] } 800a7a4: 4618 mov r0, r3 800a7a6: 3710 adds r7, #16 800a7a8: 46bd mov sp, r7 800a7aa: bd80 pop {r7, pc} 0800a7ac : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a7ac: b580 push {r7, lr} 800a7ae: b084 sub sp, #16 800a7b0: af00 add r7, sp, #0 800a7b2: 6078 str r0, [r7, #4] 800a7b4: 460b mov r3, r1 800a7b6: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a7b8: 2300 movs r3, #0 800a7ba: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a7bc: 2300 movs r3, #0 800a7be: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800a7c0: 687b ldr r3, [r7, #4] 800a7c2: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a7c6: 78fa ldrb r2, [r7, #3] 800a7c8: 4611 mov r1, r2 800a7ca: 4618 mov r0, r3 800a7cc: f7f9 f982 bl 8003ad4 800a7d0: 4603 mov r3, r0 800a7d2: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a7d4: 7bfb ldrb r3, [r7, #15] 800a7d6: 4618 mov r0, r3 800a7d8: f000 f91a bl 800aa10 800a7dc: 4603 mov r3, r0 800a7de: 73bb strb r3, [r7, #14] return usb_status; 800a7e0: 7bbb ldrb r3, [r7, #14] } 800a7e2: 4618 mov r0, r3 800a7e4: 3710 adds r7, #16 800a7e6: 46bd mov sp, r7 800a7e8: bd80 pop {r7, pc} 0800a7ea : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a7ea: b580 push {r7, lr} 800a7ec: b084 sub sp, #16 800a7ee: af00 add r7, sp, #0 800a7f0: 6078 str r0, [r7, #4] 800a7f2: 460b mov r3, r1 800a7f4: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a7f6: 2300 movs r3, #0 800a7f8: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a7fa: 2300 movs r3, #0 800a7fc: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800a7fe: 687b ldr r3, [r7, #4] 800a800: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a804: 78fa ldrb r2, [r7, #3] 800a806: 4611 mov r1, r2 800a808: 4618 mov r0, r3 800a80a: f7f9 f9c6 bl 8003b9a 800a80e: 4603 mov r3, r0 800a810: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a812: 7bfb ldrb r3, [r7, #15] 800a814: 4618 mov r0, r3 800a816: f000 f8fb bl 800aa10 800a81a: 4603 mov r3, r0 800a81c: 73bb strb r3, [r7, #14] return usb_status; 800a81e: 7bbb ldrb r3, [r7, #14] } 800a820: 4618 mov r0, r3 800a822: 3710 adds r7, #16 800a824: 46bd mov sp, r7 800a826: bd80 pop {r7, pc} 0800a828 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a828: b480 push {r7} 800a82a: b085 sub sp, #20 800a82c: af00 add r7, sp, #0 800a82e: 6078 str r0, [r7, #4] 800a830: 460b mov r3, r1 800a832: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800a834: 687b ldr r3, [r7, #4] 800a836: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a83a: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800a83c: f997 3003 ldrsb.w r3, [r7, #3] 800a840: 2b00 cmp r3, #0 800a842: da0b bge.n 800a85c { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800a844: 78fb ldrb r3, [r7, #3] 800a846: f003 027f and.w r2, r3, #127 @ 0x7f 800a84a: 68f9 ldr r1, [r7, #12] 800a84c: 4613 mov r3, r2 800a84e: 00db lsls r3, r3, #3 800a850: 4413 add r3, r2 800a852: 009b lsls r3, r3, #2 800a854: 440b add r3, r1 800a856: 3316 adds r3, #22 800a858: 781b ldrb r3, [r3, #0] 800a85a: e00b b.n 800a874 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800a85c: 78fb ldrb r3, [r7, #3] 800a85e: f003 027f and.w r2, r3, #127 @ 0x7f 800a862: 68f9 ldr r1, [r7, #12] 800a864: 4613 mov r3, r2 800a866: 00db lsls r3, r3, #3 800a868: 4413 add r3, r2 800a86a: 009b lsls r3, r3, #2 800a86c: 440b add r3, r1 800a86e: f203 2356 addw r3, r3, #598 @ 0x256 800a872: 781b ldrb r3, [r3, #0] } } 800a874: 4618 mov r0, r3 800a876: 3714 adds r7, #20 800a878: 46bd mov sp, r7 800a87a: f85d 7b04 ldr.w r7, [sp], #4 800a87e: 4770 bx lr 0800a880 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800a880: b580 push {r7, lr} 800a882: b084 sub sp, #16 800a884: af00 add r7, sp, #0 800a886: 6078 str r0, [r7, #4] 800a888: 460b mov r3, r1 800a88a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a88c: 2300 movs r3, #0 800a88e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a890: 2300 movs r3, #0 800a892: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800a894: 687b ldr r3, [r7, #4] 800a896: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a89a: 78fa ldrb r2, [r7, #3] 800a89c: 4611 mov r1, r2 800a89e: 4618 mov r0, r3 800a8a0: f7f8 ffcb bl 800383a 800a8a4: 4603 mov r3, r0 800a8a6: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a8a8: 7bfb ldrb r3, [r7, #15] 800a8aa: 4618 mov r0, r3 800a8ac: f000 f8b0 bl 800aa10 800a8b0: 4603 mov r3, r0 800a8b2: 73bb strb r3, [r7, #14] return usb_status; 800a8b4: 7bbb ldrb r3, [r7, #14] } 800a8b6: 4618 mov r0, r3 800a8b8: 3710 adds r7, #16 800a8ba: 46bd mov sp, r7 800a8bc: bd80 pop {r7, pc} 0800a8be : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a8be: b580 push {r7, lr} 800a8c0: b086 sub sp, #24 800a8c2: af00 add r7, sp, #0 800a8c4: 60f8 str r0, [r7, #12] 800a8c6: 607a str r2, [r7, #4] 800a8c8: 603b str r3, [r7, #0] 800a8ca: 460b mov r3, r1 800a8cc: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a8ce: 2300 movs r3, #0 800a8d0: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a8d2: 2300 movs r3, #0 800a8d4: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800a8d6: 68fb ldr r3, [r7, #12] 800a8d8: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a8dc: 7af9 ldrb r1, [r7, #11] 800a8de: 683b ldr r3, [r7, #0] 800a8e0: 687a ldr r2, [r7, #4] 800a8e2: f7f9 f8bd bl 8003a60 800a8e6: 4603 mov r3, r0 800a8e8: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a8ea: 7dfb ldrb r3, [r7, #23] 800a8ec: 4618 mov r0, r3 800a8ee: f000 f88f bl 800aa10 800a8f2: 4603 mov r3, r0 800a8f4: 75bb strb r3, [r7, #22] return usb_status; 800a8f6: 7dbb ldrb r3, [r7, #22] } 800a8f8: 4618 mov r0, r3 800a8fa: 3718 adds r7, #24 800a8fc: 46bd mov sp, r7 800a8fe: bd80 pop {r7, pc} 0800a900 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a900: b580 push {r7, lr} 800a902: b086 sub sp, #24 800a904: af00 add r7, sp, #0 800a906: 60f8 str r0, [r7, #12] 800a908: 607a str r2, [r7, #4] 800a90a: 603b str r3, [r7, #0] 800a90c: 460b mov r3, r1 800a90e: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a910: 2300 movs r3, #0 800a912: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a914: 2300 movs r3, #0 800a916: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800a918: 68fb ldr r3, [r7, #12] 800a91a: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a91e: 7af9 ldrb r1, [r7, #11] 800a920: 683b ldr r3, [r7, #0] 800a922: 687a ldr r2, [r7, #4] 800a924: f7f9 f861 bl 80039ea 800a928: 4603 mov r3, r0 800a92a: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a92c: 7dfb ldrb r3, [r7, #23] 800a92e: 4618 mov r0, r3 800a930: f000 f86e bl 800aa10 800a934: 4603 mov r3, r0 800a936: 75bb strb r3, [r7, #22] return usb_status; 800a938: 7dbb ldrb r3, [r7, #22] } 800a93a: 4618 mov r0, r3 800a93c: 3718 adds r7, #24 800a93e: 46bd mov sp, r7 800a940: bd80 pop {r7, pc} ... 0800a944 : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 800a944: b580 push {r7, lr} 800a946: b082 sub sp, #8 800a948: af00 add r7, sp, #0 800a94a: 6078 str r0, [r7, #4] 800a94c: 460b mov r3, r1 800a94e: 70fb strb r3, [r7, #3] switch (msg) 800a950: 78fb ldrb r3, [r7, #3] 800a952: 2b00 cmp r3, #0 800a954: d002 beq.n 800a95c 800a956: 2b01 cmp r3, #1 800a958: d01f beq.n 800a99a /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 800a95a: e03b b.n 800a9d4 if (hpcd->Init.low_power_enable) 800a95c: 687b ldr r3, [r7, #4] 800a95e: 7adb ldrb r3, [r3, #11] 800a960: 2b00 cmp r3, #0 800a962: d007 beq.n 800a974 SystemClock_Config(); 800a964: f7f6 f844 bl 80009f0 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a968: 4b1c ldr r3, [pc, #112] @ (800a9dc ) 800a96a: 691b ldr r3, [r3, #16] 800a96c: 4a1b ldr r2, [pc, #108] @ (800a9dc ) 800a96e: f023 0306 bic.w r3, r3, #6 800a972: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 800a974: 687b ldr r3, [r7, #4] 800a976: 681b ldr r3, [r3, #0] 800a978: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a97c: 681b ldr r3, [r3, #0] 800a97e: 687a ldr r2, [r7, #4] 800a980: 6812 ldr r2, [r2, #0] 800a982: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a986: f023 0301 bic.w r3, r3, #1 800a98a: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 800a98c: 687b ldr r3, [r7, #4] 800a98e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a992: 4618 mov r0, r3 800a994: f7fe fb90 bl 80090b8 break; 800a998: e01c b.n 800a9d4 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a99a: 687b ldr r3, [r7, #4] 800a99c: 681b ldr r3, [r3, #0] 800a99e: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a9a2: 681b ldr r3, [r3, #0] 800a9a4: 687a ldr r2, [r7, #4] 800a9a6: 6812 ldr r2, [r2, #0] 800a9a8: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a9ac: f043 0301 orr.w r3, r3, #1 800a9b0: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 800a9b2: 687b ldr r3, [r7, #4] 800a9b4: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a9b8: 4618 mov r0, r3 800a9ba: f7fe fb61 bl 8009080 if (hpcd->Init.low_power_enable) 800a9be: 687b ldr r3, [r7, #4] 800a9c0: 7adb ldrb r3, [r3, #11] 800a9c2: 2b00 cmp r3, #0 800a9c4: d005 beq.n 800a9d2 SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a9c6: 4b05 ldr r3, [pc, #20] @ (800a9dc ) 800a9c8: 691b ldr r3, [r3, #16] 800a9ca: 4a04 ldr r2, [pc, #16] @ (800a9dc ) 800a9cc: f043 0306 orr.w r3, r3, #6 800a9d0: 6113 str r3, [r2, #16] break; 800a9d2: bf00 nop } 800a9d4: bf00 nop 800a9d6: 3708 adds r7, #8 800a9d8: 46bd mov sp, r7 800a9da: bd80 pop {r7, pc} 800a9dc: e000ed00 .word 0xe000ed00 0800a9e0 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800a9e0: b480 push {r7} 800a9e2: b083 sub sp, #12 800a9e4: af00 add r7, sp, #0 800a9e6: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800a9e8: 4b03 ldr r3, [pc, #12] @ (800a9f8 ) } 800a9ea: 4618 mov r0, r3 800a9ec: 370c adds r7, #12 800a9ee: 46bd mov sp, r7 800a9f0: f85d 7b04 ldr.w r7, [sp], #4 800a9f4: 4770 bx lr 800a9f6: bf00 nop 800a9f8: 200010f8 .word 0x200010f8 0800a9fc : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800a9fc: b480 push {r7} 800a9fe: b083 sub sp, #12 800aa00: af00 add r7, sp, #0 800aa02: 6078 str r0, [r7, #4] } 800aa04: bf00 nop 800aa06: 370c adds r7, #12 800aa08: 46bd mov sp, r7 800aa0a: f85d 7b04 ldr.w r7, [sp], #4 800aa0e: 4770 bx lr 0800aa10 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800aa10: b480 push {r7} 800aa12: b085 sub sp, #20 800aa14: af00 add r7, sp, #0 800aa16: 4603 mov r3, r0 800aa18: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800aa1a: 2300 movs r3, #0 800aa1c: 73fb strb r3, [r7, #15] switch (hal_status) 800aa1e: 79fb ldrb r3, [r7, #7] 800aa20: 2b03 cmp r3, #3 800aa22: d817 bhi.n 800aa54 800aa24: a201 add r2, pc, #4 @ (adr r2, 800aa2c ) 800aa26: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800aa2a: bf00 nop 800aa2c: 0800aa3d .word 0x0800aa3d 800aa30: 0800aa43 .word 0x0800aa43 800aa34: 0800aa49 .word 0x0800aa49 800aa38: 0800aa4f .word 0x0800aa4f { case HAL_OK : usb_status = USBD_OK; 800aa3c: 2300 movs r3, #0 800aa3e: 73fb strb r3, [r7, #15] break; 800aa40: e00b b.n 800aa5a case HAL_ERROR : usb_status = USBD_FAIL; 800aa42: 2303 movs r3, #3 800aa44: 73fb strb r3, [r7, #15] break; 800aa46: e008 b.n 800aa5a case HAL_BUSY : usb_status = USBD_BUSY; 800aa48: 2301 movs r3, #1 800aa4a: 73fb strb r3, [r7, #15] break; 800aa4c: e005 b.n 800aa5a case HAL_TIMEOUT : usb_status = USBD_FAIL; 800aa4e: 2303 movs r3, #3 800aa50: 73fb strb r3, [r7, #15] break; 800aa52: e002 b.n 800aa5a default : usb_status = USBD_FAIL; 800aa54: 2303 movs r3, #3 800aa56: 73fb strb r3, [r7, #15] break; 800aa58: bf00 nop } return usb_status; 800aa5a: 7bfb ldrb r3, [r7, #15] } 800aa5c: 4618 mov r0, r3 800aa5e: 3714 adds r7, #20 800aa60: 46bd mov sp, r7 800aa62: f85d 7b04 ldr.w r7, [sp], #4 800aa66: 4770 bx lr 0800aa68 : 800aa68: 4402 add r2, r0 800aa6a: 4603 mov r3, r0 800aa6c: 4293 cmp r3, r2 800aa6e: d100 bne.n 800aa72 800aa70: 4770 bx lr 800aa72: f803 1b01 strb.w r1, [r3], #1 800aa76: e7f9 b.n 800aa6c 0800aa78 <__libc_init_array>: 800aa78: b570 push {r4, r5, r6, lr} 800aa7a: 4d0d ldr r5, [pc, #52] @ (800aab0 <__libc_init_array+0x38>) 800aa7c: 4c0d ldr r4, [pc, #52] @ (800aab4 <__libc_init_array+0x3c>) 800aa7e: 1b64 subs r4, r4, r5 800aa80: 10a4 asrs r4, r4, #2 800aa82: 2600 movs r6, #0 800aa84: 42a6 cmp r6, r4 800aa86: d109 bne.n 800aa9c <__libc_init_array+0x24> 800aa88: 4d0b ldr r5, [pc, #44] @ (800aab8 <__libc_init_array+0x40>) 800aa8a: 4c0c ldr r4, [pc, #48] @ (800aabc <__libc_init_array+0x44>) 800aa8c: f000 f818 bl 800aac0 <_init> 800aa90: 1b64 subs r4, r4, r5 800aa92: 10a4 asrs r4, r4, #2 800aa94: 2600 movs r6, #0 800aa96: 42a6 cmp r6, r4 800aa98: d105 bne.n 800aaa6 <__libc_init_array+0x2e> 800aa9a: bd70 pop {r4, r5, r6, pc} 800aa9c: f855 3b04 ldr.w r3, [r5], #4 800aaa0: 4798 blx r3 800aaa2: 3601 adds r6, #1 800aaa4: e7ee b.n 800aa84 <__libc_init_array+0xc> 800aaa6: f855 3b04 ldr.w r3, [r5], #4 800aaaa: 4798 blx r3 800aaac: 3601 adds r6, #1 800aaae: e7f2 b.n 800aa96 <__libc_init_array+0x1e> 800aab0: 0800ab3c .word 0x0800ab3c 800aab4: 0800ab3c .word 0x0800ab3c 800aab8: 0800ab3c .word 0x0800ab3c 800aabc: 0800ab40 .word 0x0800ab40 0800aac0 <_init>: 800aac0: b5f8 push {r3, r4, r5, r6, r7, lr} 800aac2: bf00 nop 800aac4: bcf8 pop {r3, r4, r5, r6, r7} 800aac6: bc08 pop {r3} 800aac8: 469e mov lr, r3 800aaca: 4770 bx lr 0800aacc <_fini>: 800aacc: b5f8 push {r3, r4, r5, r6, r7, lr} 800aace: bf00 nop 800aad0: bcf8 pop {r3, r4, r5, r6, r7} 800aad2: bc08 pop {r3} 800aad4: 469e mov lr, r3 800aad6: 4770 bx lr