modularkbd.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000a8bc 080001c4 080001c4 000011c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000005c 0800aa80 0800aa80 0000ba80 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800aadc 0800aadc 0000c1a0 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800aadc 0800aadc 0000badc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800aae4 0800aae4 0000c1a0 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800aae4 0800aae4 0000bae4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800aae8 0800aae8 0000bae8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 000001a0 20000000 0800aaec 0000c000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000f68 200001a0 0800ac8c 0000c1a0 2**2 ALLOC 10 ._user_heap_stack 00000600 20001108 0800ac8c 0000d108 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000c1a0 2**0 CONTENTS, READONLY 12 .debug_info 0001af9a 00000000 00000000 0000c1d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004037 00000000 00000000 0002716a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001788 00000000 00000000 0002b1a8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001246 00000000 00000000 0002c930 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026060 00000000 00000000 0002db76 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001e6cd 00000000 00000000 00053bd6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d7ec2 00000000 00000000 000722a3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014a165 2**0 CONTENTS, READONLY 20 .debug_frame 000062c0 00000000 00000000 0014a1a8 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000062 00000000 00000000 00150468 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 200001a0 .word 0x200001a0 80001e0: 00000000 .word 0x00000000 80001e4: 0800aa68 .word 0x0800aa68 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 200001a4 .word 0x200001a4 8000200: 0800aa68 .word 0x0800aa68 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 468e mov lr, r1 800023c: 4604 mov r4, r0 800023e: 4688 mov r8, r1 8000240: 2b00 cmp r3, #0 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> 800024a: fab2 f682 clz r6, r2 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> 8000250: f1c6 0320 rsb r3, r6, #32 8000254: fa01 f806 lsl.w r8, r1, r6 8000258: fa20 f303 lsr.w r3, r0, r3 800025c: 40b7 lsls r7, r6 800025e: ea43 0808 orr.w r8, r3, r8 8000262: 40b4 lsls r4, r6 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 8000268: fa1f fc87 uxth.w ip, r7 800026c: fbb8 f1fe udiv r1, r8, lr 8000270: 0c23 lsrs r3, r4, #16 8000272: fb0e 8811 mls r8, lr, r1, r8 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 800027a: fb01 f20c mul.w r2, r1, ip 800027e: 429a cmp r2, r3 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> 8000282: 18fb adds r3, r7, r3 8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> 800028c: 429a cmp r2, r3 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> 8000292: 3902 subs r1, #2 8000294: 443b add r3, r7 8000296: 1a9a subs r2, r3, r2 8000298: b2a3 uxth r3, r4 800029a: fbb2 f0fe udiv r0, r2, lr 800029e: fb0e 2210 mls r2, lr, r0, r2 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 80002a6: fb00 fc0c mul.w ip, r0, ip 80002aa: 459c cmp ip, r3 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> 80002ae: 18fb adds r3, r7, r3 80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> 80002b8: 459c cmp ip, r3 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> 80002be: 443b add r3, r7 80002c0: 3802 subs r0, #2 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 80002c6: eba3 030c sub.w r3, r3, ip 80002ca: 2100 movs r1, #0 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> 80002ce: 40f3 lsrs r3, r6 80002d0: 2200 movs r2, #0 80002d2: e9c5 3200 strd r3, r2, [r5] 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: 428b cmp r3, r1 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> 80002e0: e9c5 0100 strd r0, r1, [r5] 80002e4: 2100 movs r1, #0 80002e6: 4608 mov r0, r1 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> 80002ea: fab3 f183 clz r1, r3 80002ee: 2900 cmp r1, #0 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> 80002f2: 4573 cmp r3, lr 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> 80002f6: 4282 cmp r2, r0 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> 80002fc: 1a84 subs r4, r0, r2 80002fe: eb6e 0203 sbc.w r2, lr, r3 8000302: 2001 movs r0, #1 8000304: 4690 mov r8, r2 8000306: 2d00 cmp r5, #0 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> 800030a: e9c5 4800 strd r4, r8, [r5] 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> 8000310: 2a00 cmp r2, #0 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> 8000316: fab2 f682 clz r6, r2 800031a: 2e00 cmp r6, #0 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> 8000320: 1a8a subs r2, r1, r2 8000322: 0c03 lsrs r3, r0, #16 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 8000328: b280 uxth r0, r0 800032a: b2bc uxth r4, r7 800032c: 2101 movs r1, #1 800032e: fbb2 fcfe udiv ip, r2, lr 8000332: fb0e 221c mls r2, lr, ip, r2 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 800033a: fb04 f20c mul.w r2, r4, ip 800033e: 429a cmp r2, r3 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> 8000342: 18fb adds r3, r7, r3 8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> 800034a: 429a cmp r2, r3 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> 8000350: 46c4 mov ip, r8 8000352: 1a9b subs r3, r3, r2 8000354: fbb3 f2fe udiv r2, r3, lr 8000358: fb0e 3312 mls r3, lr, r2, r3 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 8000360: fb02 f404 mul.w r4, r2, r4 8000364: 429c cmp r4, r3 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> 8000368: 18fb adds r3, r7, r3 800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> 8000370: 429c cmp r4, r3 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> 8000376: 4602 mov r2, r0 8000378: 1b1b subs r3, r3, r4 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> 8000380: f1c1 0620 rsb r6, r1, #32 8000384: 408b lsls r3, r1 8000386: fa22 f706 lsr.w r7, r2, r6 800038a: 431f orrs r7, r3 800038c: fa0e f401 lsl.w r4, lr, r1 8000390: fa20 f306 lsr.w r3, r0, r6 8000394: fa2e fe06 lsr.w lr, lr, r6 8000398: ea4f 4917 mov.w r9, r7, lsr #16 800039c: 4323 orrs r3, r4 800039e: fa00 f801 lsl.w r8, r0, r1 80003a2: fa1f fc87 uxth.w ip, r7 80003a6: fbbe f0f9 udiv r0, lr, r9 80003aa: 0c1c lsrs r4, r3, #16 80003ac: fb09 ee10 mls lr, r9, r0, lr 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 80003b4: fb00 fe0c mul.w lr, r0, ip 80003b8: 45a6 cmp lr, r4 80003ba: fa02 f201 lsl.w r2, r2, r1 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> 80003c0: 193c adds r4, r7, r4 80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> 80003ca: 45a6 cmp lr, r4 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> 80003d0: 3802 subs r0, #2 80003d2: 443c add r4, r7 80003d4: eba4 040e sub.w r4, r4, lr 80003d8: fa1f fe83 uxth.w lr, r3 80003dc: fbb4 f3f9 udiv r3, r4, r9 80003e0: fb09 4413 mls r4, r9, r3, r4 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003e8: fb03 fc0c mul.w ip, r3, ip 80003ec: 45a4 cmp ip, r4 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> 80003f0: 193c adds r4, r7, r4 80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> 80003fa: 45a4 cmp ip, r4 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> 80003fe: 3b02 subs r3, #2 8000400: 443c add r4, r7 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 8000406: eba4 040c sub.w r4, r4, ip 800040a: fba0 ec02 umull lr, ip, r0, r2 800040e: 4564 cmp r4, ip 8000410: 4673 mov r3, lr 8000412: 46e1 mov r9, ip 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> 800041a: ebb8 0203 subs.w r2, r8, r3 800041e: eb64 0409 sbc.w r4, r4, r9 8000422: fa04 f606 lsl.w r6, r4, r6 8000426: fa22 f301 lsr.w r3, r2, r1 800042a: 431e orrs r6, r3 800042c: 40cc lsrs r4, r1 800042e: e9c5 6400 strd r6, r4, [r5] 8000432: 2100 movs r1, #0 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> 8000436: fbb1 fcf2 udiv ip, r1, r2 800043a: 0c01 lsrs r1, r0, #16 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 8000440: b280 uxth r0, r0 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 8000446: 463b mov r3, r7 8000448: 4638 mov r0, r7 800044a: 463c mov r4, r7 800044c: 46b8 mov r8, r7 800044e: 46be mov lr, r7 8000450: 2620 movs r6, #32 8000452: fbb1 f1f7 udiv r1, r1, r7 8000456: eba2 0208 sub.w r2, r2, r8 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> 8000460: 4601 mov r1, r0 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> 8000464: 4610 mov r0, r2 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> 8000468: f1c6 0220 rsb r2, r6, #32 800046c: fa2e f302 lsr.w r3, lr, r2 8000470: 40b7 lsls r7, r6 8000472: 40b1 lsls r1, r6 8000474: fa20 f202 lsr.w r2, r0, r2 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 800047c: 430a orrs r2, r1 800047e: fbb3 f8fe udiv r8, r3, lr 8000482: b2bc uxth r4, r7 8000484: fb0e 3318 mls r3, lr, r8, r3 8000488: 0c11 lsrs r1, r2, #16 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 800048e: fb08 f904 mul.w r9, r8, r4 8000492: 40b0 lsls r0, r6 8000494: 4589 cmp r9, r1 8000496: ea4f 4310 mov.w r3, r0, lsr #16 800049a: b280 uxth r0, r0 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> 800049e: 1879 adds r1, r7, r1 80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> 80004a6: 4589 cmp r9, r1 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> 80004aa: eba1 0109 sub.w r1, r1, r9 80004ae: fbb1 f9fe udiv r9, r1, lr 80004b2: fb09 f804 mul.w r8, r9, r4 80004b6: fb0e 1119 mls r1, lr, r9, r1 80004ba: b292 uxth r2, r2 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 80004c0: 4542 cmp r2, r8 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> 80004c4: 18ba adds r2, r7, r2 80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> 80004cc: 4542 cmp r2, r8 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> 80004d0: f1a9 0102 sub.w r1, r9, #2 80004d4: 443a add r2, r7 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> 80004d8: 45f0 cmp r8, lr 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> 80004dc: ebbe 0302 subs.w r3, lr, r2 80004e0: eb6c 0c07 sbc.w ip, ip, r7 80004e4: 3801 subs r0, #1 80004e6: 46e1 mov r9, ip 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> 80004ea: eba7 0909 sub.w r9, r7, r9 80004ee: 4449 add r1, r9 80004f0: f1a8 0c02 sub.w ip, r8, #2 80004f4: fbb1 f9fe udiv r9, r1, lr 80004f8: fb09 f804 mul.w r8, r9, r4 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> 80004fe: 4673 mov r3, lr 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> 8000502: 4650 mov r0, sl 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> 8000506: 4608 mov r0, r1 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> 800050a: 443b add r3, r7 800050c: 3a02 subs r2, #2 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> 8000510: f1ac 0c02 sub.w ip, ip, #2 8000514: 443b add r3, r7 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> 8000518: 4649 mov r1, r9 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> 800051c: eba1 0109 sub.w r1, r1, r9 8000520: 46c4 mov ip, r8 8000522: fbb1 f9fe udiv r9, r1, lr 8000526: fb09 f804 mul.w r8, r9, r4 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> 0800052c <__aeabi_idiv0>: 800052c: 4770 bx lr 800052e: bf00 nop 08000530 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000530: b580 push {r7, lr} 8000532: b082 sub sp, #8 8000534: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000536: 2300 movs r3, #0 8000538: 607b str r3, [r7, #4] 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000544: 6313 str r3, [r2, #48] @ 0x30 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 8000552: 2300 movs r3, #0 8000554: 603b str r3, [r7, #0] 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000560: 6313 str r3, [r2, #48] @ 0x30 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800056a: 603b str r3, [r7, #0] 800056c: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 800056e: 2200 movs r2, #0 8000570: 2100 movs r1, #0 8000572: 200b movs r0, #11 8000574: f001 fbd9 bl 8001d2a HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000578: 200b movs r0, #11 800057a: f001 fbf2 bl 8001d62 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 800057e: 2200 movs r2, #0 8000580: 2100 movs r1, #0 8000582: 200d movs r0, #13 8000584: f001 fbd1 bl 8001d2a HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000588: 200d movs r0, #13 800058a: f001 fbea bl 8001d62 /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); 800058e: 2200 movs r2, #0 8000590: 2100 movs r1, #0 8000592: 200f movs r0, #15 8000594: f001 fbc9 bl 8001d2a HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 8000598: 200f movs r0, #15 800059a: f001 fbe2 bl 8001d62 /* DMA1_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); 800059e: 2200 movs r2, #0 80005a0: 2100 movs r1, #0 80005a2: 2010 movs r0, #16 80005a4: f001 fbc1 bl 8001d2a HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); 80005a8: 2010 movs r0, #16 80005aa: f001 fbda bl 8001d62 /* DMA1_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); 80005ae: 2200 movs r2, #0 80005b0: 2100 movs r1, #0 80005b2: 2011 movs r0, #17 80005b4: f001 fbb9 bl 8001d2a HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); 80005b8: 2011 movs r0, #17 80005ba: f001 fbd2 bl 8001d62 /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); 80005be: 2200 movs r2, #0 80005c0: 2100 movs r1, #0 80005c2: 202f movs r0, #47 @ 0x2f 80005c4: f001 fbb1 bl 8001d2a HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); 80005c8: 202f movs r0, #47 @ 0x2f 80005ca: f001 fbca bl 8001d62 /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); 80005ce: 2200 movs r2, #0 80005d0: 2100 movs r1, #0 80005d2: 203a movs r0, #58 @ 0x3a 80005d4: f001 fba9 bl 8001d2a HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); 80005d8: 203a movs r0, #58 @ 0x3a 80005da: f001 fbc2 bl 8001d62 /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 80005de: 2200 movs r2, #0 80005e0: 2100 movs r1, #0 80005e2: 2046 movs r0, #70 @ 0x46 80005e4: f001 fba1 bl 8001d2a HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 80005e8: 2046 movs r0, #70 @ 0x46 80005ea: f001 fbba bl 8001d62 } 80005ee: bf00 nop 80005f0: 3708 adds r7, #8 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 80005f6: bf00 nop 80005f8: 40023800 .word 0x40023800 080005fc : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000602: f107 0314 add.w r3, r7, #20 8000606: 2200 movs r2, #0 8000608: 601a str r2, [r3, #0] 800060a: 605a str r2, [r3, #4] 800060c: 609a str r2, [r3, #8] 800060e: 60da str r2, [r3, #12] 8000610: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000612: 2300 movs r3, #0 8000614: 613b str r3, [r7, #16] 8000616: 4b45 ldr r3, [pc, #276] @ (800072c ) 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 800061a: 4a44 ldr r2, [pc, #272] @ (800072c ) 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000620: 6313 str r3, [r2, #48] @ 0x30 8000622: 4b42 ldr r3, [pc, #264] @ (800072c ) 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 800062a: 613b str r3, [r7, #16] 800062c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800062e: 2300 movs r3, #0 8000630: 60fb str r3, [r7, #12] 8000632: 4b3e ldr r3, [pc, #248] @ (800072c ) 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 8000636: 4a3d ldr r2, [pc, #244] @ (800072c ) 8000638: f043 0301 orr.w r3, r3, #1 800063c: 6313 str r3, [r2, #48] @ 0x30 800063e: 4b3b ldr r3, [pc, #236] @ (800072c ) 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 8000642: f003 0301 and.w r3, r3, #1 8000646: 60fb str r3, [r7, #12] 8000648: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800064a: 2300 movs r3, #0 800064c: 60bb str r3, [r7, #8] 800064e: 4b37 ldr r3, [pc, #220] @ (800072c ) 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 8000652: 4a36 ldr r2, [pc, #216] @ (800072c ) 8000654: f043 0304 orr.w r3, r3, #4 8000658: 6313 str r3, [r2, #48] @ 0x30 800065a: 4b34 ldr r3, [pc, #208] @ (800072c ) 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 800065e: f003 0304 and.w r3, r3, #4 8000662: 60bb str r3, [r7, #8] 8000664: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000666: 2300 movs r3, #0 8000668: 607b str r3, [r7, #4] 800066a: 4b30 ldr r3, [pc, #192] @ (800072c ) 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 800066e: 4a2f ldr r2, [pc, #188] @ (800072c ) 8000670: f043 0302 orr.w r3, r3, #2 8000674: 6313 str r3, [r2, #48] @ 0x30 8000676: 4b2d ldr r3, [pc, #180] @ (800072c ) 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 800067a: f003 0302 and.w r3, r3, #2 800067e: 607b str r3, [r7, #4] 8000680: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000682: 2300 movs r3, #0 8000684: 603b str r3, [r7, #0] 8000686: 4b29 ldr r3, [pc, #164] @ (800072c ) 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 800068a: 4a28 ldr r2, [pc, #160] @ (800072c ) 800068c: f043 0308 orr.w r3, r3, #8 8000690: 6313 str r3, [r2, #48] @ 0x30 8000692: 4b26 ldr r3, [pc, #152] @ (800072c ) 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 8000696: f003 0308 and.w r3, r3, #8 800069a: 603b str r3, [r7, #0] 800069c: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); 800069e: 2200 movs r2, #0 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 80006a4: 4822 ldr r0, [pc, #136] @ (8000730 ) 80006a6: f002 f925 bl 80028f4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); 80006aa: 2200 movs r2, #0 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 80006b0: 4820 ldr r0, [pc, #128] @ (8000734 ) 80006b2: f002 f91f bl 80028f4 /*Configure GPIO pins : PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80006b6: 2330 movs r3, #48 @ 0x30 80006b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ba: 2300 movs r3, #0 80006bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006be: 2302 movs r3, #2 80006c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006c2: f107 0314 add.w r3, r7, #20 80006c6: 4619 mov r1, r3 80006c8: 4819 ldr r0, [pc, #100] @ (8000730 ) 80006ca: f001 ff67 bl 800259c /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; 80006ce: f240 4307 movw r3, #1031 @ 0x407 80006d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 2300 movs r3, #0 80006d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006d8: 2302 movs r3, #2 80006da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006dc: f107 0314 add.w r3, r7, #20 80006e0: 4619 mov r1, r3 80006e2: 4815 ldr r0, [pc, #84] @ (8000738 ) 80006e4: f001 ff5a bl 800259c /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 80006ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006ee: 2301 movs r3, #1 80006f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006f2: 2300 movs r3, #0 80006f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006f6: 2300 movs r3, #0 80006f8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006fa: f107 0314 add.w r3, r7, #20 80006fe: 4619 mov r1, r3 8000700: 480b ldr r0, [pc, #44] @ (8000730 ) 8000702: f001 ff4b bl 800259c /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000706: f44f 7380 mov.w r3, #256 @ 0x100 800070a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 2301 movs r3, #1 800070e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 2300 movs r3, #0 8000712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000714: 2300 movs r3, #0 8000716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000718: f107 0314 add.w r3, r7, #20 800071c: 4619 mov r1, r3 800071e: 4805 ldr r0, [pc, #20] @ (8000734 ) 8000720: f001 ff3c bl 800259c } 8000724: bf00 nop 8000726: 3728 adds r7, #40 @ 0x28 8000728: 46bd mov sp, r7 800072a: bd80 pop {r7, pc} 800072c: 40023800 .word 0x40023800 8000730: 40020800 .word 0x40020800 8000734: 40020000 .word 0x40020000 8000738: 40020400 .word 0x40020400 0800073c : I2C_HandleTypeDef hi2c1; /* I2C1 init function */ void MX_I2C1_Init(void) { 800073c: b580 push {r7, lr} 800073e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000740: 4b12 ldr r3, [pc, #72] @ (800078c ) 8000742: 4a13 ldr r2, [pc, #76] @ (8000790 ) 8000744: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8000746: 4b11 ldr r3, [pc, #68] @ (800078c ) 8000748: 4a12 ldr r2, [pc, #72] @ (8000794 ) 800074a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800074c: 4b0f ldr r3, [pc, #60] @ (800078c ) 800074e: 2200 movs r2, #0 8000750: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8000752: 4b0e ldr r3, [pc, #56] @ (800078c ) 8000754: 2200 movs r2, #0 8000756: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000758: 4b0c ldr r3, [pc, #48] @ (800078c ) 800075a: f44f 4280 mov.w r2, #16384 @ 0x4000 800075e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000760: 4b0a ldr r3, [pc, #40] @ (800078c ) 8000762: 2200 movs r2, #0 8000764: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8000766: 4b09 ldr r3, [pc, #36] @ (800078c ) 8000768: 2200 movs r2, #0 800076a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800076c: 4b07 ldr r3, [pc, #28] @ (800078c ) 800076e: 2200 movs r2, #0 8000770: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000772: 4b06 ldr r3, [pc, #24] @ (800078c ) 8000774: 2200 movs r2, #0 8000776: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000778: 4804 ldr r0, [pc, #16] @ (800078c ) 800077a: f002 f8d5 bl 8002928 800077e: 4603 mov r3, r0 8000780: 2b00 cmp r3, #0 8000782: d001 beq.n 8000788 { Error_Handler(); 8000784: f000 fb8e bl 8000ea4 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000788: bf00 nop 800078a: bd80 pop {r7, pc} 800078c: 200001bc .word 0x200001bc 8000790: 40005400 .word 0x40005400 8000794: 000186a0 .word 0x000186a0 08000798 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 8000798: b580 push {r7, lr} 800079a: b08a sub sp, #40 @ 0x28 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007a0: f107 0314 add.w r3, r7, #20 80007a4: 2200 movs r2, #0 80007a6: 601a str r2, [r3, #0] 80007a8: 605a str r2, [r3, #4] 80007aa: 609a str r2, [r3, #8] 80007ac: 60da str r2, [r3, #12] 80007ae: 611a str r2, [r3, #16] if(i2cHandle->Instance==I2C1) 80007b0: 687b ldr r3, [r7, #4] 80007b2: 681b ldr r3, [r3, #0] 80007b4: 4a19 ldr r2, [pc, #100] @ (800081c ) 80007b6: 4293 cmp r3, r2 80007b8: d12b bne.n 8000812 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007ba: 2300 movs r3, #0 80007bc: 613b str r3, [r7, #16] 80007be: 4b18 ldr r3, [pc, #96] @ (8000820 ) 80007c0: 6b1b ldr r3, [r3, #48] @ 0x30 80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 ) 80007c4: f043 0302 orr.w r3, r3, #2 80007c8: 6313 str r3, [r2, #48] @ 0x30 80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 ) 80007cc: 6b1b ldr r3, [r3, #48] @ 0x30 80007ce: f003 0302 and.w r3, r3, #2 80007d2: 613b str r3, [r7, #16] 80007d4: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80007d6: 23c0 movs r3, #192 @ 0xc0 80007d8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80007da: 2312 movs r3, #18 80007dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80007de: 2300 movs r3, #0 80007e0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80007e2: 2303 movs r3, #3 80007e4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 80007e6: 2304 movs r3, #4 80007e8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80007ea: f107 0314 add.w r3, r7, #20 80007ee: 4619 mov r1, r3 80007f0: 480c ldr r0, [pc, #48] @ (8000824 ) 80007f2: f001 fed3 bl 800259c /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 80007f6: 2300 movs r3, #0 80007f8: 60fb str r3, [r7, #12] 80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 ) 80007fc: 6c1b ldr r3, [r3, #64] @ 0x40 80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 ) 8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000804: 6413 str r3, [r2, #64] @ 0x40 8000806: 4b06 ldr r3, [pc, #24] @ (8000820 ) 8000808: 6c1b ldr r3, [r3, #64] @ 0x40 800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800080e: 60fb str r3, [r7, #12] 8000810: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000812: bf00 nop 8000814: 3728 adds r7, #40 @ 0x28 8000816: 46bd mov sp, r7 8000818: bd80 pop {r7, pc} 800081a: bf00 nop 800081c: 40005400 .word 0x40005400 8000820: 40023800 .word 0x40023800 8000824: 40020400 .word 0x40020400 08000828
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000828: b580 push {r7, lr} 800082a: b08a sub sp, #40 @ 0x28 800082c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800082e: f001 f90b bl 8001a48 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000832: f000 f8c9 bl 80009c8 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000836: f7ff fee1 bl 80005fc MX_DMA_Init(); 800083a: f7ff fe79 bl 8000530 MX_TIM2_Init(); 800083e: f000 fc23 bl 8001088 MX_TIM3_Init(); 8000842: f000 fc79 bl 8001138 MX_UART4_Init(); 8000846: f000 fd6b bl 8001320 MX_UART5_Init(); 800084a: f000 fd93 bl 8001374 MX_USART1_UART_Init(); 800084e: f000 fdbb bl 80013c8 MX_USART2_UART_Init(); 8000852: f000 fde3 bl 800141c MX_I2C1_Init(); 8000856: f7ff ff71 bl 800073c MX_USB_DEVICE_Init(); 800085a: f009 fc2b bl 800a0b4 /* USER CODE BEGIN 2 */ //Enable UART RX DMA for all ports HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 800085e: 2210 movs r2, #16 8000860: 494b ldr r1, [pc, #300] @ (8000990 ) 8000862: 484c ldr r0, [pc, #304] @ (8000994 ) 8000864: f005 fa2c bl 8005cc0 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000868: 2210 movs r2, #16 800086a: 494b ldr r1, [pc, #300] @ (8000998 ) 800086c: 484b ldr r0, [pc, #300] @ (800099c ) 800086e: f005 fa27 bl 8005cc0 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000872: 2210 movs r2, #16 8000874: 494a ldr r1, [pc, #296] @ (80009a0 ) 8000876: 484b ldr r0, [pc, #300] @ (80009a4 ) 8000878: f005 fa22 bl 8005cc0 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 800087c: 2210 movs r2, #16 800087e: 494a ldr r1, [pc, #296] @ (80009a8 ) 8000880: 484a ldr r0, [pc, #296] @ (80009ac ) 8000882: f005 fa1d bl 8005cc0 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { switch (MODE){ 8000886: 4b4a ldr r3, [pc, #296] @ (80009b0 ) 8000888: 781b ldrb r3, [r3, #0] 800088a: b2db uxtb r3, r3 800088c: 2b02 cmp r3, #2 800088e: d006 beq.n 800089e 8000890: 2b02 cmp r3, #2 8000892: dc78 bgt.n 8000986 8000894: 2b00 cmp r3, #0 8000896: d035 beq.n 8000904 8000898: 2b01 cmp r3, #1 800089a: d06a beq.n 8000972 matrixScan(); USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); break; default: break; 800089c: e073 b.n 8000986 matrixScan(); 800089e: f000 fa97 bl 8000dd0 UARTREPORT.DEPTH = DEPTH; 80008a2: 4b44 ldr r3, [pc, #272] @ (80009b4 ) 80008a4: 881b ldrh r3, [r3, #0] 80008a6: 82bb strh r3, [r7, #20] UARTREPORT.TYPE = 0xEE; 80008a8: 23ee movs r3, #238 @ 0xee 80008aa: 82fb strh r3, [r7, #22] memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS)); 80008ac: 4a42 ldr r2, [pc, #264] @ (80009b8 ) 80008ae: f107 0318 add.w r3, r7, #24 80008b2: 3202 adds r2, #2 80008b4: 6810 ldr r0, [r2, #0] 80008b6: 6851 ldr r1, [r2, #4] 80008b8: 6892 ldr r2, [r2, #8] 80008ba: c307 stmia r3!, {r0, r1, r2} for (int i = 0; i < sizeof(REPORT.KEYPRESS); i++) { 80008bc: 2300 movs r3, #0 80008be: 627b str r3, [r7, #36] @ 0x24 80008c0: e014 b.n 80008ec UARTREPORT.KEYPRESS[i] |= BUFFER.KEYPRESS[i]; // bitwise merge keys 80008c2: f107 0218 add.w r2, r7, #24 80008c6: 6a7b ldr r3, [r7, #36] @ 0x24 80008c8: 4413 add r3, r2 80008ca: 781a ldrb r2, [r3, #0] 80008cc: 493b ldr r1, [pc, #236] @ (80009bc ) 80008ce: 6a7b ldr r3, [r7, #36] @ 0x24 80008d0: 440b add r3, r1 80008d2: 3304 adds r3, #4 80008d4: 781b ldrb r3, [r3, #0] 80008d6: 4313 orrs r3, r2 80008d8: b2d9 uxtb r1, r3 80008da: f107 0218 add.w r2, r7, #24 80008de: 6a7b ldr r3, [r7, #36] @ 0x24 80008e0: 4413 add r3, r2 80008e2: 460a mov r2, r1 80008e4: 701a strb r2, [r3, #0] for (int i = 0; i < sizeof(REPORT.KEYPRESS); i++) { 80008e6: 6a7b ldr r3, [r7, #36] @ 0x24 80008e8: 3301 adds r3, #1 80008ea: 627b str r3, [r7, #36] @ 0x24 80008ec: 6a7b ldr r3, [r7, #36] @ 0x24 80008ee: 2b0b cmp r3, #11 80008f0: d9e7 bls.n 80008c2 HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT)); 80008f2: 4b33 ldr r3, [pc, #204] @ (80009c0 ) 80008f4: 681b ldr r3, [r3, #0] 80008f6: f107 0114 add.w r1, r7, #20 80008fa: 2210 movs r2, #16 80008fc: 4618 mov r0, r3 80008fe: f005 f963 bl 8005bc8 break; 8000902: e041 b.n 8000988 if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ 8000904: 4b2f ldr r3, [pc, #188] @ (80009c4 ) 8000906: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800090a: b2db uxtb r3, r3 800090c: 2b03 cmp r3, #3 800090e: d106 bne.n 800091e MODE = MODE_MAINBOARD; 8000910: 4b27 ldr r3, [pc, #156] @ (80009b0 ) 8000912: 2201 movs r2, #1 8000914: 701a strb r2, [r3, #0] DEPTH = 0; 8000916: 4b27 ldr r3, [pc, #156] @ (80009b4 ) 8000918: 2200 movs r2, #0 800091a: 801a strh r2, [r3, #0] break; 800091c: e034 b.n 8000988 REQ.DEPTH = 0; 800091e: 2300 movs r3, #0 8000920: 80bb strh r3, [r7, #4] REQ.TYPE = 0xFF; //Message code for request is 0xFF 8000922: 23ff movs r3, #255 @ 0xff 8000924: 80fb strh r3, [r7, #6] memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); 8000926: 1d3b adds r3, r7, #4 8000928: 3304 adds r3, #4 800092a: 220c movs r2, #12 800092c: 2100 movs r1, #0 800092e: 4618 mov r0, r3 8000930: f00a f86e bl 800aa10 HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); 8000934: 1d3b adds r3, r7, #4 8000936: 2210 movs r2, #16 8000938: 4619 mov r1, r3 800093a: 4816 ldr r0, [pc, #88] @ (8000994 ) 800093c: f005 f944 bl 8005bc8 HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); 8000940: 1d3b adds r3, r7, #4 8000942: 2210 movs r2, #16 8000944: 4619 mov r1, r3 8000946: 4815 ldr r0, [pc, #84] @ (800099c ) 8000948: f005 f93e bl 8005bc8 HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); 800094c: 1d3b adds r3, r7, #4 800094e: 2210 movs r2, #16 8000950: 4619 mov r1, r3 8000952: 4814 ldr r0, [pc, #80] @ (80009a4 ) 8000954: f005 f938 bl 8005bc8 HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); 8000958: 1d3b adds r3, r7, #4 800095a: 2210 movs r2, #16 800095c: 4619 mov r1, r3 800095e: 4813 ldr r0, [pc, #76] @ (80009ac ) 8000960: f005 f932 bl 8005bc8 HAL_Delay(500); 8000964: f44f 70fa mov.w r0, #500 @ 0x1f4 8000968: f001 f8e0 bl 8001b2c findBestParent(); //So true... 800096c: f000 f940 bl 8000bf0 break; 8000970: e00a b.n 8000988 resetReport(); 8000972: f000 fa87 bl 8000e84 matrixScan(); 8000976: f000 fa2b bl 8000dd0 USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); 800097a: 220e movs r2, #14 800097c: 490e ldr r1, [pc, #56] @ (80009b8 ) 800097e: 4811 ldr r0, [pc, #68] @ (80009c4 ) 8000980: f007 ffcc bl 800891c break; 8000984: e000 b.n 8000988 break; 8000986: bf00 nop } HAL_Delay(50); 8000988: 2032 movs r0, #50 @ 0x32 800098a: f001 f8cf bl 8001b2c switch (MODE){ 800098e: e77a b.n 8000886 8000990: 20000240 .word 0x20000240 8000994: 2000039c .word 0x2000039c 8000998: 20000250 .word 0x20000250 800099c: 200003e4 .word 0x200003e4 80009a0: 20000260 .word 0x20000260 80009a4: 2000030c .word 0x2000030c 80009a8: 20000230 .word 0x20000230 80009ac: 20000354 .word 0x20000354 80009b0: 20000278 .word 0x20000278 80009b4: 20000270 .word 0x20000270 80009b8: 20000210 .word 0x20000210 80009bc: 20000220 .word 0x20000220 80009c0: 20000274 .word 0x20000274 80009c4: 20000734 .word 0x20000734 080009c8 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80009c8: b580 push {r7, lr} 80009ca: b094 sub sp, #80 @ 0x50 80009cc: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80009ce: f107 031c add.w r3, r7, #28 80009d2: 2234 movs r2, #52 @ 0x34 80009d4: 2100 movs r1, #0 80009d6: 4618 mov r0, r3 80009d8: f00a f81a bl 800aa10 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80009dc: f107 0308 add.w r3, r7, #8 80009e0: 2200 movs r2, #0 80009e2: 601a str r2, [r3, #0] 80009e4: 605a str r2, [r3, #4] 80009e6: 609a str r2, [r3, #8] 80009e8: 60da str r2, [r3, #12] 80009ea: 611a str r2, [r3, #16] /** Configure the main internal regulator out put voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 80009ec: 2300 movs r3, #0 80009ee: 607b str r3, [r7, #4] 80009f0: 4b29 ldr r3, [pc, #164] @ (8000a98 ) 80009f2: 6c1b ldr r3, [r3, #64] @ 0x40 80009f4: 4a28 ldr r2, [pc, #160] @ (8000a98 ) 80009f6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80009fa: 6413 str r3, [r2, #64] @ 0x40 80009fc: 4b26 ldr r3, [pc, #152] @ (8000a98 ) 80009fe: 6c1b ldr r3, [r3, #64] @ 0x40 8000a00: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000a04: 607b str r3, [r7, #4] 8000a06: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 8000a08: 2300 movs r3, #0 8000a0a: 603b str r3, [r7, #0] 8000a0c: 4b23 ldr r3, [pc, #140] @ (8000a9c ) 8000a0e: 681b ldr r3, [r3, #0] 8000a10: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8000a14: 4a21 ldr r2, [pc, #132] @ (8000a9c ) 8000a16: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000a1a: 6013 str r3, [r2, #0] 8000a1c: 4b1f ldr r3, [pc, #124] @ (8000a9c ) 8000a1e: 681b ldr r3, [r3, #0] 8000a20: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000a24: 603b str r3, [r7, #0] 8000a26: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000a28: 2301 movs r3, #1 8000a2a: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000a2c: f44f 3380 mov.w r3, #65536 @ 0x10000 8000a30: 623b str r3, [r7, #32] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000a32: 2302 movs r3, #2 8000a34: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000a36: f44f 0380 mov.w r3, #4194304 @ 0x400000 8000a3a: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 8000a3c: 2304 movs r3, #4 8000a3e: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 96; 8000a40: 2360 movs r3, #96 @ 0x60 8000a42: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000a44: 2302 movs r3, #2 8000a46: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 8000a48: 2304 movs r3, #4 8000a4a: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 8000a4c: 2302 movs r3, #2 8000a4e: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000a50: f107 031c add.w r3, r7, #28 8000a54: 4618 mov r0, r3 8000a56: f004 f9a5 bl 8004da4 8000a5a: 4603 mov r3, r0 8000a5c: 2b00 cmp r3, #0 8000a5e: d001 beq.n 8000a64 { Error_Handler(); 8000a60: f000 fa20 bl 8000ea4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000a64: 230f movs r3, #15 8000a66: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000a68: 2302 movs r3, #2 8000a6a: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; 8000a6c: 2380 movs r3, #128 @ 0x80 8000a6e: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000a70: f44f 5380 mov.w r3, #4096 @ 0x1000 8000a74: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000a76: 2300 movs r3, #0 8000a78: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000a7a: f107 0308 add.w r3, r7, #8 8000a7e: 2101 movs r1, #1 8000a80: 4618 mov r0, r3 8000a82: f003 fb1b bl 80040bc 8000a86: 4603 mov r3, r0 8000a88: 2b00 cmp r3, #0 8000a8a: d001 beq.n 8000a90 { Error_Handler(); 8000a8c: f000 fa0a bl 8000ea4 } } 8000a90: bf00 nop 8000a92: 3750 adds r7, #80 @ 0x50 8000a94: 46bd mov sp, r7 8000a96: bd80 pop {r7, pc} 8000a98: 40023800 .word 0x40023800 8000a9c: 40007000 .word 0x40007000 08000aa0 : /* USER CODE BEGIN 4 */ // UART Message Requests Goes Here void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000aa0: b580 push {r7, lr} 8000aa2: b082 sub sp, #8 8000aa4: af00 add r7, sp, #0 8000aa6: 6078 str r0, [r7, #4] if (huart->Instance == USART1) { 8000aa8: 687b ldr r3, [r7, #4] 8000aaa: 681b ldr r3, [r3, #0] 8000aac: 4a1e ldr r2, [pc, #120] @ (8000b28 ) 8000aae: 4293 cmp r3, r2 8000ab0: d109 bne.n 8000ac6 handleUARTMessages((uint8_t*)&RX1Msg, &huart1); 8000ab2: 491e ldr r1, [pc, #120] @ (8000b2c ) 8000ab4: 481e ldr r0, [pc, #120] @ (8000b30 ) 8000ab6: f000 f8dd bl 8000c74 HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000aba: 2210 movs r2, #16 8000abc: 491c ldr r1, [pc, #112] @ (8000b30 ) 8000abe: 481b ldr r0, [pc, #108] @ (8000b2c ) 8000ac0: f005 f8fe bl 8005cc0 } else if (huart->Instance == UART5) { handleUARTMessages((uint8_t*)&RX5Msg, &huart5); HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000ac4: e02b b.n 8000b1e else if (huart->Instance == USART2) { 8000ac6: 687b ldr r3, [r7, #4] 8000ac8: 681b ldr r3, [r3, #0] 8000aca: 4a1a ldr r2, [pc, #104] @ (8000b34 ) 8000acc: 4293 cmp r3, r2 8000ace: d109 bne.n 8000ae4 handleUARTMessages((uint8_t*)&RX2Msg, &huart2); 8000ad0: 4919 ldr r1, [pc, #100] @ (8000b38 ) 8000ad2: 481a ldr r0, [pc, #104] @ (8000b3c ) 8000ad4: f000 f8ce bl 8000c74 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000ad8: 2210 movs r2, #16 8000ada: 4918 ldr r1, [pc, #96] @ (8000b3c ) 8000adc: 4816 ldr r0, [pc, #88] @ (8000b38 ) 8000ade: f005 f8ef bl 8005cc0 } 8000ae2: e01c b.n 8000b1e else if (huart->Instance == UART4) { 8000ae4: 687b ldr r3, [r7, #4] 8000ae6: 681b ldr r3, [r3, #0] 8000ae8: 4a15 ldr r2, [pc, #84] @ (8000b40 ) 8000aea: 4293 cmp r3, r2 8000aec: d109 bne.n 8000b02 handleUARTMessages((uint8_t*)&RX4Msg, &huart4); 8000aee: 4915 ldr r1, [pc, #84] @ (8000b44 ) 8000af0: 4815 ldr r0, [pc, #84] @ (8000b48 ) 8000af2: f000 f8bf bl 8000c74 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000af6: 2210 movs r2, #16 8000af8: 4913 ldr r1, [pc, #76] @ (8000b48 ) 8000afa: 4812 ldr r0, [pc, #72] @ (8000b44 ) 8000afc: f005 f8e0 bl 8005cc0 } 8000b00: e00d b.n 8000b1e else if (huart->Instance == UART5) { 8000b02: 687b ldr r3, [r7, #4] 8000b04: 681b ldr r3, [r3, #0] 8000b06: 4a11 ldr r2, [pc, #68] @ (8000b4c ) 8000b08: 4293 cmp r3, r2 8000b0a: d108 bne.n 8000b1e handleUARTMessages((uint8_t*)&RX5Msg, &huart5); 8000b0c: 4910 ldr r1, [pc, #64] @ (8000b50 ) 8000b0e: 4811 ldr r0, [pc, #68] @ (8000b54 ) 8000b10: f000 f8b0 bl 8000c74 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000b14: 2210 movs r2, #16 8000b16: 490f ldr r1, [pc, #60] @ (8000b54 ) 8000b18: 480d ldr r0, [pc, #52] @ (8000b50 ) 8000b1a: f005 f8d1 bl 8005cc0 } 8000b1e: bf00 nop 8000b20: 3708 adds r7, #8 8000b22: 46bd mov sp, r7 8000b24: bd80 pop {r7, pc} 8000b26: bf00 nop 8000b28: 40011000 .word 0x40011000 8000b2c: 2000039c .word 0x2000039c 8000b30: 20000240 .word 0x20000240 8000b34: 40004400 .word 0x40004400 8000b38: 200003e4 .word 0x200003e4 8000b3c: 20000250 .word 0x20000250 8000b40: 40004c00 .word 0x40004c00 8000b44: 2000030c .word 0x2000030c 8000b48: 20000260 .word 0x20000260 8000b4c: 40005000 .word 0x40005000 8000b50: 20000354 .word 0x20000354 8000b54: 20000230 .word 0x20000230 08000b58 : void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8000b58: b580 push {r7, lr} 8000b5a: b082 sub sp, #8 8000b5c: af00 add r7, sp, #0 8000b5e: 6078 str r0, [r7, #4] // Restart DMA on error if (huart->Instance == USART1) { 8000b60: 687b ldr r3, [r7, #4] 8000b62: 681b ldr r3, [r3, #0] 8000b64: 4a16 ldr r2, [pc, #88] @ (8000bc0 ) 8000b66: 4293 cmp r3, r2 8000b68: d105 bne.n 8000b76 HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000b6a: 2210 movs r2, #16 8000b6c: 4915 ldr r1, [pc, #84] @ (8000bc4 ) 8000b6e: 4816 ldr r0, [pc, #88] @ (8000bc8 ) 8000b70: f005 f8a6 bl 8005cc0 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); } else if (huart->Instance == UART5) { HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000b74: e01f b.n 8000bb6 else if (huart->Instance == USART2) { 8000b76: 687b ldr r3, [r7, #4] 8000b78: 681b ldr r3, [r3, #0] 8000b7a: 4a14 ldr r2, [pc, #80] @ (8000bcc ) 8000b7c: 4293 cmp r3, r2 8000b7e: d105 bne.n 8000b8c HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000b80: 2210 movs r2, #16 8000b82: 4913 ldr r1, [pc, #76] @ (8000bd0 ) 8000b84: 4813 ldr r0, [pc, #76] @ (8000bd4 ) 8000b86: f005 f89b bl 8005cc0 } 8000b8a: e014 b.n 8000bb6 else if (huart->Instance == UART4) { 8000b8c: 687b ldr r3, [r7, #4] 8000b8e: 681b ldr r3, [r3, #0] 8000b90: 4a11 ldr r2, [pc, #68] @ (8000bd8 ) 8000b92: 4293 cmp r3, r2 8000b94: d105 bne.n 8000ba2 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000b96: 2210 movs r2, #16 8000b98: 4910 ldr r1, [pc, #64] @ (8000bdc ) 8000b9a: 4811 ldr r0, [pc, #68] @ (8000be0 ) 8000b9c: f005 f890 bl 8005cc0 } 8000ba0: e009 b.n 8000bb6 else if (huart->Instance == UART5) { 8000ba2: 687b ldr r3, [r7, #4] 8000ba4: 681b ldr r3, [r3, #0] 8000ba6: 4a0f ldr r2, [pc, #60] @ (8000be4 ) 8000ba8: 4293 cmp r3, r2 8000baa: d104 bne.n 8000bb6 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000bac: 2210 movs r2, #16 8000bae: 490e ldr r1, [pc, #56] @ (8000be8 ) 8000bb0: 480e ldr r0, [pc, #56] @ (8000bec ) 8000bb2: f005 f885 bl 8005cc0 } 8000bb6: bf00 nop 8000bb8: 3708 adds r7, #8 8000bba: 46bd mov sp, r7 8000bbc: bd80 pop {r7, pc} 8000bbe: bf00 nop 8000bc0: 40011000 .word 0x40011000 8000bc4: 20000240 .word 0x20000240 8000bc8: 2000039c .word 0x2000039c 8000bcc: 40004400 .word 0x40004400 8000bd0: 20000250 .word 0x20000250 8000bd4: 200003e4 .word 0x200003e4 8000bd8: 40004c00 .word 0x40004c00 8000bdc: 20000260 .word 0x20000260 8000be0: 2000030c .word 0x2000030c 8000be4: 40005000 .word 0x40005000 8000be8: 20000230 .word 0x20000230 8000bec: 20000354 .word 0x20000354 08000bf0 : void findBestParent(){ 8000bf0: b580 push {r7, lr} 8000bf2: b084 sub sp, #16 8000bf4: af00 add r7, sp, #0 //Find least depth parent uint16_t least_val = 0xFF; 8000bf6: 23ff movs r3, #255 @ 0xff 8000bf8: 81fb strh r3, [r7, #14] UART_HandleTypeDef* least_port = NULL; 8000bfa: 2300 movs r3, #0 8000bfc: 60bb str r3, [r7, #8] for(uint8_t i = 0; i < 4; i++){ 8000bfe: 2300 movs r3, #0 8000c00: 71fb strb r3, [r7, #7] 8000c02: e013 b.n 8000c2c if(PORT_DEPTH[i]) 8000c08: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000c0c: 89fa ldrh r2, [r7, #14] 8000c0e: 429a cmp r2, r3 8000c10: d909 bls.n 8000c26 least_port = PORTS[i]; 8000c12: 79fb ldrb r3, [r7, #7] 8000c14: 4a13 ldr r2, [pc, #76] @ (8000c64 ) 8000c16: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000c1a: 60bb str r3, [r7, #8] least_val = PORT_DEPTH[i]; 8000c1c: 79fb ldrb r3, [r7, #7] 8000c1e: 4a10 ldr r2, [pc, #64] @ (8000c60 ) 8000c20: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000c24: 81fb strh r3, [r7, #14] for(uint8_t i = 0; i < 4; i++){ 8000c26: 79fb ldrb r3, [r7, #7] 8000c28: 3301 adds r3, #1 8000c2a: 71fb strb r3, [r7, #7] 8000c2c: 79fb ldrb r3, [r7, #7] 8000c2e: 2b03 cmp r3, #3 8000c30: d9e8 bls.n 8000c04 } } //Assign if valid if(least_val < 0xFF){ 8000c32: 89fb ldrh r3, [r7, #14] 8000c34: 2bfe cmp r3, #254 @ 0xfe 8000c36: d80e bhi.n 8000c56 PARENT = least_port; 8000c38: 4a0b ldr r2, [pc, #44] @ (8000c68 ) 8000c3a: 68bb ldr r3, [r7, #8] 8000c3c: 6013 str r3, [r2, #0] DEPTH = least_val + 1; 8000c3e: 89fb ldrh r3, [r7, #14] 8000c40: 3301 adds r3, #1 8000c42: b29a uxth r2, r3 8000c44: 4b09 ldr r3, [pc, #36] @ (8000c6c ) 8000c46: 801a strh r2, [r3, #0] MODE = MODE_ACTIVE; 8000c48: 4b09 ldr r3, [pc, #36] @ (8000c70 ) 8000c4a: 2202 movs r2, #2 8000c4c: 701a strb r2, [r3, #0] HAL_Delay(500); 8000c4e: f44f 70fa mov.w r0, #500 @ 0x1f4 8000c52: f000 ff6b bl 8001b2c } } 8000c56: bf00 nop 8000c58: 3710 adds r7, #16 8000c5a: 46bd mov sp, r7 8000c5c: bd80 pop {r7, pc} 8000c5e: bf00 nop 8000c60: 20000078 .word 0x20000078 8000c64: 20000080 .word 0x20000080 8000c68: 20000274 .word 0x20000274 8000c6c: 20000270 .word 0x20000270 8000c70: 20000278 .word 0x20000278 08000c74 : // Called when UART RX interrupt completes void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) { 8000c74: b590 push {r4, r7, lr} 8000c76: b08b sub sp, #44 @ 0x2c 8000c78: af00 add r7, sp, #0 8000c7a: 6078 str r0, [r7, #4] 8000c7c: 6039 str r1, [r7, #0] UARTMessage msg; UARTMessage reply; // Parse incoming message into struct memcpy(&msg, data, sizeof(UARTMessage)); 8000c7e: 687b ldr r3, [r7, #4] 8000c80: f107 0418 add.w r4, r7, #24 8000c84: 6818 ldr r0, [r3, #0] 8000c86: 6859 ldr r1, [r3, #4] 8000c88: 689a ldr r2, [r3, #8] 8000c8a: 68db ldr r3, [r3, #12] 8000c8c: c40f stmia r4!, {r0, r1, r2, r3} switch(msg.TYPE) { 8000c8e: 8b7b ldrh r3, [r7, #26] 8000c90: 2bff cmp r3, #255 @ 0xff 8000c92: d026 beq.n 8000ce2 8000c94: 2bff cmp r3, #255 @ 0xff 8000c96: dc4b bgt.n 8000d30 8000c98: 2baa cmp r3, #170 @ 0xaa 8000c9a: d002 beq.n 8000ca2 8000c9c: 2bee cmp r3, #238 @ 0xee 8000c9e: d03a beq.n 8000d16 memcpy(msg.KEYPRESS, BUFFER.KEYPRESS, sizeof(msg.KEYPRESS)); } break; default: break; 8000ca0: e046 b.n 8000d30 if(sender == &huart5) { 8000ca2: 683b ldr r3, [r7, #0] 8000ca4: 4a28 ldr r2, [pc, #160] @ (8000d48 ) 8000ca6: 4293 cmp r3, r2 8000ca8: d103 bne.n 8000cb2 PORT_DEPTH[0] = msg.DEPTH; 8000caa: 8b3a ldrh r2, [r7, #24] 8000cac: 4b27 ldr r3, [pc, #156] @ (8000d4c ) 8000cae: 801a strh r2, [r3, #0] break; 8000cb0: e040 b.n 8000d34 } else if(sender == &huart1) { 8000cb2: 683b ldr r3, [r7, #0] 8000cb4: 4a26 ldr r2, [pc, #152] @ (8000d50 ) 8000cb6: 4293 cmp r3, r2 8000cb8: d103 bne.n 8000cc2 PORT_DEPTH[1] = msg.DEPTH; 8000cba: 8b3a ldrh r2, [r7, #24] 8000cbc: 4b23 ldr r3, [pc, #140] @ (8000d4c ) 8000cbe: 805a strh r2, [r3, #2] break; 8000cc0: e038 b.n 8000d34 } else if(sender == &huart2) { 8000cc2: 683b ldr r3, [r7, #0] 8000cc4: 4a23 ldr r2, [pc, #140] @ (8000d54 ) 8000cc6: 4293 cmp r3, r2 8000cc8: d103 bne.n 8000cd2 PORT_DEPTH[2] = msg.DEPTH; 8000cca: 8b3a ldrh r2, [r7, #24] 8000ccc: 4b1f ldr r3, [pc, #124] @ (8000d4c ) 8000cce: 809a strh r2, [r3, #4] break; 8000cd0: e030 b.n 8000d34 } else if(sender == &huart4) { 8000cd2: 683b ldr r3, [r7, #0] 8000cd4: 4a20 ldr r2, [pc, #128] @ (8000d58 ) 8000cd6: 4293 cmp r3, r2 8000cd8: d12c bne.n 8000d34 PORT_DEPTH[3] = msg.DEPTH; 8000cda: 8b3a ldrh r2, [r7, #24] 8000cdc: 4b1b ldr r3, [pc, #108] @ (8000d4c ) 8000cde: 80da strh r2, [r3, #6] break; 8000ce0: e028 b.n 8000d34 if(MODE!=MODE_INACTIVE){ 8000ce2: 4b1e ldr r3, [pc, #120] @ (8000d5c ) 8000ce4: 781b ldrb r3, [r3, #0] 8000ce6: b2db uxtb r3, r3 8000ce8: 2b00 cmp r3, #0 8000cea: d025 beq.n 8000d38 reply.TYPE = 0xAA; 8000cec: 23aa movs r3, #170 @ 0xaa 8000cee: 817b strh r3, [r7, #10] reply.DEPTH = DEPTH; // use your local DEPTH 8000cf0: 4b1b ldr r3, [pc, #108] @ (8000d60 ) 8000cf2: 881b ldrh r3, [r3, #0] 8000cf4: 813b strh r3, [r7, #8] memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS)); 8000cf6: f107 0308 add.w r3, r7, #8 8000cfa: 3304 adds r3, #4 8000cfc: 220c movs r2, #12 8000cfe: 2100 movs r1, #0 8000d00: 4618 mov r0, r3 8000d02: f009 fe85 bl 800aa10 HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply)); 8000d06: f107 0308 add.w r3, r7, #8 8000d0a: 2210 movs r2, #16 8000d0c: 4619 mov r1, r3 8000d0e: 6838 ldr r0, [r7, #0] 8000d10: f004 ff5a bl 8005bc8 break; 8000d14: e010 b.n 8000d38 if(MODE!=MODE_INACTIVE){ 8000d16: 4b11 ldr r3, [pc, #68] @ (8000d5c ) 8000d18: 781b ldrb r3, [r3, #0] 8000d1a: b2db uxtb r3, r3 8000d1c: 2b00 cmp r3, #0 8000d1e: d00d beq.n 8000d3c memcpy(msg.KEYPRESS, BUFFER.KEYPRESS, sizeof(msg.KEYPRESS)); 8000d20: 4a10 ldr r2, [pc, #64] @ (8000d64 ) 8000d22: f107 031c add.w r3, r7, #28 8000d26: 3204 adds r2, #4 8000d28: ca07 ldmia r2, {r0, r1, r2} 8000d2a: e883 0007 stmia.w r3, {r0, r1, r2} break; 8000d2e: e005 b.n 8000d3c break; 8000d30: bf00 nop 8000d32: e004 b.n 8000d3e break; 8000d34: bf00 nop 8000d36: e002 b.n 8000d3e break; 8000d38: bf00 nop 8000d3a: e000 b.n 8000d3e break; 8000d3c: bf00 nop } } 8000d3e: bf00 nop 8000d40: 372c adds r7, #44 @ 0x2c 8000d42: 46bd mov sp, r7 8000d44: bd90 pop {r4, r7, pc} 8000d46: bf00 nop 8000d48: 20000354 .word 0x20000354 8000d4c: 20000078 .word 0x20000078 8000d50: 2000039c .word 0x2000039c 8000d54: 200003e4 .word 0x200003e4 8000d58: 2000030c .word 0x2000030c 8000d5c: 20000278 .word 0x20000278 8000d60: 20000270 .word 0x20000270 8000d64: 20000220 .word 0x20000220 08000d68 : void addUSBReport(uint8_t usageID){ 8000d68: b480 push {r7} 8000d6a: b085 sub sp, #20 8000d6c: af00 add r7, sp, #0 8000d6e: 4603 mov r3, r0 8000d70: 71fb strb r3, [r7, #7] if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000d72: 79fb ldrb r3, [r7, #7] 8000d74: 2b03 cmp r3, #3 8000d76: d922 bls.n 8000dbe 8000d78: 79fb ldrb r3, [r7, #7] 8000d7a: 2b73 cmp r3, #115 @ 0x73 8000d7c: d81f bhi.n 8000dbe uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit 8000d7e: 79fb ldrb r3, [r7, #7] 8000d80: b29b uxth r3, r3 8000d82: 3b04 subs r3, #4 8000d84: 81fb strh r3, [r7, #14] uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array 8000d86: 89fb ldrh r3, [r7, #14] 8000d88: 08db lsrs r3, r3, #3 8000d8a: b29b uxth r3, r3 8000d8c: 737b strb r3, [r7, #13] uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset 8000d8e: 89fb ldrh r3, [r7, #14] 8000d90: b2db uxtb r3, r3 8000d92: f003 0307 and.w r3, r3, #7 8000d96: 733b strb r3, [r7, #12] REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); 8000d98: 7b7b ldrb r3, [r7, #13] 8000d9a: 4a0c ldr r2, [pc, #48] @ (8000dcc ) 8000d9c: 4413 add r3, r2 8000d9e: 789b ldrb r3, [r3, #2] 8000da0: b25a sxtb r2, r3 8000da2: 7b3b ldrb r3, [r7, #12] 8000da4: 2101 movs r1, #1 8000da6: fa01 f303 lsl.w r3, r1, r3 8000daa: b25b sxtb r3, r3 8000dac: 4313 orrs r3, r2 8000dae: b25a sxtb r2, r3 8000db0: 7b7b ldrb r3, [r7, #13] 8000db2: b2d1 uxtb r1, r2 8000db4: 4a05 ldr r2, [pc, #20] @ (8000dcc ) 8000db6: 4413 add r3, r2 8000db8: 460a mov r2, r1 8000dba: 709a strb r2, [r3, #2] 8000dbc: e000 b.n 8000dc0 if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000dbe: bf00 nop } 8000dc0: 3714 adds r7, #20 8000dc2: 46bd mov sp, r7 8000dc4: f85d 7b04 ldr.w r7, [sp], #4 8000dc8: 4770 bx lr 8000dca: bf00 nop 8000dcc: 20000210 .word 0x20000210 08000dd0 : void matrixScan(void){ 8000dd0: b580 push {r7, lr} 8000dd2: b082 sub sp, #8 8000dd4: af00 add r7, sp, #0 for (uint8_t col = 0; col < COL; col++){ 8000dd6: 2300 movs r3, #0 8000dd8: 71fb strb r3, [r7, #7] 8000dda: e044 b.n 8000e66 HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); 8000ddc: 79fb ldrb r3, [r7, #7] 8000dde: 4a26 ldr r2, [pc, #152] @ (8000e78 ) 8000de0: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000de4: 79fb ldrb r3, [r7, #7] 8000de6: 4a24 ldr r2, [pc, #144] @ (8000e78 ) 8000de8: 00db lsls r3, r3, #3 8000dea: 4413 add r3, r2 8000dec: 889b ldrh r3, [r3, #4] 8000dee: 2201 movs r2, #1 8000df0: 4619 mov r1, r3 8000df2: f001 fd7f bl 80028f4 HAL_Delay(1); 8000df6: 2001 movs r0, #1 8000df8: f000 fe98 bl 8001b2c for(uint8_t row = 0; row < ROW; row++){ 8000dfc: 2300 movs r3, #0 8000dfe: 71bb strb r3, [r7, #6] 8000e00: e01e b.n 8000e40 if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){ 8000e02: 79bb ldrb r3, [r7, #6] 8000e04: 4a1d ldr r2, [pc, #116] @ (8000e7c ) 8000e06: f852 2033 ldr.w r2, [r2, r3, lsl #3] 8000e0a: 79bb ldrb r3, [r7, #6] 8000e0c: 491b ldr r1, [pc, #108] @ (8000e7c ) 8000e0e: 00db lsls r3, r3, #3 8000e10: 440b add r3, r1 8000e12: 889b ldrh r3, [r3, #4] 8000e14: 4619 mov r1, r3 8000e16: 4610 mov r0, r2 8000e18: f001 fd54 bl 80028c4 8000e1c: 4603 mov r3, r0 8000e1e: 2b00 cmp r3, #0 8000e20: d00b beq.n 8000e3a addUSBReport(KEYCODES[row][col]); 8000e22: 79ba ldrb r2, [r7, #6] 8000e24: 79f9 ldrb r1, [r7, #7] 8000e26: 4816 ldr r0, [pc, #88] @ (8000e80 ) 8000e28: 4613 mov r3, r2 8000e2a: 009b lsls r3, r3, #2 8000e2c: 4413 add r3, r2 8000e2e: 4403 add r3, r0 8000e30: 440b add r3, r1 8000e32: 781b ldrb r3, [r3, #0] 8000e34: 4618 mov r0, r3 8000e36: f7ff ff97 bl 8000d68 for(uint8_t row = 0; row < ROW; row++){ 8000e3a: 79bb ldrb r3, [r7, #6] 8000e3c: 3301 adds r3, #1 8000e3e: 71bb strb r3, [r7, #6] 8000e40: 79bb ldrb r3, [r7, #6] 8000e42: 2b05 cmp r3, #5 8000e44: d9dd bls.n 8000e02 } } HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); 8000e46: 79fb ldrb r3, [r7, #7] 8000e48: 4a0b ldr r2, [pc, #44] @ (8000e78 ) 8000e4a: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000e4e: 79fb ldrb r3, [r7, #7] 8000e50: 4a09 ldr r2, [pc, #36] @ (8000e78 ) 8000e52: 00db lsls r3, r3, #3 8000e54: 4413 add r3, r2 8000e56: 889b ldrh r3, [r3, #4] 8000e58: 2200 movs r2, #0 8000e5a: 4619 mov r1, r3 8000e5c: f001 fd4a bl 80028f4 for (uint8_t col = 0; col < COL; col++){ 8000e60: 79fb ldrb r3, [r7, #7] 8000e62: 3301 adds r3, #1 8000e64: 71fb strb r3, [r7, #7] 8000e66: 79fb ldrb r3, [r7, #7] 8000e68: 2b04 cmp r3, #4 8000e6a: d9b7 bls.n 8000ddc } } 8000e6c: bf00 nop 8000e6e: bf00 nop 8000e70: 3708 adds r7, #8 8000e72: 46bd mov sp, r7 8000e74: bd80 pop {r7, pc} 8000e76: bf00 nop 8000e78: 20000030 .word 0x20000030 8000e7c: 20000000 .word 0x20000000 8000e80: 20000058 .word 0x20000058 08000e84 : void resetReport(void){ 8000e84: b580 push {r7, lr} 8000e86: af00 add r7, sp, #0 REPORT.MODIFIER = 0; 8000e88: 4b04 ldr r3, [pc, #16] @ (8000e9c ) 8000e8a: 2200 movs r2, #0 8000e8c: 701a strb r2, [r3, #0] memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); 8000e8e: 220c movs r2, #12 8000e90: 2100 movs r1, #0 8000e92: 4803 ldr r0, [pc, #12] @ (8000ea0 ) 8000e94: f009 fdbc bl 800aa10 } 8000e98: bf00 nop 8000e9a: bd80 pop {r7, pc} 8000e9c: 20000210 .word 0x20000210 8000ea0: 20000212 .word 0x20000212 08000ea4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000ea4: b480 push {r7} 8000ea6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000ea8: b672 cpsid i } 8000eaa: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000eac: bf00 nop 8000eae: e7fd b.n 8000eac 08000eb0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000eb0: b480 push {r7} 8000eb2: b083 sub sp, #12 8000eb4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000eb6: 2300 movs r3, #0 8000eb8: 607b str r3, [r7, #4] 8000eba: 4b10 ldr r3, [pc, #64] @ (8000efc ) 8000ebc: 6c5b ldr r3, [r3, #68] @ 0x44 8000ebe: 4a0f ldr r2, [pc, #60] @ (8000efc ) 8000ec0: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000ec4: 6453 str r3, [r2, #68] @ 0x44 8000ec6: 4b0d ldr r3, [pc, #52] @ (8000efc ) 8000ec8: 6c5b ldr r3, [r3, #68] @ 0x44 8000eca: f403 4380 and.w r3, r3, #16384 @ 0x4000 8000ece: 607b str r3, [r7, #4] 8000ed0: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000ed2: 2300 movs r3, #0 8000ed4: 603b str r3, [r7, #0] 8000ed6: 4b09 ldr r3, [pc, #36] @ (8000efc ) 8000ed8: 6c1b ldr r3, [r3, #64] @ 0x40 8000eda: 4a08 ldr r2, [pc, #32] @ (8000efc ) 8000edc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000ee0: 6413 str r3, [r2, #64] @ 0x40 8000ee2: 4b06 ldr r3, [pc, #24] @ (8000efc ) 8000ee4: 6c1b ldr r3, [r3, #64] @ 0x40 8000ee6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000eea: 603b str r3, [r7, #0] 8000eec: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000eee: bf00 nop 8000ef0: 370c adds r7, #12 8000ef2: 46bd mov sp, r7 8000ef4: f85d 7b04 ldr.w r7, [sp], #4 8000ef8: 4770 bx lr 8000efa: bf00 nop 8000efc: 40023800 .word 0x40023800 08000f00 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000f00: b480 push {r7} 8000f02: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000f04: bf00 nop 8000f06: e7fd b.n 8000f04 08000f08 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000f08: b480 push {r7} 8000f0a: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000f0c: bf00 nop 8000f0e: e7fd b.n 8000f0c 08000f10 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000f10: b480 push {r7} 8000f12: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000f14: bf00 nop 8000f16: e7fd b.n 8000f14 08000f18 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000f18: b480 push {r7} 8000f1a: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000f1c: bf00 nop 8000f1e: e7fd b.n 8000f1c 08000f20 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000f20: b480 push {r7} 8000f22: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000f24: bf00 nop 8000f26: e7fd b.n 8000f24 08000f28 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000f28: b480 push {r7} 8000f2a: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000f2c: bf00 nop 8000f2e: 46bd mov sp, r7 8000f30: f85d 7b04 ldr.w r7, [sp], #4 8000f34: 4770 bx lr 08000f36 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000f36: b480 push {r7} 8000f38: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000f3a: bf00 nop 8000f3c: 46bd mov sp, r7 8000f3e: f85d 7b04 ldr.w r7, [sp], #4 8000f42: 4770 bx lr 08000f44 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000f44: b480 push {r7} 8000f46: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000f48: bf00 nop 8000f4a: 46bd mov sp, r7 8000f4c: f85d 7b04 ldr.w r7, [sp], #4 8000f50: 4770 bx lr 08000f52 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000f52: b580 push {r7, lr} 8000f54: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000f56: f000 fdc9 bl 8001aec /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000f5a: bf00 nop 8000f5c: bd80 pop {r7, pc} ... 08000f60 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8000f60: b580 push {r7, lr} 8000f62: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_rx); 8000f64: 4802 ldr r0, [pc, #8] @ (8000f70 ) 8000f66: f001 f8af bl 80020c8 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8000f6a: bf00 nop 8000f6c: bd80 pop {r7, pc} 8000f6e: bf00 nop 8000f70: 200004ec .word 0x200004ec 08000f74 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8000f74: b580 push {r7, lr} 8000f76: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_rx); 8000f78: 4802 ldr r0, [pc, #8] @ (8000f84 ) 8000f7a: f001 f8a5 bl 80020c8 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8000f7e: bf00 nop 8000f80: bd80 pop {r7, pc} 8000f82: bf00 nop 8000f84: 2000042c .word 0x2000042c 08000f88 : /** * @brief This function handles DMA1 stream4 global interrupt. */ void DMA1_Stream4_IRQHandler(void) { 8000f88: b580 push {r7, lr} 8000f8a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ /* USER CODE END DMA1_Stream4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_tx); 8000f8c: 4802 ldr r0, [pc, #8] @ (8000f98 ) 8000f8e: f001 f89b bl 80020c8 /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ /* USER CODE END DMA1_Stream4_IRQn 1 */ } 8000f92: bf00 nop 8000f94: bd80 pop {r7, pc} 8000f96: bf00 nop 8000f98: 2000048c .word 0x2000048c 08000f9c : /** * @brief This function handles DMA1 stream5 global interrupt. */ void DMA1_Stream5_IRQHandler(void) { 8000f9c: b580 push {r7, lr} 8000f9e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ /* USER CODE END DMA1_Stream5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8000fa0: 4802 ldr r0, [pc, #8] @ (8000fac ) 8000fa2: f001 f891 bl 80020c8 /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ /* USER CODE END DMA1_Stream5_IRQn 1 */ } 8000fa6: bf00 nop 8000fa8: bd80 pop {r7, pc} 8000faa: bf00 nop 8000fac: 2000066c .word 0x2000066c 08000fb0 : /** * @brief This function handles DMA1 stream6 global interrupt. */ void DMA1_Stream6_IRQHandler(void) { 8000fb0: b580 push {r7, lr} 8000fb2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ /* USER CODE END DMA1_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 8000fb4: 4802 ldr r0, [pc, #8] @ (8000fc0 ) 8000fb6: f001 f887 bl 80020c8 /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ /* USER CODE END DMA1_Stream6_IRQn 1 */ } 8000fba: bf00 nop 8000fbc: bd80 pop {r7, pc} 8000fbe: bf00 nop 8000fc0: 200006cc .word 0x200006cc 08000fc4 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8000fc4: b580 push {r7, lr} 8000fc6: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8000fc8: 4802 ldr r0, [pc, #8] @ (8000fd4 ) 8000fca: f004 fe9f bl 8005d0c /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8000fce: bf00 nop 8000fd0: bd80 pop {r7, pc} 8000fd2: bf00 nop 8000fd4: 2000039c .word 0x2000039c 08000fd8 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 8000fd8: b580 push {r7, lr} 8000fda: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8000fdc: 4802 ldr r0, [pc, #8] @ (8000fe8 ) 8000fde: f004 fe95 bl 8005d0c /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 8000fe2: bf00 nop 8000fe4: bd80 pop {r7, pc} 8000fe6: bf00 nop 8000fe8: 200003e4 .word 0x200003e4 08000fec : /** * @brief This function handles DMA1 stream7 global interrupt. */ void DMA1_Stream7_IRQHandler(void) { 8000fec: b580 push {r7, lr} 8000fee: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ /* USER CODE END DMA1_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_tx); 8000ff0: 4802 ldr r0, [pc, #8] @ (8000ffc ) 8000ff2: f001 f869 bl 80020c8 /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ /* USER CODE END DMA1_Stream7_IRQn 1 */ } 8000ff6: bf00 nop 8000ff8: bd80 pop {r7, pc} 8000ffa: bf00 nop 8000ffc: 2000054c .word 0x2000054c 08001000 : /** * @brief This function handles UART4 global interrupt. */ void UART4_IRQHandler(void) { 8001000: b580 push {r7, lr} 8001002: af00 add r7, sp, #0 /* USER CODE BEGIN UART4_IRQn 0 */ /* USER CODE END UART4_IRQn 0 */ HAL_UART_IRQHandler(&huart4); 8001004: 4802 ldr r0, [pc, #8] @ (8001010 ) 8001006: f004 fe81 bl 8005d0c /* USER CODE BEGIN UART4_IRQn 1 */ /* USER CODE END UART4_IRQn 1 */ } 800100a: bf00 nop 800100c: bd80 pop {r7, pc} 800100e: bf00 nop 8001010: 2000030c .word 0x2000030c 08001014 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 8001014: b580 push {r7, lr} 8001016: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 8001018: 4802 ldr r0, [pc, #8] @ (8001024 ) 800101a: f004 fe77 bl 8005d0c /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 800101e: bf00 nop 8001020: bd80 pop {r7, pc} 8001022: bf00 nop 8001024: 20000354 .word 0x20000354 08001028 : /** * @brief This function handles DMA2 stream2 global interrupt. */ void DMA2_Stream2_IRQHandler(void) { 8001028: b580 push {r7, lr} 800102a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 800102c: 4802 ldr r0, [pc, #8] @ (8001038 ) 800102e: f001 f84b bl 80020c8 /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } 8001032: bf00 nop 8001034: bd80 pop {r7, pc} 8001036: bf00 nop 8001038: 200005ac .word 0x200005ac 0800103c : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 800103c: b580 push {r7, lr} 800103e: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 8001040: 4802 ldr r0, [pc, #8] @ (800104c ) 8001042: f001 ff00 bl 8002e46 /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 8001046: bf00 nop 8001048: bd80 pop {r7, pc} 800104a: bf00 nop 800104c: 20000c10 .word 0x20000c10 08001050 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 8001050: b580 push {r7, lr} 8001052: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8001054: 4802 ldr r0, [pc, #8] @ (8001060 ) 8001056: f001 f837 bl 80020c8 /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 800105a: bf00 nop 800105c: bd80 pop {r7, pc} 800105e: bf00 nop 8001060: 2000060c .word 0x2000060c 08001064 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8001064: b480 push {r7} 8001066: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8001068: 4b06 ldr r3, [pc, #24] @ (8001084 ) 800106a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800106e: 4a05 ldr r2, [pc, #20] @ (8001084 ) 8001070: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8001074: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001078: bf00 nop 800107a: 46bd mov sp, r7 800107c: f85d 7b04 ldr.w r7, [sp], #4 8001080: 4770 bx lr 8001082: bf00 nop 8001084: e000ed00 .word 0xe000ed00 08001088 : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { 8001088: b580 push {r7, lr} 800108a: b08a sub sp, #40 @ 0x28 800108c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 800108e: f107 0320 add.w r3, r7, #32 8001092: 2200 movs r2, #0 8001094: 601a str r2, [r3, #0] 8001096: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 8001098: 1d3b adds r3, r7, #4 800109a: 2200 movs r2, #0 800109c: 601a str r2, [r3, #0] 800109e: 605a str r2, [r3, #4] 80010a0: 609a str r2, [r3, #8] 80010a2: 60da str r2, [r3, #12] 80010a4: 611a str r2, [r3, #16] 80010a6: 615a str r2, [r3, #20] 80010a8: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80010aa: 4b22 ldr r3, [pc, #136] @ (8001134 ) 80010ac: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80010b0: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 80010b2: 4b20 ldr r3, [pc, #128] @ (8001134 ) 80010b4: 2200 movs r2, #0 80010b6: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80010b8: 4b1e ldr r3, [pc, #120] @ (8001134 ) 80010ba: 2200 movs r2, #0 80010bc: 609a str r2, [r3, #8] htim2.Init.Period = 4294967295; 80010be: 4b1d ldr r3, [pc, #116] @ (8001134 ) 80010c0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80010c4: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80010c6: 4b1b ldr r3, [pc, #108] @ (8001134 ) 80010c8: 2200 movs r2, #0 80010ca: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80010cc: 4b19 ldr r3, [pc, #100] @ (8001134 ) 80010ce: 2200 movs r2, #0 80010d0: 619a str r2, [r3, #24] if (HAL_TIM_OC_Init(&htim2) != HAL_OK) 80010d2: 4818 ldr r0, [pc, #96] @ (8001134 ) 80010d4: f004 f904 bl 80052e0 80010d8: 4603 mov r3, r0 80010da: 2b00 cmp r3, #0 80010dc: d001 beq.n 80010e2 { Error_Handler(); 80010de: f7ff fee1 bl 8000ea4 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80010e2: 2300 movs r3, #0 80010e4: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80010e6: 2300 movs r3, #0 80010e8: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 80010ea: f107 0320 add.w r3, r7, #32 80010ee: 4619 mov r1, r3 80010f0: 4810 ldr r0, [pc, #64] @ (8001134 ) 80010f2: f004 fc9d bl 8005a30 80010f6: 4603 mov r3, r0 80010f8: 2b00 cmp r3, #0 80010fa: d001 beq.n 8001100 { Error_Handler(); 80010fc: f7ff fed2 bl 8000ea4 } sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; 8001100: 2350 movs r3, #80 @ 0x50 8001102: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 8001104: 2300 movs r3, #0 8001106: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001108: 2300 movs r3, #0 800110a: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800110c: 2300 movs r3, #0 800110e: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001110: 1d3b adds r3, r7, #4 8001112: 2200 movs r2, #0 8001114: 4619 mov r1, r3 8001116: 4807 ldr r0, [pc, #28] @ (8001134 ) 8001118: f004 f9d8 bl 80054cc 800111c: 4603 mov r3, r0 800111e: 2b00 cmp r3, #0 8001120: d001 beq.n 8001126 { Error_Handler(); 8001122: f7ff febf bl 8000ea4 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 8001126: 4803 ldr r0, [pc, #12] @ (8001134 ) 8001128: f000 f8c2 bl 80012b0 } 800112c: bf00 nop 800112e: 3728 adds r7, #40 @ 0x28 8001130: 46bd mov sp, r7 8001132: bd80 pop {r7, pc} 8001134: 2000027c .word 0x2000027c 08001138 : /* TIM3 init function */ void MX_TIM3_Init(void) { 8001138: b580 push {r7, lr} 800113a: b08c sub sp, #48 @ 0x30 800113c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 800113e: f107 030c add.w r3, r7, #12 8001142: 2224 movs r2, #36 @ 0x24 8001144: 2100 movs r1, #0 8001146: 4618 mov r0, r3 8001148: f009 fc62 bl 800aa10 TIM_MasterConfigTypeDef sMasterConfig = {0}; 800114c: 1d3b adds r3, r7, #4 800114e: 2200 movs r2, #0 8001150: 601a str r2, [r3, #0] 8001152: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8001154: 4b20 ldr r3, [pc, #128] @ (80011d8 ) 8001156: 4a21 ldr r2, [pc, #132] @ (80011dc ) 8001158: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800115a: 4b1f ldr r3, [pc, #124] @ (80011d8 ) 800115c: 2200 movs r2, #0 800115e: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001160: 4b1d ldr r3, [pc, #116] @ (80011d8 ) 8001162: 2200 movs r2, #0 8001164: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 8001166: 4b1c ldr r3, [pc, #112] @ (80011d8 ) 8001168: f64f 72ff movw r2, #65535 @ 0xffff 800116c: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800116e: 4b1a ldr r3, [pc, #104] @ (80011d8 ) 8001170: 2200 movs r2, #0 8001172: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001174: 4b18 ldr r3, [pc, #96] @ (80011d8 ) 8001176: 2200 movs r2, #0 8001178: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI1; 800117a: 2301 movs r3, #1 800117c: 60fb str r3, [r7, #12] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 800117e: 2300 movs r3, #0 8001180: 613b str r3, [r7, #16] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 8001182: 2301 movs r3, #1 8001184: 617b str r3, [r7, #20] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 8001186: 2300 movs r3, #0 8001188: 61bb str r3, [r7, #24] sConfig.IC1Filter = 0; 800118a: 2300 movs r3, #0 800118c: 61fb str r3, [r7, #28] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 800118e: 2300 movs r3, #0 8001190: 623b str r3, [r7, #32] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 8001192: 2301 movs r3, #1 8001194: 627b str r3, [r7, #36] @ 0x24 sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 8001196: 2300 movs r3, #0 8001198: 62bb str r3, [r7, #40] @ 0x28 sConfig.IC2Filter = 0; 800119a: 2300 movs r3, #0 800119c: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 800119e: f107 030c add.w r3, r7, #12 80011a2: 4619 mov r1, r3 80011a4: 480c ldr r0, [pc, #48] @ (80011d8 ) 80011a6: f004 f8ea bl 800537e 80011aa: 4603 mov r3, r0 80011ac: 2b00 cmp r3, #0 80011ae: d001 beq.n 80011b4 { Error_Handler(); 80011b0: f7ff fe78 bl 8000ea4 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80011b4: 2300 movs r3, #0 80011b6: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80011b8: 2300 movs r3, #0 80011ba: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80011bc: 1d3b adds r3, r7, #4 80011be: 4619 mov r1, r3 80011c0: 4805 ldr r0, [pc, #20] @ (80011d8 ) 80011c2: f004 fc35 bl 8005a30 80011c6: 4603 mov r3, r0 80011c8: 2b00 cmp r3, #0 80011ca: d001 beq.n 80011d0 { Error_Handler(); 80011cc: f7ff fe6a bl 8000ea4 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 80011d0: bf00 nop 80011d2: 3730 adds r7, #48 @ 0x30 80011d4: 46bd mov sp, r7 80011d6: bd80 pop {r7, pc} 80011d8: 200002c4 .word 0x200002c4 80011dc: 40000400 .word 0x40000400 080011e0 : void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) { 80011e0: b480 push {r7} 80011e2: b085 sub sp, #20 80011e4: af00 add r7, sp, #0 80011e6: 6078 str r0, [r7, #4] if(tim_ocHandle->Instance==TIM2) 80011e8: 687b ldr r3, [r7, #4] 80011ea: 681b ldr r3, [r3, #0] 80011ec: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80011f0: d10d bne.n 800120e { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 80011f2: 2300 movs r3, #0 80011f4: 60fb str r3, [r7, #12] 80011f6: 4b09 ldr r3, [pc, #36] @ (800121c ) 80011f8: 6c1b ldr r3, [r3, #64] @ 0x40 80011fa: 4a08 ldr r2, [pc, #32] @ (800121c ) 80011fc: f043 0301 orr.w r3, r3, #1 8001200: 6413 str r3, [r2, #64] @ 0x40 8001202: 4b06 ldr r3, [pc, #24] @ (800121c ) 8001204: 6c1b ldr r3, [r3, #64] @ 0x40 8001206: f003 0301 and.w r3, r3, #1 800120a: 60fb str r3, [r7, #12] 800120c: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 800120e: bf00 nop 8001210: 3714 adds r7, #20 8001212: 46bd mov sp, r7 8001214: f85d 7b04 ldr.w r7, [sp], #4 8001218: 4770 bx lr 800121a: bf00 nop 800121c: 40023800 .word 0x40023800 08001220 : void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) { 8001220: b580 push {r7, lr} 8001222: b08a sub sp, #40 @ 0x28 8001224: af00 add r7, sp, #0 8001226: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001228: f107 0314 add.w r3, r7, #20 800122c: 2200 movs r2, #0 800122e: 601a str r2, [r3, #0] 8001230: 605a str r2, [r3, #4] 8001232: 609a str r2, [r3, #8] 8001234: 60da str r2, [r3, #12] 8001236: 611a str r2, [r3, #16] if(tim_encoderHandle->Instance==TIM3) 8001238: 687b ldr r3, [r7, #4] 800123a: 681b ldr r3, [r3, #0] 800123c: 4a19 ldr r2, [pc, #100] @ (80012a4 ) 800123e: 4293 cmp r3, r2 8001240: d12b bne.n 800129a { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 8001242: 2300 movs r3, #0 8001244: 613b str r3, [r7, #16] 8001246: 4b18 ldr r3, [pc, #96] @ (80012a8 ) 8001248: 6c1b ldr r3, [r3, #64] @ 0x40 800124a: 4a17 ldr r2, [pc, #92] @ (80012a8 ) 800124c: f043 0302 orr.w r3, r3, #2 8001250: 6413 str r3, [r2, #64] @ 0x40 8001252: 4b15 ldr r3, [pc, #84] @ (80012a8 ) 8001254: 6c1b ldr r3, [r3, #64] @ 0x40 8001256: f003 0302 and.w r3, r3, #2 800125a: 613b str r3, [r7, #16] 800125c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800125e: 2300 movs r3, #0 8001260: 60fb str r3, [r7, #12] 8001262: 4b11 ldr r3, [pc, #68] @ (80012a8 ) 8001264: 6b1b ldr r3, [r3, #48] @ 0x30 8001266: 4a10 ldr r2, [pc, #64] @ (80012a8 ) 8001268: f043 0301 orr.w r3, r3, #1 800126c: 6313 str r3, [r2, #48] @ 0x30 800126e: 4b0e ldr r3, [pc, #56] @ (80012a8 ) 8001270: 6b1b ldr r3, [r3, #48] @ 0x30 8001272: f003 0301 and.w r3, r3, #1 8001276: 60fb str r3, [r7, #12] 8001278: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 800127a: 23c0 movs r3, #192 @ 0xc0 800127c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800127e: 2302 movs r3, #2 8001280: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001282: 2300 movs r3, #0 8001284: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001286: 2300 movs r3, #0 8001288: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 800128a: 2302 movs r3, #2 800128c: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800128e: f107 0314 add.w r3, r7, #20 8001292: 4619 mov r1, r3 8001294: 4805 ldr r0, [pc, #20] @ (80012ac ) 8001296: f001 f981 bl 800259c /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 800129a: bf00 nop 800129c: 3728 adds r7, #40 @ 0x28 800129e: 46bd mov sp, r7 80012a0: bd80 pop {r7, pc} 80012a2: bf00 nop 80012a4: 40000400 .word 0x40000400 80012a8: 40023800 .word 0x40023800 80012ac: 40020000 .word 0x40020000 080012b0 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 80012b0: b580 push {r7, lr} 80012b2: b088 sub sp, #32 80012b4: af00 add r7, sp, #0 80012b6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80012b8: f107 030c add.w r3, r7, #12 80012bc: 2200 movs r2, #0 80012be: 601a str r2, [r3, #0] 80012c0: 605a str r2, [r3, #4] 80012c2: 609a str r2, [r3, #8] 80012c4: 60da str r2, [r3, #12] 80012c6: 611a str r2, [r3, #16] if(timHandle->Instance==TIM2) 80012c8: 687b ldr r3, [r7, #4] 80012ca: 681b ldr r3, [r3, #0] 80012cc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80012d0: d11d bne.n 800130e { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80012d2: 2300 movs r3, #0 80012d4: 60bb str r3, [r7, #8] 80012d6: 4b10 ldr r3, [pc, #64] @ (8001318 ) 80012d8: 6b1b ldr r3, [r3, #48] @ 0x30 80012da: 4a0f ldr r2, [pc, #60] @ (8001318 ) 80012dc: f043 0301 orr.w r3, r3, #1 80012e0: 6313 str r3, [r2, #48] @ 0x30 80012e2: 4b0d ldr r3, [pc, #52] @ (8001318 ) 80012e4: 6b1b ldr r3, [r3, #48] @ 0x30 80012e6: f003 0301 and.w r3, r3, #1 80012ea: 60bb str r3, [r7, #8] 80012ec: 68bb ldr r3, [r7, #8] /**TIM2 GPIO Configuration PA5 ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 80012ee: 2320 movs r3, #32 80012f0: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80012f2: 2302 movs r3, #2 80012f4: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012f6: 2300 movs r3, #0 80012f8: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80012fa: 2300 movs r3, #0 80012fc: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 80012fe: 2301 movs r3, #1 8001300: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001302: f107 030c add.w r3, r7, #12 8001306: 4619 mov r1, r3 8001308: 4804 ldr r0, [pc, #16] @ (800131c ) 800130a: f001 f947 bl 800259c /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 800130e: bf00 nop 8001310: 3720 adds r7, #32 8001312: 46bd mov sp, r7 8001314: bd80 pop {r7, pc} 8001316: bf00 nop 8001318: 40023800 .word 0x40023800 800131c: 40020000 .word 0x40020000 08001320 : DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart2_tx; /* UART4 init function */ void MX_UART4_Init(void) { 8001320: b580 push {r7, lr} 8001322: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 8001324: 4b11 ldr r3, [pc, #68] @ (800136c ) 8001326: 4a12 ldr r2, [pc, #72] @ (8001370 ) 8001328: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 800132a: 4b10 ldr r3, [pc, #64] @ (800136c ) 800132c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001330: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 8001332: 4b0e ldr r3, [pc, #56] @ (800136c ) 8001334: 2200 movs r2, #0 8001336: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 8001338: 4b0c ldr r3, [pc, #48] @ (800136c ) 800133a: 2200 movs r2, #0 800133c: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 800133e: 4b0b ldr r3, [pc, #44] @ (800136c ) 8001340: 2200 movs r2, #0 8001342: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 8001344: 4b09 ldr r3, [pc, #36] @ (800136c ) 8001346: 220c movs r2, #12 8001348: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800134a: 4b08 ldr r3, [pc, #32] @ (800136c ) 800134c: 2200 movs r2, #0 800134e: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 8001350: 4b06 ldr r3, [pc, #24] @ (800136c ) 8001352: 2200 movs r2, #0 8001354: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart4) != HAL_OK) 8001356: 4805 ldr r0, [pc, #20] @ (800136c ) 8001358: f004 fbe6 bl 8005b28 800135c: 4603 mov r3, r0 800135e: 2b00 cmp r3, #0 8001360: d001 beq.n 8001366 { Error_Handler(); 8001362: f7ff fd9f bl 8000ea4 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 8001366: bf00 nop 8001368: bd80 pop {r7, pc} 800136a: bf00 nop 800136c: 2000030c .word 0x2000030c 8001370: 40004c00 .word 0x40004c00 08001374 : /* UART5 init function */ void MX_UART5_Init(void) { 8001374: b580 push {r7, lr} 8001376: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 8001378: 4b11 ldr r3, [pc, #68] @ (80013c0 ) 800137a: 4a12 ldr r2, [pc, #72] @ (80013c4 ) 800137c: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 800137e: 4b10 ldr r3, [pc, #64] @ (80013c0 ) 8001380: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001384: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 8001386: 4b0e ldr r3, [pc, #56] @ (80013c0 ) 8001388: 2200 movs r2, #0 800138a: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800138c: 4b0c ldr r3, [pc, #48] @ (80013c0 ) 800138e: 2200 movs r2, #0 8001390: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 8001392: 4b0b ldr r3, [pc, #44] @ (80013c0 ) 8001394: 2200 movs r2, #0 8001396: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 8001398: 4b09 ldr r3, [pc, #36] @ (80013c0 ) 800139a: 220c movs r2, #12 800139c: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800139e: 4b08 ldr r3, [pc, #32] @ (80013c0 ) 80013a0: 2200 movs r2, #0 80013a2: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 80013a4: 4b06 ldr r3, [pc, #24] @ (80013c0 ) 80013a6: 2200 movs r2, #0 80013a8: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 80013aa: 4805 ldr r0, [pc, #20] @ (80013c0 ) 80013ac: f004 fbbc bl 8005b28 80013b0: 4603 mov r3, r0 80013b2: 2b00 cmp r3, #0 80013b4: d001 beq.n 80013ba { Error_Handler(); 80013b6: f7ff fd75 bl 8000ea4 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 80013ba: bf00 nop 80013bc: bd80 pop {r7, pc} 80013be: bf00 nop 80013c0: 20000354 .word 0x20000354 80013c4: 40005000 .word 0x40005000 080013c8 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 80013c8: b580 push {r7, lr} 80013ca: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80013cc: 4b11 ldr r3, [pc, #68] @ (8001414 ) 80013ce: 4a12 ldr r2, [pc, #72] @ (8001418 ) 80013d0: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80013d2: 4b10 ldr r3, [pc, #64] @ (8001414 ) 80013d4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80013d8: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80013da: 4b0e ldr r3, [pc, #56] @ (8001414 ) 80013dc: 2200 movs r2, #0 80013de: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80013e0: 4b0c ldr r3, [pc, #48] @ (8001414 ) 80013e2: 2200 movs r2, #0 80013e4: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80013e6: 4b0b ldr r3, [pc, #44] @ (8001414 ) 80013e8: 2200 movs r2, #0 80013ea: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80013ec: 4b09 ldr r3, [pc, #36] @ (8001414 ) 80013ee: 220c movs r2, #12 80013f0: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80013f2: 4b08 ldr r3, [pc, #32] @ (8001414 ) 80013f4: 2200 movs r2, #0 80013f6: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80013f8: 4b06 ldr r3, [pc, #24] @ (8001414 ) 80013fa: 2200 movs r2, #0 80013fc: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 80013fe: 4805 ldr r0, [pc, #20] @ (8001414 ) 8001400: f004 fb92 bl 8005b28 8001404: 4603 mov r3, r0 8001406: 2b00 cmp r3, #0 8001408: d001 beq.n 800140e { Error_Handler(); 800140a: f7ff fd4b bl 8000ea4 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800140e: bf00 nop 8001410: bd80 pop {r7, pc} 8001412: bf00 nop 8001414: 2000039c .word 0x2000039c 8001418: 40011000 .word 0x40011000 0800141c : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800141c: b580 push {r7, lr} 800141e: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8001420: 4b11 ldr r3, [pc, #68] @ (8001468 ) 8001422: 4a12 ldr r2, [pc, #72] @ (800146c ) 8001424: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 8001426: 4b10 ldr r3, [pc, #64] @ (8001468 ) 8001428: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800142c: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800142e: 4b0e ldr r3, [pc, #56] @ (8001468 ) 8001430: 2200 movs r2, #0 8001432: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8001434: 4b0c ldr r3, [pc, #48] @ (8001468 ) 8001436: 2200 movs r2, #0 8001438: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800143a: 4b0b ldr r3, [pc, #44] @ (8001468 ) 800143c: 2200 movs r2, #0 800143e: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8001440: 4b09 ldr r3, [pc, #36] @ (8001468 ) 8001442: 220c movs r2, #12 8001444: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001446: 4b08 ldr r3, [pc, #32] @ (8001468 ) 8001448: 2200 movs r2, #0 800144a: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800144c: 4b06 ldr r3, [pc, #24] @ (8001468 ) 800144e: 2200 movs r2, #0 8001450: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8001452: 4805 ldr r0, [pc, #20] @ (8001468 ) 8001454: f004 fb68 bl 8005b28 8001458: 4603 mov r3, r0 800145a: 2b00 cmp r3, #0 800145c: d001 beq.n 8001462 { Error_Handler(); 800145e: f7ff fd21 bl 8000ea4 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8001462: bf00 nop 8001464: bd80 pop {r7, pc} 8001466: bf00 nop 8001468: 200003e4 .word 0x200003e4 800146c: 40004400 .word 0x40004400 08001470 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8001470: b580 push {r7, lr} 8001472: b090 sub sp, #64 @ 0x40 8001474: af00 add r7, sp, #0 8001476: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001478: f107 032c add.w r3, r7, #44 @ 0x2c 800147c: 2200 movs r2, #0 800147e: 601a str r2, [r3, #0] 8001480: 605a str r2, [r3, #4] 8001482: 609a str r2, [r3, #8] 8001484: 60da str r2, [r3, #12] 8001486: 611a str r2, [r3, #16] if(uartHandle->Instance==UART4) 8001488: 687b ldr r3, [r7, #4] 800148a: 681b ldr r3, [r3, #0] 800148c: 4a4a ldr r2, [pc, #296] @ (80015b8 ) 800148e: 4293 cmp r3, r2 8001490: f040 80a0 bne.w 80015d4 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* UART4 clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 8001494: 2300 movs r3, #0 8001496: 62bb str r3, [r7, #40] @ 0x28 8001498: 4b48 ldr r3, [pc, #288] @ (80015bc ) 800149a: 6c1b ldr r3, [r3, #64] @ 0x40 800149c: 4a47 ldr r2, [pc, #284] @ (80015bc ) 800149e: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80014a2: 6413 str r3, [r2, #64] @ 0x40 80014a4: 4b45 ldr r3, [pc, #276] @ (80015bc ) 80014a6: 6c1b ldr r3, [r3, #64] @ 0x40 80014a8: f403 2300 and.w r3, r3, #524288 @ 0x80000 80014ac: 62bb str r3, [r7, #40] @ 0x28 80014ae: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 80014b0: 2300 movs r3, #0 80014b2: 627b str r3, [r7, #36] @ 0x24 80014b4: 4b41 ldr r3, [pc, #260] @ (80015bc ) 80014b6: 6b1b ldr r3, [r3, #48] @ 0x30 80014b8: 4a40 ldr r2, [pc, #256] @ (80015bc ) 80014ba: f043 0301 orr.w r3, r3, #1 80014be: 6313 str r3, [r2, #48] @ 0x30 80014c0: 4b3e ldr r3, [pc, #248] @ (80015bc ) 80014c2: 6b1b ldr r3, [r3, #48] @ 0x30 80014c4: f003 0301 and.w r3, r3, #1 80014c8: 627b str r3, [r7, #36] @ 0x24 80014ca: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART4 GPIO Configuration PA0-WKUP ------> UART4_TX PA1 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 80014cc: 2303 movs r3, #3 80014ce: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80014d0: 2302 movs r3, #2 80014d2: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80014d4: 2300 movs r3, #0 80014d6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80014d8: 2303 movs r3, #3 80014da: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 80014dc: 2308 movs r3, #8 80014de: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80014e0: f107 032c add.w r3, r7, #44 @ 0x2c 80014e4: 4619 mov r1, r3 80014e6: 4836 ldr r0, [pc, #216] @ (80015c0 ) 80014e8: f001 f858 bl 800259c /* UART4 DMA Init */ /* UART4_RX Init */ hdma_uart4_rx.Instance = DMA1_Stream2; 80014ec: 4b35 ldr r3, [pc, #212] @ (80015c4 ) 80014ee: 4a36 ldr r2, [pc, #216] @ (80015c8 ) 80014f0: 601a str r2, [r3, #0] hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; 80014f2: 4b34 ldr r3, [pc, #208] @ (80015c4 ) 80014f4: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80014f8: 605a str r2, [r3, #4] hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80014fa: 4b32 ldr r3, [pc, #200] @ (80015c4 ) 80014fc: 2200 movs r2, #0 80014fe: 609a str r2, [r3, #8] hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001500: 4b30 ldr r3, [pc, #192] @ (80015c4 ) 8001502: 2200 movs r2, #0 8001504: 60da str r2, [r3, #12] hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; 8001506: 4b2f ldr r3, [pc, #188] @ (80015c4 ) 8001508: f44f 6280 mov.w r2, #1024 @ 0x400 800150c: 611a str r2, [r3, #16] hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800150e: 4b2d ldr r3, [pc, #180] @ (80015c4 ) 8001510: 2200 movs r2, #0 8001512: 615a str r2, [r3, #20] hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001514: 4b2b ldr r3, [pc, #172] @ (80015c4 ) 8001516: 2200 movs r2, #0 8001518: 619a str r2, [r3, #24] hdma_uart4_rx.Init.Mode = DMA_NORMAL; 800151a: 4b2a ldr r3, [pc, #168] @ (80015c4 ) 800151c: 2200 movs r2, #0 800151e: 61da str r2, [r3, #28] hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; 8001520: 4b28 ldr r3, [pc, #160] @ (80015c4 ) 8001522: 2200 movs r2, #0 8001524: 621a str r2, [r3, #32] hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001526: 4b27 ldr r3, [pc, #156] @ (80015c4 ) 8001528: 2200 movs r2, #0 800152a: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) 800152c: 4825 ldr r0, [pc, #148] @ (80015c4 ) 800152e: f000 fc33 bl 8001d98 8001532: 4603 mov r3, r0 8001534: 2b00 cmp r3, #0 8001536: d001 beq.n 800153c { Error_Handler(); 8001538: f7ff fcb4 bl 8000ea4 } __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); 800153c: 687b ldr r3, [r7, #4] 800153e: 4a21 ldr r2, [pc, #132] @ (80015c4 ) 8001540: 63da str r2, [r3, #60] @ 0x3c 8001542: 4a20 ldr r2, [pc, #128] @ (80015c4 ) 8001544: 687b ldr r3, [r7, #4] 8001546: 6393 str r3, [r2, #56] @ 0x38 /* UART4_TX Init */ hdma_uart4_tx.Instance = DMA1_Stream4; 8001548: 4b20 ldr r3, [pc, #128] @ (80015cc ) 800154a: 4a21 ldr r2, [pc, #132] @ (80015d0 ) 800154c: 601a str r2, [r3, #0] hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; 800154e: 4b1f ldr r3, [pc, #124] @ (80015cc ) 8001550: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001554: 605a str r2, [r3, #4] hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001556: 4b1d ldr r3, [pc, #116] @ (80015cc ) 8001558: 2240 movs r2, #64 @ 0x40 800155a: 609a str r2, [r3, #8] hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800155c: 4b1b ldr r3, [pc, #108] @ (80015cc ) 800155e: 2200 movs r2, #0 8001560: 60da str r2, [r3, #12] hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; 8001562: 4b1a ldr r3, [pc, #104] @ (80015cc ) 8001564: f44f 6280 mov.w r2, #1024 @ 0x400 8001568: 611a str r2, [r3, #16] hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800156a: 4b18 ldr r3, [pc, #96] @ (80015cc ) 800156c: 2200 movs r2, #0 800156e: 615a str r2, [r3, #20] hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001570: 4b16 ldr r3, [pc, #88] @ (80015cc ) 8001572: 2200 movs r2, #0 8001574: 619a str r2, [r3, #24] hdma_uart4_tx.Init.Mode = DMA_NORMAL; 8001576: 4b15 ldr r3, [pc, #84] @ (80015cc ) 8001578: 2200 movs r2, #0 800157a: 61da str r2, [r3, #28] hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; 800157c: 4b13 ldr r3, [pc, #76] @ (80015cc ) 800157e: 2200 movs r2, #0 8001580: 621a str r2, [r3, #32] hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001582: 4b12 ldr r3, [pc, #72] @ (80015cc ) 8001584: 2200 movs r2, #0 8001586: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) 8001588: 4810 ldr r0, [pc, #64] @ (80015cc ) 800158a: f000 fc05 bl 8001d98 800158e: 4603 mov r3, r0 8001590: 2b00 cmp r3, #0 8001592: d001 beq.n 8001598 { Error_Handler(); 8001594: f7ff fc86 bl 8000ea4 } __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); 8001598: 687b ldr r3, [r7, #4] 800159a: 4a0c ldr r2, [pc, #48] @ (80015cc ) 800159c: 639a str r2, [r3, #56] @ 0x38 800159e: 4a0b ldr r2, [pc, #44] @ (80015cc ) 80015a0: 687b ldr r3, [r7, #4] 80015a2: 6393 str r3, [r2, #56] @ 0x38 /* UART4 interrupt Init */ HAL_NVIC_SetPriority(UART4_IRQn, 5, 0); 80015a4: 2200 movs r2, #0 80015a6: 2105 movs r1, #5 80015a8: 2034 movs r0, #52 @ 0x34 80015aa: f000 fbbe bl 8001d2a HAL_NVIC_EnableIRQ(UART4_IRQn); 80015ae: 2034 movs r0, #52 @ 0x34 80015b0: f000 fbd7 bl 8001d62 HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 80015b4: e202 b.n 80019bc 80015b6: bf00 nop 80015b8: 40004c00 .word 0x40004c00 80015bc: 40023800 .word 0x40023800 80015c0: 40020000 .word 0x40020000 80015c4: 2000042c .word 0x2000042c 80015c8: 40026040 .word 0x40026040 80015cc: 2000048c .word 0x2000048c 80015d0: 40026070 .word 0x40026070 else if(uartHandle->Instance==UART5) 80015d4: 687b ldr r3, [r7, #4] 80015d6: 681b ldr r3, [r3, #0] 80015d8: 4a59 ldr r2, [pc, #356] @ (8001740 ) 80015da: 4293 cmp r3, r2 80015dc: f040 80c0 bne.w 8001760 __HAL_RCC_UART5_CLK_ENABLE(); 80015e0: 2300 movs r3, #0 80015e2: 623b str r3, [r7, #32] 80015e4: 4b57 ldr r3, [pc, #348] @ (8001744 ) 80015e6: 6c1b ldr r3, [r3, #64] @ 0x40 80015e8: 4a56 ldr r2, [pc, #344] @ (8001744 ) 80015ea: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80015ee: 6413 str r3, [r2, #64] @ 0x40 80015f0: 4b54 ldr r3, [pc, #336] @ (8001744 ) 80015f2: 6c1b ldr r3, [r3, #64] @ 0x40 80015f4: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80015f8: 623b str r3, [r7, #32] 80015fa: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 80015fc: 2300 movs r3, #0 80015fe: 61fb str r3, [r7, #28] 8001600: 4b50 ldr r3, [pc, #320] @ (8001744 ) 8001602: 6b1b ldr r3, [r3, #48] @ 0x30 8001604: 4a4f ldr r2, [pc, #316] @ (8001744 ) 8001606: f043 0304 orr.w r3, r3, #4 800160a: 6313 str r3, [r2, #48] @ 0x30 800160c: 4b4d ldr r3, [pc, #308] @ (8001744 ) 800160e: 6b1b ldr r3, [r3, #48] @ 0x30 8001610: f003 0304 and.w r3, r3, #4 8001614: 61fb str r3, [r7, #28] 8001616: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001618: 2300 movs r3, #0 800161a: 61bb str r3, [r7, #24] 800161c: 4b49 ldr r3, [pc, #292] @ (8001744 ) 800161e: 6b1b ldr r3, [r3, #48] @ 0x30 8001620: 4a48 ldr r2, [pc, #288] @ (8001744 ) 8001622: f043 0308 orr.w r3, r3, #8 8001626: 6313 str r3, [r2, #48] @ 0x30 8001628: 4b46 ldr r3, [pc, #280] @ (8001744 ) 800162a: 6b1b ldr r3, [r3, #48] @ 0x30 800162c: f003 0308 and.w r3, r3, #8 8001630: 61bb str r3, [r7, #24] 8001632: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_12; 8001634: f44f 5380 mov.w r3, #4096 @ 0x1000 8001638: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800163a: 2302 movs r3, #2 800163c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 800163e: 2300 movs r3, #0 8001640: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001642: 2303 movs r3, #3 8001644: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 8001646: 2308 movs r3, #8 8001648: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800164a: f107 032c add.w r3, r7, #44 @ 0x2c 800164e: 4619 mov r1, r3 8001650: 483d ldr r0, [pc, #244] @ (8001748 ) 8001652: f000 ffa3 bl 800259c GPIO_InitStruct.Pin = GPIO_PIN_2; 8001656: 2304 movs r3, #4 8001658: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800165a: 2302 movs r3, #2 800165c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 800165e: 2300 movs r3, #0 8001660: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001662: 2303 movs r3, #3 8001664: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 8001666: 2308 movs r3, #8 8001668: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800166a: f107 032c add.w r3, r7, #44 @ 0x2c 800166e: 4619 mov r1, r3 8001670: 4836 ldr r0, [pc, #216] @ (800174c ) 8001672: f000 ff93 bl 800259c hdma_uart5_rx.Instance = DMA1_Stream0; 8001676: 4b36 ldr r3, [pc, #216] @ (8001750 ) 8001678: 4a36 ldr r2, [pc, #216] @ (8001754 ) 800167a: 601a str r2, [r3, #0] hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; 800167c: 4b34 ldr r3, [pc, #208] @ (8001750 ) 800167e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001682: 605a str r2, [r3, #4] hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001684: 4b32 ldr r3, [pc, #200] @ (8001750 ) 8001686: 2200 movs r2, #0 8001688: 609a str r2, [r3, #8] hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800168a: 4b31 ldr r3, [pc, #196] @ (8001750 ) 800168c: 2200 movs r2, #0 800168e: 60da str r2, [r3, #12] hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; 8001690: 4b2f ldr r3, [pc, #188] @ (8001750 ) 8001692: f44f 6280 mov.w r2, #1024 @ 0x400 8001696: 611a str r2, [r3, #16] hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001698: 4b2d ldr r3, [pc, #180] @ (8001750 ) 800169a: 2200 movs r2, #0 800169c: 615a str r2, [r3, #20] hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800169e: 4b2c ldr r3, [pc, #176] @ (8001750 ) 80016a0: 2200 movs r2, #0 80016a2: 619a str r2, [r3, #24] hdma_uart5_rx.Init.Mode = DMA_NORMAL; 80016a4: 4b2a ldr r3, [pc, #168] @ (8001750 ) 80016a6: 2200 movs r2, #0 80016a8: 61da str r2, [r3, #28] hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; 80016aa: 4b29 ldr r3, [pc, #164] @ (8001750 ) 80016ac: 2200 movs r2, #0 80016ae: 621a str r2, [r3, #32] hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80016b0: 4b27 ldr r3, [pc, #156] @ (8001750 ) 80016b2: 2200 movs r2, #0 80016b4: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) 80016b6: 4826 ldr r0, [pc, #152] @ (8001750 ) 80016b8: f000 fb6e bl 8001d98 80016bc: 4603 mov r3, r0 80016be: 2b00 cmp r3, #0 80016c0: d001 beq.n 80016c6 Error_Handler(); 80016c2: f7ff fbef bl 8000ea4 __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); 80016c6: 687b ldr r3, [r7, #4] 80016c8: 4a21 ldr r2, [pc, #132] @ (8001750 ) 80016ca: 63da str r2, [r3, #60] @ 0x3c 80016cc: 4a20 ldr r2, [pc, #128] @ (8001750 ) 80016ce: 687b ldr r3, [r7, #4] 80016d0: 6393 str r3, [r2, #56] @ 0x38 hdma_uart5_tx.Instance = DMA1_Stream7; 80016d2: 4b21 ldr r3, [pc, #132] @ (8001758 ) 80016d4: 4a21 ldr r2, [pc, #132] @ (800175c ) 80016d6: 601a str r2, [r3, #0] hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; 80016d8: 4b1f ldr r3, [pc, #124] @ (8001758 ) 80016da: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80016de: 605a str r2, [r3, #4] hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80016e0: 4b1d ldr r3, [pc, #116] @ (8001758 ) 80016e2: 2240 movs r2, #64 @ 0x40 80016e4: 609a str r2, [r3, #8] hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80016e6: 4b1c ldr r3, [pc, #112] @ (8001758 ) 80016e8: 2200 movs r2, #0 80016ea: 60da str r2, [r3, #12] hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; 80016ec: 4b1a ldr r3, [pc, #104] @ (8001758 ) 80016ee: f44f 6280 mov.w r2, #1024 @ 0x400 80016f2: 611a str r2, [r3, #16] hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80016f4: 4b18 ldr r3, [pc, #96] @ (8001758 ) 80016f6: 2200 movs r2, #0 80016f8: 615a str r2, [r3, #20] hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80016fa: 4b17 ldr r3, [pc, #92] @ (8001758 ) 80016fc: 2200 movs r2, #0 80016fe: 619a str r2, [r3, #24] hdma_uart5_tx.Init.Mode = DMA_NORMAL; 8001700: 4b15 ldr r3, [pc, #84] @ (8001758 ) 8001702: 2200 movs r2, #0 8001704: 61da str r2, [r3, #28] hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; 8001706: 4b14 ldr r3, [pc, #80] @ (8001758 ) 8001708: 2200 movs r2, #0 800170a: 621a str r2, [r3, #32] hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800170c: 4b12 ldr r3, [pc, #72] @ (8001758 ) 800170e: 2200 movs r2, #0 8001710: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) 8001712: 4811 ldr r0, [pc, #68] @ (8001758 ) 8001714: f000 fb40 bl 8001d98 8001718: 4603 mov r3, r0 800171a: 2b00 cmp r3, #0 800171c: d001 beq.n 8001722 Error_Handler(); 800171e: f7ff fbc1 bl 8000ea4 __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); 8001722: 687b ldr r3, [r7, #4] 8001724: 4a0c ldr r2, [pc, #48] @ (8001758 ) 8001726: 639a str r2, [r3, #56] @ 0x38 8001728: 4a0b ldr r2, [pc, #44] @ (8001758 ) 800172a: 687b ldr r3, [r7, #4] 800172c: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); 800172e: 2200 movs r2, #0 8001730: 2105 movs r1, #5 8001732: 2035 movs r0, #53 @ 0x35 8001734: f000 faf9 bl 8001d2a HAL_NVIC_EnableIRQ(UART5_IRQn); 8001738: 2035 movs r0, #53 @ 0x35 800173a: f000 fb12 bl 8001d62 } 800173e: e13d b.n 80019bc 8001740: 40005000 .word 0x40005000 8001744: 40023800 .word 0x40023800 8001748: 40020800 .word 0x40020800 800174c: 40020c00 .word 0x40020c00 8001750: 200004ec .word 0x200004ec 8001754: 40026010 .word 0x40026010 8001758: 2000054c .word 0x2000054c 800175c: 400260b8 .word 0x400260b8 else if(uartHandle->Instance==USART1) 8001760: 687b ldr r3, [r7, #4] 8001762: 681b ldr r3, [r3, #0] 8001764: 4a97 ldr r2, [pc, #604] @ (80019c4 ) 8001766: 4293 cmp r3, r2 8001768: f040 8092 bne.w 8001890 __HAL_RCC_USART1_CLK_ENABLE(); 800176c: 2300 movs r3, #0 800176e: 617b str r3, [r7, #20] 8001770: 4b95 ldr r3, [pc, #596] @ (80019c8 ) 8001772: 6c5b ldr r3, [r3, #68] @ 0x44 8001774: 4a94 ldr r2, [pc, #592] @ (80019c8 ) 8001776: f043 0310 orr.w r3, r3, #16 800177a: 6453 str r3, [r2, #68] @ 0x44 800177c: 4b92 ldr r3, [pc, #584] @ (80019c8 ) 800177e: 6c5b ldr r3, [r3, #68] @ 0x44 8001780: f003 0310 and.w r3, r3, #16 8001784: 617b str r3, [r7, #20] 8001786: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001788: 2300 movs r3, #0 800178a: 613b str r3, [r7, #16] 800178c: 4b8e ldr r3, [pc, #568] @ (80019c8 ) 800178e: 6b1b ldr r3, [r3, #48] @ 0x30 8001790: 4a8d ldr r2, [pc, #564] @ (80019c8 ) 8001792: f043 0301 orr.w r3, r3, #1 8001796: 6313 str r3, [r2, #48] @ 0x30 8001798: 4b8b ldr r3, [pc, #556] @ (80019c8 ) 800179a: 6b1b ldr r3, [r3, #48] @ 0x30 800179c: f003 0301 and.w r3, r3, #1 80017a0: 613b str r3, [r7, #16] 80017a2: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 80017a4: f44f 63c0 mov.w r3, #1536 @ 0x600 80017a8: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80017aa: 2302 movs r3, #2 80017ac: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80017ae: 2300 movs r3, #0 80017b0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80017b2: 2303 movs r3, #3 80017b4: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 80017b6: 2307 movs r3, #7 80017b8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80017ba: f107 032c add.w r3, r7, #44 @ 0x2c 80017be: 4619 mov r1, r3 80017c0: 4882 ldr r0, [pc, #520] @ (80019cc ) 80017c2: f000 feeb bl 800259c hdma_usart1_rx.Instance = DMA2_Stream2; 80017c6: 4b82 ldr r3, [pc, #520] @ (80019d0 ) 80017c8: 4a82 ldr r2, [pc, #520] @ (80019d4 ) 80017ca: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; 80017cc: 4b80 ldr r3, [pc, #512] @ (80019d0 ) 80017ce: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80017d2: 605a str r2, [r3, #4] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80017d4: 4b7e ldr r3, [pc, #504] @ (80019d0 ) 80017d6: 2200 movs r2, #0 80017d8: 609a str r2, [r3, #8] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80017da: 4b7d ldr r3, [pc, #500] @ (80019d0 ) 80017dc: 2200 movs r2, #0 80017de: 60da str r2, [r3, #12] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 80017e0: 4b7b ldr r3, [pc, #492] @ (80019d0 ) 80017e2: f44f 6280 mov.w r2, #1024 @ 0x400 80017e6: 611a str r2, [r3, #16] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80017e8: 4b79 ldr r3, [pc, #484] @ (80019d0 ) 80017ea: 2200 movs r2, #0 80017ec: 615a str r2, [r3, #20] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80017ee: 4b78 ldr r3, [pc, #480] @ (80019d0 ) 80017f0: 2200 movs r2, #0 80017f2: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 80017f4: 4b76 ldr r3, [pc, #472] @ (80019d0 ) 80017f6: 2200 movs r2, #0 80017f8: 61da str r2, [r3, #28] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 80017fa: 4b75 ldr r3, [pc, #468] @ (80019d0 ) 80017fc: 2200 movs r2, #0 80017fe: 621a str r2, [r3, #32] hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001800: 4b73 ldr r3, [pc, #460] @ (80019d0 ) 8001802: 2200 movs r2, #0 8001804: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 8001806: 4872 ldr r0, [pc, #456] @ (80019d0 ) 8001808: f000 fac6 bl 8001d98 800180c: 4603 mov r3, r0 800180e: 2b00 cmp r3, #0 8001810: d001 beq.n 8001816 Error_Handler(); 8001812: f7ff fb47 bl 8000ea4 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); 8001816: 687b ldr r3, [r7, #4] 8001818: 4a6d ldr r2, [pc, #436] @ (80019d0 ) 800181a: 63da str r2, [r3, #60] @ 0x3c 800181c: 4a6c ldr r2, [pc, #432] @ (80019d0 ) 800181e: 687b ldr r3, [r7, #4] 8001820: 6393 str r3, [r2, #56] @ 0x38 hdma_usart1_tx.Instance = DMA2_Stream7; 8001822: 4b6d ldr r3, [pc, #436] @ (80019d8 ) 8001824: 4a6d ldr r2, [pc, #436] @ (80019dc ) 8001826: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; 8001828: 4b6b ldr r3, [pc, #428] @ (80019d8 ) 800182a: f04f 6200 mov.w r2, #134217728 @ 0x8000000 800182e: 605a str r2, [r3, #4] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001830: 4b69 ldr r3, [pc, #420] @ (80019d8 ) 8001832: 2240 movs r2, #64 @ 0x40 8001834: 609a str r2, [r3, #8] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001836: 4b68 ldr r3, [pc, #416] @ (80019d8 ) 8001838: 2200 movs r2, #0 800183a: 60da str r2, [r3, #12] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 800183c: 4b66 ldr r3, [pc, #408] @ (80019d8 ) 800183e: f44f 6280 mov.w r2, #1024 @ 0x400 8001842: 611a str r2, [r3, #16] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001844: 4b64 ldr r3, [pc, #400] @ (80019d8 ) 8001846: 2200 movs r2, #0 8001848: 615a str r2, [r3, #20] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800184a: 4b63 ldr r3, [pc, #396] @ (80019d8 ) 800184c: 2200 movs r2, #0 800184e: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 8001850: 4b61 ldr r3, [pc, #388] @ (80019d8 ) 8001852: 2200 movs r2, #0 8001854: 61da str r2, [r3, #28] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 8001856: 4b60 ldr r3, [pc, #384] @ (80019d8 ) 8001858: 2200 movs r2, #0 800185a: 621a str r2, [r3, #32] hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800185c: 4b5e ldr r3, [pc, #376] @ (80019d8 ) 800185e: 2200 movs r2, #0 8001860: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 8001862: 485d ldr r0, [pc, #372] @ (80019d8 ) 8001864: f000 fa98 bl 8001d98 8001868: 4603 mov r3, r0 800186a: 2b00 cmp r3, #0 800186c: d001 beq.n 8001872 Error_Handler(); 800186e: f7ff fb19 bl 8000ea4 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); 8001872: 687b ldr r3, [r7, #4] 8001874: 4a58 ldr r2, [pc, #352] @ (80019d8 ) 8001876: 639a str r2, [r3, #56] @ 0x38 8001878: 4a57 ldr r2, [pc, #348] @ (80019d8 ) 800187a: 687b ldr r3, [r7, #4] 800187c: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 800187e: 2200 movs r2, #0 8001880: 2105 movs r1, #5 8001882: 2025 movs r0, #37 @ 0x25 8001884: f000 fa51 bl 8001d2a HAL_NVIC_EnableIRQ(USART1_IRQn); 8001888: 2025 movs r0, #37 @ 0x25 800188a: f000 fa6a bl 8001d62 } 800188e: e095 b.n 80019bc else if(uartHandle->Instance==USART2) 8001890: 687b ldr r3, [r7, #4] 8001892: 681b ldr r3, [r3, #0] 8001894: 4a52 ldr r2, [pc, #328] @ (80019e0 ) 8001896: 4293 cmp r3, r2 8001898: f040 8090 bne.w 80019bc __HAL_RCC_USART2_CLK_ENABLE(); 800189c: 2300 movs r3, #0 800189e: 60fb str r3, [r7, #12] 80018a0: 4b49 ldr r3, [pc, #292] @ (80019c8 ) 80018a2: 6c1b ldr r3, [r3, #64] @ 0x40 80018a4: 4a48 ldr r2, [pc, #288] @ (80019c8 ) 80018a6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80018aa: 6413 str r3, [r2, #64] @ 0x40 80018ac: 4b46 ldr r3, [pc, #280] @ (80019c8 ) 80018ae: 6c1b ldr r3, [r3, #64] @ 0x40 80018b0: f403 3300 and.w r3, r3, #131072 @ 0x20000 80018b4: 60fb str r3, [r7, #12] 80018b6: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80018b8: 2300 movs r3, #0 80018ba: 60bb str r3, [r7, #8] 80018bc: 4b42 ldr r3, [pc, #264] @ (80019c8 ) 80018be: 6b1b ldr r3, [r3, #48] @ 0x30 80018c0: 4a41 ldr r2, [pc, #260] @ (80019c8 ) 80018c2: f043 0301 orr.w r3, r3, #1 80018c6: 6313 str r3, [r2, #48] @ 0x30 80018c8: 4b3f ldr r3, [pc, #252] @ (80019c8 ) 80018ca: 6b1b ldr r3, [r3, #48] @ 0x30 80018cc: f003 0301 and.w r3, r3, #1 80018d0: 60bb str r3, [r7, #8] 80018d2: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 80018d4: 230c movs r3, #12 80018d6: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80018d8: 2302 movs r3, #2 80018da: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80018dc: 2300 movs r3, #0 80018de: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80018e0: 2303 movs r3, #3 80018e2: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 80018e4: 2307 movs r3, #7 80018e6: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80018e8: f107 032c add.w r3, r7, #44 @ 0x2c 80018ec: 4619 mov r1, r3 80018ee: 4837 ldr r0, [pc, #220] @ (80019cc ) 80018f0: f000 fe54 bl 800259c hdma_usart2_rx.Instance = DMA1_Stream5; 80018f4: 4b3b ldr r3, [pc, #236] @ (80019e4 ) 80018f6: 4a3c ldr r2, [pc, #240] @ (80019e8 ) 80018f8: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; 80018fa: 4b3a ldr r3, [pc, #232] @ (80019e4 ) 80018fc: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001900: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001902: 4b38 ldr r3, [pc, #224] @ (80019e4 ) 8001904: 2200 movs r2, #0 8001906: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001908: 4b36 ldr r3, [pc, #216] @ (80019e4 ) 800190a: 2200 movs r2, #0 800190c: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 800190e: 4b35 ldr r3, [pc, #212] @ (80019e4 ) 8001910: f44f 6280 mov.w r2, #1024 @ 0x400 8001914: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001916: 4b33 ldr r3, [pc, #204] @ (80019e4 ) 8001918: 2200 movs r2, #0 800191a: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800191c: 4b31 ldr r3, [pc, #196] @ (80019e4 ) 800191e: 2200 movs r2, #0 8001920: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 8001922: 4b30 ldr r3, [pc, #192] @ (80019e4 ) 8001924: 2200 movs r2, #0 8001926: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 8001928: 4b2e ldr r3, [pc, #184] @ (80019e4 ) 800192a: 2200 movs r2, #0 800192c: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800192e: 4b2d ldr r3, [pc, #180] @ (80019e4 ) 8001930: 2200 movs r2, #0 8001932: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8001934: 482b ldr r0, [pc, #172] @ (80019e4 ) 8001936: f000 fa2f bl 8001d98 800193a: 4603 mov r3, r0 800193c: 2b00 cmp r3, #0 800193e: d001 beq.n 8001944 Error_Handler(); 8001940: f7ff fab0 bl 8000ea4 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 8001944: 687b ldr r3, [r7, #4] 8001946: 4a27 ldr r2, [pc, #156] @ (80019e4 ) 8001948: 63da str r2, [r3, #60] @ 0x3c 800194a: 4a26 ldr r2, [pc, #152] @ (80019e4 ) 800194c: 687b ldr r3, [r7, #4] 800194e: 6393 str r3, [r2, #56] @ 0x38 hdma_usart2_tx.Instance = DMA1_Stream6; 8001950: 4b26 ldr r3, [pc, #152] @ (80019ec ) 8001952: 4a27 ldr r2, [pc, #156] @ (80019f0 ) 8001954: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; 8001956: 4b25 ldr r3, [pc, #148] @ (80019ec ) 8001958: f04f 6200 mov.w r2, #134217728 @ 0x8000000 800195c: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800195e: 4b23 ldr r3, [pc, #140] @ (80019ec ) 8001960: 2240 movs r2, #64 @ 0x40 8001962: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001964: 4b21 ldr r3, [pc, #132] @ (80019ec ) 8001966: 2200 movs r2, #0 8001968: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 800196a: 4b20 ldr r3, [pc, #128] @ (80019ec ) 800196c: f44f 6280 mov.w r2, #1024 @ 0x400 8001970: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001972: 4b1e ldr r3, [pc, #120] @ (80019ec ) 8001974: 2200 movs r2, #0 8001976: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001978: 4b1c ldr r3, [pc, #112] @ (80019ec ) 800197a: 2200 movs r2, #0 800197c: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 800197e: 4b1b ldr r3, [pc, #108] @ (80019ec ) 8001980: 2200 movs r2, #0 8001982: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 8001984: 4b19 ldr r3, [pc, #100] @ (80019ec ) 8001986: 2200 movs r2, #0 8001988: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800198a: 4b18 ldr r3, [pc, #96] @ (80019ec ) 800198c: 2200 movs r2, #0 800198e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 8001990: 4816 ldr r0, [pc, #88] @ (80019ec ) 8001992: f000 fa01 bl 8001d98 8001996: 4603 mov r3, r0 8001998: 2b00 cmp r3, #0 800199a: d001 beq.n 80019a0 Error_Handler(); 800199c: f7ff fa82 bl 8000ea4 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 80019a0: 687b ldr r3, [r7, #4] 80019a2: 4a12 ldr r2, [pc, #72] @ (80019ec ) 80019a4: 639a str r2, [r3, #56] @ 0x38 80019a6: 4a11 ldr r2, [pc, #68] @ (80019ec ) 80019a8: 687b ldr r3, [r7, #4] 80019aa: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); 80019ac: 2200 movs r2, #0 80019ae: 2105 movs r1, #5 80019b0: 2026 movs r0, #38 @ 0x26 80019b2: f000 f9ba bl 8001d2a HAL_NVIC_EnableIRQ(USART2_IRQn); 80019b6: 2026 movs r0, #38 @ 0x26 80019b8: f000 f9d3 bl 8001d62 } 80019bc: bf00 nop 80019be: 3740 adds r7, #64 @ 0x40 80019c0: 46bd mov sp, r7 80019c2: bd80 pop {r7, pc} 80019c4: 40011000 .word 0x40011000 80019c8: 40023800 .word 0x40023800 80019cc: 40020000 .word 0x40020000 80019d0: 200005ac .word 0x200005ac 80019d4: 40026440 .word 0x40026440 80019d8: 2000060c .word 0x2000060c 80019dc: 400264b8 .word 0x400264b8 80019e0: 40004400 .word 0x40004400 80019e4: 2000066c .word 0x2000066c 80019e8: 40026088 .word 0x40026088 80019ec: 200006cc .word 0x200006cc 80019f0: 400260a0 .word 0x400260a0 080019f4 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 80019f4: f8df d034 ldr.w sp, [pc, #52] @ 8001a2c /* Call the clock system initialization function.*/ bl SystemInit 80019f8: f7ff fb34 bl 8001064 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80019fc: 480c ldr r0, [pc, #48] @ (8001a30 ) ldr r1, =_edata 80019fe: 490d ldr r1, [pc, #52] @ (8001a34 ) ldr r2, =_sidata 8001a00: 4a0d ldr r2, [pc, #52] @ (8001a38 ) movs r3, #0 8001a02: 2300 movs r3, #0 b LoopCopyDataInit 8001a04: e002 b.n 8001a0c 08001a06 : CopyDataInit: ldr r4, [r2, r3] 8001a06: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001a08: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001a0a: 3304 adds r3, #4 08001a0c : LoopCopyDataInit: adds r4, r0, r3 8001a0c: 18c4 adds r4, r0, r3 cmp r4, r1 8001a0e: 428c cmp r4, r1 bcc CopyDataInit 8001a10: d3f9 bcc.n 8001a06 /* Zero fill the bss segment. */ ldr r2, =_sbss 8001a12: 4a0a ldr r2, [pc, #40] @ (8001a3c ) ldr r4, =_ebss 8001a14: 4c0a ldr r4, [pc, #40] @ (8001a40 ) movs r3, #0 8001a16: 2300 movs r3, #0 b LoopFillZerobss 8001a18: e001 b.n 8001a1e 08001a1a : FillZerobss: str r3, [r2] 8001a1a: 6013 str r3, [r2, #0] adds r2, r2, #4 8001a1c: 3204 adds r2, #4 08001a1e : LoopFillZerobss: cmp r2, r4 8001a1e: 42a2 cmp r2, r4 bcc FillZerobss 8001a20: d3fb bcc.n 8001a1a /* Call static constructors */ bl __libc_init_array 8001a22: f008 fffd bl 800aa20 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001a26: f7fe feff bl 8000828
bx lr 8001a2a: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001a2c: 20020000 .word 0x20020000 ldr r0, =_sdata 8001a30: 20000000 .word 0x20000000 ldr r1, =_edata 8001a34: 200001a0 .word 0x200001a0 ldr r2, =_sidata 8001a38: 0800aaec .word 0x0800aaec ldr r2, =_sbss 8001a3c: 200001a0 .word 0x200001a0 ldr r4, =_ebss 8001a40: 20001108 .word 0x20001108 08001a44 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001a44: e7fe b.n 8001a44 ... 08001a48 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001a48: b580 push {r7, lr} 8001a4a: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8001a4c: 4b0e ldr r3, [pc, #56] @ (8001a88 ) 8001a4e: 681b ldr r3, [r3, #0] 8001a50: 4a0d ldr r2, [pc, #52] @ (8001a88 ) 8001a52: f443 7300 orr.w r3, r3, #512 @ 0x200 8001a56: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8001a58: 4b0b ldr r3, [pc, #44] @ (8001a88 ) 8001a5a: 681b ldr r3, [r3, #0] 8001a5c: 4a0a ldr r2, [pc, #40] @ (8001a88 ) 8001a5e: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001a62: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001a64: 4b08 ldr r3, [pc, #32] @ (8001a88 ) 8001a66: 681b ldr r3, [r3, #0] 8001a68: 4a07 ldr r2, [pc, #28] @ (8001a88 ) 8001a6a: f443 7380 orr.w r3, r3, #256 @ 0x100 8001a6e: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001a70: 2003 movs r0, #3 8001a72: f000 f94f bl 8001d14 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001a76: 200f movs r0, #15 8001a78: f000 f808 bl 8001a8c /* Init the low level hardware */ HAL_MspInit(); 8001a7c: f7ff fa18 bl 8000eb0 /* Return function status */ return HAL_OK; 8001a80: 2300 movs r3, #0 } 8001a82: 4618 mov r0, r3 8001a84: bd80 pop {r7, pc} 8001a86: bf00 nop 8001a88: 40023c00 .word 0x40023c00 08001a8c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001a8c: b580 push {r7, lr} 8001a8e: b082 sub sp, #8 8001a90: af00 add r7, sp, #0 8001a92: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001a94: 4b12 ldr r3, [pc, #72] @ (8001ae0 ) 8001a96: 681a ldr r2, [r3, #0] 8001a98: 4b12 ldr r3, [pc, #72] @ (8001ae4 ) 8001a9a: 781b ldrb r3, [r3, #0] 8001a9c: 4619 mov r1, r3 8001a9e: f44f 737a mov.w r3, #1000 @ 0x3e8 8001aa2: fbb3 f3f1 udiv r3, r3, r1 8001aa6: fbb2 f3f3 udiv r3, r2, r3 8001aaa: 4618 mov r0, r3 8001aac: f000 f967 bl 8001d7e 8001ab0: 4603 mov r3, r0 8001ab2: 2b00 cmp r3, #0 8001ab4: d001 beq.n 8001aba { return HAL_ERROR; 8001ab6: 2301 movs r3, #1 8001ab8: e00e b.n 8001ad8 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001aba: 687b ldr r3, [r7, #4] 8001abc: 2b0f cmp r3, #15 8001abe: d80a bhi.n 8001ad6 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001ac0: 2200 movs r2, #0 8001ac2: 6879 ldr r1, [r7, #4] 8001ac4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001ac8: f000 f92f bl 8001d2a uwTickPrio = TickPriority; 8001acc: 4a06 ldr r2, [pc, #24] @ (8001ae8 ) 8001ace: 687b ldr r3, [r7, #4] 8001ad0: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8001ad2: 2300 movs r3, #0 8001ad4: e000 b.n 8001ad8 return HAL_ERROR; 8001ad6: 2301 movs r3, #1 } 8001ad8: 4618 mov r0, r3 8001ada: 3708 adds r7, #8 8001adc: 46bd mov sp, r7 8001ade: bd80 pop {r7, pc} 8001ae0: 20000090 .word 0x20000090 8001ae4: 20000098 .word 0x20000098 8001ae8: 20000094 .word 0x20000094 08001aec : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001aec: b480 push {r7} 8001aee: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001af0: 4b06 ldr r3, [pc, #24] @ (8001b0c ) 8001af2: 781b ldrb r3, [r3, #0] 8001af4: 461a mov r2, r3 8001af6: 4b06 ldr r3, [pc, #24] @ (8001b10 ) 8001af8: 681b ldr r3, [r3, #0] 8001afa: 4413 add r3, r2 8001afc: 4a04 ldr r2, [pc, #16] @ (8001b10 ) 8001afe: 6013 str r3, [r2, #0] } 8001b00: bf00 nop 8001b02: 46bd mov sp, r7 8001b04: f85d 7b04 ldr.w r7, [sp], #4 8001b08: 4770 bx lr 8001b0a: bf00 nop 8001b0c: 20000098 .word 0x20000098 8001b10: 2000072c .word 0x2000072c 08001b14 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001b14: b480 push {r7} 8001b16: af00 add r7, sp, #0 return uwTick; 8001b18: 4b03 ldr r3, [pc, #12] @ (8001b28 ) 8001b1a: 681b ldr r3, [r3, #0] } 8001b1c: 4618 mov r0, r3 8001b1e: 46bd mov sp, r7 8001b20: f85d 7b04 ldr.w r7, [sp], #4 8001b24: 4770 bx lr 8001b26: bf00 nop 8001b28: 2000072c .word 0x2000072c 08001b2c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001b2c: b580 push {r7, lr} 8001b2e: b084 sub sp, #16 8001b30: af00 add r7, sp, #0 8001b32: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001b34: f7ff ffee bl 8001b14 8001b38: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001b3a: 687b ldr r3, [r7, #4] 8001b3c: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001b3e: 68fb ldr r3, [r7, #12] 8001b40: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001b44: d005 beq.n 8001b52 { wait += (uint32_t)(uwTickFreq); 8001b46: 4b0a ldr r3, [pc, #40] @ (8001b70 ) 8001b48: 781b ldrb r3, [r3, #0] 8001b4a: 461a mov r2, r3 8001b4c: 68fb ldr r3, [r7, #12] 8001b4e: 4413 add r3, r2 8001b50: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001b52: bf00 nop 8001b54: f7ff ffde bl 8001b14 8001b58: 4602 mov r2, r0 8001b5a: 68bb ldr r3, [r7, #8] 8001b5c: 1ad3 subs r3, r2, r3 8001b5e: 68fa ldr r2, [r7, #12] 8001b60: 429a cmp r2, r3 8001b62: d8f7 bhi.n 8001b54 { } } 8001b64: bf00 nop 8001b66: bf00 nop 8001b68: 3710 adds r7, #16 8001b6a: 46bd mov sp, r7 8001b6c: bd80 pop {r7, pc} 8001b6e: bf00 nop 8001b70: 20000098 .word 0x20000098 08001b74 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001b74: b480 push {r7} 8001b76: b085 sub sp, #20 8001b78: af00 add r7, sp, #0 8001b7a: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001b7c: 687b ldr r3, [r7, #4] 8001b7e: f003 0307 and.w r3, r3, #7 8001b82: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001b84: 4b0c ldr r3, [pc, #48] @ (8001bb8 <__NVIC_SetPriorityGrouping+0x44>) 8001b86: 68db ldr r3, [r3, #12] 8001b88: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001b8a: 68ba ldr r2, [r7, #8] 8001b8c: f64f 03ff movw r3, #63743 @ 0xf8ff 8001b90: 4013 ands r3, r2 8001b92: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001b94: 68fb ldr r3, [r7, #12] 8001b96: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001b98: 68bb ldr r3, [r7, #8] 8001b9a: 4313 orrs r3, r2 reg_value = (reg_value | 8001b9c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8001ba0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001ba4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001ba6: 4a04 ldr r2, [pc, #16] @ (8001bb8 <__NVIC_SetPriorityGrouping+0x44>) 8001ba8: 68bb ldr r3, [r7, #8] 8001baa: 60d3 str r3, [r2, #12] } 8001bac: bf00 nop 8001bae: 3714 adds r7, #20 8001bb0: 46bd mov sp, r7 8001bb2: f85d 7b04 ldr.w r7, [sp], #4 8001bb6: 4770 bx lr 8001bb8: e000ed00 .word 0xe000ed00 08001bbc <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001bbc: b480 push {r7} 8001bbe: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001bc0: 4b04 ldr r3, [pc, #16] @ (8001bd4 <__NVIC_GetPriorityGrouping+0x18>) 8001bc2: 68db ldr r3, [r3, #12] 8001bc4: 0a1b lsrs r3, r3, #8 8001bc6: f003 0307 and.w r3, r3, #7 } 8001bca: 4618 mov r0, r3 8001bcc: 46bd mov sp, r7 8001bce: f85d 7b04 ldr.w r7, [sp], #4 8001bd2: 4770 bx lr 8001bd4: e000ed00 .word 0xe000ed00 08001bd8 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001bd8: b480 push {r7} 8001bda: b083 sub sp, #12 8001bdc: af00 add r7, sp, #0 8001bde: 4603 mov r3, r0 8001be0: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001be2: f997 3007 ldrsb.w r3, [r7, #7] 8001be6: 2b00 cmp r3, #0 8001be8: db0b blt.n 8001c02 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001bea: 79fb ldrb r3, [r7, #7] 8001bec: f003 021f and.w r2, r3, #31 8001bf0: 4907 ldr r1, [pc, #28] @ (8001c10 <__NVIC_EnableIRQ+0x38>) 8001bf2: f997 3007 ldrsb.w r3, [r7, #7] 8001bf6: 095b lsrs r3, r3, #5 8001bf8: 2001 movs r0, #1 8001bfa: fa00 f202 lsl.w r2, r0, r2 8001bfe: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001c02: bf00 nop 8001c04: 370c adds r7, #12 8001c06: 46bd mov sp, r7 8001c08: f85d 7b04 ldr.w r7, [sp], #4 8001c0c: 4770 bx lr 8001c0e: bf00 nop 8001c10: e000e100 .word 0xe000e100 08001c14 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001c14: b480 push {r7} 8001c16: b083 sub sp, #12 8001c18: af00 add r7, sp, #0 8001c1a: 4603 mov r3, r0 8001c1c: 6039 str r1, [r7, #0] 8001c1e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001c20: f997 3007 ldrsb.w r3, [r7, #7] 8001c24: 2b00 cmp r3, #0 8001c26: db0a blt.n 8001c3e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001c28: 683b ldr r3, [r7, #0] 8001c2a: b2da uxtb r2, r3 8001c2c: 490c ldr r1, [pc, #48] @ (8001c60 <__NVIC_SetPriority+0x4c>) 8001c2e: f997 3007 ldrsb.w r3, [r7, #7] 8001c32: 0112 lsls r2, r2, #4 8001c34: b2d2 uxtb r2, r2 8001c36: 440b add r3, r1 8001c38: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001c3c: e00a b.n 8001c54 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001c3e: 683b ldr r3, [r7, #0] 8001c40: b2da uxtb r2, r3 8001c42: 4908 ldr r1, [pc, #32] @ (8001c64 <__NVIC_SetPriority+0x50>) 8001c44: 79fb ldrb r3, [r7, #7] 8001c46: f003 030f and.w r3, r3, #15 8001c4a: 3b04 subs r3, #4 8001c4c: 0112 lsls r2, r2, #4 8001c4e: b2d2 uxtb r2, r2 8001c50: 440b add r3, r1 8001c52: 761a strb r2, [r3, #24] } 8001c54: bf00 nop 8001c56: 370c adds r7, #12 8001c58: 46bd mov sp, r7 8001c5a: f85d 7b04 ldr.w r7, [sp], #4 8001c5e: 4770 bx lr 8001c60: e000e100 .word 0xe000e100 8001c64: e000ed00 .word 0xe000ed00 08001c68 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001c68: b480 push {r7} 8001c6a: b089 sub sp, #36 @ 0x24 8001c6c: af00 add r7, sp, #0 8001c6e: 60f8 str r0, [r7, #12] 8001c70: 60b9 str r1, [r7, #8] 8001c72: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001c74: 68fb ldr r3, [r7, #12] 8001c76: f003 0307 and.w r3, r3, #7 8001c7a: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001c7c: 69fb ldr r3, [r7, #28] 8001c7e: f1c3 0307 rsb r3, r3, #7 8001c82: 2b04 cmp r3, #4 8001c84: bf28 it cs 8001c86: 2304 movcs r3, #4 8001c88: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001c8a: 69fb ldr r3, [r7, #28] 8001c8c: 3304 adds r3, #4 8001c8e: 2b06 cmp r3, #6 8001c90: d902 bls.n 8001c98 8001c92: 69fb ldr r3, [r7, #28] 8001c94: 3b03 subs r3, #3 8001c96: e000 b.n 8001c9a 8001c98: 2300 movs r3, #0 8001c9a: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001c9c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001ca0: 69bb ldr r3, [r7, #24] 8001ca2: fa02 f303 lsl.w r3, r2, r3 8001ca6: 43da mvns r2, r3 8001ca8: 68bb ldr r3, [r7, #8] 8001caa: 401a ands r2, r3 8001cac: 697b ldr r3, [r7, #20] 8001cae: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001cb0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001cb4: 697b ldr r3, [r7, #20] 8001cb6: fa01 f303 lsl.w r3, r1, r3 8001cba: 43d9 mvns r1, r3 8001cbc: 687b ldr r3, [r7, #4] 8001cbe: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001cc0: 4313 orrs r3, r2 ); } 8001cc2: 4618 mov r0, r3 8001cc4: 3724 adds r7, #36 @ 0x24 8001cc6: 46bd mov sp, r7 8001cc8: f85d 7b04 ldr.w r7, [sp], #4 8001ccc: 4770 bx lr ... 08001cd0 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001cd0: b580 push {r7, lr} 8001cd2: b082 sub sp, #8 8001cd4: af00 add r7, sp, #0 8001cd6: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001cd8: 687b ldr r3, [r7, #4] 8001cda: 3b01 subs r3, #1 8001cdc: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8001ce0: d301 bcc.n 8001ce6 { return (1UL); /* Reload value impossible */ 8001ce2: 2301 movs r3, #1 8001ce4: e00f b.n 8001d06 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001ce6: 4a0a ldr r2, [pc, #40] @ (8001d10 ) 8001ce8: 687b ldr r3, [r7, #4] 8001cea: 3b01 subs r3, #1 8001cec: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001cee: 210f movs r1, #15 8001cf0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001cf4: f7ff ff8e bl 8001c14 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001cf8: 4b05 ldr r3, [pc, #20] @ (8001d10 ) 8001cfa: 2200 movs r2, #0 8001cfc: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001cfe: 4b04 ldr r3, [pc, #16] @ (8001d10 ) 8001d00: 2207 movs r2, #7 8001d02: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001d04: 2300 movs r3, #0 } 8001d06: 4618 mov r0, r3 8001d08: 3708 adds r7, #8 8001d0a: 46bd mov sp, r7 8001d0c: bd80 pop {r7, pc} 8001d0e: bf00 nop 8001d10: e000e010 .word 0xe000e010 08001d14 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001d14: b580 push {r7, lr} 8001d16: b082 sub sp, #8 8001d18: af00 add r7, sp, #0 8001d1a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001d1c: 6878 ldr r0, [r7, #4] 8001d1e: f7ff ff29 bl 8001b74 <__NVIC_SetPriorityGrouping> } 8001d22: bf00 nop 8001d24: 3708 adds r7, #8 8001d26: 46bd mov sp, r7 8001d28: bd80 pop {r7, pc} 08001d2a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001d2a: b580 push {r7, lr} 8001d2c: b086 sub sp, #24 8001d2e: af00 add r7, sp, #0 8001d30: 4603 mov r3, r0 8001d32: 60b9 str r1, [r7, #8] 8001d34: 607a str r2, [r7, #4] 8001d36: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001d38: 2300 movs r3, #0 8001d3a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001d3c: f7ff ff3e bl 8001bbc <__NVIC_GetPriorityGrouping> 8001d40: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001d42: 687a ldr r2, [r7, #4] 8001d44: 68b9 ldr r1, [r7, #8] 8001d46: 6978 ldr r0, [r7, #20] 8001d48: f7ff ff8e bl 8001c68 8001d4c: 4602 mov r2, r0 8001d4e: f997 300f ldrsb.w r3, [r7, #15] 8001d52: 4611 mov r1, r2 8001d54: 4618 mov r0, r3 8001d56: f7ff ff5d bl 8001c14 <__NVIC_SetPriority> } 8001d5a: bf00 nop 8001d5c: 3718 adds r7, #24 8001d5e: 46bd mov sp, r7 8001d60: bd80 pop {r7, pc} 08001d62 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001d62: b580 push {r7, lr} 8001d64: b082 sub sp, #8 8001d66: af00 add r7, sp, #0 8001d68: 4603 mov r3, r0 8001d6a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001d6c: f997 3007 ldrsb.w r3, [r7, #7] 8001d70: 4618 mov r0, r3 8001d72: f7ff ff31 bl 8001bd8 <__NVIC_EnableIRQ> } 8001d76: bf00 nop 8001d78: 3708 adds r7, #8 8001d7a: 46bd mov sp, r7 8001d7c: bd80 pop {r7, pc} 08001d7e : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001d7e: b580 push {r7, lr} 8001d80: b082 sub sp, #8 8001d82: af00 add r7, sp, #0 8001d84: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001d86: 6878 ldr r0, [r7, #4] 8001d88: f7ff ffa2 bl 8001cd0 8001d8c: 4603 mov r3, r0 } 8001d8e: 4618 mov r0, r3 8001d90: 3708 adds r7, #8 8001d92: 46bd mov sp, r7 8001d94: bd80 pop {r7, pc} ... 08001d98 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8001d98: b580 push {r7, lr} 8001d9a: b086 sub sp, #24 8001d9c: af00 add r7, sp, #0 8001d9e: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8001da0: 2300 movs r3, #0 8001da2: 617b str r3, [r7, #20] uint32_t tickstart = HAL_GetTick(); 8001da4: f7ff feb6 bl 8001b14 8001da8: 6138 str r0, [r7, #16] DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) 8001daa: 687b ldr r3, [r7, #4] 8001dac: 2b00 cmp r3, #0 8001dae: d101 bne.n 8001db4 { return HAL_ERROR; 8001db0: 2301 movs r3, #1 8001db2: e099 b.n 8001ee8 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001db4: 687b ldr r3, [r7, #4] 8001db6: 2202 movs r2, #2 8001db8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8001dbc: 687b ldr r3, [r7, #4] 8001dbe: 2200 movs r2, #0 8001dc0: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8001dc4: 687b ldr r3, [r7, #4] 8001dc6: 681b ldr r3, [r3, #0] 8001dc8: 681a ldr r2, [r3, #0] 8001dca: 687b ldr r3, [r7, #4] 8001dcc: 681b ldr r3, [r3, #0] 8001dce: f022 0201 bic.w r2, r2, #1 8001dd2: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001dd4: e00f b.n 8001df6 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001dd6: f7ff fe9d bl 8001b14 8001dda: 4602 mov r2, r0 8001ddc: 693b ldr r3, [r7, #16] 8001dde: 1ad3 subs r3, r2, r3 8001de0: 2b05 cmp r3, #5 8001de2: d908 bls.n 8001df6 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001de4: 687b ldr r3, [r7, #4] 8001de6: 2220 movs r2, #32 8001de8: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001dea: 687b ldr r3, [r7, #4] 8001dec: 2203 movs r2, #3 8001dee: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_TIMEOUT; 8001df2: 2303 movs r3, #3 8001df4: e078 b.n 8001ee8 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001df6: 687b ldr r3, [r7, #4] 8001df8: 681b ldr r3, [r3, #0] 8001dfa: 681b ldr r3, [r3, #0] 8001dfc: f003 0301 and.w r3, r3, #1 8001e00: 2b00 cmp r3, #0 8001e02: d1e8 bne.n 8001dd6 } } /* Get the CR register value */ tmp = hdma->Instance->CR; 8001e04: 687b ldr r3, [r7, #4] 8001e06: 681b ldr r3, [r3, #0] 8001e08: 681b ldr r3, [r3, #0] 8001e0a: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8001e0c: 697a ldr r2, [r7, #20] 8001e0e: 4b38 ldr r3, [pc, #224] @ (8001ef0 ) 8001e10: 4013 ands r3, r2 8001e12: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001e14: 687b ldr r3, [r7, #4] 8001e16: 685a ldr r2, [r3, #4] 8001e18: 687b ldr r3, [r7, #4] 8001e1a: 689b ldr r3, [r3, #8] 8001e1c: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001e1e: 687b ldr r3, [r7, #4] 8001e20: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001e22: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001e24: 687b ldr r3, [r7, #4] 8001e26: 691b ldr r3, [r3, #16] 8001e28: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001e2a: 687b ldr r3, [r7, #4] 8001e2c: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001e2e: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001e30: 687b ldr r3, [r7, #4] 8001e32: 699b ldr r3, [r3, #24] 8001e34: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001e36: 687b ldr r3, [r7, #4] 8001e38: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001e3a: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001e3c: 687b ldr r3, [r7, #4] 8001e3e: 6a1b ldr r3, [r3, #32] 8001e40: 4313 orrs r3, r2 tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001e42: 697a ldr r2, [r7, #20] 8001e44: 4313 orrs r3, r2 8001e46: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001e48: 687b ldr r3, [r7, #4] 8001e4a: 6a5b ldr r3, [r3, #36] @ 0x24 8001e4c: 2b04 cmp r3, #4 8001e4e: d107 bne.n 8001e60 { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8001e50: 687b ldr r3, [r7, #4] 8001e52: 6ada ldr r2, [r3, #44] @ 0x2c 8001e54: 687b ldr r3, [r7, #4] 8001e56: 6b1b ldr r3, [r3, #48] @ 0x30 8001e58: 4313 orrs r3, r2 8001e5a: 697a ldr r2, [r7, #20] 8001e5c: 4313 orrs r3, r2 8001e5e: 617b str r3, [r7, #20] } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; 8001e60: 687b ldr r3, [r7, #4] 8001e62: 681b ldr r3, [r3, #0] 8001e64: 697a ldr r2, [r7, #20] 8001e66: 601a str r2, [r3, #0] /* Get the FCR register value */ tmp = hdma->Instance->FCR; 8001e68: 687b ldr r3, [r7, #4] 8001e6a: 681b ldr r3, [r3, #0] 8001e6c: 695b ldr r3, [r3, #20] 8001e6e: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8001e70: 697b ldr r3, [r7, #20] 8001e72: f023 0307 bic.w r3, r3, #7 8001e76: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; 8001e78: 687b ldr r3, [r7, #4] 8001e7a: 6a5b ldr r3, [r3, #36] @ 0x24 8001e7c: 697a ldr r2, [r7, #20] 8001e7e: 4313 orrs r3, r2 8001e80: 617b str r3, [r7, #20] /* The FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001e82: 687b ldr r3, [r7, #4] 8001e84: 6a5b ldr r3, [r3, #36] @ 0x24 8001e86: 2b04 cmp r3, #4 8001e88: d117 bne.n 8001eba { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; 8001e8a: 687b ldr r3, [r7, #4] 8001e8c: 6a9b ldr r3, [r3, #40] @ 0x28 8001e8e: 697a ldr r2, [r7, #20] 8001e90: 4313 orrs r3, r2 8001e92: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8001e94: 687b ldr r3, [r7, #4] 8001e96: 6adb ldr r3, [r3, #44] @ 0x2c 8001e98: 2b00 cmp r3, #0 8001e9a: d00e beq.n 8001eba { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8001e9c: 6878 ldr r0, [r7, #4] 8001e9e: f000 fb01 bl 80024a4 8001ea2: 4603 mov r3, r0 8001ea4: 2b00 cmp r3, #0 8001ea6: d008 beq.n 8001eba { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8001ea8: 687b ldr r3, [r7, #4] 8001eaa: 2240 movs r2, #64 @ 0x40 8001eac: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001eae: 687b ldr r3, [r7, #4] 8001eb0: 2201 movs r2, #1 8001eb2: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8001eb6: 2301 movs r3, #1 8001eb8: e016 b.n 8001ee8 } } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; 8001eba: 687b ldr r3, [r7, #4] 8001ebc: 681b ldr r3, [r3, #0] 8001ebe: 697a ldr r2, [r7, #20] 8001ec0: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8001ec2: 6878 ldr r0, [r7, #4] 8001ec4: f000 fab8 bl 8002438 8001ec8: 4603 mov r3, r0 8001eca: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001ecc: 687b ldr r3, [r7, #4] 8001ece: 6ddb ldr r3, [r3, #92] @ 0x5c 8001ed0: 223f movs r2, #63 @ 0x3f 8001ed2: 409a lsls r2, r3 8001ed4: 68fb ldr r3, [r7, #12] 8001ed6: 609a str r2, [r3, #8] /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001ed8: 687b ldr r3, [r7, #4] 8001eda: 2200 movs r2, #0 8001edc: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001ede: 687b ldr r3, [r7, #4] 8001ee0: 2201 movs r2, #1 8001ee2: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8001ee6: 2300 movs r3, #0 } 8001ee8: 4618 mov r0, r3 8001eea: 3718 adds r7, #24 8001eec: 46bd mov sp, r7 8001eee: bd80 pop {r7, pc} 8001ef0: f010803f .word 0xf010803f 08001ef4 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8001ef4: b580 push {r7, lr} 8001ef6: b086 sub sp, #24 8001ef8: af00 add r7, sp, #0 8001efa: 60f8 str r0, [r7, #12] 8001efc: 60b9 str r1, [r7, #8] 8001efe: 607a str r2, [r7, #4] 8001f00: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8001f02: 2300 movs r3, #0 8001f04: 75fb strb r3, [r7, #23] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001f06: 68fb ldr r3, [r7, #12] 8001f08: 6d9b ldr r3, [r3, #88] @ 0x58 8001f0a: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8001f0c: 68fb ldr r3, [r7, #12] 8001f0e: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8001f12: 2b01 cmp r3, #1 8001f14: d101 bne.n 8001f1a 8001f16: 2302 movs r3, #2 8001f18: e040 b.n 8001f9c 8001f1a: 68fb ldr r3, [r7, #12] 8001f1c: 2201 movs r2, #1 8001f1e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8001f22: 68fb ldr r3, [r7, #12] 8001f24: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001f28: b2db uxtb r3, r3 8001f2a: 2b01 cmp r3, #1 8001f2c: d12f bne.n 8001f8e { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001f2e: 68fb ldr r3, [r7, #12] 8001f30: 2202 movs r2, #2 8001f32: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001f36: 68fb ldr r3, [r7, #12] 8001f38: 2200 movs r2, #0 8001f3a: 655a str r2, [r3, #84] @ 0x54 /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8001f3c: 683b ldr r3, [r7, #0] 8001f3e: 687a ldr r2, [r7, #4] 8001f40: 68b9 ldr r1, [r7, #8] 8001f42: 68f8 ldr r0, [r7, #12] 8001f44: f000 fa4a bl 80023dc /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001f48: 68fb ldr r3, [r7, #12] 8001f4a: 6ddb ldr r3, [r3, #92] @ 0x5c 8001f4c: 223f movs r2, #63 @ 0x3f 8001f4e: 409a lsls r2, r3 8001f50: 693b ldr r3, [r7, #16] 8001f52: 609a str r2, [r3, #8] /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 8001f54: 68fb ldr r3, [r7, #12] 8001f56: 681b ldr r3, [r3, #0] 8001f58: 681a ldr r2, [r3, #0] 8001f5a: 68fb ldr r3, [r7, #12] 8001f5c: 681b ldr r3, [r3, #0] 8001f5e: f042 0216 orr.w r2, r2, #22 8001f62: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8001f64: 68fb ldr r3, [r7, #12] 8001f66: 6c1b ldr r3, [r3, #64] @ 0x40 8001f68: 2b00 cmp r3, #0 8001f6a: d007 beq.n 8001f7c { hdma->Instance->CR |= DMA_IT_HT; 8001f6c: 68fb ldr r3, [r7, #12] 8001f6e: 681b ldr r3, [r3, #0] 8001f70: 681a ldr r2, [r3, #0] 8001f72: 68fb ldr r3, [r7, #12] 8001f74: 681b ldr r3, [r3, #0] 8001f76: f042 0208 orr.w r2, r2, #8 8001f7a: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8001f7c: 68fb ldr r3, [r7, #12] 8001f7e: 681b ldr r3, [r3, #0] 8001f80: 681a ldr r2, [r3, #0] 8001f82: 68fb ldr r3, [r7, #12] 8001f84: 681b ldr r3, [r3, #0] 8001f86: f042 0201 orr.w r2, r2, #1 8001f8a: 601a str r2, [r3, #0] 8001f8c: e005 b.n 8001f9a } else { /* Process unlocked */ __HAL_UNLOCK(hdma); 8001f8e: 68fb ldr r3, [r7, #12] 8001f90: 2200 movs r2, #0 8001f92: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_BUSY; 8001f96: 2302 movs r3, #2 8001f98: 75fb strb r3, [r7, #23] } return status; 8001f9a: 7dfb ldrb r3, [r7, #23] } 8001f9c: 4618 mov r0, r3 8001f9e: 3718 adds r7, #24 8001fa0: 46bd mov sp, r7 8001fa2: bd80 pop {r7, pc} 08001fa4 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8001fa4: b580 push {r7, lr} 8001fa6: b084 sub sp, #16 8001fa8: af00 add r7, sp, #0 8001faa: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001fac: 687b ldr r3, [r7, #4] 8001fae: 6d9b ldr r3, [r3, #88] @ 0x58 8001fb0: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 8001fb2: f7ff fdaf bl 8001b14 8001fb6: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 8001fb8: 687b ldr r3, [r7, #4] 8001fba: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001fbe: b2db uxtb r3, r3 8001fc0: 2b02 cmp r3, #2 8001fc2: d008 beq.n 8001fd6 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001fc4: 687b ldr r3, [r7, #4] 8001fc6: 2280 movs r2, #128 @ 0x80 8001fc8: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001fca: 687b ldr r3, [r7, #4] 8001fcc: 2200 movs r2, #0 8001fce: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8001fd2: 2301 movs r3, #1 8001fd4: e052 b.n 800207c } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8001fd6: 687b ldr r3, [r7, #4] 8001fd8: 681b ldr r3, [r3, #0] 8001fda: 681a ldr r2, [r3, #0] 8001fdc: 687b ldr r3, [r7, #4] 8001fde: 681b ldr r3, [r3, #0] 8001fe0: f022 0216 bic.w r2, r2, #22 8001fe4: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8001fe6: 687b ldr r3, [r7, #4] 8001fe8: 681b ldr r3, [r3, #0] 8001fea: 695a ldr r2, [r3, #20] 8001fec: 687b ldr r3, [r7, #4] 8001fee: 681b ldr r3, [r3, #0] 8001ff0: f022 0280 bic.w r2, r2, #128 @ 0x80 8001ff4: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8001ff6: 687b ldr r3, [r7, #4] 8001ff8: 6c1b ldr r3, [r3, #64] @ 0x40 8001ffa: 2b00 cmp r3, #0 8001ffc: d103 bne.n 8002006 8001ffe: 687b ldr r3, [r7, #4] 8002000: 6c9b ldr r3, [r3, #72] @ 0x48 8002002: 2b00 cmp r3, #0 8002004: d007 beq.n 8002016 { hdma->Instance->CR &= ~(DMA_IT_HT); 8002006: 687b ldr r3, [r7, #4] 8002008: 681b ldr r3, [r3, #0] 800200a: 681a ldr r2, [r3, #0] 800200c: 687b ldr r3, [r7, #4] 800200e: 681b ldr r3, [r3, #0] 8002010: f022 0208 bic.w r2, r2, #8 8002014: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8002016: 687b ldr r3, [r7, #4] 8002018: 681b ldr r3, [r3, #0] 800201a: 681a ldr r2, [r3, #0] 800201c: 687b ldr r3, [r7, #4] 800201e: 681b ldr r3, [r3, #0] 8002020: f022 0201 bic.w r2, r2, #1 8002024: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8002026: e013 b.n 8002050 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8002028: f7ff fd74 bl 8001b14 800202c: 4602 mov r2, r0 800202e: 68bb ldr r3, [r7, #8] 8002030: 1ad3 subs r3, r2, r3 8002032: 2b05 cmp r3, #5 8002034: d90c bls.n 8002050 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8002036: 687b ldr r3, [r7, #4] 8002038: 2220 movs r2, #32 800203a: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 800203c: 687b ldr r3, [r7, #4] 800203e: 2203 movs r2, #3 8002040: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002044: 687b ldr r3, [r7, #4] 8002046: 2200 movs r2, #0 8002048: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_TIMEOUT; 800204c: 2303 movs r3, #3 800204e: e015 b.n 800207c while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8002050: 687b ldr r3, [r7, #4] 8002052: 681b ldr r3, [r3, #0] 8002054: 681b ldr r3, [r3, #0] 8002056: f003 0301 and.w r3, r3, #1 800205a: 2b00 cmp r3, #0 800205c: d1e4 bne.n 8002028 } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 800205e: 687b ldr r3, [r7, #4] 8002060: 6ddb ldr r3, [r3, #92] @ 0x5c 8002062: 223f movs r2, #63 @ 0x3f 8002064: 409a lsls r2, r3 8002066: 68fb ldr r3, [r7, #12] 8002068: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800206a: 687b ldr r3, [r7, #4] 800206c: 2201 movs r2, #1 800206e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002072: 687b ldr r3, [r7, #4] 8002074: 2200 movs r2, #0 8002076: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 800207a: 2300 movs r3, #0 } 800207c: 4618 mov r0, r3 800207e: 3710 adds r7, #16 8002080: 46bd mov sp, r7 8002082: bd80 pop {r7, pc} 08002084 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8002084: b480 push {r7} 8002086: b083 sub sp, #12 8002088: af00 add r7, sp, #0 800208a: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 800208c: 687b ldr r3, [r7, #4] 800208e: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8002092: b2db uxtb r3, r3 8002094: 2b02 cmp r3, #2 8002096: d004 beq.n 80020a2 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002098: 687b ldr r3, [r7, #4] 800209a: 2280 movs r2, #128 @ 0x80 800209c: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 800209e: 2301 movs r3, #1 80020a0: e00c b.n 80020bc } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 80020a2: 687b ldr r3, [r7, #4] 80020a4: 2205 movs r2, #5 80020a6: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80020aa: 687b ldr r3, [r7, #4] 80020ac: 681b ldr r3, [r3, #0] 80020ae: 681a ldr r2, [r3, #0] 80020b0: 687b ldr r3, [r7, #4] 80020b2: 681b ldr r3, [r3, #0] 80020b4: f022 0201 bic.w r2, r2, #1 80020b8: 601a str r2, [r3, #0] } return HAL_OK; 80020ba: 2300 movs r3, #0 } 80020bc: 4618 mov r0, r3 80020be: 370c adds r7, #12 80020c0: 46bd mov sp, r7 80020c2: f85d 7b04 ldr.w r7, [sp], #4 80020c6: 4770 bx lr 080020c8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 80020c8: b580 push {r7, lr} 80020ca: b086 sub sp, #24 80020cc: af00 add r7, sp, #0 80020ce: 6078 str r0, [r7, #4] uint32_t tmpisr; __IO uint32_t count = 0U; 80020d0: 2300 movs r3, #0 80020d2: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 80020d4: 4b8e ldr r3, [pc, #568] @ (8002310 ) 80020d6: 681b ldr r3, [r3, #0] 80020d8: 4a8e ldr r2, [pc, #568] @ (8002314 ) 80020da: fba2 2303 umull r2, r3, r2, r3 80020de: 0a9b lsrs r3, r3, #10 80020e0: 617b str r3, [r7, #20] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 80020e2: 687b ldr r3, [r7, #4] 80020e4: 6d9b ldr r3, [r3, #88] @ 0x58 80020e6: 613b str r3, [r7, #16] tmpisr = regs->ISR; 80020e8: 693b ldr r3, [r7, #16] 80020ea: 681b ldr r3, [r3, #0] 80020ec: 60fb str r3, [r7, #12] /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) 80020ee: 687b ldr r3, [r7, #4] 80020f0: 6ddb ldr r3, [r3, #92] @ 0x5c 80020f2: 2208 movs r2, #8 80020f4: 409a lsls r2, r3 80020f6: 68fb ldr r3, [r7, #12] 80020f8: 4013 ands r3, r2 80020fa: 2b00 cmp r3, #0 80020fc: d01a beq.n 8002134 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) 80020fe: 687b ldr r3, [r7, #4] 8002100: 681b ldr r3, [r3, #0] 8002102: 681b ldr r3, [r3, #0] 8002104: f003 0304 and.w r3, r3, #4 8002108: 2b00 cmp r3, #0 800210a: d013 beq.n 8002134 { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); 800210c: 687b ldr r3, [r7, #4] 800210e: 681b ldr r3, [r3, #0] 8002110: 681a ldr r2, [r3, #0] 8002112: 687b ldr r3, [r7, #4] 8002114: 681b ldr r3, [r3, #0] 8002116: f022 0204 bic.w r2, r2, #4 800211a: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; 800211c: 687b ldr r3, [r7, #4] 800211e: 6ddb ldr r3, [r3, #92] @ 0x5c 8002120: 2208 movs r2, #8 8002122: 409a lsls r2, r3 8002124: 693b ldr r3, [r7, #16] 8002126: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8002128: 687b ldr r3, [r7, #4] 800212a: 6d5b ldr r3, [r3, #84] @ 0x54 800212c: f043 0201 orr.w r2, r3, #1 8002130: 687b ldr r3, [r7, #4] 8002132: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) 8002134: 687b ldr r3, [r7, #4] 8002136: 6ddb ldr r3, [r3, #92] @ 0x5c 8002138: 2201 movs r2, #1 800213a: 409a lsls r2, r3 800213c: 68fb ldr r3, [r7, #12] 800213e: 4013 ands r3, r2 8002140: 2b00 cmp r3, #0 8002142: d012 beq.n 800216a { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) 8002144: 687b ldr r3, [r7, #4] 8002146: 681b ldr r3, [r3, #0] 8002148: 695b ldr r3, [r3, #20] 800214a: f003 0380 and.w r3, r3, #128 @ 0x80 800214e: 2b00 cmp r3, #0 8002150: d00b beq.n 800216a { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; 8002152: 687b ldr r3, [r7, #4] 8002154: 6ddb ldr r3, [r3, #92] @ 0x5c 8002156: 2201 movs r2, #1 8002158: 409a lsls r2, r3 800215a: 693b ldr r3, [r7, #16] 800215c: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 800215e: 687b ldr r3, [r7, #4] 8002160: 6d5b ldr r3, [r3, #84] @ 0x54 8002162: f043 0202 orr.w r2, r3, #2 8002166: 687b ldr r3, [r7, #4] 8002168: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) 800216a: 687b ldr r3, [r7, #4] 800216c: 6ddb ldr r3, [r3, #92] @ 0x5c 800216e: 2204 movs r2, #4 8002170: 409a lsls r2, r3 8002172: 68fb ldr r3, [r7, #12] 8002174: 4013 ands r3, r2 8002176: 2b00 cmp r3, #0 8002178: d012 beq.n 80021a0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) 800217a: 687b ldr r3, [r7, #4] 800217c: 681b ldr r3, [r3, #0] 800217e: 681b ldr r3, [r3, #0] 8002180: f003 0302 and.w r3, r3, #2 8002184: 2b00 cmp r3, #0 8002186: d00b beq.n 80021a0 { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; 8002188: 687b ldr r3, [r7, #4] 800218a: 6ddb ldr r3, [r3, #92] @ 0x5c 800218c: 2204 movs r2, #4 800218e: 409a lsls r2, r3 8002190: 693b ldr r3, [r7, #16] 8002192: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8002194: 687b ldr r3, [r7, #4] 8002196: 6d5b ldr r3, [r3, #84] @ 0x54 8002198: f043 0204 orr.w r2, r3, #4 800219c: 687b ldr r3, [r7, #4] 800219e: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) 80021a0: 687b ldr r3, [r7, #4] 80021a2: 6ddb ldr r3, [r3, #92] @ 0x5c 80021a4: 2210 movs r2, #16 80021a6: 409a lsls r2, r3 80021a8: 68fb ldr r3, [r7, #12] 80021aa: 4013 ands r3, r2 80021ac: 2b00 cmp r3, #0 80021ae: d043 beq.n 8002238 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) 80021b0: 687b ldr r3, [r7, #4] 80021b2: 681b ldr r3, [r3, #0] 80021b4: 681b ldr r3, [r3, #0] 80021b6: f003 0308 and.w r3, r3, #8 80021ba: 2b00 cmp r3, #0 80021bc: d03c beq.n 8002238 { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; 80021be: 687b ldr r3, [r7, #4] 80021c0: 6ddb ldr r3, [r3, #92] @ 0x5c 80021c2: 2210 movs r2, #16 80021c4: 409a lsls r2, r3 80021c6: 693b ldr r3, [r7, #16] 80021c8: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 80021ca: 687b ldr r3, [r7, #4] 80021cc: 681b ldr r3, [r3, #0] 80021ce: 681b ldr r3, [r3, #0] 80021d0: f403 2380 and.w r3, r3, #262144 @ 0x40000 80021d4: 2b00 cmp r3, #0 80021d6: d018 beq.n 800220a { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 80021d8: 687b ldr r3, [r7, #4] 80021da: 681b ldr r3, [r3, #0] 80021dc: 681b ldr r3, [r3, #0] 80021de: f403 2300 and.w r3, r3, #524288 @ 0x80000 80021e2: 2b00 cmp r3, #0 80021e4: d108 bne.n 80021f8 { if(hdma->XferHalfCpltCallback != NULL) 80021e6: 687b ldr r3, [r7, #4] 80021e8: 6c1b ldr r3, [r3, #64] @ 0x40 80021ea: 2b00 cmp r3, #0 80021ec: d024 beq.n 8002238 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 80021ee: 687b ldr r3, [r7, #4] 80021f0: 6c1b ldr r3, [r3, #64] @ 0x40 80021f2: 6878 ldr r0, [r7, #4] 80021f4: 4798 blx r3 80021f6: e01f b.n 8002238 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 80021f8: 687b ldr r3, [r7, #4] 80021fa: 6c9b ldr r3, [r3, #72] @ 0x48 80021fc: 2b00 cmp r3, #0 80021fe: d01b beq.n 8002238 { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8002200: 687b ldr r3, [r7, #4] 8002202: 6c9b ldr r3, [r3, #72] @ 0x48 8002204: 6878 ldr r0, [r7, #4] 8002206: 4798 blx r3 8002208: e016 b.n 8002238 } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 800220a: 687b ldr r3, [r7, #4] 800220c: 681b ldr r3, [r3, #0] 800220e: 681b ldr r3, [r3, #0] 8002210: f403 7380 and.w r3, r3, #256 @ 0x100 8002214: 2b00 cmp r3, #0 8002216: d107 bne.n 8002228 { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); 8002218: 687b ldr r3, [r7, #4] 800221a: 681b ldr r3, [r3, #0] 800221c: 681a ldr r2, [r3, #0] 800221e: 687b ldr r3, [r7, #4] 8002220: 681b ldr r3, [r3, #0] 8002222: f022 0208 bic.w r2, r2, #8 8002226: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 8002228: 687b ldr r3, [r7, #4] 800222a: 6c1b ldr r3, [r3, #64] @ 0x40 800222c: 2b00 cmp r3, #0 800222e: d003 beq.n 8002238 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002230: 687b ldr r3, [r7, #4] 8002232: 6c1b ldr r3, [r3, #64] @ 0x40 8002234: 6878 ldr r0, [r7, #4] 8002236: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) 8002238: 687b ldr r3, [r7, #4] 800223a: 6ddb ldr r3, [r3, #92] @ 0x5c 800223c: 2220 movs r2, #32 800223e: 409a lsls r2, r3 8002240: 68fb ldr r3, [r7, #12] 8002242: 4013 ands r3, r2 8002244: 2b00 cmp r3, #0 8002246: f000 808f beq.w 8002368 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) 800224a: 687b ldr r3, [r7, #4] 800224c: 681b ldr r3, [r3, #0] 800224e: 681b ldr r3, [r3, #0] 8002250: f003 0310 and.w r3, r3, #16 8002254: 2b00 cmp r3, #0 8002256: f000 8087 beq.w 8002368 { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; 800225a: 687b ldr r3, [r7, #4] 800225c: 6ddb ldr r3, [r3, #92] @ 0x5c 800225e: 2220 movs r2, #32 8002260: 409a lsls r2, r3 8002262: 693b ldr r3, [r7, #16] 8002264: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8002266: 687b ldr r3, [r7, #4] 8002268: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800226c: b2db uxtb r3, r3 800226e: 2b05 cmp r3, #5 8002270: d136 bne.n 80022e0 { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8002272: 687b ldr r3, [r7, #4] 8002274: 681b ldr r3, [r3, #0] 8002276: 681a ldr r2, [r3, #0] 8002278: 687b ldr r3, [r7, #4] 800227a: 681b ldr r3, [r3, #0] 800227c: f022 0216 bic.w r2, r2, #22 8002280: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8002282: 687b ldr r3, [r7, #4] 8002284: 681b ldr r3, [r3, #0] 8002286: 695a ldr r2, [r3, #20] 8002288: 687b ldr r3, [r7, #4] 800228a: 681b ldr r3, [r3, #0] 800228c: f022 0280 bic.w r2, r2, #128 @ 0x80 8002290: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8002292: 687b ldr r3, [r7, #4] 8002294: 6c1b ldr r3, [r3, #64] @ 0x40 8002296: 2b00 cmp r3, #0 8002298: d103 bne.n 80022a2 800229a: 687b ldr r3, [r7, #4] 800229c: 6c9b ldr r3, [r3, #72] @ 0x48 800229e: 2b00 cmp r3, #0 80022a0: d007 beq.n 80022b2 { hdma->Instance->CR &= ~(DMA_IT_HT); 80022a2: 687b ldr r3, [r7, #4] 80022a4: 681b ldr r3, [r3, #0] 80022a6: 681a ldr r2, [r3, #0] 80022a8: 687b ldr r3, [r7, #4] 80022aa: 681b ldr r3, [r3, #0] 80022ac: f022 0208 bic.w r2, r2, #8 80022b0: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 80022b2: 687b ldr r3, [r7, #4] 80022b4: 6ddb ldr r3, [r3, #92] @ 0x5c 80022b6: 223f movs r2, #63 @ 0x3f 80022b8: 409a lsls r2, r3 80022ba: 693b ldr r3, [r7, #16] 80022bc: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80022be: 687b ldr r3, [r7, #4] 80022c0: 2201 movs r2, #1 80022c2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80022c6: 687b ldr r3, [r7, #4] 80022c8: 2200 movs r2, #0 80022ca: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 80022ce: 687b ldr r3, [r7, #4] 80022d0: 6d1b ldr r3, [r3, #80] @ 0x50 80022d2: 2b00 cmp r3, #0 80022d4: d07e beq.n 80023d4 { hdma->XferAbortCallback(hdma); 80022d6: 687b ldr r3, [r7, #4] 80022d8: 6d1b ldr r3, [r3, #80] @ 0x50 80022da: 6878 ldr r0, [r7, #4] 80022dc: 4798 blx r3 } return; 80022de: e079 b.n 80023d4 } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 80022e0: 687b ldr r3, [r7, #4] 80022e2: 681b ldr r3, [r3, #0] 80022e4: 681b ldr r3, [r3, #0] 80022e6: f403 2380 and.w r3, r3, #262144 @ 0x40000 80022ea: 2b00 cmp r3, #0 80022ec: d01d beq.n 800232a { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 80022ee: 687b ldr r3, [r7, #4] 80022f0: 681b ldr r3, [r3, #0] 80022f2: 681b ldr r3, [r3, #0] 80022f4: f403 2300 and.w r3, r3, #524288 @ 0x80000 80022f8: 2b00 cmp r3, #0 80022fa: d10d bne.n 8002318 { if(hdma->XferM1CpltCallback != NULL) 80022fc: 687b ldr r3, [r7, #4] 80022fe: 6c5b ldr r3, [r3, #68] @ 0x44 8002300: 2b00 cmp r3, #0 8002302: d031 beq.n 8002368 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8002304: 687b ldr r3, [r7, #4] 8002306: 6c5b ldr r3, [r3, #68] @ 0x44 8002308: 6878 ldr r0, [r7, #4] 800230a: 4798 blx r3 800230c: e02c b.n 8002368 800230e: bf00 nop 8002310: 20000090 .word 0x20000090 8002314: 1b4e81b5 .word 0x1b4e81b5 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8002318: 687b ldr r3, [r7, #4] 800231a: 6bdb ldr r3, [r3, #60] @ 0x3c 800231c: 2b00 cmp r3, #0 800231e: d023 beq.n 8002368 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8002320: 687b ldr r3, [r7, #4] 8002322: 6bdb ldr r3, [r3, #60] @ 0x3c 8002324: 6878 ldr r0, [r7, #4] 8002326: 4798 blx r3 8002328: e01e b.n 8002368 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 800232a: 687b ldr r3, [r7, #4] 800232c: 681b ldr r3, [r3, #0] 800232e: 681b ldr r3, [r3, #0] 8002330: f403 7380 and.w r3, r3, #256 @ 0x100 8002334: 2b00 cmp r3, #0 8002336: d10f bne.n 8002358 { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); 8002338: 687b ldr r3, [r7, #4] 800233a: 681b ldr r3, [r3, #0] 800233c: 681a ldr r2, [r3, #0] 800233e: 687b ldr r3, [r7, #4] 8002340: 681b ldr r3, [r3, #0] 8002342: f022 0210 bic.w r2, r2, #16 8002346: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002348: 687b ldr r3, [r7, #4] 800234a: 2201 movs r2, #1 800234c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002350: 687b ldr r3, [r7, #4] 8002352: 2200 movs r2, #0 8002354: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 8002358: 687b ldr r3, [r7, #4] 800235a: 6bdb ldr r3, [r3, #60] @ 0x3c 800235c: 2b00 cmp r3, #0 800235e: d003 beq.n 8002368 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8002360: 687b ldr r3, [r7, #4] 8002362: 6bdb ldr r3, [r3, #60] @ 0x3c 8002364: 6878 ldr r0, [r7, #4] 8002366: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 8002368: 687b ldr r3, [r7, #4] 800236a: 6d5b ldr r3, [r3, #84] @ 0x54 800236c: 2b00 cmp r3, #0 800236e: d032 beq.n 80023d6 { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) 8002370: 687b ldr r3, [r7, #4] 8002372: 6d5b ldr r3, [r3, #84] @ 0x54 8002374: f003 0301 and.w r3, r3, #1 8002378: 2b00 cmp r3, #0 800237a: d022 beq.n 80023c2 { hdma->State = HAL_DMA_STATE_ABORT; 800237c: 687b ldr r3, [r7, #4] 800237e: 2205 movs r2, #5 8002380: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8002384: 687b ldr r3, [r7, #4] 8002386: 681b ldr r3, [r3, #0] 8002388: 681a ldr r2, [r3, #0] 800238a: 687b ldr r3, [r7, #4] 800238c: 681b ldr r3, [r3, #0] 800238e: f022 0201 bic.w r2, r2, #1 8002392: 601a str r2, [r3, #0] do { if (++count > timeout) 8002394: 68bb ldr r3, [r7, #8] 8002396: 3301 adds r3, #1 8002398: 60bb str r3, [r7, #8] 800239a: 697a ldr r2, [r7, #20] 800239c: 429a cmp r2, r3 800239e: d307 bcc.n 80023b0 { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); 80023a0: 687b ldr r3, [r7, #4] 80023a2: 681b ldr r3, [r3, #0] 80023a4: 681b ldr r3, [r3, #0] 80023a6: f003 0301 and.w r3, r3, #1 80023aa: 2b00 cmp r3, #0 80023ac: d1f2 bne.n 8002394 80023ae: e000 b.n 80023b2 break; 80023b0: bf00 nop /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80023b2: 687b ldr r3, [r7, #4] 80023b4: 2201 movs r2, #1 80023b6: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80023ba: 687b ldr r3, [r7, #4] 80023bc: 2200 movs r2, #0 80023be: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 80023c2: 687b ldr r3, [r7, #4] 80023c4: 6cdb ldr r3, [r3, #76] @ 0x4c 80023c6: 2b00 cmp r3, #0 80023c8: d005 beq.n 80023d6 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80023ca: 687b ldr r3, [r7, #4] 80023cc: 6cdb ldr r3, [r3, #76] @ 0x4c 80023ce: 6878 ldr r0, [r7, #4] 80023d0: 4798 blx r3 80023d2: e000 b.n 80023d6 return; 80023d4: bf00 nop } } } 80023d6: 3718 adds r7, #24 80023d8: 46bd mov sp, r7 80023da: bd80 pop {r7, pc} 080023dc : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80023dc: b480 push {r7} 80023de: b085 sub sp, #20 80023e0: af00 add r7, sp, #0 80023e2: 60f8 str r0, [r7, #12] 80023e4: 60b9 str r1, [r7, #8] 80023e6: 607a str r2, [r7, #4] 80023e8: 603b str r3, [r7, #0] /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); 80023ea: 68fb ldr r3, [r7, #12] 80023ec: 681b ldr r3, [r3, #0] 80023ee: 681a ldr r2, [r3, #0] 80023f0: 68fb ldr r3, [r7, #12] 80023f2: 681b ldr r3, [r3, #0] 80023f4: f422 2280 bic.w r2, r2, #262144 @ 0x40000 80023f8: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; 80023fa: 68fb ldr r3, [r7, #12] 80023fc: 681b ldr r3, [r3, #0] 80023fe: 683a ldr r2, [r7, #0] 8002400: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002402: 68fb ldr r3, [r7, #12] 8002404: 689b ldr r3, [r3, #8] 8002406: 2b40 cmp r3, #64 @ 0x40 8002408: d108 bne.n 800241c { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; 800240a: 68fb ldr r3, [r7, #12] 800240c: 681b ldr r3, [r3, #0] 800240e: 687a ldr r2, [r7, #4] 8002410: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; 8002412: 68fb ldr r3, [r7, #12] 8002414: 681b ldr r3, [r3, #0] 8002416: 68ba ldr r2, [r7, #8] 8002418: 60da str r2, [r3, #12] hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } 800241a: e007 b.n 800242c hdma->Instance->PAR = SrcAddress; 800241c: 68fb ldr r3, [r7, #12] 800241e: 681b ldr r3, [r3, #0] 8002420: 68ba ldr r2, [r7, #8] 8002422: 609a str r2, [r3, #8] hdma->Instance->M0AR = DstAddress; 8002424: 68fb ldr r3, [r7, #12] 8002426: 681b ldr r3, [r3, #0] 8002428: 687a ldr r2, [r7, #4] 800242a: 60da str r2, [r3, #12] } 800242c: bf00 nop 800242e: 3714 adds r7, #20 8002430: 46bd mov sp, r7 8002432: f85d 7b04 ldr.w r7, [sp], #4 8002436: 4770 bx lr 08002438 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 8002438: b480 push {r7} 800243a: b085 sub sp, #20 800243c: af00 add r7, sp, #0 800243e: 6078 str r0, [r7, #4] uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; 8002440: 687b ldr r3, [r7, #4] 8002442: 681b ldr r3, [r3, #0] 8002444: b2db uxtb r3, r3 8002446: 3b10 subs r3, #16 8002448: 4a14 ldr r2, [pc, #80] @ (800249c ) 800244a: fba2 2303 umull r2, r3, r2, r3 800244e: 091b lsrs r3, r3, #4 8002450: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; 8002452: 4a13 ldr r2, [pc, #76] @ (80024a0 ) 8002454: 68fb ldr r3, [r7, #12] 8002456: 4413 add r3, r2 8002458: 781b ldrb r3, [r3, #0] 800245a: 461a mov r2, r3 800245c: 687b ldr r3, [r7, #4] 800245e: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 8002460: 68fb ldr r3, [r7, #12] 8002462: 2b03 cmp r3, #3 8002464: d909 bls.n 800247a { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); 8002466: 687b ldr r3, [r7, #4] 8002468: 681b ldr r3, [r3, #0] 800246a: f423 737f bic.w r3, r3, #1020 @ 0x3fc 800246e: f023 0303 bic.w r3, r3, #3 8002472: 1d1a adds r2, r3, #4 8002474: 687b ldr r3, [r7, #4] 8002476: 659a str r2, [r3, #88] @ 0x58 8002478: e007 b.n 800248a } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); 800247a: 687b ldr r3, [r7, #4] 800247c: 681b ldr r3, [r3, #0] 800247e: f423 737f bic.w r3, r3, #1020 @ 0x3fc 8002482: f023 0303 bic.w r3, r3, #3 8002486: 687a ldr r2, [r7, #4] 8002488: 6593 str r3, [r2, #88] @ 0x58 } return hdma->StreamBaseAddress; 800248a: 687b ldr r3, [r7, #4] 800248c: 6d9b ldr r3, [r3, #88] @ 0x58 } 800248e: 4618 mov r0, r3 8002490: 3714 adds r7, #20 8002492: 46bd mov sp, r7 8002494: f85d 7b04 ldr.w r7, [sp], #4 8002498: 4770 bx lr 800249a: bf00 nop 800249c: aaaaaaab .word 0xaaaaaaab 80024a0: 0800aad4 .word 0x0800aad4 080024a4 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 80024a4: b480 push {r7} 80024a6: b085 sub sp, #20 80024a8: af00 add r7, sp, #0 80024aa: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80024ac: 2300 movs r3, #0 80024ae: 73fb strb r3, [r7, #15] uint32_t tmp = hdma->Init.FIFOThreshold; 80024b0: 687b ldr r3, [r7, #4] 80024b2: 6a9b ldr r3, [r3, #40] @ 0x28 80024b4: 60bb str r3, [r7, #8] /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 80024b6: 687b ldr r3, [r7, #4] 80024b8: 699b ldr r3, [r3, #24] 80024ba: 2b00 cmp r3, #0 80024bc: d11f bne.n 80024fe { switch (tmp) 80024be: 68bb ldr r3, [r7, #8] 80024c0: 2b03 cmp r3, #3 80024c2: d856 bhi.n 8002572 80024c4: a201 add r2, pc, #4 @ (adr r2, 80024cc ) 80024c6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80024ca: bf00 nop 80024cc: 080024dd .word 0x080024dd 80024d0: 080024ef .word 0x080024ef 80024d4: 080024dd .word 0x080024dd 80024d8: 08002573 .word 0x08002573 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 80024dc: 687b ldr r3, [r7, #4] 80024de: 6adb ldr r3, [r3, #44] @ 0x2c 80024e0: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80024e4: 2b00 cmp r3, #0 80024e6: d046 beq.n 8002576 { status = HAL_ERROR; 80024e8: 2301 movs r3, #1 80024ea: 73fb strb r3, [r7, #15] } break; 80024ec: e043 b.n 8002576 case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 80024ee: 687b ldr r3, [r7, #4] 80024f0: 6adb ldr r3, [r3, #44] @ 0x2c 80024f2: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 80024f6: d140 bne.n 800257a { status = HAL_ERROR; 80024f8: 2301 movs r3, #1 80024fa: 73fb strb r3, [r7, #15] } break; 80024fc: e03d b.n 800257a break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 80024fe: 687b ldr r3, [r7, #4] 8002500: 699b ldr r3, [r3, #24] 8002502: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002506: d121 bne.n 800254c { switch (tmp) 8002508: 68bb ldr r3, [r7, #8] 800250a: 2b03 cmp r3, #3 800250c: d837 bhi.n 800257e 800250e: a201 add r2, pc, #4 @ (adr r2, 8002514 ) 8002510: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002514: 08002525 .word 0x08002525 8002518: 0800252b .word 0x0800252b 800251c: 08002525 .word 0x08002525 8002520: 0800253d .word 0x0800253d { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 8002524: 2301 movs r3, #1 8002526: 73fb strb r3, [r7, #15] break; 8002528: e030 b.n 800258c case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800252a: 687b ldr r3, [r7, #4] 800252c: 6adb ldr r3, [r3, #44] @ 0x2c 800252e: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002532: 2b00 cmp r3, #0 8002534: d025 beq.n 8002582 { status = HAL_ERROR; 8002536: 2301 movs r3, #1 8002538: 73fb strb r3, [r7, #15] } break; 800253a: e022 b.n 8002582 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800253c: 687b ldr r3, [r7, #4] 800253e: 6adb ldr r3, [r3, #44] @ 0x2c 8002540: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 8002544: d11f bne.n 8002586 { status = HAL_ERROR; 8002546: 2301 movs r3, #1 8002548: 73fb strb r3, [r7, #15] } break; 800254a: e01c b.n 8002586 } /* Memory Data size equal to Word */ else { switch (tmp) 800254c: 68bb ldr r3, [r7, #8] 800254e: 2b02 cmp r3, #2 8002550: d903 bls.n 800255a 8002552: 68bb ldr r3, [r7, #8] 8002554: 2b03 cmp r3, #3 8002556: d003 beq.n 8002560 { status = HAL_ERROR; } break; default: break; 8002558: e018 b.n 800258c status = HAL_ERROR; 800255a: 2301 movs r3, #1 800255c: 73fb strb r3, [r7, #15] break; 800255e: e015 b.n 800258c if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002560: 687b ldr r3, [r7, #4] 8002562: 6adb ldr r3, [r3, #44] @ 0x2c 8002564: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002568: 2b00 cmp r3, #0 800256a: d00e beq.n 800258a status = HAL_ERROR; 800256c: 2301 movs r3, #1 800256e: 73fb strb r3, [r7, #15] break; 8002570: e00b b.n 800258a break; 8002572: bf00 nop 8002574: e00a b.n 800258c break; 8002576: bf00 nop 8002578: e008 b.n 800258c break; 800257a: bf00 nop 800257c: e006 b.n 800258c break; 800257e: bf00 nop 8002580: e004 b.n 800258c break; 8002582: bf00 nop 8002584: e002 b.n 800258c break; 8002586: bf00 nop 8002588: e000 b.n 800258c break; 800258a: bf00 nop } } return status; 800258c: 7bfb ldrb r3, [r7, #15] } 800258e: 4618 mov r0, r3 8002590: 3714 adds r7, #20 8002592: 46bd mov sp, r7 8002594: f85d 7b04 ldr.w r7, [sp], #4 8002598: 4770 bx lr 800259a: bf00 nop 0800259c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800259c: b480 push {r7} 800259e: b089 sub sp, #36 @ 0x24 80025a0: af00 add r7, sp, #0 80025a2: 6078 str r0, [r7, #4] 80025a4: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 80025a6: 2300 movs r3, #0 80025a8: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 80025aa: 2300 movs r3, #0 80025ac: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 80025ae: 2300 movs r3, #0 80025b0: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 80025b2: 2300 movs r3, #0 80025b4: 61fb str r3, [r7, #28] 80025b6: e165 b.n 8002884 { /* Get the IO position */ ioposition = 0x01U << position; 80025b8: 2201 movs r2, #1 80025ba: 69fb ldr r3, [r7, #28] 80025bc: fa02 f303 lsl.w r3, r2, r3 80025c0: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80025c2: 683b ldr r3, [r7, #0] 80025c4: 681b ldr r3, [r3, #0] 80025c6: 697a ldr r2, [r7, #20] 80025c8: 4013 ands r3, r2 80025ca: 613b str r3, [r7, #16] if(iocurrent == ioposition) 80025cc: 693a ldr r2, [r7, #16] 80025ce: 697b ldr r3, [r7, #20] 80025d0: 429a cmp r2, r3 80025d2: f040 8154 bne.w 800287e { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 80025d6: 683b ldr r3, [r7, #0] 80025d8: 685b ldr r3, [r3, #4] 80025da: f003 0303 and.w r3, r3, #3 80025de: 2b01 cmp r3, #1 80025e0: d005 beq.n 80025ee (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80025e2: 683b ldr r3, [r7, #0] 80025e4: 685b ldr r3, [r3, #4] 80025e6: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 80025ea: 2b02 cmp r3, #2 80025ec: d130 bne.n 8002650 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80025ee: 687b ldr r3, [r7, #4] 80025f0: 689b ldr r3, [r3, #8] 80025f2: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 80025f4: 69fb ldr r3, [r7, #28] 80025f6: 005b lsls r3, r3, #1 80025f8: 2203 movs r2, #3 80025fa: fa02 f303 lsl.w r3, r2, r3 80025fe: 43db mvns r3, r3 8002600: 69ba ldr r2, [r7, #24] 8002602: 4013 ands r3, r2 8002604: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8002606: 683b ldr r3, [r7, #0] 8002608: 68da ldr r2, [r3, #12] 800260a: 69fb ldr r3, [r7, #28] 800260c: 005b lsls r3, r3, #1 800260e: fa02 f303 lsl.w r3, r2, r3 8002612: 69ba ldr r2, [r7, #24] 8002614: 4313 orrs r3, r2 8002616: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8002618: 687b ldr r3, [r7, #4] 800261a: 69ba ldr r2, [r7, #24] 800261c: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800261e: 687b ldr r3, [r7, #4] 8002620: 685b ldr r3, [r3, #4] 8002622: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8002624: 2201 movs r2, #1 8002626: 69fb ldr r3, [r7, #28] 8002628: fa02 f303 lsl.w r3, r2, r3 800262c: 43db mvns r3, r3 800262e: 69ba ldr r2, [r7, #24] 8002630: 4013 ands r3, r2 8002632: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002634: 683b ldr r3, [r7, #0] 8002636: 685b ldr r3, [r3, #4] 8002638: 091b lsrs r3, r3, #4 800263a: f003 0201 and.w r2, r3, #1 800263e: 69fb ldr r3, [r7, #28] 8002640: fa02 f303 lsl.w r3, r2, r3 8002644: 69ba ldr r2, [r7, #24] 8002646: 4313 orrs r3, r2 8002648: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800264a: 687b ldr r3, [r7, #4] 800264c: 69ba ldr r2, [r7, #24] 800264e: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002650: 683b ldr r3, [r7, #0] 8002652: 685b ldr r3, [r3, #4] 8002654: f003 0303 and.w r3, r3, #3 8002658: 2b03 cmp r3, #3 800265a: d017 beq.n 800268c { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800265c: 687b ldr r3, [r7, #4] 800265e: 68db ldr r3, [r3, #12] 8002660: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8002662: 69fb ldr r3, [r7, #28] 8002664: 005b lsls r3, r3, #1 8002666: 2203 movs r2, #3 8002668: fa02 f303 lsl.w r3, r2, r3 800266c: 43db mvns r3, r3 800266e: 69ba ldr r2, [r7, #24] 8002670: 4013 ands r3, r2 8002672: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002674: 683b ldr r3, [r7, #0] 8002676: 689a ldr r2, [r3, #8] 8002678: 69fb ldr r3, [r7, #28] 800267a: 005b lsls r3, r3, #1 800267c: fa02 f303 lsl.w r3, r2, r3 8002680: 69ba ldr r2, [r7, #24] 8002682: 4313 orrs r3, r2 8002684: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8002686: 687b ldr r3, [r7, #4] 8002688: 69ba ldr r2, [r7, #24] 800268a: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800268c: 683b ldr r3, [r7, #0] 800268e: 685b ldr r3, [r3, #4] 8002690: f003 0303 and.w r3, r3, #3 8002694: 2b02 cmp r3, #2 8002696: d123 bne.n 80026e0 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8002698: 69fb ldr r3, [r7, #28] 800269a: 08da lsrs r2, r3, #3 800269c: 687b ldr r3, [r7, #4] 800269e: 3208 adds r2, #8 80026a0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80026a4: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 80026a6: 69fb ldr r3, [r7, #28] 80026a8: f003 0307 and.w r3, r3, #7 80026ac: 009b lsls r3, r3, #2 80026ae: 220f movs r2, #15 80026b0: fa02 f303 lsl.w r3, r2, r3 80026b4: 43db mvns r3, r3 80026b6: 69ba ldr r2, [r7, #24] 80026b8: 4013 ands r3, r2 80026ba: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 80026bc: 683b ldr r3, [r7, #0] 80026be: 691a ldr r2, [r3, #16] 80026c0: 69fb ldr r3, [r7, #28] 80026c2: f003 0307 and.w r3, r3, #7 80026c6: 009b lsls r3, r3, #2 80026c8: fa02 f303 lsl.w r3, r2, r3 80026cc: 69ba ldr r2, [r7, #24] 80026ce: 4313 orrs r3, r2 80026d0: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 80026d2: 69fb ldr r3, [r7, #28] 80026d4: 08da lsrs r2, r3, #3 80026d6: 687b ldr r3, [r7, #4] 80026d8: 3208 adds r2, #8 80026da: 69b9 ldr r1, [r7, #24] 80026dc: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 80026e0: 687b ldr r3, [r7, #4] 80026e2: 681b ldr r3, [r3, #0] 80026e4: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 80026e6: 69fb ldr r3, [r7, #28] 80026e8: 005b lsls r3, r3, #1 80026ea: 2203 movs r2, #3 80026ec: fa02 f303 lsl.w r3, r2, r3 80026f0: 43db mvns r3, r3 80026f2: 69ba ldr r2, [r7, #24] 80026f4: 4013 ands r3, r2 80026f6: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 80026f8: 683b ldr r3, [r7, #0] 80026fa: 685b ldr r3, [r3, #4] 80026fc: f003 0203 and.w r2, r3, #3 8002700: 69fb ldr r3, [r7, #28] 8002702: 005b lsls r3, r3, #1 8002704: fa02 f303 lsl.w r3, r2, r3 8002708: 69ba ldr r2, [r7, #24] 800270a: 4313 orrs r3, r2 800270c: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 800270e: 687b ldr r3, [r7, #4] 8002710: 69ba ldr r2, [r7, #24] 8002712: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8002714: 683b ldr r3, [r7, #0] 8002716: 685b ldr r3, [r3, #4] 8002718: f403 3340 and.w r3, r3, #196608 @ 0x30000 800271c: 2b00 cmp r3, #0 800271e: f000 80ae beq.w 800287e { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002722: 2300 movs r3, #0 8002724: 60fb str r3, [r7, #12] 8002726: 4b5d ldr r3, [pc, #372] @ (800289c ) 8002728: 6c5b ldr r3, [r3, #68] @ 0x44 800272a: 4a5c ldr r2, [pc, #368] @ (800289c ) 800272c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002730: 6453 str r3, [r2, #68] @ 0x44 8002732: 4b5a ldr r3, [pc, #360] @ (800289c ) 8002734: 6c5b ldr r3, [r3, #68] @ 0x44 8002736: f403 4380 and.w r3, r3, #16384 @ 0x4000 800273a: 60fb str r3, [r7, #12] 800273c: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800273e: 4a58 ldr r2, [pc, #352] @ (80028a0 ) 8002740: 69fb ldr r3, [r7, #28] 8002742: 089b lsrs r3, r3, #2 8002744: 3302 adds r3, #2 8002746: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800274a: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 800274c: 69fb ldr r3, [r7, #28] 800274e: f003 0303 and.w r3, r3, #3 8002752: 009b lsls r3, r3, #2 8002754: 220f movs r2, #15 8002756: fa02 f303 lsl.w r3, r2, r3 800275a: 43db mvns r3, r3 800275c: 69ba ldr r2, [r7, #24] 800275e: 4013 ands r3, r2 8002760: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8002762: 687b ldr r3, [r7, #4] 8002764: 4a4f ldr r2, [pc, #316] @ (80028a4 ) 8002766: 4293 cmp r3, r2 8002768: d025 beq.n 80027b6 800276a: 687b ldr r3, [r7, #4] 800276c: 4a4e ldr r2, [pc, #312] @ (80028a8 ) 800276e: 4293 cmp r3, r2 8002770: d01f beq.n 80027b2 8002772: 687b ldr r3, [r7, #4] 8002774: 4a4d ldr r2, [pc, #308] @ (80028ac ) 8002776: 4293 cmp r3, r2 8002778: d019 beq.n 80027ae 800277a: 687b ldr r3, [r7, #4] 800277c: 4a4c ldr r2, [pc, #304] @ (80028b0 ) 800277e: 4293 cmp r3, r2 8002780: d013 beq.n 80027aa 8002782: 687b ldr r3, [r7, #4] 8002784: 4a4b ldr r2, [pc, #300] @ (80028b4 ) 8002786: 4293 cmp r3, r2 8002788: d00d beq.n 80027a6 800278a: 687b ldr r3, [r7, #4] 800278c: 4a4a ldr r2, [pc, #296] @ (80028b8 ) 800278e: 4293 cmp r3, r2 8002790: d007 beq.n 80027a2 8002792: 687b ldr r3, [r7, #4] 8002794: 4a49 ldr r2, [pc, #292] @ (80028bc ) 8002796: 4293 cmp r3, r2 8002798: d101 bne.n 800279e 800279a: 2306 movs r3, #6 800279c: e00c b.n 80027b8 800279e: 2307 movs r3, #7 80027a0: e00a b.n 80027b8 80027a2: 2305 movs r3, #5 80027a4: e008 b.n 80027b8 80027a6: 2304 movs r3, #4 80027a8: e006 b.n 80027b8 80027aa: 2303 movs r3, #3 80027ac: e004 b.n 80027b8 80027ae: 2302 movs r3, #2 80027b0: e002 b.n 80027b8 80027b2: 2301 movs r3, #1 80027b4: e000 b.n 80027b8 80027b6: 2300 movs r3, #0 80027b8: 69fa ldr r2, [r7, #28] 80027ba: f002 0203 and.w r2, r2, #3 80027be: 0092 lsls r2, r2, #2 80027c0: 4093 lsls r3, r2 80027c2: 69ba ldr r2, [r7, #24] 80027c4: 4313 orrs r3, r2 80027c6: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 80027c8: 4935 ldr r1, [pc, #212] @ (80028a0 ) 80027ca: 69fb ldr r3, [r7, #28] 80027cc: 089b lsrs r3, r3, #2 80027ce: 3302 adds r3, #2 80027d0: 69ba ldr r2, [r7, #24] 80027d2: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 80027d6: 4b3a ldr r3, [pc, #232] @ (80028c0 ) 80027d8: 689b ldr r3, [r3, #8] 80027da: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 80027dc: 693b ldr r3, [r7, #16] 80027de: 43db mvns r3, r3 80027e0: 69ba ldr r2, [r7, #24] 80027e2: 4013 ands r3, r2 80027e4: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 80027e6: 683b ldr r3, [r7, #0] 80027e8: 685b ldr r3, [r3, #4] 80027ea: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80027ee: 2b00 cmp r3, #0 80027f0: d003 beq.n 80027fa { temp |= iocurrent; 80027f2: 69ba ldr r2, [r7, #24] 80027f4: 693b ldr r3, [r7, #16] 80027f6: 4313 orrs r3, r2 80027f8: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 80027fa: 4a31 ldr r2, [pc, #196] @ (80028c0 ) 80027fc: 69bb ldr r3, [r7, #24] 80027fe: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8002800: 4b2f ldr r3, [pc, #188] @ (80028c0 ) 8002802: 68db ldr r3, [r3, #12] 8002804: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002806: 693b ldr r3, [r7, #16] 8002808: 43db mvns r3, r3 800280a: 69ba ldr r2, [r7, #24] 800280c: 4013 ands r3, r2 800280e: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8002810: 683b ldr r3, [r7, #0] 8002812: 685b ldr r3, [r3, #4] 8002814: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8002818: 2b00 cmp r3, #0 800281a: d003 beq.n 8002824 { temp |= iocurrent; 800281c: 69ba ldr r2, [r7, #24] 800281e: 693b ldr r3, [r7, #16] 8002820: 4313 orrs r3, r2 8002822: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8002824: 4a26 ldr r2, [pc, #152] @ (80028c0 ) 8002826: 69bb ldr r3, [r7, #24] 8002828: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 800282a: 4b25 ldr r3, [pc, #148] @ (80028c0 ) 800282c: 685b ldr r3, [r3, #4] 800282e: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002830: 693b ldr r3, [r7, #16] 8002832: 43db mvns r3, r3 8002834: 69ba ldr r2, [r7, #24] 8002836: 4013 ands r3, r2 8002838: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800283a: 683b ldr r3, [r7, #0] 800283c: 685b ldr r3, [r3, #4] 800283e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002842: 2b00 cmp r3, #0 8002844: d003 beq.n 800284e { temp |= iocurrent; 8002846: 69ba ldr r2, [r7, #24] 8002848: 693b ldr r3, [r7, #16] 800284a: 4313 orrs r3, r2 800284c: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 800284e: 4a1c ldr r2, [pc, #112] @ (80028c0 ) 8002850: 69bb ldr r3, [r7, #24] 8002852: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8002854: 4b1a ldr r3, [pc, #104] @ (80028c0 ) 8002856: 681b ldr r3, [r3, #0] 8002858: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800285a: 693b ldr r3, [r7, #16] 800285c: 43db mvns r3, r3 800285e: 69ba ldr r2, [r7, #24] 8002860: 4013 ands r3, r2 8002862: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8002864: 683b ldr r3, [r7, #0] 8002866: 685b ldr r3, [r3, #4] 8002868: f403 3380 and.w r3, r3, #65536 @ 0x10000 800286c: 2b00 cmp r3, #0 800286e: d003 beq.n 8002878 { temp |= iocurrent; 8002870: 69ba ldr r2, [r7, #24] 8002872: 693b ldr r3, [r7, #16] 8002874: 4313 orrs r3, r2 8002876: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8002878: 4a11 ldr r2, [pc, #68] @ (80028c0 ) 800287a: 69bb ldr r3, [r7, #24] 800287c: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 800287e: 69fb ldr r3, [r7, #28] 8002880: 3301 adds r3, #1 8002882: 61fb str r3, [r7, #28] 8002884: 69fb ldr r3, [r7, #28] 8002886: 2b0f cmp r3, #15 8002888: f67f ae96 bls.w 80025b8 } } } } 800288c: bf00 nop 800288e: bf00 nop 8002890: 3724 adds r7, #36 @ 0x24 8002892: 46bd mov sp, r7 8002894: f85d 7b04 ldr.w r7, [sp], #4 8002898: 4770 bx lr 800289a: bf00 nop 800289c: 40023800 .word 0x40023800 80028a0: 40013800 .word 0x40013800 80028a4: 40020000 .word 0x40020000 80028a8: 40020400 .word 0x40020400 80028ac: 40020800 .word 0x40020800 80028b0: 40020c00 .word 0x40020c00 80028b4: 40021000 .word 0x40021000 80028b8: 40021400 .word 0x40021400 80028bc: 40021800 .word 0x40021800 80028c0: 40013c00 .word 0x40013c00 080028c4 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 80028c4: b480 push {r7} 80028c6: b085 sub sp, #20 80028c8: af00 add r7, sp, #0 80028ca: 6078 str r0, [r7, #4] 80028cc: 460b mov r3, r1 80028ce: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80028d0: 687b ldr r3, [r7, #4] 80028d2: 691a ldr r2, [r3, #16] 80028d4: 887b ldrh r3, [r7, #2] 80028d6: 4013 ands r3, r2 80028d8: 2b00 cmp r3, #0 80028da: d002 beq.n 80028e2 { bitstatus = GPIO_PIN_SET; 80028dc: 2301 movs r3, #1 80028de: 73fb strb r3, [r7, #15] 80028e0: e001 b.n 80028e6 } else { bitstatus = GPIO_PIN_RESET; 80028e2: 2300 movs r3, #0 80028e4: 73fb strb r3, [r7, #15] } return bitstatus; 80028e6: 7bfb ldrb r3, [r7, #15] } 80028e8: 4618 mov r0, r3 80028ea: 3714 adds r7, #20 80028ec: 46bd mov sp, r7 80028ee: f85d 7b04 ldr.w r7, [sp], #4 80028f2: 4770 bx lr 080028f4 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80028f4: b480 push {r7} 80028f6: b083 sub sp, #12 80028f8: af00 add r7, sp, #0 80028fa: 6078 str r0, [r7, #4] 80028fc: 460b mov r3, r1 80028fe: 807b strh r3, [r7, #2] 8002900: 4613 mov r3, r2 8002902: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8002904: 787b ldrb r3, [r7, #1] 8002906: 2b00 cmp r3, #0 8002908: d003 beq.n 8002912 { GPIOx->BSRR = GPIO_Pin; 800290a: 887a ldrh r2, [r7, #2] 800290c: 687b ldr r3, [r7, #4] 800290e: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002910: e003 b.n 800291a GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8002912: 887b ldrh r3, [r7, #2] 8002914: 041a lsls r2, r3, #16 8002916: 687b ldr r3, [r7, #4] 8002918: 619a str r2, [r3, #24] } 800291a: bf00 nop 800291c: 370c adds r7, #12 800291e: 46bd mov sp, r7 8002920: f85d 7b04 ldr.w r7, [sp], #4 8002924: 4770 bx lr ... 08002928 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8002928: b580 push {r7, lr} 800292a: b084 sub sp, #16 800292c: af00 add r7, sp, #0 800292e: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8002930: 687b ldr r3, [r7, #4] 8002932: 2b00 cmp r3, #0 8002934: d101 bne.n 800293a { return HAL_ERROR; 8002936: 2301 movs r3, #1 8002938: e12b b.n 8002b92 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 800293a: 687b ldr r3, [r7, #4] 800293c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8002940: b2db uxtb r3, r3 8002942: 2b00 cmp r3, #0 8002944: d106 bne.n 8002954 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8002946: 687b ldr r3, [r7, #4] 8002948: 2200 movs r2, #0 800294a: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 800294e: 6878 ldr r0, [r7, #4] 8002950: f7fd ff22 bl 8000798 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8002954: 687b ldr r3, [r7, #4] 8002956: 2224 movs r2, #36 @ 0x24 8002958: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 800295c: 687b ldr r3, [r7, #4] 800295e: 681b ldr r3, [r3, #0] 8002960: 681a ldr r2, [r3, #0] 8002962: 687b ldr r3, [r7, #4] 8002964: 681b ldr r3, [r3, #0] 8002966: f022 0201 bic.w r2, r2, #1 800296a: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 800296c: 687b ldr r3, [r7, #4] 800296e: 681b ldr r3, [r3, #0] 8002970: 681a ldr r2, [r3, #0] 8002972: 687b ldr r3, [r7, #4] 8002974: 681b ldr r3, [r3, #0] 8002976: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800297a: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 800297c: 687b ldr r3, [r7, #4] 800297e: 681b ldr r3, [r3, #0] 8002980: 681a ldr r2, [r3, #0] 8002982: 687b ldr r3, [r7, #4] 8002984: 681b ldr r3, [r3, #0] 8002986: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800298a: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 800298c: f001 fc88 bl 80042a0 8002990: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8002992: 687b ldr r3, [r7, #4] 8002994: 685b ldr r3, [r3, #4] 8002996: 4a81 ldr r2, [pc, #516] @ (8002b9c ) 8002998: 4293 cmp r3, r2 800299a: d807 bhi.n 80029ac 800299c: 68fb ldr r3, [r7, #12] 800299e: 4a80 ldr r2, [pc, #512] @ (8002ba0 ) 80029a0: 4293 cmp r3, r2 80029a2: bf94 ite ls 80029a4: 2301 movls r3, #1 80029a6: 2300 movhi r3, #0 80029a8: b2db uxtb r3, r3 80029aa: e006 b.n 80029ba 80029ac: 68fb ldr r3, [r7, #12] 80029ae: 4a7d ldr r2, [pc, #500] @ (8002ba4 ) 80029b0: 4293 cmp r3, r2 80029b2: bf94 ite ls 80029b4: 2301 movls r3, #1 80029b6: 2300 movhi r3, #0 80029b8: b2db uxtb r3, r3 80029ba: 2b00 cmp r3, #0 80029bc: d001 beq.n 80029c2 { return HAL_ERROR; 80029be: 2301 movs r3, #1 80029c0: e0e7 b.n 8002b92 } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 80029c2: 68fb ldr r3, [r7, #12] 80029c4: 4a78 ldr r2, [pc, #480] @ (8002ba8 ) 80029c6: fba2 2303 umull r2, r3, r2, r3 80029ca: 0c9b lsrs r3, r3, #18 80029cc: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 80029ce: 687b ldr r3, [r7, #4] 80029d0: 681b ldr r3, [r3, #0] 80029d2: 685b ldr r3, [r3, #4] 80029d4: f023 013f bic.w r1, r3, #63 @ 0x3f 80029d8: 687b ldr r3, [r7, #4] 80029da: 681b ldr r3, [r3, #0] 80029dc: 68ba ldr r2, [r7, #8] 80029de: 430a orrs r2, r1 80029e0: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 80029e2: 687b ldr r3, [r7, #4] 80029e4: 681b ldr r3, [r3, #0] 80029e6: 6a1b ldr r3, [r3, #32] 80029e8: f023 013f bic.w r1, r3, #63 @ 0x3f 80029ec: 687b ldr r3, [r7, #4] 80029ee: 685b ldr r3, [r3, #4] 80029f0: 4a6a ldr r2, [pc, #424] @ (8002b9c ) 80029f2: 4293 cmp r3, r2 80029f4: d802 bhi.n 80029fc 80029f6: 68bb ldr r3, [r7, #8] 80029f8: 3301 adds r3, #1 80029fa: e009 b.n 8002a10 80029fc: 68bb ldr r3, [r7, #8] 80029fe: f44f 7296 mov.w r2, #300 @ 0x12c 8002a02: fb02 f303 mul.w r3, r2, r3 8002a06: 4a69 ldr r2, [pc, #420] @ (8002bac ) 8002a08: fba2 2303 umull r2, r3, r2, r3 8002a0c: 099b lsrs r3, r3, #6 8002a0e: 3301 adds r3, #1 8002a10: 687a ldr r2, [r7, #4] 8002a12: 6812 ldr r2, [r2, #0] 8002a14: 430b orrs r3, r1 8002a16: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8002a18: 687b ldr r3, [r7, #4] 8002a1a: 681b ldr r3, [r3, #0] 8002a1c: 69db ldr r3, [r3, #28] 8002a1e: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8002a22: f022 02ff bic.w r2, r2, #255 @ 0xff 8002a26: 687b ldr r3, [r7, #4] 8002a28: 685b ldr r3, [r3, #4] 8002a2a: 495c ldr r1, [pc, #368] @ (8002b9c ) 8002a2c: 428b cmp r3, r1 8002a2e: d819 bhi.n 8002a64 8002a30: 68fb ldr r3, [r7, #12] 8002a32: 1e59 subs r1, r3, #1 8002a34: 687b ldr r3, [r7, #4] 8002a36: 685b ldr r3, [r3, #4] 8002a38: 005b lsls r3, r3, #1 8002a3a: fbb1 f3f3 udiv r3, r1, r3 8002a3e: 1c59 adds r1, r3, #1 8002a40: f640 73fc movw r3, #4092 @ 0xffc 8002a44: 400b ands r3, r1 8002a46: 2b00 cmp r3, #0 8002a48: d00a beq.n 8002a60 8002a4a: 68fb ldr r3, [r7, #12] 8002a4c: 1e59 subs r1, r3, #1 8002a4e: 687b ldr r3, [r7, #4] 8002a50: 685b ldr r3, [r3, #4] 8002a52: 005b lsls r3, r3, #1 8002a54: fbb1 f3f3 udiv r3, r1, r3 8002a58: 3301 adds r3, #1 8002a5a: f3c3 030b ubfx r3, r3, #0, #12 8002a5e: e051 b.n 8002b04 8002a60: 2304 movs r3, #4 8002a62: e04f b.n 8002b04 8002a64: 687b ldr r3, [r7, #4] 8002a66: 689b ldr r3, [r3, #8] 8002a68: 2b00 cmp r3, #0 8002a6a: d111 bne.n 8002a90 8002a6c: 68fb ldr r3, [r7, #12] 8002a6e: 1e58 subs r0, r3, #1 8002a70: 687b ldr r3, [r7, #4] 8002a72: 6859 ldr r1, [r3, #4] 8002a74: 460b mov r3, r1 8002a76: 005b lsls r3, r3, #1 8002a78: 440b add r3, r1 8002a7a: fbb0 f3f3 udiv r3, r0, r3 8002a7e: 3301 adds r3, #1 8002a80: f3c3 030b ubfx r3, r3, #0, #12 8002a84: 2b00 cmp r3, #0 8002a86: bf0c ite eq 8002a88: 2301 moveq r3, #1 8002a8a: 2300 movne r3, #0 8002a8c: b2db uxtb r3, r3 8002a8e: e012 b.n 8002ab6 8002a90: 68fb ldr r3, [r7, #12] 8002a92: 1e58 subs r0, r3, #1 8002a94: 687b ldr r3, [r7, #4] 8002a96: 6859 ldr r1, [r3, #4] 8002a98: 460b mov r3, r1 8002a9a: 009b lsls r3, r3, #2 8002a9c: 440b add r3, r1 8002a9e: 0099 lsls r1, r3, #2 8002aa0: 440b add r3, r1 8002aa2: fbb0 f3f3 udiv r3, r0, r3 8002aa6: 3301 adds r3, #1 8002aa8: f3c3 030b ubfx r3, r3, #0, #12 8002aac: 2b00 cmp r3, #0 8002aae: bf0c ite eq 8002ab0: 2301 moveq r3, #1 8002ab2: 2300 movne r3, #0 8002ab4: b2db uxtb r3, r3 8002ab6: 2b00 cmp r3, #0 8002ab8: d001 beq.n 8002abe 8002aba: 2301 movs r3, #1 8002abc: e022 b.n 8002b04 8002abe: 687b ldr r3, [r7, #4] 8002ac0: 689b ldr r3, [r3, #8] 8002ac2: 2b00 cmp r3, #0 8002ac4: d10e bne.n 8002ae4 8002ac6: 68fb ldr r3, [r7, #12] 8002ac8: 1e58 subs r0, r3, #1 8002aca: 687b ldr r3, [r7, #4] 8002acc: 6859 ldr r1, [r3, #4] 8002ace: 460b mov r3, r1 8002ad0: 005b lsls r3, r3, #1 8002ad2: 440b add r3, r1 8002ad4: fbb0 f3f3 udiv r3, r0, r3 8002ad8: 3301 adds r3, #1 8002ada: f3c3 030b ubfx r3, r3, #0, #12 8002ade: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002ae2: e00f b.n 8002b04 8002ae4: 68fb ldr r3, [r7, #12] 8002ae6: 1e58 subs r0, r3, #1 8002ae8: 687b ldr r3, [r7, #4] 8002aea: 6859 ldr r1, [r3, #4] 8002aec: 460b mov r3, r1 8002aee: 009b lsls r3, r3, #2 8002af0: 440b add r3, r1 8002af2: 0099 lsls r1, r3, #2 8002af4: 440b add r3, r1 8002af6: fbb0 f3f3 udiv r3, r0, r3 8002afa: 3301 adds r3, #1 8002afc: f3c3 030b ubfx r3, r3, #0, #12 8002b00: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8002b04: 6879 ldr r1, [r7, #4] 8002b06: 6809 ldr r1, [r1, #0] 8002b08: 4313 orrs r3, r2 8002b0a: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002b0c: 687b ldr r3, [r7, #4] 8002b0e: 681b ldr r3, [r3, #0] 8002b10: 681b ldr r3, [r3, #0] 8002b12: f023 01c0 bic.w r1, r3, #192 @ 0xc0 8002b16: 687b ldr r3, [r7, #4] 8002b18: 69da ldr r2, [r3, #28] 8002b1a: 687b ldr r3, [r7, #4] 8002b1c: 6a1b ldr r3, [r3, #32] 8002b1e: 431a orrs r2, r3 8002b20: 687b ldr r3, [r7, #4] 8002b22: 681b ldr r3, [r3, #0] 8002b24: 430a orrs r2, r1 8002b26: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002b28: 687b ldr r3, [r7, #4] 8002b2a: 681b ldr r3, [r3, #0] 8002b2c: 689b ldr r3, [r3, #8] 8002b2e: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8002b32: f023 03ff bic.w r3, r3, #255 @ 0xff 8002b36: 687a ldr r2, [r7, #4] 8002b38: 6911 ldr r1, [r2, #16] 8002b3a: 687a ldr r2, [r7, #4] 8002b3c: 68d2 ldr r2, [r2, #12] 8002b3e: 4311 orrs r1, r2 8002b40: 687a ldr r2, [r7, #4] 8002b42: 6812 ldr r2, [r2, #0] 8002b44: 430b orrs r3, r1 8002b46: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8002b48: 687b ldr r3, [r7, #4] 8002b4a: 681b ldr r3, [r3, #0] 8002b4c: 68db ldr r3, [r3, #12] 8002b4e: f023 01ff bic.w r1, r3, #255 @ 0xff 8002b52: 687b ldr r3, [r7, #4] 8002b54: 695a ldr r2, [r3, #20] 8002b56: 687b ldr r3, [r7, #4] 8002b58: 699b ldr r3, [r3, #24] 8002b5a: 431a orrs r2, r3 8002b5c: 687b ldr r3, [r7, #4] 8002b5e: 681b ldr r3, [r3, #0] 8002b60: 430a orrs r2, r1 8002b62: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002b64: 687b ldr r3, [r7, #4] 8002b66: 681b ldr r3, [r3, #0] 8002b68: 681a ldr r2, [r3, #0] 8002b6a: 687b ldr r3, [r7, #4] 8002b6c: 681b ldr r3, [r3, #0] 8002b6e: f042 0201 orr.w r2, r2, #1 8002b72: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002b74: 687b ldr r3, [r7, #4] 8002b76: 2200 movs r2, #0 8002b78: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8002b7a: 687b ldr r3, [r7, #4] 8002b7c: 2220 movs r2, #32 8002b7e: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8002b82: 687b ldr r3, [r7, #4] 8002b84: 2200 movs r2, #0 8002b86: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002b88: 687b ldr r3, [r7, #4] 8002b8a: 2200 movs r2, #0 8002b8c: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8002b90: 2300 movs r3, #0 } 8002b92: 4618 mov r0, r3 8002b94: 3710 adds r7, #16 8002b96: 46bd mov sp, r7 8002b98: bd80 pop {r7, pc} 8002b9a: bf00 nop 8002b9c: 000186a0 .word 0x000186a0 8002ba0: 001e847f .word 0x001e847f 8002ba4: 003d08ff .word 0x003d08ff 8002ba8: 431bde83 .word 0x431bde83 8002bac: 10624dd3 .word 0x10624dd3 08002bb0 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8002bb0: b580 push {r7, lr} 8002bb2: b086 sub sp, #24 8002bb4: af02 add r7, sp, #8 8002bb6: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8002bb8: 687b ldr r3, [r7, #4] 8002bba: 2b00 cmp r3, #0 8002bbc: d101 bne.n 8002bc2 { return HAL_ERROR; 8002bbe: 2301 movs r3, #1 8002bc0: e108 b.n 8002dd4 /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); #if defined (USB_OTG_FS) USBx = hpcd->Instance; 8002bc2: 687b ldr r3, [r7, #4] 8002bc4: 681b ldr r3, [r3, #0] 8002bc6: 60bb str r3, [r7, #8] #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) 8002bc8: 687b ldr r3, [r7, #4] 8002bca: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 8002bce: b2db uxtb r3, r3 8002bd0: 2b00 cmp r3, #0 8002bd2: d106 bne.n 8002be2 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8002bd4: 687b ldr r3, [r7, #4] 8002bd6: 2200 movs r2, #0 8002bd8: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8002bdc: 6878 ldr r0, [r7, #4] 8002bde: f007 fbb1 bl 800a344 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8002be2: 687b ldr r3, [r7, #4] 8002be4: 2203 movs r2, #3 8002be6: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ if (USBx == USB_OTG_FS) 8002bea: 68bb ldr r3, [r7, #8] 8002bec: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002bf0: d102 bne.n 8002bf8 { hpcd->Init.dma_enable = 0U; 8002bf2: 687b ldr r3, [r7, #4] 8002bf4: 2200 movs r2, #0 8002bf6: 719a strb r2, [r3, #6] } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8002bf8: 687b ldr r3, [r7, #4] 8002bfa: 681b ldr r3, [r3, #0] 8002bfc: 4618 mov r0, r3 8002bfe: f004 faa6 bl 800714e /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002c02: 687b ldr r3, [r7, #4] 8002c04: 6818 ldr r0, [r3, #0] 8002c06: 687b ldr r3, [r7, #4] 8002c08: 7c1a ldrb r2, [r3, #16] 8002c0a: f88d 2000 strb.w r2, [sp] 8002c0e: 3304 adds r3, #4 8002c10: cb0e ldmia r3, {r1, r2, r3} 8002c12: f004 f985 bl 8006f20 8002c16: 4603 mov r3, r0 8002c18: 2b00 cmp r3, #0 8002c1a: d005 beq.n 8002c28 { hpcd->State = HAL_PCD_STATE_ERROR; 8002c1c: 687b ldr r3, [r7, #4] 8002c1e: 2202 movs r2, #2 8002c20: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002c24: 2301 movs r3, #1 8002c26: e0d5 b.n 8002dd4 } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 8002c28: 687b ldr r3, [r7, #4] 8002c2a: 681b ldr r3, [r3, #0] 8002c2c: 2100 movs r1, #0 8002c2e: 4618 mov r0, r3 8002c30: f004 fa9e bl 8007170 8002c34: 4603 mov r3, r0 8002c36: 2b00 cmp r3, #0 8002c38: d005 beq.n 8002c46 { hpcd->State = HAL_PCD_STATE_ERROR; 8002c3a: 687b ldr r3, [r7, #4] 8002c3c: 2202 movs r2, #2 8002c3e: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002c42: 2301 movs r3, #1 8002c44: e0c6 b.n 8002dd4 } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002c46: 2300 movs r3, #0 8002c48: 73fb strb r3, [r7, #15] 8002c4a: e04a b.n 8002ce2 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8002c4c: 7bfa ldrb r2, [r7, #15] 8002c4e: 6879 ldr r1, [r7, #4] 8002c50: 4613 mov r3, r2 8002c52: 00db lsls r3, r3, #3 8002c54: 4413 add r3, r2 8002c56: 009b lsls r3, r3, #2 8002c58: 440b add r3, r1 8002c5a: 3315 adds r3, #21 8002c5c: 2201 movs r2, #1 8002c5e: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8002c60: 7bfa ldrb r2, [r7, #15] 8002c62: 6879 ldr r1, [r7, #4] 8002c64: 4613 mov r3, r2 8002c66: 00db lsls r3, r3, #3 8002c68: 4413 add r3, r2 8002c6a: 009b lsls r3, r3, #2 8002c6c: 440b add r3, r1 8002c6e: 3314 adds r3, #20 8002c70: 7bfa ldrb r2, [r7, #15] 8002c72: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8002c74: 7bfa ldrb r2, [r7, #15] 8002c76: 7bfb ldrb r3, [r7, #15] 8002c78: b298 uxth r0, r3 8002c7a: 6879 ldr r1, [r7, #4] 8002c7c: 4613 mov r3, r2 8002c7e: 00db lsls r3, r3, #3 8002c80: 4413 add r3, r2 8002c82: 009b lsls r3, r3, #2 8002c84: 440b add r3, r1 8002c86: 332e adds r3, #46 @ 0x2e 8002c88: 4602 mov r2, r0 8002c8a: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8002c8c: 7bfa ldrb r2, [r7, #15] 8002c8e: 6879 ldr r1, [r7, #4] 8002c90: 4613 mov r3, r2 8002c92: 00db lsls r3, r3, #3 8002c94: 4413 add r3, r2 8002c96: 009b lsls r3, r3, #2 8002c98: 440b add r3, r1 8002c9a: 3318 adds r3, #24 8002c9c: 2200 movs r2, #0 8002c9e: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8002ca0: 7bfa ldrb r2, [r7, #15] 8002ca2: 6879 ldr r1, [r7, #4] 8002ca4: 4613 mov r3, r2 8002ca6: 00db lsls r3, r3, #3 8002ca8: 4413 add r3, r2 8002caa: 009b lsls r3, r3, #2 8002cac: 440b add r3, r1 8002cae: 331c adds r3, #28 8002cb0: 2200 movs r2, #0 8002cb2: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8002cb4: 7bfa ldrb r2, [r7, #15] 8002cb6: 6879 ldr r1, [r7, #4] 8002cb8: 4613 mov r3, r2 8002cba: 00db lsls r3, r3, #3 8002cbc: 4413 add r3, r2 8002cbe: 009b lsls r3, r3, #2 8002cc0: 440b add r3, r1 8002cc2: 3320 adds r3, #32 8002cc4: 2200 movs r2, #0 8002cc6: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8002cc8: 7bfa ldrb r2, [r7, #15] 8002cca: 6879 ldr r1, [r7, #4] 8002ccc: 4613 mov r3, r2 8002cce: 00db lsls r3, r3, #3 8002cd0: 4413 add r3, r2 8002cd2: 009b lsls r3, r3, #2 8002cd4: 440b add r3, r1 8002cd6: 3324 adds r3, #36 @ 0x24 8002cd8: 2200 movs r2, #0 8002cda: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002cdc: 7bfb ldrb r3, [r7, #15] 8002cde: 3301 adds r3, #1 8002ce0: 73fb strb r3, [r7, #15] 8002ce2: 687b ldr r3, [r7, #4] 8002ce4: 791b ldrb r3, [r3, #4] 8002ce6: 7bfa ldrb r2, [r7, #15] 8002ce8: 429a cmp r2, r3 8002cea: d3af bcc.n 8002c4c } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002cec: 2300 movs r3, #0 8002cee: 73fb strb r3, [r7, #15] 8002cf0: e044 b.n 8002d7c { hpcd->OUT_ep[i].is_in = 0U; 8002cf2: 7bfa ldrb r2, [r7, #15] 8002cf4: 6879 ldr r1, [r7, #4] 8002cf6: 4613 mov r3, r2 8002cf8: 00db lsls r3, r3, #3 8002cfa: 4413 add r3, r2 8002cfc: 009b lsls r3, r3, #2 8002cfe: 440b add r3, r1 8002d00: f203 2355 addw r3, r3, #597 @ 0x255 8002d04: 2200 movs r2, #0 8002d06: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8002d08: 7bfa ldrb r2, [r7, #15] 8002d0a: 6879 ldr r1, [r7, #4] 8002d0c: 4613 mov r3, r2 8002d0e: 00db lsls r3, r3, #3 8002d10: 4413 add r3, r2 8002d12: 009b lsls r3, r3, #2 8002d14: 440b add r3, r1 8002d16: f503 7315 add.w r3, r3, #596 @ 0x254 8002d1a: 7bfa ldrb r2, [r7, #15] 8002d1c: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8002d1e: 7bfa ldrb r2, [r7, #15] 8002d20: 6879 ldr r1, [r7, #4] 8002d22: 4613 mov r3, r2 8002d24: 00db lsls r3, r3, #3 8002d26: 4413 add r3, r2 8002d28: 009b lsls r3, r3, #2 8002d2a: 440b add r3, r1 8002d2c: f503 7316 add.w r3, r3, #600 @ 0x258 8002d30: 2200 movs r2, #0 8002d32: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8002d34: 7bfa ldrb r2, [r7, #15] 8002d36: 6879 ldr r1, [r7, #4] 8002d38: 4613 mov r3, r2 8002d3a: 00db lsls r3, r3, #3 8002d3c: 4413 add r3, r2 8002d3e: 009b lsls r3, r3, #2 8002d40: 440b add r3, r1 8002d42: f503 7317 add.w r3, r3, #604 @ 0x25c 8002d46: 2200 movs r2, #0 8002d48: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 8002d4a: 7bfa ldrb r2, [r7, #15] 8002d4c: 6879 ldr r1, [r7, #4] 8002d4e: 4613 mov r3, r2 8002d50: 00db lsls r3, r3, #3 8002d52: 4413 add r3, r2 8002d54: 009b lsls r3, r3, #2 8002d56: 440b add r3, r1 8002d58: f503 7318 add.w r3, r3, #608 @ 0x260 8002d5c: 2200 movs r2, #0 8002d5e: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8002d60: 7bfa ldrb r2, [r7, #15] 8002d62: 6879 ldr r1, [r7, #4] 8002d64: 4613 mov r3, r2 8002d66: 00db lsls r3, r3, #3 8002d68: 4413 add r3, r2 8002d6a: 009b lsls r3, r3, #2 8002d6c: 440b add r3, r1 8002d6e: f503 7319 add.w r3, r3, #612 @ 0x264 8002d72: 2200 movs r2, #0 8002d74: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002d76: 7bfb ldrb r3, [r7, #15] 8002d78: 3301 adds r3, #1 8002d7a: 73fb strb r3, [r7, #15] 8002d7c: 687b ldr r3, [r7, #4] 8002d7e: 791b ldrb r3, [r3, #4] 8002d80: 7bfa ldrb r2, [r7, #15] 8002d82: 429a cmp r2, r3 8002d84: d3b5 bcc.n 8002cf2 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002d86: 687b ldr r3, [r7, #4] 8002d88: 6818 ldr r0, [r3, #0] 8002d8a: 687b ldr r3, [r7, #4] 8002d8c: 7c1a ldrb r2, [r3, #16] 8002d8e: f88d 2000 strb.w r2, [sp] 8002d92: 3304 adds r3, #4 8002d94: cb0e ldmia r3, {r1, r2, r3} 8002d96: f004 fa37 bl 8007208 8002d9a: 4603 mov r3, r0 8002d9c: 2b00 cmp r3, #0 8002d9e: d005 beq.n 8002dac { hpcd->State = HAL_PCD_STATE_ERROR; 8002da0: 687b ldr r3, [r7, #4] 8002da2: 2202 movs r2, #2 8002da4: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002da8: 2301 movs r3, #1 8002daa: e013 b.n 8002dd4 } hpcd->USB_Address = 0U; 8002dac: 687b ldr r3, [r7, #4] 8002dae: 2200 movs r2, #0 8002db0: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 8002db2: 687b ldr r3, [r7, #4] 8002db4: 2201 movs r2, #1 8002db6: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8002dba: 687b ldr r3, [r7, #4] 8002dbc: 7b1b ldrb r3, [r3, #12] 8002dbe: 2b01 cmp r3, #1 8002dc0: d102 bne.n 8002dc8 { (void)HAL_PCDEx_ActivateLPM(hpcd); 8002dc2: 6878 ldr r0, [r7, #4] 8002dc4: f001 f956 bl 8004074 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 8002dc8: 687b ldr r3, [r7, #4] 8002dca: 681b ldr r3, [r3, #0] 8002dcc: 4618 mov r0, r3 8002dce: f005 fa74 bl 80082ba return HAL_OK; 8002dd2: 2300 movs r3, #0 } 8002dd4: 4618 mov r0, r3 8002dd6: 3710 adds r7, #16 8002dd8: 46bd mov sp, r7 8002dda: bd80 pop {r7, pc} 08002ddc : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8002ddc: b580 push {r7, lr} 8002dde: b084 sub sp, #16 8002de0: af00 add r7, sp, #0 8002de2: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002de4: 687b ldr r3, [r7, #4] 8002de6: 681b ldr r3, [r3, #0] 8002de8: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8002dea: 687b ldr r3, [r7, #4] 8002dec: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8002df0: 2b01 cmp r3, #1 8002df2: d101 bne.n 8002df8 8002df4: 2302 movs r3, #2 8002df6: e022 b.n 8002e3e 8002df8: 687b ldr r3, [r7, #4] 8002dfa: 2201 movs r2, #1 8002dfc: f883 2494 strb.w r2, [r3, #1172] @ 0x494 if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002e00: 68fb ldr r3, [r7, #12] 8002e02: 68db ldr r3, [r3, #12] 8002e04: f003 0340 and.w r3, r3, #64 @ 0x40 8002e08: 2b00 cmp r3, #0 8002e0a: d009 beq.n 8002e20 (hpcd->Init.battery_charging_enable == 1U)) 8002e0c: 687b ldr r3, [r7, #4] 8002e0e: 7b5b ldrb r3, [r3, #13] if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002e10: 2b01 cmp r3, #1 8002e12: d105 bne.n 8002e20 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8002e14: 68fb ldr r3, [r7, #12] 8002e16: 6b9b ldr r3, [r3, #56] @ 0x38 8002e18: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8002e1c: 68fb ldr r3, [r7, #12] 8002e1e: 639a str r2, [r3, #56] @ 0x38 } __HAL_PCD_ENABLE(hpcd); 8002e20: 687b ldr r3, [r7, #4] 8002e22: 681b ldr r3, [r3, #0] 8002e24: 4618 mov r0, r3 8002e26: f004 f981 bl 800712c (void)USB_DevConnect(hpcd->Instance); 8002e2a: 687b ldr r3, [r7, #4] 8002e2c: 681b ldr r3, [r3, #0] 8002e2e: 4618 mov r0, r3 8002e30: f005 fa22 bl 8008278 __HAL_UNLOCK(hpcd); 8002e34: 687b ldr r3, [r7, #4] 8002e36: 2200 movs r2, #0 8002e38: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8002e3c: 2300 movs r3, #0 } 8002e3e: 4618 mov r0, r3 8002e40: 3710 adds r7, #16 8002e42: 46bd mov sp, r7 8002e44: bd80 pop {r7, pc} 08002e46 : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8002e46: b590 push {r4, r7, lr} 8002e48: b08d sub sp, #52 @ 0x34 8002e4a: af00 add r7, sp, #0 8002e4c: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002e4e: 687b ldr r3, [r7, #4] 8002e50: 681b ldr r3, [r3, #0] 8002e52: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8002e54: 6a3b ldr r3, [r7, #32] 8002e56: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 8002e58: 687b ldr r3, [r7, #4] 8002e5a: 681b ldr r3, [r3, #0] 8002e5c: 4618 mov r0, r3 8002e5e: f005 fae0 bl 8008422 8002e62: 4603 mov r3, r0 8002e64: 2b00 cmp r3, #0 8002e66: f040 84b9 bne.w 80037dc { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 8002e6a: 687b ldr r3, [r7, #4] 8002e6c: 681b ldr r3, [r3, #0] 8002e6e: 4618 mov r0, r3 8002e70: f005 fa44 bl 80082fc 8002e74: 4603 mov r3, r0 8002e76: 2b00 cmp r3, #0 8002e78: f000 84af beq.w 80037da { return; } /* store current frame number */ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; 8002e7c: 69fb ldr r3, [r7, #28] 8002e7e: f503 6300 add.w r3, r3, #2048 @ 0x800 8002e82: 689b ldr r3, [r3, #8] 8002e84: 0a1b lsrs r3, r3, #8 8002e86: f3c3 020d ubfx r2, r3, #0, #14 8002e8a: 687b ldr r3, [r7, #4] 8002e8c: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8002e90: 687b ldr r3, [r7, #4] 8002e92: 681b ldr r3, [r3, #0] 8002e94: 4618 mov r0, r3 8002e96: f005 fa31 bl 80082fc 8002e9a: 4603 mov r3, r0 8002e9c: f003 0302 and.w r3, r3, #2 8002ea0: 2b02 cmp r3, #2 8002ea2: d107 bne.n 8002eb4 { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8002ea4: 687b ldr r3, [r7, #4] 8002ea6: 681b ldr r3, [r3, #0] 8002ea8: 695a ldr r2, [r3, #20] 8002eaa: 687b ldr r3, [r7, #4] 8002eac: 681b ldr r3, [r3, #0] 8002eae: f002 0202 and.w r2, r2, #2 8002eb2: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8002eb4: 687b ldr r3, [r7, #4] 8002eb6: 681b ldr r3, [r3, #0] 8002eb8: 4618 mov r0, r3 8002eba: f005 fa1f bl 80082fc 8002ebe: 4603 mov r3, r0 8002ec0: f003 0310 and.w r3, r3, #16 8002ec4: 2b10 cmp r3, #16 8002ec6: d161 bne.n 8002f8c { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002ec8: 687b ldr r3, [r7, #4] 8002eca: 681b ldr r3, [r3, #0] 8002ecc: 699a ldr r2, [r3, #24] 8002ece: 687b ldr r3, [r7, #4] 8002ed0: 681b ldr r3, [r3, #0] 8002ed2: f022 0210 bic.w r2, r2, #16 8002ed6: 619a str r2, [r3, #24] RegVal = USBx->GRXSTSP; 8002ed8: 6a3b ldr r3, [r7, #32] 8002eda: 6a1b ldr r3, [r3, #32] 8002edc: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; 8002ede: 69bb ldr r3, [r7, #24] 8002ee0: f003 020f and.w r2, r3, #15 8002ee4: 4613 mov r3, r2 8002ee6: 00db lsls r3, r3, #3 8002ee8: 4413 add r3, r2 8002eea: 009b lsls r3, r3, #2 8002eec: f503 7314 add.w r3, r3, #592 @ 0x250 8002ef0: 687a ldr r2, [r7, #4] 8002ef2: 4413 add r3, r2 8002ef4: 3304 adds r3, #4 8002ef6: 617b str r3, [r7, #20] if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 8002ef8: 69bb ldr r3, [r7, #24] 8002efa: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002efe: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8002f02: d124 bne.n 8002f4e { if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) 8002f04: 69ba ldr r2, [r7, #24] 8002f06: f647 73f0 movw r3, #32752 @ 0x7ff0 8002f0a: 4013 ands r3, r2 8002f0c: 2b00 cmp r3, #0 8002f0e: d035 beq.n 8002f7c { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002f10: 697b ldr r3, [r7, #20] 8002f12: 68d9 ldr r1, [r3, #12] (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); 8002f14: 69bb ldr r3, [r7, #24] 8002f16: 091b lsrs r3, r3, #4 8002f18: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002f1a: f3c3 030a ubfx r3, r3, #0, #11 8002f1e: b29b uxth r3, r3 8002f20: 461a mov r2, r3 8002f22: 6a38 ldr r0, [r7, #32] 8002f24: f005 f856 bl 8007fd4 ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002f28: 697b ldr r3, [r7, #20] 8002f2a: 68da ldr r2, [r3, #12] 8002f2c: 69bb ldr r3, [r7, #24] 8002f2e: 091b lsrs r3, r3, #4 8002f30: f3c3 030a ubfx r3, r3, #0, #11 8002f34: 441a add r2, r3 8002f36: 697b ldr r3, [r7, #20] 8002f38: 60da str r2, [r3, #12] ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002f3a: 697b ldr r3, [r7, #20] 8002f3c: 695a ldr r2, [r3, #20] 8002f3e: 69bb ldr r3, [r7, #24] 8002f40: 091b lsrs r3, r3, #4 8002f42: f3c3 030a ubfx r3, r3, #0, #11 8002f46: 441a add r2, r3 8002f48: 697b ldr r3, [r7, #20] 8002f4a: 615a str r2, [r3, #20] 8002f4c: e016 b.n 8002f7c } } else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 8002f4e: 69bb ldr r3, [r7, #24] 8002f50: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002f54: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8002f58: d110 bne.n 8002f7c { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 8002f5a: 687b ldr r3, [r7, #4] 8002f5c: f203 439c addw r3, r3, #1180 @ 0x49c 8002f60: 2208 movs r2, #8 8002f62: 4619 mov r1, r3 8002f64: 6a38 ldr r0, [r7, #32] 8002f66: f005 f835 bl 8007fd4 ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002f6a: 697b ldr r3, [r7, #20] 8002f6c: 695a ldr r2, [r3, #20] 8002f6e: 69bb ldr r3, [r7, #24] 8002f70: 091b lsrs r3, r3, #4 8002f72: f3c3 030a ubfx r3, r3, #0, #11 8002f76: 441a add r2, r3 8002f78: 697b ldr r3, [r7, #20] 8002f7a: 615a str r2, [r3, #20] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002f7c: 687b ldr r3, [r7, #4] 8002f7e: 681b ldr r3, [r3, #0] 8002f80: 699a ldr r2, [r3, #24] 8002f82: 687b ldr r3, [r7, #4] 8002f84: 681b ldr r3, [r3, #0] 8002f86: f042 0210 orr.w r2, r2, #16 8002f8a: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 8002f8c: 687b ldr r3, [r7, #4] 8002f8e: 681b ldr r3, [r3, #0] 8002f90: 4618 mov r0, r3 8002f92: f005 f9b3 bl 80082fc 8002f96: 4603 mov r3, r0 8002f98: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002f9c: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8002fa0: f040 80a7 bne.w 80030f2 { epnum = 0U; 8002fa4: 2300 movs r3, #0 8002fa6: 627b str r3, [r7, #36] @ 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8002fa8: 687b ldr r3, [r7, #4] 8002faa: 681b ldr r3, [r3, #0] 8002fac: 4618 mov r0, r3 8002fae: f005 f9b8 bl 8008322 8002fb2: 62b8 str r0, [r7, #40] @ 0x28 while (ep_intr != 0U) 8002fb4: e099 b.n 80030ea { if ((ep_intr & 0x1U) != 0U) 8002fb6: 6abb ldr r3, [r7, #40] @ 0x28 8002fb8: f003 0301 and.w r3, r3, #1 8002fbc: 2b00 cmp r3, #0 8002fbe: f000 808e beq.w 80030de { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002fc2: 687b ldr r3, [r7, #4] 8002fc4: 681b ldr r3, [r3, #0] 8002fc6: 6a7a ldr r2, [r7, #36] @ 0x24 8002fc8: b2d2 uxtb r2, r2 8002fca: 4611 mov r1, r2 8002fcc: 4618 mov r0, r3 8002fce: f005 f9dc bl 800838a 8002fd2: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 8002fd4: 693b ldr r3, [r7, #16] 8002fd6: f003 0301 and.w r3, r3, #1 8002fda: 2b00 cmp r3, #0 8002fdc: d00c beq.n 8002ff8 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 8002fde: 6a7b ldr r3, [r7, #36] @ 0x24 8002fe0: 015a lsls r2, r3, #5 8002fe2: 69fb ldr r3, [r7, #28] 8002fe4: 4413 add r3, r2 8002fe6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002fea: 461a mov r2, r3 8002fec: 2301 movs r3, #1 8002fee: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 8002ff0: 6a79 ldr r1, [r7, #36] @ 0x24 8002ff2: 6878 ldr r0, [r7, #4] 8002ff4: f000 feb8 bl 8003d68 } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 8002ff8: 693b ldr r3, [r7, #16] 8002ffa: f003 0308 and.w r3, r3, #8 8002ffe: 2b00 cmp r3, #0 8003000: d00c beq.n 800301c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 8003002: 6a7b ldr r3, [r7, #36] @ 0x24 8003004: 015a lsls r2, r3, #5 8003006: 69fb ldr r3, [r7, #28] 8003008: 4413 add r3, r2 800300a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800300e: 461a mov r2, r3 8003010: 2308 movs r3, #8 8003012: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 8003014: 6a79 ldr r1, [r7, #36] @ 0x24 8003016: 6878 ldr r0, [r7, #4] 8003018: f000 ff8e bl 8003f38 } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 800301c: 693b ldr r3, [r7, #16] 800301e: f003 0310 and.w r3, r3, #16 8003022: 2b00 cmp r3, #0 8003024: d008 beq.n 8003038 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 8003026: 6a7b ldr r3, [r7, #36] @ 0x24 8003028: 015a lsls r2, r3, #5 800302a: 69fb ldr r3, [r7, #28] 800302c: 4413 add r3, r2 800302e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003032: 461a mov r2, r3 8003034: 2310 movs r3, #16 8003036: 6093 str r3, [r2, #8] } /* Clear OUT Endpoint disable interrupt */ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) 8003038: 693b ldr r3, [r7, #16] 800303a: f003 0302 and.w r3, r3, #2 800303e: 2b00 cmp r3, #0 8003040: d030 beq.n 80030a4 { if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) 8003042: 6a3b ldr r3, [r7, #32] 8003044: 695b ldr r3, [r3, #20] 8003046: f003 0380 and.w r3, r3, #128 @ 0x80 800304a: 2b80 cmp r3, #128 @ 0x80 800304c: d109 bne.n 8003062 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; 800304e: 69fb ldr r3, [r7, #28] 8003050: f503 6300 add.w r3, r3, #2048 @ 0x800 8003054: 685b ldr r3, [r3, #4] 8003056: 69fa ldr r2, [r7, #28] 8003058: f502 6200 add.w r2, r2, #2048 @ 0x800 800305c: f443 6380 orr.w r3, r3, #1024 @ 0x400 8003060: 6053 str r3, [r2, #4] } ep = &hpcd->OUT_ep[epnum]; 8003062: 6a7a ldr r2, [r7, #36] @ 0x24 8003064: 4613 mov r3, r2 8003066: 00db lsls r3, r3, #3 8003068: 4413 add r3, r2 800306a: 009b lsls r3, r3, #2 800306c: f503 7314 add.w r3, r3, #592 @ 0x250 8003070: 687a ldr r2, [r7, #4] 8003072: 4413 add r3, r2 8003074: 3304 adds r3, #4 8003076: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 8003078: 697b ldr r3, [r7, #20] 800307a: 78db ldrb r3, [r3, #3] 800307c: 2b01 cmp r3, #1 800307e: d108 bne.n 8003092 { ep->is_iso_incomplete = 0U; 8003080: 697b ldr r3, [r7, #20] 8003082: 2200 movs r2, #0 8003084: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 8003086: 6a7b ldr r3, [r7, #36] @ 0x24 8003088: b2db uxtb r3, r3 800308a: 4619 mov r1, r3 800308c: 6878 ldr r0, [r7, #4] 800308e: f007 fa75 bl 800a57c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); 8003092: 6a7b ldr r3, [r7, #36] @ 0x24 8003094: 015a lsls r2, r3, #5 8003096: 69fb ldr r3, [r7, #28] 8003098: 4413 add r3, r2 800309a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800309e: 461a mov r2, r3 80030a0: 2302 movs r3, #2 80030a2: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 80030a4: 693b ldr r3, [r7, #16] 80030a6: f003 0320 and.w r3, r3, #32 80030aa: 2b00 cmp r3, #0 80030ac: d008 beq.n 80030c0 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 80030ae: 6a7b ldr r3, [r7, #36] @ 0x24 80030b0: 015a lsls r2, r3, #5 80030b2: 69fb ldr r3, [r7, #28] 80030b4: 4413 add r3, r2 80030b6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80030ba: 461a mov r2, r3 80030bc: 2320 movs r3, #32 80030be: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 80030c0: 693b ldr r3, [r7, #16] 80030c2: f403 5300 and.w r3, r3, #8192 @ 0x2000 80030c6: 2b00 cmp r3, #0 80030c8: d009 beq.n 80030de { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 80030ca: 6a7b ldr r3, [r7, #36] @ 0x24 80030cc: 015a lsls r2, r3, #5 80030ce: 69fb ldr r3, [r7, #28] 80030d0: 4413 add r3, r2 80030d2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80030d6: 461a mov r2, r3 80030d8: f44f 5300 mov.w r3, #8192 @ 0x2000 80030dc: 6093 str r3, [r2, #8] } } epnum++; 80030de: 6a7b ldr r3, [r7, #36] @ 0x24 80030e0: 3301 adds r3, #1 80030e2: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 80030e4: 6abb ldr r3, [r7, #40] @ 0x28 80030e6: 085b lsrs r3, r3, #1 80030e8: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 80030ea: 6abb ldr r3, [r7, #40] @ 0x28 80030ec: 2b00 cmp r3, #0 80030ee: f47f af62 bne.w 8002fb6 } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 80030f2: 687b ldr r3, [r7, #4] 80030f4: 681b ldr r3, [r3, #0] 80030f6: 4618 mov r0, r3 80030f8: f005 f900 bl 80082fc 80030fc: 4603 mov r3, r0 80030fe: f403 2380 and.w r3, r3, #262144 @ 0x40000 8003102: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8003106: f040 80db bne.w 80032c0 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 800310a: 687b ldr r3, [r7, #4] 800310c: 681b ldr r3, [r3, #0] 800310e: 4618 mov r0, r3 8003110: f005 f921 bl 8008356 8003114: 62b8 str r0, [r7, #40] @ 0x28 epnum = 0U; 8003116: 2300 movs r3, #0 8003118: 627b str r3, [r7, #36] @ 0x24 while (ep_intr != 0U) 800311a: e0cd b.n 80032b8 { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 800311c: 6abb ldr r3, [r7, #40] @ 0x28 800311e: f003 0301 and.w r3, r3, #1 8003122: 2b00 cmp r3, #0 8003124: f000 80c2 beq.w 80032ac { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8003128: 687b ldr r3, [r7, #4] 800312a: 681b ldr r3, [r3, #0] 800312c: 6a7a ldr r2, [r7, #36] @ 0x24 800312e: b2d2 uxtb r2, r2 8003130: 4611 mov r1, r2 8003132: 4618 mov r0, r3 8003134: f005 f947 bl 80083c6 8003138: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 800313a: 693b ldr r3, [r7, #16] 800313c: f003 0301 and.w r3, r3, #1 8003140: 2b00 cmp r3, #0 8003142: d057 beq.n 80031f4 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8003144: 6a7b ldr r3, [r7, #36] @ 0x24 8003146: f003 030f and.w r3, r3, #15 800314a: 2201 movs r2, #1 800314c: fa02 f303 lsl.w r3, r2, r3 8003150: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003152: 69fb ldr r3, [r7, #28] 8003154: f503 6300 add.w r3, r3, #2048 @ 0x800 8003158: 6b5a ldr r2, [r3, #52] @ 0x34 800315a: 68fb ldr r3, [r7, #12] 800315c: 43db mvns r3, r3 800315e: 69f9 ldr r1, [r7, #28] 8003160: f501 6100 add.w r1, r1, #2048 @ 0x800 8003164: 4013 ands r3, r2 8003166: 634b str r3, [r1, #52] @ 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 8003168: 6a7b ldr r3, [r7, #36] @ 0x24 800316a: 015a lsls r2, r3, #5 800316c: 69fb ldr r3, [r7, #28] 800316e: 4413 add r3, r2 8003170: f503 6310 add.w r3, r3, #2304 @ 0x900 8003174: 461a mov r2, r3 8003176: 2301 movs r3, #1 8003178: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 800317a: 687b ldr r3, [r7, #4] 800317c: 799b ldrb r3, [r3, #6] 800317e: 2b01 cmp r3, #1 8003180: d132 bne.n 80031e8 { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 8003182: 6879 ldr r1, [r7, #4] 8003184: 6a7a ldr r2, [r7, #36] @ 0x24 8003186: 4613 mov r3, r2 8003188: 00db lsls r3, r3, #3 800318a: 4413 add r3, r2 800318c: 009b lsls r3, r3, #2 800318e: 440b add r3, r1 8003190: 3320 adds r3, #32 8003192: 6819 ldr r1, [r3, #0] 8003194: 6878 ldr r0, [r7, #4] 8003196: 6a7a ldr r2, [r7, #36] @ 0x24 8003198: 4613 mov r3, r2 800319a: 00db lsls r3, r3, #3 800319c: 4413 add r3, r2 800319e: 009b lsls r3, r3, #2 80031a0: 4403 add r3, r0 80031a2: 331c adds r3, #28 80031a4: 681b ldr r3, [r3, #0] 80031a6: 4419 add r1, r3 80031a8: 6878 ldr r0, [r7, #4] 80031aa: 6a7a ldr r2, [r7, #36] @ 0x24 80031ac: 4613 mov r3, r2 80031ae: 00db lsls r3, r3, #3 80031b0: 4413 add r3, r2 80031b2: 009b lsls r3, r3, #2 80031b4: 4403 add r3, r0 80031b6: 3320 adds r3, #32 80031b8: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 80031ba: 6a7b ldr r3, [r7, #36] @ 0x24 80031bc: 2b00 cmp r3, #0 80031be: d113 bne.n 80031e8 80031c0: 6879 ldr r1, [r7, #4] 80031c2: 6a7a ldr r2, [r7, #36] @ 0x24 80031c4: 4613 mov r3, r2 80031c6: 00db lsls r3, r3, #3 80031c8: 4413 add r3, r2 80031ca: 009b lsls r3, r3, #2 80031cc: 440b add r3, r1 80031ce: 3324 adds r3, #36 @ 0x24 80031d0: 681b ldr r3, [r3, #0] 80031d2: 2b00 cmp r3, #0 80031d4: d108 bne.n 80031e8 { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 80031d6: 687b ldr r3, [r7, #4] 80031d8: 6818 ldr r0, [r3, #0] 80031da: 687b ldr r3, [r7, #4] 80031dc: f203 439c addw r3, r3, #1180 @ 0x49c 80031e0: 461a mov r2, r3 80031e2: 2101 movs r1, #1 80031e4: f005 f94e bl 8008484 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 80031e8: 6a7b ldr r3, [r7, #36] @ 0x24 80031ea: b2db uxtb r3, r3 80031ec: 4619 mov r1, r3 80031ee: 6878 ldr r0, [r7, #4] 80031f0: f007 f93f bl 800a472 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 80031f4: 693b ldr r3, [r7, #16] 80031f6: f003 0308 and.w r3, r3, #8 80031fa: 2b00 cmp r3, #0 80031fc: d008 beq.n 8003210 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 80031fe: 6a7b ldr r3, [r7, #36] @ 0x24 8003200: 015a lsls r2, r3, #5 8003202: 69fb ldr r3, [r7, #28] 8003204: 4413 add r3, r2 8003206: f503 6310 add.w r3, r3, #2304 @ 0x900 800320a: 461a mov r2, r3 800320c: 2308 movs r3, #8 800320e: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 8003210: 693b ldr r3, [r7, #16] 8003212: f003 0310 and.w r3, r3, #16 8003216: 2b00 cmp r3, #0 8003218: d008 beq.n 800322c { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 800321a: 6a7b ldr r3, [r7, #36] @ 0x24 800321c: 015a lsls r2, r3, #5 800321e: 69fb ldr r3, [r7, #28] 8003220: 4413 add r3, r2 8003222: f503 6310 add.w r3, r3, #2304 @ 0x900 8003226: 461a mov r2, r3 8003228: 2310 movs r3, #16 800322a: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 800322c: 693b ldr r3, [r7, #16] 800322e: f003 0340 and.w r3, r3, #64 @ 0x40 8003232: 2b00 cmp r3, #0 8003234: d008 beq.n 8003248 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 8003236: 6a7b ldr r3, [r7, #36] @ 0x24 8003238: 015a lsls r2, r3, #5 800323a: 69fb ldr r3, [r7, #28] 800323c: 4413 add r3, r2 800323e: f503 6310 add.w r3, r3, #2304 @ 0x900 8003242: 461a mov r2, r3 8003244: 2340 movs r3, #64 @ 0x40 8003246: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 8003248: 693b ldr r3, [r7, #16] 800324a: f003 0302 and.w r3, r3, #2 800324e: 2b00 cmp r3, #0 8003250: d023 beq.n 800329a { (void)USB_FlushTxFifo(USBx, epnum); 8003252: 6a79 ldr r1, [r7, #36] @ 0x24 8003254: 6a38 ldr r0, [r7, #32] 8003256: f004 f935 bl 80074c4 ep = &hpcd->IN_ep[epnum]; 800325a: 6a7a ldr r2, [r7, #36] @ 0x24 800325c: 4613 mov r3, r2 800325e: 00db lsls r3, r3, #3 8003260: 4413 add r3, r2 8003262: 009b lsls r3, r3, #2 8003264: 3310 adds r3, #16 8003266: 687a ldr r2, [r7, #4] 8003268: 4413 add r3, r2 800326a: 3304 adds r3, #4 800326c: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 800326e: 697b ldr r3, [r7, #20] 8003270: 78db ldrb r3, [r3, #3] 8003272: 2b01 cmp r3, #1 8003274: d108 bne.n 8003288 { ep->is_iso_incomplete = 0U; 8003276: 697b ldr r3, [r7, #20] 8003278: 2200 movs r2, #0 800327a: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 800327c: 6a7b ldr r3, [r7, #36] @ 0x24 800327e: b2db uxtb r3, r3 8003280: 4619 mov r1, r3 8003282: 6878 ldr r0, [r7, #4] 8003284: f007 f98c bl 800a5a0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 8003288: 6a7b ldr r3, [r7, #36] @ 0x24 800328a: 015a lsls r2, r3, #5 800328c: 69fb ldr r3, [r7, #28] 800328e: 4413 add r3, r2 8003290: f503 6310 add.w r3, r3, #2304 @ 0x900 8003294: 461a mov r2, r3 8003296: 2302 movs r3, #2 8003298: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 800329a: 693b ldr r3, [r7, #16] 800329c: f003 0380 and.w r3, r3, #128 @ 0x80 80032a0: 2b00 cmp r3, #0 80032a2: d003 beq.n 80032ac { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 80032a4: 6a79 ldr r1, [r7, #36] @ 0x24 80032a6: 6878 ldr r0, [r7, #4] 80032a8: f000 fcd2 bl 8003c50 } } epnum++; 80032ac: 6a7b ldr r3, [r7, #36] @ 0x24 80032ae: 3301 adds r3, #1 80032b0: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 80032b2: 6abb ldr r3, [r7, #40] @ 0x28 80032b4: 085b lsrs r3, r3, #1 80032b6: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 80032b8: 6abb ldr r3, [r7, #40] @ 0x28 80032ba: 2b00 cmp r3, #0 80032bc: f47f af2e bne.w 800311c } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 80032c0: 687b ldr r3, [r7, #4] 80032c2: 681b ldr r3, [r3, #0] 80032c4: 4618 mov r0, r3 80032c6: f005 f819 bl 80082fc 80032ca: 4603 mov r3, r0 80032cc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80032d0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80032d4: d122 bne.n 800331c { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 80032d6: 69fb ldr r3, [r7, #28] 80032d8: f503 6300 add.w r3, r3, #2048 @ 0x800 80032dc: 685b ldr r3, [r3, #4] 80032de: 69fa ldr r2, [r7, #28] 80032e0: f502 6200 add.w r2, r2, #2048 @ 0x800 80032e4: f023 0301 bic.w r3, r3, #1 80032e8: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 80032ea: 687b ldr r3, [r7, #4] 80032ec: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 80032f0: 2b01 cmp r3, #1 80032f2: d108 bne.n 8003306 { hpcd->LPM_State = LPM_L0; 80032f4: 687b ldr r3, [r7, #4] 80032f6: 2200 movs r2, #0 80032f8: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 80032fc: 2100 movs r1, #0 80032fe: 6878 ldr r0, [r7, #4] 8003300: f007 faf4 bl 800a8ec 8003304: e002 b.n 800330c else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 8003306: 6878 ldr r0, [r7, #4] 8003308: f007 f92a bl 800a560 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 800330c: 687b ldr r3, [r7, #4] 800330e: 681b ldr r3, [r3, #0] 8003310: 695a ldr r2, [r3, #20] 8003312: 687b ldr r3, [r7, #4] 8003314: 681b ldr r3, [r3, #0] 8003316: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 800331a: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 800331c: 687b ldr r3, [r7, #4] 800331e: 681b ldr r3, [r3, #0] 8003320: 4618 mov r0, r3 8003322: f004 ffeb bl 80082fc 8003326: 4603 mov r3, r0 8003328: f403 6300 and.w r3, r3, #2048 @ 0x800 800332c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8003330: d112 bne.n 8003358 { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 8003332: 69fb ldr r3, [r7, #28] 8003334: f503 6300 add.w r3, r3, #2048 @ 0x800 8003338: 689b ldr r3, [r3, #8] 800333a: f003 0301 and.w r3, r3, #1 800333e: 2b01 cmp r3, #1 8003340: d102 bne.n 8003348 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8003342: 6878 ldr r0, [r7, #4] 8003344: f007 f8e6 bl 800a514 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 8003348: 687b ldr r3, [r7, #4] 800334a: 681b ldr r3, [r3, #0] 800334c: 695a ldr r2, [r3, #20] 800334e: 687b ldr r3, [r7, #4] 8003350: 681b ldr r3, [r3, #0] 8003352: f402 6200 and.w r2, r2, #2048 @ 0x800 8003356: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 8003358: 687b ldr r3, [r7, #4] 800335a: 681b ldr r3, [r3, #0] 800335c: 4618 mov r0, r3 800335e: f004 ffcd bl 80082fc 8003362: 4603 mov r3, r0 8003364: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8003368: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800336c: d121 bne.n 80033b2 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 800336e: 687b ldr r3, [r7, #4] 8003370: 681b ldr r3, [r3, #0] 8003372: 695a ldr r2, [r3, #20] 8003374: 687b ldr r3, [r7, #4] 8003376: 681b ldr r3, [r3, #0] 8003378: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 800337c: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 800337e: 687b ldr r3, [r7, #4] 8003380: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003384: 2b00 cmp r3, #0 8003386: d111 bne.n 80033ac { hpcd->LPM_State = LPM_L1; 8003388: 687b ldr r3, [r7, #4] 800338a: 2201 movs r2, #1 800338c: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 8003390: 687b ldr r3, [r7, #4] 8003392: 681b ldr r3, [r3, #0] 8003394: 6d5b ldr r3, [r3, #84] @ 0x54 8003396: 089b lsrs r3, r3, #2 8003398: f003 020f and.w r2, r3, #15 800339c: 687b ldr r3, [r7, #4] 800339e: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 80033a2: 2101 movs r1, #1 80033a4: 6878 ldr r0, [r7, #4] 80033a6: f007 faa1 bl 800a8ec 80033aa: e002 b.n 80033b2 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80033ac: 6878 ldr r0, [r7, #4] 80033ae: f007 f8b1 bl 800a514 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 80033b2: 687b ldr r3, [r7, #4] 80033b4: 681b ldr r3, [r3, #0] 80033b6: 4618 mov r0, r3 80033b8: f004 ffa0 bl 80082fc 80033bc: 4603 mov r3, r0 80033be: f403 5380 and.w r3, r3, #4096 @ 0x1000 80033c2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80033c6: f040 80b7 bne.w 8003538 { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 80033ca: 69fb ldr r3, [r7, #28] 80033cc: f503 6300 add.w r3, r3, #2048 @ 0x800 80033d0: 685b ldr r3, [r3, #4] 80033d2: 69fa ldr r2, [r7, #28] 80033d4: f502 6200 add.w r2, r2, #2048 @ 0x800 80033d8: f023 0301 bic.w r3, r3, #1 80033dc: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 80033de: 687b ldr r3, [r7, #4] 80033e0: 681b ldr r3, [r3, #0] 80033e2: 2110 movs r1, #16 80033e4: 4618 mov r0, r3 80033e6: f004 f86d bl 80074c4 for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80033ea: 2300 movs r3, #0 80033ec: 62fb str r3, [r7, #44] @ 0x2c 80033ee: e046 b.n 800347e { USBx_INEP(i)->DIEPINT = 0xFB7FU; 80033f0: 6afb ldr r3, [r7, #44] @ 0x2c 80033f2: 015a lsls r2, r3, #5 80033f4: 69fb ldr r3, [r7, #28] 80033f6: 4413 add r3, r2 80033f8: f503 6310 add.w r3, r3, #2304 @ 0x900 80033fc: 461a mov r2, r3 80033fe: f64f 337f movw r3, #64383 @ 0xfb7f 8003402: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8003404: 6afb ldr r3, [r7, #44] @ 0x2c 8003406: 015a lsls r2, r3, #5 8003408: 69fb ldr r3, [r7, #28] 800340a: 4413 add r3, r2 800340c: f503 6310 add.w r3, r3, #2304 @ 0x900 8003410: 681b ldr r3, [r3, #0] 8003412: 6afa ldr r2, [r7, #44] @ 0x2c 8003414: 0151 lsls r1, r2, #5 8003416: 69fa ldr r2, [r7, #28] 8003418: 440a add r2, r1 800341a: f502 6210 add.w r2, r2, #2304 @ 0x900 800341e: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8003422: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8003424: 6afb ldr r3, [r7, #44] @ 0x2c 8003426: 015a lsls r2, r3, #5 8003428: 69fb ldr r3, [r7, #28] 800342a: 4413 add r3, r2 800342c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003430: 461a mov r2, r3 8003432: f64f 337f movw r3, #64383 @ 0xfb7f 8003436: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8003438: 6afb ldr r3, [r7, #44] @ 0x2c 800343a: 015a lsls r2, r3, #5 800343c: 69fb ldr r3, [r7, #28] 800343e: 4413 add r3, r2 8003440: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003444: 681b ldr r3, [r3, #0] 8003446: 6afa ldr r2, [r7, #44] @ 0x2c 8003448: 0151 lsls r1, r2, #5 800344a: 69fa ldr r2, [r7, #28] 800344c: 440a add r2, r1 800344e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003452: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8003456: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8003458: 6afb ldr r3, [r7, #44] @ 0x2c 800345a: 015a lsls r2, r3, #5 800345c: 69fb ldr r3, [r7, #28] 800345e: 4413 add r3, r2 8003460: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003464: 681b ldr r3, [r3, #0] 8003466: 6afa ldr r2, [r7, #44] @ 0x2c 8003468: 0151 lsls r1, r2, #5 800346a: 69fa ldr r2, [r7, #28] 800346c: 440a add r2, r1 800346e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003472: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8003476: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8003478: 6afb ldr r3, [r7, #44] @ 0x2c 800347a: 3301 adds r3, #1 800347c: 62fb str r3, [r7, #44] @ 0x2c 800347e: 687b ldr r3, [r7, #4] 8003480: 791b ldrb r3, [r3, #4] 8003482: 461a mov r2, r3 8003484: 6afb ldr r3, [r7, #44] @ 0x2c 8003486: 4293 cmp r3, r2 8003488: d3b2 bcc.n 80033f0 } USBx_DEVICE->DAINTMSK |= 0x10001U; 800348a: 69fb ldr r3, [r7, #28] 800348c: f503 6300 add.w r3, r3, #2048 @ 0x800 8003490: 69db ldr r3, [r3, #28] 8003492: 69fa ldr r2, [r7, #28] 8003494: f502 6200 add.w r2, r2, #2048 @ 0x800 8003498: f043 1301 orr.w r3, r3, #65537 @ 0x10001 800349c: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 800349e: 687b ldr r3, [r7, #4] 80034a0: 7bdb ldrb r3, [r3, #15] 80034a2: 2b00 cmp r3, #0 80034a4: d016 beq.n 80034d4 { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 80034a6: 69fb ldr r3, [r7, #28] 80034a8: f503 6300 add.w r3, r3, #2048 @ 0x800 80034ac: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80034b0: 69fa ldr r2, [r7, #28] 80034b2: f502 6200 add.w r2, r2, #2048 @ 0x800 80034b6: f043 030b orr.w r3, r3, #11 80034ba: f8c2 3084 str.w r3, [r2, #132] @ 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 80034be: 69fb ldr r3, [r7, #28] 80034c0: f503 6300 add.w r3, r3, #2048 @ 0x800 80034c4: 6c5b ldr r3, [r3, #68] @ 0x44 80034c6: 69fa ldr r2, [r7, #28] 80034c8: f502 6200 add.w r2, r2, #2048 @ 0x800 80034cc: f043 030b orr.w r3, r3, #11 80034d0: 6453 str r3, [r2, #68] @ 0x44 80034d2: e015 b.n 8003500 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 80034d4: 69fb ldr r3, [r7, #28] 80034d6: f503 6300 add.w r3, r3, #2048 @ 0x800 80034da: 695b ldr r3, [r3, #20] 80034dc: 69fa ldr r2, [r7, #28] 80034de: f502 6200 add.w r2, r2, #2048 @ 0x800 80034e2: f443 5300 orr.w r3, r3, #8192 @ 0x2000 80034e6: f043 032b orr.w r3, r3, #43 @ 0x2b 80034ea: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 80034ec: 69fb ldr r3, [r7, #28] 80034ee: f503 6300 add.w r3, r3, #2048 @ 0x800 80034f2: 691b ldr r3, [r3, #16] 80034f4: 69fa ldr r2, [r7, #28] 80034f6: f502 6200 add.w r2, r2, #2048 @ 0x800 80034fa: f043 030b orr.w r3, r3, #11 80034fe: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8003500: 69fb ldr r3, [r7, #28] 8003502: f503 6300 add.w r3, r3, #2048 @ 0x800 8003506: 681b ldr r3, [r3, #0] 8003508: 69fa ldr r2, [r7, #28] 800350a: f502 6200 add.w r2, r2, #2048 @ 0x800 800350e: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8003512: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003514: 687b ldr r3, [r7, #4] 8003516: 6818 ldr r0, [r3, #0] 8003518: 687b ldr r3, [r7, #4] 800351a: 7999 ldrb r1, [r3, #6] (uint8_t *)hpcd->Setup); 800351c: 687b ldr r3, [r7, #4] 800351e: f203 439c addw r3, r3, #1180 @ 0x49c (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003522: 461a mov r2, r3 8003524: f004 ffae bl 8008484 __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 8003528: 687b ldr r3, [r7, #4] 800352a: 681b ldr r3, [r3, #0] 800352c: 695a ldr r2, [r3, #20] 800352e: 687b ldr r3, [r7, #4] 8003530: 681b ldr r3, [r3, #0] 8003532: f402 5280 and.w r2, r2, #4096 @ 0x1000 8003536: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 8003538: 687b ldr r3, [r7, #4] 800353a: 681b ldr r3, [r3, #0] 800353c: 4618 mov r0, r3 800353e: f004 fedd bl 80082fc 8003542: 4603 mov r3, r0 8003544: f403 5300 and.w r3, r3, #8192 @ 0x2000 8003548: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800354c: d123 bne.n 8003596 { (void)USB_ActivateSetup(hpcd->Instance); 800354e: 687b ldr r3, [r7, #4] 8003550: 681b ldr r3, [r3, #0] 8003552: 4618 mov r0, r3 8003554: f004 ff73 bl 800843e hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 8003558: 687b ldr r3, [r7, #4] 800355a: 681b ldr r3, [r3, #0] 800355c: 4618 mov r0, r3 800355e: f004 f82a bl 80075b6 8003562: 4603 mov r3, r0 8003564: 461a mov r2, r3 8003566: 687b ldr r3, [r7, #4] 8003568: 71da strb r2, [r3, #7] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 800356a: 687b ldr r3, [r7, #4] 800356c: 681c ldr r4, [r3, #0] 800356e: f000 fe8b bl 8004288 8003572: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 8003574: 687b ldr r3, [r7, #4] 8003576: 79db ldrb r3, [r3, #7] (void)USB_SetTurnaroundTime(hpcd->Instance, 8003578: 461a mov r2, r3 800357a: 4620 mov r0, r4 800357c: f003 fd34 bl 8006fe8 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 8003580: 6878 ldr r0, [r7, #4] 8003582: f006 ff9e bl 800a4c2 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 8003586: 687b ldr r3, [r7, #4] 8003588: 681b ldr r3, [r3, #0] 800358a: 695a ldr r2, [r3, #20] 800358c: 687b ldr r3, [r7, #4] 800358e: 681b ldr r3, [r3, #0] 8003590: f402 5200 and.w r2, r2, #8192 @ 0x2000 8003594: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 8003596: 687b ldr r3, [r7, #4] 8003598: 681b ldr r3, [r3, #0] 800359a: 4618 mov r0, r3 800359c: f004 feae bl 80082fc 80035a0: 4603 mov r3, r0 80035a2: f003 0308 and.w r3, r3, #8 80035a6: 2b08 cmp r3, #8 80035a8: d10a bne.n 80035c0 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 80035aa: 6878 ldr r0, [r7, #4] 80035ac: f006 ff7b bl 800a4a6 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 80035b0: 687b ldr r3, [r7, #4] 80035b2: 681b ldr r3, [r3, #0] 80035b4: 695a ldr r2, [r3, #20] 80035b6: 687b ldr r3, [r7, #4] 80035b8: 681b ldr r3, [r3, #0] 80035ba: f002 0208 and.w r2, r2, #8 80035be: 615a str r2, [r3, #20] } /* Handle Global OUT NAK effective Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) 80035c0: 687b ldr r3, [r7, #4] 80035c2: 681b ldr r3, [r3, #0] 80035c4: 4618 mov r0, r3 80035c6: f004 fe99 bl 80082fc 80035ca: 4603 mov r3, r0 80035cc: f003 0380 and.w r3, r3, #128 @ 0x80 80035d0: 2b80 cmp r3, #128 @ 0x80 80035d2: d123 bne.n 800361c { USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; 80035d4: 6a3b ldr r3, [r7, #32] 80035d6: 699b ldr r3, [r3, #24] 80035d8: f023 0280 bic.w r2, r3, #128 @ 0x80 80035dc: 6a3b ldr r3, [r7, #32] 80035de: 619a str r2, [r3, #24] for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80035e0: 2301 movs r3, #1 80035e2: 627b str r3, [r7, #36] @ 0x24 80035e4: e014 b.n 8003610 { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) 80035e6: 6879 ldr r1, [r7, #4] 80035e8: 6a7a ldr r2, [r7, #36] @ 0x24 80035ea: 4613 mov r3, r2 80035ec: 00db lsls r3, r3, #3 80035ee: 4413 add r3, r2 80035f0: 009b lsls r3, r3, #2 80035f2: 440b add r3, r1 80035f4: f203 2357 addw r3, r3, #599 @ 0x257 80035f8: 781b ldrb r3, [r3, #0] 80035fa: 2b01 cmp r3, #1 80035fc: d105 bne.n 800360a { /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); 80035fe: 6a7b ldr r3, [r7, #36] @ 0x24 8003600: b2db uxtb r3, r3 8003602: 4619 mov r1, r3 8003604: 6878 ldr r0, [r7, #4] 8003606: f000 faf2 bl 8003bee for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800360a: 6a7b ldr r3, [r7, #36] @ 0x24 800360c: 3301 adds r3, #1 800360e: 627b str r3, [r7, #36] @ 0x24 8003610: 687b ldr r3, [r7, #4] 8003612: 791b ldrb r3, [r3, #4] 8003614: 461a mov r2, r3 8003616: 6a7b ldr r3, [r7, #36] @ 0x24 8003618: 4293 cmp r3, r2 800361a: d3e4 bcc.n 80035e6 } } } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 800361c: 687b ldr r3, [r7, #4] 800361e: 681b ldr r3, [r3, #0] 8003620: 4618 mov r0, r3 8003622: f004 fe6b bl 80082fc 8003626: 4603 mov r3, r0 8003628: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800362c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003630: d13c bne.n 80036ac { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003632: 2301 movs r3, #1 8003634: 627b str r3, [r7, #36] @ 0x24 8003636: e02b b.n 8003690 { RegVal = USBx_INEP(epnum)->DIEPCTL; 8003638: 6a7b ldr r3, [r7, #36] @ 0x24 800363a: 015a lsls r2, r3, #5 800363c: 69fb ldr r3, [r7, #28] 800363e: 4413 add r3, r2 8003640: f503 6310 add.w r3, r3, #2304 @ 0x900 8003644: 681b ldr r3, [r3, #0] 8003646: 61bb str r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003648: 6879 ldr r1, [r7, #4] 800364a: 6a7a ldr r2, [r7, #36] @ 0x24 800364c: 4613 mov r3, r2 800364e: 00db lsls r3, r3, #3 8003650: 4413 add r3, r2 8003652: 009b lsls r3, r3, #2 8003654: 440b add r3, r1 8003656: 3318 adds r3, #24 8003658: 781b ldrb r3, [r3, #0] 800365a: 2b01 cmp r3, #1 800365c: d115 bne.n 800368a ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) 800365e: 69bb ldr r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003660: 2b00 cmp r3, #0 8003662: da12 bge.n 800368a { hpcd->IN_ep[epnum].is_iso_incomplete = 1U; 8003664: 6879 ldr r1, [r7, #4] 8003666: 6a7a ldr r2, [r7, #36] @ 0x24 8003668: 4613 mov r3, r2 800366a: 00db lsls r3, r3, #3 800366c: 4413 add r3, r2 800366e: 009b lsls r3, r3, #2 8003670: 440b add r3, r1 8003672: 3317 adds r3, #23 8003674: 2201 movs r2, #1 8003676: 701a strb r2, [r3, #0] /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); 8003678: 6a7b ldr r3, [r7, #36] @ 0x24 800367a: b2db uxtb r3, r3 800367c: f063 037f orn r3, r3, #127 @ 0x7f 8003680: b2db uxtb r3, r3 8003682: 4619 mov r1, r3 8003684: 6878 ldr r0, [r7, #4] 8003686: f000 fab2 bl 8003bee for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800368a: 6a7b ldr r3, [r7, #36] @ 0x24 800368c: 3301 adds r3, #1 800368e: 627b str r3, [r7, #36] @ 0x24 8003690: 687b ldr r3, [r7, #4] 8003692: 791b ldrb r3, [r3, #4] 8003694: 461a mov r2, r3 8003696: 6a7b ldr r3, [r7, #36] @ 0x24 8003698: 4293 cmp r3, r2 800369a: d3cd bcc.n 8003638 } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 800369c: 687b ldr r3, [r7, #4] 800369e: 681b ldr r3, [r3, #0] 80036a0: 695a ldr r2, [r3, #20] 80036a2: 687b ldr r3, [r7, #4] 80036a4: 681b ldr r3, [r3, #0] 80036a6: f402 1280 and.w r2, r2, #1048576 @ 0x100000 80036aa: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 80036ac: 687b ldr r3, [r7, #4] 80036ae: 681b ldr r3, [r3, #0] 80036b0: 4618 mov r0, r3 80036b2: f004 fe23 bl 80082fc 80036b6: 4603 mov r3, r0 80036b8: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80036bc: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80036c0: d156 bne.n 8003770 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80036c2: 2301 movs r3, #1 80036c4: 627b str r3, [r7, #36] @ 0x24 80036c6: e045 b.n 8003754 { RegVal = USBx_OUTEP(epnum)->DOEPCTL; 80036c8: 6a7b ldr r3, [r7, #36] @ 0x24 80036ca: 015a lsls r2, r3, #5 80036cc: 69fb ldr r3, [r7, #28] 80036ce: 4413 add r3, r2 80036d0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80036d4: 681b ldr r3, [r3, #0] 80036d6: 61bb str r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 80036d8: 6879 ldr r1, [r7, #4] 80036da: 6a7a ldr r2, [r7, #36] @ 0x24 80036dc: 4613 mov r3, r2 80036de: 00db lsls r3, r3, #3 80036e0: 4413 add r3, r2 80036e2: 009b lsls r3, r3, #2 80036e4: 440b add r3, r1 80036e6: f503 7316 add.w r3, r3, #600 @ 0x258 80036ea: 781b ldrb r3, [r3, #0] 80036ec: 2b01 cmp r3, #1 80036ee: d12e bne.n 800374e ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 80036f0: 69bb ldr r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 80036f2: 2b00 cmp r3, #0 80036f4: da2b bge.n 800374e (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) 80036f6: 69bb ldr r3, [r7, #24] 80036f8: 0c1a lsrs r2, r3, #16 80036fa: 687b ldr r3, [r7, #4] 80036fc: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 8003700: 4053 eors r3, r2 8003702: f003 0301 and.w r3, r3, #1 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003706: 2b00 cmp r3, #0 8003708: d121 bne.n 800374e { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; 800370a: 6879 ldr r1, [r7, #4] 800370c: 6a7a ldr r2, [r7, #36] @ 0x24 800370e: 4613 mov r3, r2 8003710: 00db lsls r3, r3, #3 8003712: 4413 add r3, r2 8003714: 009b lsls r3, r3, #2 8003716: 440b add r3, r1 8003718: f203 2357 addw r3, r3, #599 @ 0x257 800371c: 2201 movs r2, #1 800371e: 701a strb r2, [r3, #0] USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; 8003720: 6a3b ldr r3, [r7, #32] 8003722: 699b ldr r3, [r3, #24] 8003724: f043 0280 orr.w r2, r3, #128 @ 0x80 8003728: 6a3b ldr r3, [r7, #32] 800372a: 619a str r2, [r3, #24] if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) 800372c: 6a3b ldr r3, [r7, #32] 800372e: 695b ldr r3, [r3, #20] 8003730: f003 0380 and.w r3, r3, #128 @ 0x80 8003734: 2b00 cmp r3, #0 8003736: d10a bne.n 800374e { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; 8003738: 69fb ldr r3, [r7, #28] 800373a: f503 6300 add.w r3, r3, #2048 @ 0x800 800373e: 685b ldr r3, [r3, #4] 8003740: 69fa ldr r2, [r7, #28] 8003742: f502 6200 add.w r2, r2, #2048 @ 0x800 8003746: f443 7300 orr.w r3, r3, #512 @ 0x200 800374a: 6053 str r3, [r2, #4] break; 800374c: e008 b.n 8003760 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800374e: 6a7b ldr r3, [r7, #36] @ 0x24 8003750: 3301 adds r3, #1 8003752: 627b str r3, [r7, #36] @ 0x24 8003754: 687b ldr r3, [r7, #4] 8003756: 791b ldrb r3, [r3, #4] 8003758: 461a mov r2, r3 800375a: 6a7b ldr r3, [r7, #36] @ 0x24 800375c: 4293 cmp r3, r2 800375e: d3b3 bcc.n 80036c8 } } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8003760: 687b ldr r3, [r7, #4] 8003762: 681b ldr r3, [r3, #0] 8003764: 695a ldr r2, [r3, #20] 8003766: 687b ldr r3, [r7, #4] 8003768: 681b ldr r3, [r3, #0] 800376a: f402 1200 and.w r2, r2, #2097152 @ 0x200000 800376e: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 8003770: 687b ldr r3, [r7, #4] 8003772: 681b ldr r3, [r3, #0] 8003774: 4618 mov r0, r3 8003776: f004 fdc1 bl 80082fc 800377a: 4603 mov r3, r0 800377c: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8003780: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003784: d10a bne.n 800379c { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 8003786: 6878 ldr r0, [r7, #4] 8003788: f006 ff1c bl 800a5c4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 800378c: 687b ldr r3, [r7, #4] 800378e: 681b ldr r3, [r3, #0] 8003790: 695a ldr r2, [r3, #20] 8003792: 687b ldr r3, [r7, #4] 8003794: 681b ldr r3, [r3, #0] 8003796: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 800379a: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 800379c: 687b ldr r3, [r7, #4] 800379e: 681b ldr r3, [r3, #0] 80037a0: 4618 mov r0, r3 80037a2: f004 fdab bl 80082fc 80037a6: 4603 mov r3, r0 80037a8: f003 0304 and.w r3, r3, #4 80037ac: 2b04 cmp r3, #4 80037ae: d115 bne.n 80037dc { RegVal = hpcd->Instance->GOTGINT; 80037b0: 687b ldr r3, [r7, #4] 80037b2: 681b ldr r3, [r3, #0] 80037b4: 685b ldr r3, [r3, #4] 80037b6: 61bb str r3, [r7, #24] if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 80037b8: 69bb ldr r3, [r7, #24] 80037ba: f003 0304 and.w r3, r3, #4 80037be: 2b00 cmp r3, #0 80037c0: d002 beq.n 80037c8 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 80037c2: 6878 ldr r0, [r7, #4] 80037c4: f006 ff0c bl 800a5e0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= RegVal; 80037c8: 687b ldr r3, [r7, #4] 80037ca: 681b ldr r3, [r3, #0] 80037cc: 6859 ldr r1, [r3, #4] 80037ce: 687b ldr r3, [r7, #4] 80037d0: 681b ldr r3, [r3, #0] 80037d2: 69ba ldr r2, [r7, #24] 80037d4: 430a orrs r2, r1 80037d6: 605a str r2, [r3, #4] 80037d8: e000 b.n 80037dc return; 80037da: bf00 nop } } } 80037dc: 3734 adds r7, #52 @ 0x34 80037de: 46bd mov sp, r7 80037e0: bd90 pop {r4, r7, pc} 080037e2 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 80037e2: b580 push {r7, lr} 80037e4: b082 sub sp, #8 80037e6: af00 add r7, sp, #0 80037e8: 6078 str r0, [r7, #4] 80037ea: 460b mov r3, r1 80037ec: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 80037ee: 687b ldr r3, [r7, #4] 80037f0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80037f4: 2b01 cmp r3, #1 80037f6: d101 bne.n 80037fc 80037f8: 2302 movs r3, #2 80037fa: e012 b.n 8003822 80037fc: 687b ldr r3, [r7, #4] 80037fe: 2201 movs r2, #1 8003800: f883 2494 strb.w r2, [r3, #1172] @ 0x494 hpcd->USB_Address = address; 8003804: 687b ldr r3, [r7, #4] 8003806: 78fa ldrb r2, [r7, #3] 8003808: 745a strb r2, [r3, #17] (void)USB_SetDevAddress(hpcd->Instance, address); 800380a: 687b ldr r3, [r7, #4] 800380c: 681b ldr r3, [r3, #0] 800380e: 78fa ldrb r2, [r7, #3] 8003810: 4611 mov r1, r2 8003812: 4618 mov r0, r3 8003814: f004 fd0a bl 800822c __HAL_UNLOCK(hpcd); 8003818: 687b ldr r3, [r7, #4] 800381a: 2200 movs r2, #0 800381c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003820: 2300 movs r3, #0 } 8003822: 4618 mov r0, r3 8003824: 3708 adds r7, #8 8003826: 46bd mov sp, r7 8003828: bd80 pop {r7, pc} 0800382a : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 800382a: b580 push {r7, lr} 800382c: b084 sub sp, #16 800382e: af00 add r7, sp, #0 8003830: 6078 str r0, [r7, #4] 8003832: 4608 mov r0, r1 8003834: 4611 mov r1, r2 8003836: 461a mov r2, r3 8003838: 4603 mov r3, r0 800383a: 70fb strb r3, [r7, #3] 800383c: 460b mov r3, r1 800383e: 803b strh r3, [r7, #0] 8003840: 4613 mov r3, r2 8003842: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8003844: 2300 movs r3, #0 8003846: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8003848: f997 3003 ldrsb.w r3, [r7, #3] 800384c: 2b00 cmp r3, #0 800384e: da0f bge.n 8003870 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003850: 78fb ldrb r3, [r7, #3] 8003852: f003 020f and.w r2, r3, #15 8003856: 4613 mov r3, r2 8003858: 00db lsls r3, r3, #3 800385a: 4413 add r3, r2 800385c: 009b lsls r3, r3, #2 800385e: 3310 adds r3, #16 8003860: 687a ldr r2, [r7, #4] 8003862: 4413 add r3, r2 8003864: 3304 adds r3, #4 8003866: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003868: 68fb ldr r3, [r7, #12] 800386a: 2201 movs r2, #1 800386c: 705a strb r2, [r3, #1] 800386e: e00f b.n 8003890 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003870: 78fb ldrb r3, [r7, #3] 8003872: f003 020f and.w r2, r3, #15 8003876: 4613 mov r3, r2 8003878: 00db lsls r3, r3, #3 800387a: 4413 add r3, r2 800387c: 009b lsls r3, r3, #2 800387e: f503 7314 add.w r3, r3, #592 @ 0x250 8003882: 687a ldr r2, [r7, #4] 8003884: 4413 add r3, r2 8003886: 3304 adds r3, #4 8003888: 60fb str r3, [r7, #12] ep->is_in = 0U; 800388a: 68fb ldr r3, [r7, #12] 800388c: 2200 movs r2, #0 800388e: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003890: 78fb ldrb r3, [r7, #3] 8003892: f003 030f and.w r3, r3, #15 8003896: b2da uxtb r2, r3 8003898: 68fb ldr r3, [r7, #12] 800389a: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 800389c: 883b ldrh r3, [r7, #0] 800389e: f3c3 020a ubfx r2, r3, #0, #11 80038a2: 68fb ldr r3, [r7, #12] 80038a4: 609a str r2, [r3, #8] ep->type = ep_type; 80038a6: 68fb ldr r3, [r7, #12] 80038a8: 78ba ldrb r2, [r7, #2] 80038aa: 711a strb r2, [r3, #4] if (ep->is_in != 0U) 80038ac: 68fb ldr r3, [r7, #12] 80038ae: 785b ldrb r3, [r3, #1] 80038b0: 2b00 cmp r3, #0 80038b2: d004 beq.n 80038be { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 80038b4: 68fb ldr r3, [r7, #12] 80038b6: 781b ldrb r3, [r3, #0] 80038b8: 461a mov r2, r3 80038ba: 68fb ldr r3, [r7, #12] 80038bc: 835a strh r2, [r3, #26] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 80038be: 78bb ldrb r3, [r7, #2] 80038c0: 2b02 cmp r3, #2 80038c2: d102 bne.n 80038ca { ep->data_pid_start = 0U; 80038c4: 68fb ldr r3, [r7, #12] 80038c6: 2200 movs r2, #0 80038c8: 715a strb r2, [r3, #5] } __HAL_LOCK(hpcd); 80038ca: 687b ldr r3, [r7, #4] 80038cc: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80038d0: 2b01 cmp r3, #1 80038d2: d101 bne.n 80038d8 80038d4: 2302 movs r3, #2 80038d6: e00e b.n 80038f6 80038d8: 687b ldr r3, [r7, #4] 80038da: 2201 movs r2, #1 80038dc: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 80038e0: 687b ldr r3, [r7, #4] 80038e2: 681b ldr r3, [r3, #0] 80038e4: 68f9 ldr r1, [r7, #12] 80038e6: 4618 mov r0, r3 80038e8: f003 fe8a bl 8007600 __HAL_UNLOCK(hpcd); 80038ec: 687b ldr r3, [r7, #4] 80038ee: 2200 movs r2, #0 80038f0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return ret; 80038f4: 7afb ldrb r3, [r7, #11] } 80038f6: 4618 mov r0, r3 80038f8: 3710 adds r7, #16 80038fa: 46bd mov sp, r7 80038fc: bd80 pop {r7, pc} 080038fe : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80038fe: b580 push {r7, lr} 8003900: b084 sub sp, #16 8003902: af00 add r7, sp, #0 8003904: 6078 str r0, [r7, #4] 8003906: 460b mov r3, r1 8003908: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 800390a: f997 3003 ldrsb.w r3, [r7, #3] 800390e: 2b00 cmp r3, #0 8003910: da0f bge.n 8003932 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003912: 78fb ldrb r3, [r7, #3] 8003914: f003 020f and.w r2, r3, #15 8003918: 4613 mov r3, r2 800391a: 00db lsls r3, r3, #3 800391c: 4413 add r3, r2 800391e: 009b lsls r3, r3, #2 8003920: 3310 adds r3, #16 8003922: 687a ldr r2, [r7, #4] 8003924: 4413 add r3, r2 8003926: 3304 adds r3, #4 8003928: 60fb str r3, [r7, #12] ep->is_in = 1U; 800392a: 68fb ldr r3, [r7, #12] 800392c: 2201 movs r2, #1 800392e: 705a strb r2, [r3, #1] 8003930: e00f b.n 8003952 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003932: 78fb ldrb r3, [r7, #3] 8003934: f003 020f and.w r2, r3, #15 8003938: 4613 mov r3, r2 800393a: 00db lsls r3, r3, #3 800393c: 4413 add r3, r2 800393e: 009b lsls r3, r3, #2 8003940: f503 7314 add.w r3, r3, #592 @ 0x250 8003944: 687a ldr r2, [r7, #4] 8003946: 4413 add r3, r2 8003948: 3304 adds r3, #4 800394a: 60fb str r3, [r7, #12] ep->is_in = 0U; 800394c: 68fb ldr r3, [r7, #12] 800394e: 2200 movs r2, #0 8003950: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003952: 78fb ldrb r3, [r7, #3] 8003954: f003 030f and.w r3, r3, #15 8003958: b2da uxtb r2, r3 800395a: 68fb ldr r3, [r7, #12] 800395c: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 800395e: 687b ldr r3, [r7, #4] 8003960: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003964: 2b01 cmp r3, #1 8003966: d101 bne.n 800396c 8003968: 2302 movs r3, #2 800396a: e00e b.n 800398a 800396c: 687b ldr r3, [r7, #4] 800396e: 2201 movs r2, #1 8003970: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8003974: 687b ldr r3, [r7, #4] 8003976: 681b ldr r3, [r3, #0] 8003978: 68f9 ldr r1, [r7, #12] 800397a: 4618 mov r0, r3 800397c: f003 fec8 bl 8007710 __HAL_UNLOCK(hpcd); 8003980: 687b ldr r3, [r7, #4] 8003982: 2200 movs r2, #0 8003984: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003988: 2300 movs r3, #0 } 800398a: 4618 mov r0, r3 800398c: 3710 adds r7, #16 800398e: 46bd mov sp, r7 8003990: bd80 pop {r7, pc} 08003992 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003992: b580 push {r7, lr} 8003994: b086 sub sp, #24 8003996: af00 add r7, sp, #0 8003998: 60f8 str r0, [r7, #12] 800399a: 607a str r2, [r7, #4] 800399c: 603b str r3, [r7, #0] 800399e: 460b mov r3, r1 80039a0: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80039a2: 7afb ldrb r3, [r7, #11] 80039a4: f003 020f and.w r2, r3, #15 80039a8: 4613 mov r3, r2 80039aa: 00db lsls r3, r3, #3 80039ac: 4413 add r3, r2 80039ae: 009b lsls r3, r3, #2 80039b0: f503 7314 add.w r3, r3, #592 @ 0x250 80039b4: 68fa ldr r2, [r7, #12] 80039b6: 4413 add r3, r2 80039b8: 3304 adds r3, #4 80039ba: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 80039bc: 697b ldr r3, [r7, #20] 80039be: 687a ldr r2, [r7, #4] 80039c0: 60da str r2, [r3, #12] ep->xfer_len = len; 80039c2: 697b ldr r3, [r7, #20] 80039c4: 683a ldr r2, [r7, #0] 80039c6: 611a str r2, [r3, #16] ep->xfer_count = 0U; 80039c8: 697b ldr r3, [r7, #20] 80039ca: 2200 movs r2, #0 80039cc: 615a str r2, [r3, #20] ep->is_in = 0U; 80039ce: 697b ldr r3, [r7, #20] 80039d0: 2200 movs r2, #0 80039d2: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 80039d4: 7afb ldrb r3, [r7, #11] 80039d6: f003 030f and.w r3, r3, #15 80039da: b2da uxtb r2, r3 80039dc: 697b ldr r3, [r7, #20] 80039de: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 80039e0: 68fb ldr r3, [r7, #12] 80039e2: 799b ldrb r3, [r3, #6] 80039e4: 2b01 cmp r3, #1 80039e6: d102 bne.n 80039ee { ep->dma_addr = (uint32_t)pBuf; 80039e8: 687a ldr r2, [r7, #4] 80039ea: 697b ldr r3, [r7, #20] 80039ec: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 80039ee: 68fb ldr r3, [r7, #12] 80039f0: 6818 ldr r0, [r3, #0] 80039f2: 68fb ldr r3, [r7, #12] 80039f4: 799b ldrb r3, [r3, #6] 80039f6: 461a mov r2, r3 80039f8: 6979 ldr r1, [r7, #20] 80039fa: f003 ff65 bl 80078c8 return HAL_OK; 80039fe: 2300 movs r3, #0 } 8003a00: 4618 mov r0, r3 8003a02: 3718 adds r7, #24 8003a04: 46bd mov sp, r7 8003a06: bd80 pop {r7, pc} 08003a08 : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003a08: b580 push {r7, lr} 8003a0a: b086 sub sp, #24 8003a0c: af00 add r7, sp, #0 8003a0e: 60f8 str r0, [r7, #12] 8003a10: 607a str r2, [r7, #4] 8003a12: 603b str r3, [r7, #0] 8003a14: 460b mov r3, r1 8003a16: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003a18: 7afb ldrb r3, [r7, #11] 8003a1a: f003 020f and.w r2, r3, #15 8003a1e: 4613 mov r3, r2 8003a20: 00db lsls r3, r3, #3 8003a22: 4413 add r3, r2 8003a24: 009b lsls r3, r3, #2 8003a26: 3310 adds r3, #16 8003a28: 68fa ldr r2, [r7, #12] 8003a2a: 4413 add r3, r2 8003a2c: 3304 adds r3, #4 8003a2e: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003a30: 697b ldr r3, [r7, #20] 8003a32: 687a ldr r2, [r7, #4] 8003a34: 60da str r2, [r3, #12] ep->xfer_len = len; 8003a36: 697b ldr r3, [r7, #20] 8003a38: 683a ldr r2, [r7, #0] 8003a3a: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003a3c: 697b ldr r3, [r7, #20] 8003a3e: 2200 movs r2, #0 8003a40: 615a str r2, [r3, #20] ep->is_in = 1U; 8003a42: 697b ldr r3, [r7, #20] 8003a44: 2201 movs r2, #1 8003a46: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003a48: 7afb ldrb r3, [r7, #11] 8003a4a: f003 030f and.w r3, r3, #15 8003a4e: b2da uxtb r2, r3 8003a50: 697b ldr r3, [r7, #20] 8003a52: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003a54: 68fb ldr r3, [r7, #12] 8003a56: 799b ldrb r3, [r3, #6] 8003a58: 2b01 cmp r3, #1 8003a5a: d102 bne.n 8003a62 { ep->dma_addr = (uint32_t)pBuf; 8003a5c: 687a ldr r2, [r7, #4] 8003a5e: 697b ldr r3, [r7, #20] 8003a60: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003a62: 68fb ldr r3, [r7, #12] 8003a64: 6818 ldr r0, [r3, #0] 8003a66: 68fb ldr r3, [r7, #12] 8003a68: 799b ldrb r3, [r3, #6] 8003a6a: 461a mov r2, r3 8003a6c: 6979 ldr r1, [r7, #20] 8003a6e: f003 ff2b bl 80078c8 return HAL_OK; 8003a72: 2300 movs r3, #0 } 8003a74: 4618 mov r0, r3 8003a76: 3718 adds r7, #24 8003a78: 46bd mov sp, r7 8003a7a: bd80 pop {r7, pc} 08003a7c : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003a7c: b580 push {r7, lr} 8003a7e: b084 sub sp, #16 8003a80: af00 add r7, sp, #0 8003a82: 6078 str r0, [r7, #4] 8003a84: 460b mov r3, r1 8003a86: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 8003a88: 78fb ldrb r3, [r7, #3] 8003a8a: f003 030f and.w r3, r3, #15 8003a8e: 687a ldr r2, [r7, #4] 8003a90: 7912 ldrb r2, [r2, #4] 8003a92: 4293 cmp r3, r2 8003a94: d901 bls.n 8003a9a { return HAL_ERROR; 8003a96: 2301 movs r3, #1 8003a98: e04f b.n 8003b3a } if ((0x80U & ep_addr) == 0x80U) 8003a9a: f997 3003 ldrsb.w r3, [r7, #3] 8003a9e: 2b00 cmp r3, #0 8003aa0: da0f bge.n 8003ac2 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003aa2: 78fb ldrb r3, [r7, #3] 8003aa4: f003 020f and.w r2, r3, #15 8003aa8: 4613 mov r3, r2 8003aaa: 00db lsls r3, r3, #3 8003aac: 4413 add r3, r2 8003aae: 009b lsls r3, r3, #2 8003ab0: 3310 adds r3, #16 8003ab2: 687a ldr r2, [r7, #4] 8003ab4: 4413 add r3, r2 8003ab6: 3304 adds r3, #4 8003ab8: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003aba: 68fb ldr r3, [r7, #12] 8003abc: 2201 movs r2, #1 8003abe: 705a strb r2, [r3, #1] 8003ac0: e00d b.n 8003ade } else { ep = &hpcd->OUT_ep[ep_addr]; 8003ac2: 78fa ldrb r2, [r7, #3] 8003ac4: 4613 mov r3, r2 8003ac6: 00db lsls r3, r3, #3 8003ac8: 4413 add r3, r2 8003aca: 009b lsls r3, r3, #2 8003acc: f503 7314 add.w r3, r3, #592 @ 0x250 8003ad0: 687a ldr r2, [r7, #4] 8003ad2: 4413 add r3, r2 8003ad4: 3304 adds r3, #4 8003ad6: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003ad8: 68fb ldr r3, [r7, #12] 8003ada: 2200 movs r2, #0 8003adc: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8003ade: 68fb ldr r3, [r7, #12] 8003ae0: 2201 movs r2, #1 8003ae2: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003ae4: 78fb ldrb r3, [r7, #3] 8003ae6: f003 030f and.w r3, r3, #15 8003aea: b2da uxtb r2, r3 8003aec: 68fb ldr r3, [r7, #12] 8003aee: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003af0: 687b ldr r3, [r7, #4] 8003af2: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003af6: 2b01 cmp r3, #1 8003af8: d101 bne.n 8003afe 8003afa: 2302 movs r3, #2 8003afc: e01d b.n 8003b3a 8003afe: 687b ldr r3, [r7, #4] 8003b00: 2201 movs r2, #1 8003b02: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPSetStall(hpcd->Instance, ep); 8003b06: 687b ldr r3, [r7, #4] 8003b08: 681b ldr r3, [r3, #0] 8003b0a: 68f9 ldr r1, [r7, #12] 8003b0c: 4618 mov r0, r3 8003b0e: f004 fab9 bl 8008084 if ((ep_addr & EP_ADDR_MSK) == 0U) 8003b12: 78fb ldrb r3, [r7, #3] 8003b14: f003 030f and.w r3, r3, #15 8003b18: 2b00 cmp r3, #0 8003b1a: d109 bne.n 8003b30 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8003b1c: 687b ldr r3, [r7, #4] 8003b1e: 6818 ldr r0, [r3, #0] 8003b20: 687b ldr r3, [r7, #4] 8003b22: 7999 ldrb r1, [r3, #6] 8003b24: 687b ldr r3, [r7, #4] 8003b26: f203 439c addw r3, r3, #1180 @ 0x49c 8003b2a: 461a mov r2, r3 8003b2c: f004 fcaa bl 8008484 } __HAL_UNLOCK(hpcd); 8003b30: 687b ldr r3, [r7, #4] 8003b32: 2200 movs r2, #0 8003b34: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003b38: 2300 movs r3, #0 } 8003b3a: 4618 mov r0, r3 8003b3c: 3710 adds r7, #16 8003b3e: 46bd mov sp, r7 8003b40: bd80 pop {r7, pc} 08003b42 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003b42: b580 push {r7, lr} 8003b44: b084 sub sp, #16 8003b46: af00 add r7, sp, #0 8003b48: 6078 str r0, [r7, #4] 8003b4a: 460b mov r3, r1 8003b4c: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8003b4e: 78fb ldrb r3, [r7, #3] 8003b50: f003 030f and.w r3, r3, #15 8003b54: 687a ldr r2, [r7, #4] 8003b56: 7912 ldrb r2, [r2, #4] 8003b58: 4293 cmp r3, r2 8003b5a: d901 bls.n 8003b60 { return HAL_ERROR; 8003b5c: 2301 movs r3, #1 8003b5e: e042 b.n 8003be6 } if ((0x80U & ep_addr) == 0x80U) 8003b60: f997 3003 ldrsb.w r3, [r7, #3] 8003b64: 2b00 cmp r3, #0 8003b66: da0f bge.n 8003b88 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003b68: 78fb ldrb r3, [r7, #3] 8003b6a: f003 020f and.w r2, r3, #15 8003b6e: 4613 mov r3, r2 8003b70: 00db lsls r3, r3, #3 8003b72: 4413 add r3, r2 8003b74: 009b lsls r3, r3, #2 8003b76: 3310 adds r3, #16 8003b78: 687a ldr r2, [r7, #4] 8003b7a: 4413 add r3, r2 8003b7c: 3304 adds r3, #4 8003b7e: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003b80: 68fb ldr r3, [r7, #12] 8003b82: 2201 movs r2, #1 8003b84: 705a strb r2, [r3, #1] 8003b86: e00f b.n 8003ba8 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003b88: 78fb ldrb r3, [r7, #3] 8003b8a: f003 020f and.w r2, r3, #15 8003b8e: 4613 mov r3, r2 8003b90: 00db lsls r3, r3, #3 8003b92: 4413 add r3, r2 8003b94: 009b lsls r3, r3, #2 8003b96: f503 7314 add.w r3, r3, #592 @ 0x250 8003b9a: 687a ldr r2, [r7, #4] 8003b9c: 4413 add r3, r2 8003b9e: 3304 adds r3, #4 8003ba0: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003ba2: 68fb ldr r3, [r7, #12] 8003ba4: 2200 movs r2, #0 8003ba6: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8003ba8: 68fb ldr r3, [r7, #12] 8003baa: 2200 movs r2, #0 8003bac: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003bae: 78fb ldrb r3, [r7, #3] 8003bb0: f003 030f and.w r3, r3, #15 8003bb4: b2da uxtb r2, r3 8003bb6: 68fb ldr r3, [r7, #12] 8003bb8: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003bba: 687b ldr r3, [r7, #4] 8003bbc: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003bc0: 2b01 cmp r3, #1 8003bc2: d101 bne.n 8003bc8 8003bc4: 2302 movs r3, #2 8003bc6: e00e b.n 8003be6 8003bc8: 687b ldr r3, [r7, #4] 8003bca: 2201 movs r2, #1 8003bcc: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPClearStall(hpcd->Instance, ep); 8003bd0: 687b ldr r3, [r7, #4] 8003bd2: 681b ldr r3, [r3, #0] 8003bd4: 68f9 ldr r1, [r7, #12] 8003bd6: 4618 mov r0, r3 8003bd8: f004 fac2 bl 8008160 __HAL_UNLOCK(hpcd); 8003bdc: 687b ldr r3, [r7, #4] 8003bde: 2200 movs r2, #0 8003be0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003be4: 2300 movs r3, #0 } 8003be6: 4618 mov r0, r3 8003be8: 3710 adds r7, #16 8003bea: 46bd mov sp, r7 8003bec: bd80 pop {r7, pc} 08003bee : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003bee: b580 push {r7, lr} 8003bf0: b084 sub sp, #16 8003bf2: af00 add r7, sp, #0 8003bf4: 6078 str r0, [r7, #4] 8003bf6: 460b mov r3, r1 8003bf8: 70fb strb r3, [r7, #3] HAL_StatusTypeDef ret; PCD_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) 8003bfa: f997 3003 ldrsb.w r3, [r7, #3] 8003bfe: 2b00 cmp r3, #0 8003c00: da0c bge.n 8003c1c { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003c02: 78fb ldrb r3, [r7, #3] 8003c04: f003 020f and.w r2, r3, #15 8003c08: 4613 mov r3, r2 8003c0a: 00db lsls r3, r3, #3 8003c0c: 4413 add r3, r2 8003c0e: 009b lsls r3, r3, #2 8003c10: 3310 adds r3, #16 8003c12: 687a ldr r2, [r7, #4] 8003c14: 4413 add r3, r2 8003c16: 3304 adds r3, #4 8003c18: 60fb str r3, [r7, #12] 8003c1a: e00c b.n 8003c36 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003c1c: 78fb ldrb r3, [r7, #3] 8003c1e: f003 020f and.w r2, r3, #15 8003c22: 4613 mov r3, r2 8003c24: 00db lsls r3, r3, #3 8003c26: 4413 add r3, r2 8003c28: 009b lsls r3, r3, #2 8003c2a: f503 7314 add.w r3, r3, #592 @ 0x250 8003c2e: 687a ldr r2, [r7, #4] 8003c30: 4413 add r3, r2 8003c32: 3304 adds r3, #4 8003c34: 60fb str r3, [r7, #12] } /* Stop Xfer */ ret = USB_EPStopXfer(hpcd->Instance, ep); 8003c36: 687b ldr r3, [r7, #4] 8003c38: 681b ldr r3, [r3, #0] 8003c3a: 68f9 ldr r1, [r7, #12] 8003c3c: 4618 mov r0, r3 8003c3e: f004 f8e1 bl 8007e04 8003c42: 4603 mov r3, r0 8003c44: 72fb strb r3, [r7, #11] return ret; 8003c46: 7afb ldrb r3, [r7, #11] } 8003c48: 4618 mov r0, r3 8003c4a: 3710 adds r7, #16 8003c4c: 46bd mov sp, r7 8003c4e: bd80 pop {r7, pc} 08003c50 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003c50: b580 push {r7, lr} 8003c52: b08a sub sp, #40 @ 0x28 8003c54: af02 add r7, sp, #8 8003c56: 6078 str r0, [r7, #4] 8003c58: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003c5a: 687b ldr r3, [r7, #4] 8003c5c: 681b ldr r3, [r3, #0] 8003c5e: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003c60: 697b ldr r3, [r7, #20] 8003c62: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8003c64: 683a ldr r2, [r7, #0] 8003c66: 4613 mov r3, r2 8003c68: 00db lsls r3, r3, #3 8003c6a: 4413 add r3, r2 8003c6c: 009b lsls r3, r3, #2 8003c6e: 3310 adds r3, #16 8003c70: 687a ldr r2, [r7, #4] 8003c72: 4413 add r3, r2 8003c74: 3304 adds r3, #4 8003c76: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 8003c78: 68fb ldr r3, [r7, #12] 8003c7a: 695a ldr r2, [r3, #20] 8003c7c: 68fb ldr r3, [r7, #12] 8003c7e: 691b ldr r3, [r3, #16] 8003c80: 429a cmp r2, r3 8003c82: d901 bls.n 8003c88 { return HAL_ERROR; 8003c84: 2301 movs r3, #1 8003c86: e06b b.n 8003d60 } len = ep->xfer_len - ep->xfer_count; 8003c88: 68fb ldr r3, [r7, #12] 8003c8a: 691a ldr r2, [r3, #16] 8003c8c: 68fb ldr r3, [r7, #12] 8003c8e: 695b ldr r3, [r3, #20] 8003c90: 1ad3 subs r3, r2, r3 8003c92: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003c94: 68fb ldr r3, [r7, #12] 8003c96: 689b ldr r3, [r3, #8] 8003c98: 69fa ldr r2, [r7, #28] 8003c9a: 429a cmp r2, r3 8003c9c: d902 bls.n 8003ca4 { len = ep->maxpacket; 8003c9e: 68fb ldr r3, [r7, #12] 8003ca0: 689b ldr r3, [r3, #8] 8003ca2: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003ca4: 69fb ldr r3, [r7, #28] 8003ca6: 3303 adds r3, #3 8003ca8: 089b lsrs r3, r3, #2 8003caa: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003cac: e02a b.n 8003d04 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 8003cae: 68fb ldr r3, [r7, #12] 8003cb0: 691a ldr r2, [r3, #16] 8003cb2: 68fb ldr r3, [r7, #12] 8003cb4: 695b ldr r3, [r3, #20] 8003cb6: 1ad3 subs r3, r2, r3 8003cb8: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003cba: 68fb ldr r3, [r7, #12] 8003cbc: 689b ldr r3, [r3, #8] 8003cbe: 69fa ldr r2, [r7, #28] 8003cc0: 429a cmp r2, r3 8003cc2: d902 bls.n 8003cca { len = ep->maxpacket; 8003cc4: 68fb ldr r3, [r7, #12] 8003cc6: 689b ldr r3, [r3, #8] 8003cc8: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003cca: 69fb ldr r3, [r7, #28] 8003ccc: 3303 adds r3, #3 8003cce: 089b lsrs r3, r3, #2 8003cd0: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003cd2: 68fb ldr r3, [r7, #12] 8003cd4: 68d9 ldr r1, [r3, #12] 8003cd6: 683b ldr r3, [r7, #0] 8003cd8: b2da uxtb r2, r3 8003cda: 69fb ldr r3, [r7, #28] 8003cdc: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8003cde: 687b ldr r3, [r7, #4] 8003ce0: 799b ldrb r3, [r3, #6] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003ce2: 9300 str r3, [sp, #0] 8003ce4: 4603 mov r3, r0 8003ce6: 6978 ldr r0, [r7, #20] 8003ce8: f004 f936 bl 8007f58 ep->xfer_buff += len; 8003cec: 68fb ldr r3, [r7, #12] 8003cee: 68da ldr r2, [r3, #12] 8003cf0: 69fb ldr r3, [r7, #28] 8003cf2: 441a add r2, r3 8003cf4: 68fb ldr r3, [r7, #12] 8003cf6: 60da str r2, [r3, #12] ep->xfer_count += len; 8003cf8: 68fb ldr r3, [r7, #12] 8003cfa: 695a ldr r2, [r3, #20] 8003cfc: 69fb ldr r3, [r7, #28] 8003cfe: 441a add r2, r3 8003d00: 68fb ldr r3, [r7, #12] 8003d02: 615a str r2, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003d04: 683b ldr r3, [r7, #0] 8003d06: 015a lsls r2, r3, #5 8003d08: 693b ldr r3, [r7, #16] 8003d0a: 4413 add r3, r2 8003d0c: f503 6310 add.w r3, r3, #2304 @ 0x900 8003d10: 699b ldr r3, [r3, #24] 8003d12: b29b uxth r3, r3 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003d14: 69ba ldr r2, [r7, #24] 8003d16: 429a cmp r2, r3 8003d18: d809 bhi.n 8003d2e 8003d1a: 68fb ldr r3, [r7, #12] 8003d1c: 695a ldr r2, [r3, #20] 8003d1e: 68fb ldr r3, [r7, #12] 8003d20: 691b ldr r3, [r3, #16] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003d22: 429a cmp r2, r3 8003d24: d203 bcs.n 8003d2e (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003d26: 68fb ldr r3, [r7, #12] 8003d28: 691b ldr r3, [r3, #16] 8003d2a: 2b00 cmp r3, #0 8003d2c: d1bf bne.n 8003cae } if (ep->xfer_len <= ep->xfer_count) 8003d2e: 68fb ldr r3, [r7, #12] 8003d30: 691a ldr r2, [r3, #16] 8003d32: 68fb ldr r3, [r7, #12] 8003d34: 695b ldr r3, [r3, #20] 8003d36: 429a cmp r2, r3 8003d38: d811 bhi.n 8003d5e { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8003d3a: 683b ldr r3, [r7, #0] 8003d3c: f003 030f and.w r3, r3, #15 8003d40: 2201 movs r2, #1 8003d42: fa02 f303 lsl.w r3, r2, r3 8003d46: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003d48: 693b ldr r3, [r7, #16] 8003d4a: f503 6300 add.w r3, r3, #2048 @ 0x800 8003d4e: 6b5a ldr r2, [r3, #52] @ 0x34 8003d50: 68bb ldr r3, [r7, #8] 8003d52: 43db mvns r3, r3 8003d54: 6939 ldr r1, [r7, #16] 8003d56: f501 6100 add.w r1, r1, #2048 @ 0x800 8003d5a: 4013 ands r3, r2 8003d5c: 634b str r3, [r1, #52] @ 0x34 } return HAL_OK; 8003d5e: 2300 movs r3, #0 } 8003d60: 4618 mov r0, r3 8003d62: 3720 adds r7, #32 8003d64: 46bd mov sp, r7 8003d66: bd80 pop {r7, pc} 08003d68 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003d68: b580 push {r7, lr} 8003d6a: b088 sub sp, #32 8003d6c: af00 add r7, sp, #0 8003d6e: 6078 str r0, [r7, #4] 8003d70: 6039 str r1, [r7, #0] USB_OTG_EPTypeDef *ep; const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003d72: 687b ldr r3, [r7, #4] 8003d74: 681b ldr r3, [r3, #0] 8003d76: 61fb str r3, [r7, #28] uint32_t USBx_BASE = (uint32_t)USBx; 8003d78: 69fb ldr r3, [r7, #28] 8003d7a: 61bb str r3, [r7, #24] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003d7c: 69fb ldr r3, [r7, #28] 8003d7e: 333c adds r3, #60 @ 0x3c 8003d80: 3304 adds r3, #4 8003d82: 681b ldr r3, [r3, #0] 8003d84: 617b str r3, [r7, #20] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003d86: 683b ldr r3, [r7, #0] 8003d88: 015a lsls r2, r3, #5 8003d8a: 69bb ldr r3, [r7, #24] 8003d8c: 4413 add r3, r2 8003d8e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003d92: 689b ldr r3, [r3, #8] 8003d94: 613b str r3, [r7, #16] if (hpcd->Init.dma_enable == 1U) 8003d96: 687b ldr r3, [r7, #4] 8003d98: 799b ldrb r3, [r3, #6] 8003d9a: 2b01 cmp r3, #1 8003d9c: d17b bne.n 8003e96 { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8003d9e: 693b ldr r3, [r7, #16] 8003da0: f003 0308 and.w r3, r3, #8 8003da4: 2b00 cmp r3, #0 8003da6: d015 beq.n 8003dd4 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003da8: 697b ldr r3, [r7, #20] 8003daa: 4a61 ldr r2, [pc, #388] @ (8003f30 ) 8003dac: 4293 cmp r3, r2 8003dae: f240 80b9 bls.w 8003f24 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003db2: 693b ldr r3, [r7, #16] 8003db4: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003db8: 2b00 cmp r3, #0 8003dba: f000 80b3 beq.w 8003f24 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003dbe: 683b ldr r3, [r7, #0] 8003dc0: 015a lsls r2, r3, #5 8003dc2: 69bb ldr r3, [r7, #24] 8003dc4: 4413 add r3, r2 8003dc6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003dca: 461a mov r2, r3 8003dcc: f44f 4300 mov.w r3, #32768 @ 0x8000 8003dd0: 6093 str r3, [r2, #8] 8003dd2: e0a7 b.n 8003f24 } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8003dd4: 693b ldr r3, [r7, #16] 8003dd6: f003 0320 and.w r3, r3, #32 8003dda: 2b00 cmp r3, #0 8003ddc: d009 beq.n 8003df2 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003dde: 683b ldr r3, [r7, #0] 8003de0: 015a lsls r2, r3, #5 8003de2: 69bb ldr r3, [r7, #24] 8003de4: 4413 add r3, r2 8003de6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003dea: 461a mov r2, r3 8003dec: 2320 movs r3, #32 8003dee: 6093 str r3, [r2, #8] 8003df0: e098 b.n 8003f24 } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8003df2: 693b ldr r3, [r7, #16] 8003df4: f003 0328 and.w r3, r3, #40 @ 0x28 8003df8: 2b00 cmp r3, #0 8003dfa: f040 8093 bne.w 8003f24 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003dfe: 697b ldr r3, [r7, #20] 8003e00: 4a4b ldr r2, [pc, #300] @ (8003f30 ) 8003e02: 4293 cmp r3, r2 8003e04: d90f bls.n 8003e26 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003e06: 693b ldr r3, [r7, #16] 8003e08: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003e0c: 2b00 cmp r3, #0 8003e0e: d00a beq.n 8003e26 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003e10: 683b ldr r3, [r7, #0] 8003e12: 015a lsls r2, r3, #5 8003e14: 69bb ldr r3, [r7, #24] 8003e16: 4413 add r3, r2 8003e18: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e1c: 461a mov r2, r3 8003e1e: f44f 4300 mov.w r3, #32768 @ 0x8000 8003e22: 6093 str r3, [r2, #8] 8003e24: e07e b.n 8003f24 } else { ep = &hpcd->OUT_ep[epnum]; 8003e26: 683a ldr r2, [r7, #0] 8003e28: 4613 mov r3, r2 8003e2a: 00db lsls r3, r3, #3 8003e2c: 4413 add r3, r2 8003e2e: 009b lsls r3, r3, #2 8003e30: f503 7314 add.w r3, r3, #592 @ 0x250 8003e34: 687a ldr r2, [r7, #4] 8003e36: 4413 add r3, r2 8003e38: 3304 adds r3, #4 8003e3a: 60fb str r3, [r7, #12] /* out data packet received over EP */ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8003e3c: 68fb ldr r3, [r7, #12] 8003e3e: 6a1a ldr r2, [r3, #32] 8003e40: 683b ldr r3, [r7, #0] 8003e42: 0159 lsls r1, r3, #5 8003e44: 69bb ldr r3, [r7, #24] 8003e46: 440b add r3, r1 8003e48: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e4c: 691b ldr r3, [r3, #16] 8003e4e: f3c3 0312 ubfx r3, r3, #0, #19 8003e52: 1ad2 subs r2, r2, r3 8003e54: 68fb ldr r3, [r7, #12] 8003e56: 615a str r2, [r3, #20] if (epnum == 0U) 8003e58: 683b ldr r3, [r7, #0] 8003e5a: 2b00 cmp r3, #0 8003e5c: d114 bne.n 8003e88 { if (ep->xfer_len == 0U) 8003e5e: 68fb ldr r3, [r7, #12] 8003e60: 691b ldr r3, [r3, #16] 8003e62: 2b00 cmp r3, #0 8003e64: d109 bne.n 8003e7a { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003e66: 687b ldr r3, [r7, #4] 8003e68: 6818 ldr r0, [r3, #0] 8003e6a: 687b ldr r3, [r7, #4] 8003e6c: f203 439c addw r3, r3, #1180 @ 0x49c 8003e70: 461a mov r2, r3 8003e72: 2101 movs r1, #1 8003e74: f004 fb06 bl 8008484 8003e78: e006 b.n 8003e88 } else { ep->xfer_buff += ep->xfer_count; 8003e7a: 68fb ldr r3, [r7, #12] 8003e7c: 68da ldr r2, [r3, #12] 8003e7e: 68fb ldr r3, [r7, #12] 8003e80: 695b ldr r3, [r3, #20] 8003e82: 441a add r2, r3 8003e84: 68fb ldr r3, [r7, #12] 8003e86: 60da str r2, [r3, #12] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003e88: 683b ldr r3, [r7, #0] 8003e8a: b2db uxtb r3, r3 8003e8c: 4619 mov r1, r3 8003e8e: 6878 ldr r0, [r7, #4] 8003e90: f006 fad4 bl 800a43c 8003e94: e046 b.n 8003f24 /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8003e96: 697b ldr r3, [r7, #20] 8003e98: 4a26 ldr r2, [pc, #152] @ (8003f34 ) 8003e9a: 4293 cmp r3, r2 8003e9c: d124 bne.n 8003ee8 { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8003e9e: 693b ldr r3, [r7, #16] 8003ea0: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003ea4: 2b00 cmp r3, #0 8003ea6: d00a beq.n 8003ebe { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003ea8: 683b ldr r3, [r7, #0] 8003eaa: 015a lsls r2, r3, #5 8003eac: 69bb ldr r3, [r7, #24] 8003eae: 4413 add r3, r2 8003eb0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003eb4: 461a mov r2, r3 8003eb6: f44f 4300 mov.w r3, #32768 @ 0x8000 8003eba: 6093 str r3, [r2, #8] 8003ebc: e032 b.n 8003f24 } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8003ebe: 693b ldr r3, [r7, #16] 8003ec0: f003 0320 and.w r3, r3, #32 8003ec4: 2b00 cmp r3, #0 8003ec6: d008 beq.n 8003eda { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003ec8: 683b ldr r3, [r7, #0] 8003eca: 015a lsls r2, r3, #5 8003ecc: 69bb ldr r3, [r7, #24] 8003ece: 4413 add r3, r2 8003ed0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003ed4: 461a mov r2, r3 8003ed6: 2320 movs r3, #32 8003ed8: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003eda: 683b ldr r3, [r7, #0] 8003edc: b2db uxtb r3, r3 8003ede: 4619 mov r1, r3 8003ee0: 6878 ldr r0, [r7, #4] 8003ee2: f006 faab bl 800a43c 8003ee6: e01d b.n 8003f24 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8003ee8: 683b ldr r3, [r7, #0] 8003eea: 2b00 cmp r3, #0 8003eec: d114 bne.n 8003f18 8003eee: 6879 ldr r1, [r7, #4] 8003ef0: 683a ldr r2, [r7, #0] 8003ef2: 4613 mov r3, r2 8003ef4: 00db lsls r3, r3, #3 8003ef6: 4413 add r3, r2 8003ef8: 009b lsls r3, r3, #2 8003efa: 440b add r3, r1 8003efc: f503 7319 add.w r3, r3, #612 @ 0x264 8003f00: 681b ldr r3, [r3, #0] 8003f02: 2b00 cmp r3, #0 8003f04: d108 bne.n 8003f18 { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 8003f06: 687b ldr r3, [r7, #4] 8003f08: 6818 ldr r0, [r3, #0] 8003f0a: 687b ldr r3, [r7, #4] 8003f0c: f203 439c addw r3, r3, #1180 @ 0x49c 8003f10: 461a mov r2, r3 8003f12: 2100 movs r1, #0 8003f14: f004 fab6 bl 8008484 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003f18: 683b ldr r3, [r7, #0] 8003f1a: b2db uxtb r3, r3 8003f1c: 4619 mov r1, r3 8003f1e: 6878 ldr r0, [r7, #4] 8003f20: f006 fa8c bl 800a43c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8003f24: 2300 movs r3, #0 } 8003f26: 4618 mov r0, r3 8003f28: 3720 adds r7, #32 8003f2a: 46bd mov sp, r7 8003f2c: bd80 pop {r7, pc} 8003f2e: bf00 nop 8003f30: 4f54300a .word 0x4f54300a 8003f34: 4f54310a .word 0x4f54310a 08003f38 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003f38: b580 push {r7, lr} 8003f3a: b086 sub sp, #24 8003f3c: af00 add r7, sp, #0 8003f3e: 6078 str r0, [r7, #4] 8003f40: 6039 str r1, [r7, #0] const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003f42: 687b ldr r3, [r7, #4] 8003f44: 681b ldr r3, [r3, #0] 8003f46: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003f48: 697b ldr r3, [r7, #20] 8003f4a: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003f4c: 697b ldr r3, [r7, #20] 8003f4e: 333c adds r3, #60 @ 0x3c 8003f50: 3304 adds r3, #4 8003f52: 681b ldr r3, [r3, #0] 8003f54: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003f56: 683b ldr r3, [r7, #0] 8003f58: 015a lsls r2, r3, #5 8003f5a: 693b ldr r3, [r7, #16] 8003f5c: 4413 add r3, r2 8003f5e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003f62: 689b ldr r3, [r3, #8] 8003f64: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003f66: 68fb ldr r3, [r7, #12] 8003f68: 4a15 ldr r2, [pc, #84] @ (8003fc0 ) 8003f6a: 4293 cmp r3, r2 8003f6c: d90e bls.n 8003f8c ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003f6e: 68bb ldr r3, [r7, #8] 8003f70: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003f74: 2b00 cmp r3, #0 8003f76: d009 beq.n 8003f8c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003f78: 683b ldr r3, [r7, #0] 8003f7a: 015a lsls r2, r3, #5 8003f7c: 693b ldr r3, [r7, #16] 8003f7e: 4413 add r3, r2 8003f80: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003f84: 461a mov r2, r3 8003f86: f44f 4300 mov.w r3, #32768 @ 0x8000 8003f8a: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 8003f8c: 6878 ldr r0, [r7, #4] 8003f8e: f006 fa43 bl 800a418 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 8003f92: 68fb ldr r3, [r7, #12] 8003f94: 4a0a ldr r2, [pc, #40] @ (8003fc0 ) 8003f96: 4293 cmp r3, r2 8003f98: d90c bls.n 8003fb4 8003f9a: 687b ldr r3, [r7, #4] 8003f9c: 799b ldrb r3, [r3, #6] 8003f9e: 2b01 cmp r3, #1 8003fa0: d108 bne.n 8003fb4 { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003fa2: 687b ldr r3, [r7, #4] 8003fa4: 6818 ldr r0, [r3, #0] 8003fa6: 687b ldr r3, [r7, #4] 8003fa8: f203 439c addw r3, r3, #1180 @ 0x49c 8003fac: 461a mov r2, r3 8003fae: 2101 movs r1, #1 8003fb0: f004 fa68 bl 8008484 } return HAL_OK; 8003fb4: 2300 movs r3, #0 } 8003fb6: 4618 mov r0, r3 8003fb8: 3718 adds r7, #24 8003fba: 46bd mov sp, r7 8003fbc: bd80 pop {r7, pc} 8003fbe: bf00 nop 8003fc0: 4f54300a .word 0x4f54300a 08003fc4 : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 8003fc4: b480 push {r7} 8003fc6: b085 sub sp, #20 8003fc8: af00 add r7, sp, #0 8003fca: 6078 str r0, [r7, #4] 8003fcc: 460b mov r3, r1 8003fce: 70fb strb r3, [r7, #3] 8003fd0: 4613 mov r3, r2 8003fd2: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 8003fd4: 687b ldr r3, [r7, #4] 8003fd6: 681b ldr r3, [r3, #0] 8003fd8: 6a5b ldr r3, [r3, #36] @ 0x24 8003fda: 60bb str r3, [r7, #8] if (fifo == 0U) 8003fdc: 78fb ldrb r3, [r7, #3] 8003fde: 2b00 cmp r3, #0 8003fe0: d107 bne.n 8003ff2 { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8003fe2: 883b ldrh r3, [r7, #0] 8003fe4: 0419 lsls r1, r3, #16 8003fe6: 687b ldr r3, [r7, #4] 8003fe8: 681b ldr r3, [r3, #0] 8003fea: 68ba ldr r2, [r7, #8] 8003fec: 430a orrs r2, r1 8003fee: 629a str r2, [r3, #40] @ 0x28 8003ff0: e028 b.n 8004044 } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 8003ff2: 687b ldr r3, [r7, #4] 8003ff4: 681b ldr r3, [r3, #0] 8003ff6: 6a9b ldr r3, [r3, #40] @ 0x28 8003ff8: 0c1b lsrs r3, r3, #16 8003ffa: 68ba ldr r2, [r7, #8] 8003ffc: 4413 add r3, r2 8003ffe: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8004000: 2300 movs r3, #0 8004002: 73fb strb r3, [r7, #15] 8004004: e00d b.n 8004022 { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 8004006: 687b ldr r3, [r7, #4] 8004008: 681a ldr r2, [r3, #0] 800400a: 7bfb ldrb r3, [r7, #15] 800400c: 3340 adds r3, #64 @ 0x40 800400e: 009b lsls r3, r3, #2 8004010: 4413 add r3, r2 8004012: 685b ldr r3, [r3, #4] 8004014: 0c1b lsrs r3, r3, #16 8004016: 68ba ldr r2, [r7, #8] 8004018: 4413 add r3, r2 800401a: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 800401c: 7bfb ldrb r3, [r7, #15] 800401e: 3301 adds r3, #1 8004020: 73fb strb r3, [r7, #15] 8004022: 7bfa ldrb r2, [r7, #15] 8004024: 78fb ldrb r3, [r7, #3] 8004026: 3b01 subs r3, #1 8004028: 429a cmp r2, r3 800402a: d3ec bcc.n 8004006 } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 800402c: 883b ldrh r3, [r7, #0] 800402e: 0418 lsls r0, r3, #16 8004030: 687b ldr r3, [r7, #4] 8004032: 6819 ldr r1, [r3, #0] 8004034: 78fb ldrb r3, [r7, #3] 8004036: 3b01 subs r3, #1 8004038: 68ba ldr r2, [r7, #8] 800403a: 4302 orrs r2, r0 800403c: 3340 adds r3, #64 @ 0x40 800403e: 009b lsls r3, r3, #2 8004040: 440b add r3, r1 8004042: 605a str r2, [r3, #4] } return HAL_OK; 8004044: 2300 movs r3, #0 } 8004046: 4618 mov r0, r3 8004048: 3714 adds r7, #20 800404a: 46bd mov sp, r7 800404c: f85d 7b04 ldr.w r7, [sp], #4 8004050: 4770 bx lr 08004052 : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8004052: b480 push {r7} 8004054: b083 sub sp, #12 8004056: af00 add r7, sp, #0 8004058: 6078 str r0, [r7, #4] 800405a: 460b mov r3, r1 800405c: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 800405e: 687b ldr r3, [r7, #4] 8004060: 681b ldr r3, [r3, #0] 8004062: 887a ldrh r2, [r7, #2] 8004064: 625a str r2, [r3, #36] @ 0x24 return HAL_OK; 8004066: 2300 movs r3, #0 } 8004068: 4618 mov r0, r3 800406a: 370c adds r7, #12 800406c: 46bd mov sp, r7 800406e: f85d 7b04 ldr.w r7, [sp], #4 8004072: 4770 bx lr 08004074 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 8004074: b480 push {r7} 8004076: b085 sub sp, #20 8004078: af00 add r7, sp, #0 800407a: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 800407c: 687b ldr r3, [r7, #4] 800407e: 681b ldr r3, [r3, #0] 8004080: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 8004082: 687b ldr r3, [r7, #4] 8004084: 2201 movs r2, #1 8004086: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 800408a: 687b ldr r3, [r7, #4] 800408c: 2200 movs r2, #0 800408e: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 8004092: 68fb ldr r3, [r7, #12] 8004094: 699b ldr r3, [r3, #24] 8004096: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 800409a: 68fb ldr r3, [r7, #12] 800409c: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 800409e: 68fb ldr r3, [r7, #12] 80040a0: 6d5b ldr r3, [r3, #84] @ 0x54 80040a2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80040a6: f043 0303 orr.w r3, r3, #3 80040aa: 68fa ldr r2, [r7, #12] 80040ac: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 80040ae: 2300 movs r3, #0 } 80040b0: 4618 mov r0, r3 80040b2: 3714 adds r7, #20 80040b4: 46bd mov sp, r7 80040b6: f85d 7b04 ldr.w r7, [sp], #4 80040ba: 4770 bx lr 080040bc : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80040bc: b580 push {r7, lr} 80040be: b084 sub sp, #16 80040c0: af00 add r7, sp, #0 80040c2: 6078 str r0, [r7, #4] 80040c4: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80040c6: 687b ldr r3, [r7, #4] 80040c8: 2b00 cmp r3, #0 80040ca: d101 bne.n 80040d0 { return HAL_ERROR; 80040cc: 2301 movs r3, #1 80040ce: e0cc b.n 800426a /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80040d0: 4b68 ldr r3, [pc, #416] @ (8004274 ) 80040d2: 681b ldr r3, [r3, #0] 80040d4: f003 030f and.w r3, r3, #15 80040d8: 683a ldr r2, [r7, #0] 80040da: 429a cmp r2, r3 80040dc: d90c bls.n 80040f8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80040de: 4b65 ldr r3, [pc, #404] @ (8004274 ) 80040e0: 683a ldr r2, [r7, #0] 80040e2: b2d2 uxtb r2, r2 80040e4: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80040e6: 4b63 ldr r3, [pc, #396] @ (8004274 ) 80040e8: 681b ldr r3, [r3, #0] 80040ea: f003 030f and.w r3, r3, #15 80040ee: 683a ldr r2, [r7, #0] 80040f0: 429a cmp r2, r3 80040f2: d001 beq.n 80040f8 { return HAL_ERROR; 80040f4: 2301 movs r3, #1 80040f6: e0b8 b.n 800426a } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80040f8: 687b ldr r3, [r7, #4] 80040fa: 681b ldr r3, [r3, #0] 80040fc: f003 0302 and.w r3, r3, #2 8004100: 2b00 cmp r3, #0 8004102: d020 beq.n 8004146 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004104: 687b ldr r3, [r7, #4] 8004106: 681b ldr r3, [r3, #0] 8004108: f003 0304 and.w r3, r3, #4 800410c: 2b00 cmp r3, #0 800410e: d005 beq.n 800411c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004110: 4b59 ldr r3, [pc, #356] @ (8004278 ) 8004112: 689b ldr r3, [r3, #8] 8004114: 4a58 ldr r2, [pc, #352] @ (8004278 ) 8004116: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 800411a: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800411c: 687b ldr r3, [r7, #4] 800411e: 681b ldr r3, [r3, #0] 8004120: f003 0308 and.w r3, r3, #8 8004124: 2b00 cmp r3, #0 8004126: d005 beq.n 8004134 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8004128: 4b53 ldr r3, [pc, #332] @ (8004278 ) 800412a: 689b ldr r3, [r3, #8] 800412c: 4a52 ldr r2, [pc, #328] @ (8004278 ) 800412e: f443 4360 orr.w r3, r3, #57344 @ 0xe000 8004132: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004134: 4b50 ldr r3, [pc, #320] @ (8004278 ) 8004136: 689b ldr r3, [r3, #8] 8004138: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800413c: 687b ldr r3, [r7, #4] 800413e: 689b ldr r3, [r3, #8] 8004140: 494d ldr r1, [pc, #308] @ (8004278 ) 8004142: 4313 orrs r3, r2 8004144: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8004146: 687b ldr r3, [r7, #4] 8004148: 681b ldr r3, [r3, #0] 800414a: f003 0301 and.w r3, r3, #1 800414e: 2b00 cmp r3, #0 8004150: d044 beq.n 80041dc { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004152: 687b ldr r3, [r7, #4] 8004154: 685b ldr r3, [r3, #4] 8004156: 2b01 cmp r3, #1 8004158: d107 bne.n 800416a { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800415a: 4b47 ldr r3, [pc, #284] @ (8004278 ) 800415c: 681b ldr r3, [r3, #0] 800415e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004162: 2b00 cmp r3, #0 8004164: d119 bne.n 800419a { return HAL_ERROR; 8004166: 2301 movs r3, #1 8004168: e07f b.n 800426a } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 800416a: 687b ldr r3, [r7, #4] 800416c: 685b ldr r3, [r3, #4] 800416e: 2b02 cmp r3, #2 8004170: d003 beq.n 800417a (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8004172: 687b ldr r3, [r7, #4] 8004174: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8004176: 2b03 cmp r3, #3 8004178: d107 bne.n 800418a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800417a: 4b3f ldr r3, [pc, #252] @ (8004278 ) 800417c: 681b ldr r3, [r3, #0] 800417e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004182: 2b00 cmp r3, #0 8004184: d109 bne.n 800419a { return HAL_ERROR; 8004186: 2301 movs r3, #1 8004188: e06f b.n 800426a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800418a: 4b3b ldr r3, [pc, #236] @ (8004278 ) 800418c: 681b ldr r3, [r3, #0] 800418e: f003 0302 and.w r3, r3, #2 8004192: 2b00 cmp r3, #0 8004194: d101 bne.n 800419a { return HAL_ERROR; 8004196: 2301 movs r3, #1 8004198: e067 b.n 800426a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800419a: 4b37 ldr r3, [pc, #220] @ (8004278 ) 800419c: 689b ldr r3, [r3, #8] 800419e: f023 0203 bic.w r2, r3, #3 80041a2: 687b ldr r3, [r7, #4] 80041a4: 685b ldr r3, [r3, #4] 80041a6: 4934 ldr r1, [pc, #208] @ (8004278 ) 80041a8: 4313 orrs r3, r2 80041aa: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 80041ac: f7fd fcb2 bl 8001b14 80041b0: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80041b2: e00a b.n 80041ca { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80041b4: f7fd fcae bl 8001b14 80041b8: 4602 mov r2, r0 80041ba: 68fb ldr r3, [r7, #12] 80041bc: 1ad3 subs r3, r2, r3 80041be: f241 3288 movw r2, #5000 @ 0x1388 80041c2: 4293 cmp r3, r2 80041c4: d901 bls.n 80041ca { return HAL_TIMEOUT; 80041c6: 2303 movs r3, #3 80041c8: e04f b.n 800426a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80041ca: 4b2b ldr r3, [pc, #172] @ (8004278 ) 80041cc: 689b ldr r3, [r3, #8] 80041ce: f003 020c and.w r2, r3, #12 80041d2: 687b ldr r3, [r7, #4] 80041d4: 685b ldr r3, [r3, #4] 80041d6: 009b lsls r3, r3, #2 80041d8: 429a cmp r2, r3 80041da: d1eb bne.n 80041b4 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80041dc: 4b25 ldr r3, [pc, #148] @ (8004274 ) 80041de: 681b ldr r3, [r3, #0] 80041e0: f003 030f and.w r3, r3, #15 80041e4: 683a ldr r2, [r7, #0] 80041e6: 429a cmp r2, r3 80041e8: d20c bcs.n 8004204 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80041ea: 4b22 ldr r3, [pc, #136] @ (8004274 ) 80041ec: 683a ldr r2, [r7, #0] 80041ee: b2d2 uxtb r2, r2 80041f0: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80041f2: 4b20 ldr r3, [pc, #128] @ (8004274 ) 80041f4: 681b ldr r3, [r3, #0] 80041f6: f003 030f and.w r3, r3, #15 80041fa: 683a ldr r2, [r7, #0] 80041fc: 429a cmp r2, r3 80041fe: d001 beq.n 8004204 { return HAL_ERROR; 8004200: 2301 movs r3, #1 8004202: e032 b.n 800426a } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004204: 687b ldr r3, [r7, #4] 8004206: 681b ldr r3, [r3, #0] 8004208: f003 0304 and.w r3, r3, #4 800420c: 2b00 cmp r3, #0 800420e: d008 beq.n 8004222 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004210: 4b19 ldr r3, [pc, #100] @ (8004278 ) 8004212: 689b ldr r3, [r3, #8] 8004214: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 8004218: 687b ldr r3, [r7, #4] 800421a: 68db ldr r3, [r3, #12] 800421c: 4916 ldr r1, [pc, #88] @ (8004278 ) 800421e: 4313 orrs r3, r2 8004220: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004222: 687b ldr r3, [r7, #4] 8004224: 681b ldr r3, [r3, #0] 8004226: f003 0308 and.w r3, r3, #8 800422a: 2b00 cmp r3, #0 800422c: d009 beq.n 8004242 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 800422e: 4b12 ldr r3, [pc, #72] @ (8004278 ) 8004230: 689b ldr r3, [r3, #8] 8004232: f423 4260 bic.w r2, r3, #57344 @ 0xe000 8004236: 687b ldr r3, [r7, #4] 8004238: 691b ldr r3, [r3, #16] 800423a: 00db lsls r3, r3, #3 800423c: 490e ldr r1, [pc, #56] @ (8004278 ) 800423e: 4313 orrs r3, r2 8004240: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8004242: f000 fb7f bl 8004944 8004246: 4602 mov r2, r0 8004248: 4b0b ldr r3, [pc, #44] @ (8004278 ) 800424a: 689b ldr r3, [r3, #8] 800424c: 091b lsrs r3, r3, #4 800424e: f003 030f and.w r3, r3, #15 8004252: 490a ldr r1, [pc, #40] @ (800427c ) 8004254: 5ccb ldrb r3, [r1, r3] 8004256: fa22 f303 lsr.w r3, r2, r3 800425a: 4a09 ldr r2, [pc, #36] @ (8004280 ) 800425c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 800425e: 4b09 ldr r3, [pc, #36] @ (8004284 ) 8004260: 681b ldr r3, [r3, #0] 8004262: 4618 mov r0, r3 8004264: f7fd fc12 bl 8001a8c return HAL_OK; 8004268: 2300 movs r3, #0 } 800426a: 4618 mov r0, r3 800426c: 3710 adds r7, #16 800426e: 46bd mov sp, r7 8004270: bd80 pop {r7, pc} 8004272: bf00 nop 8004274: 40023c00 .word 0x40023c00 8004278: 40023800 .word 0x40023800 800427c: 0800aabc .word 0x0800aabc 8004280: 20000090 .word 0x20000090 8004284: 20000094 .word 0x20000094 08004288 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8004288: b480 push {r7} 800428a: af00 add r7, sp, #0 return SystemCoreClock; 800428c: 4b03 ldr r3, [pc, #12] @ (800429c ) 800428e: 681b ldr r3, [r3, #0] } 8004290: 4618 mov r0, r3 8004292: 46bd mov sp, r7 8004294: f85d 7b04 ldr.w r7, [sp], #4 8004298: 4770 bx lr 800429a: bf00 nop 800429c: 20000090 .word 0x20000090 080042a0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80042a0: b580 push {r7, lr} 80042a2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 80042a4: f7ff fff0 bl 8004288 80042a8: 4602 mov r2, r0 80042aa: 4b05 ldr r3, [pc, #20] @ (80042c0 ) 80042ac: 689b ldr r3, [r3, #8] 80042ae: 0a9b lsrs r3, r3, #10 80042b0: f003 0307 and.w r3, r3, #7 80042b4: 4903 ldr r1, [pc, #12] @ (80042c4 ) 80042b6: 5ccb ldrb r3, [r1, r3] 80042b8: fa22 f303 lsr.w r3, r2, r3 } 80042bc: 4618 mov r0, r3 80042be: bd80 pop {r7, pc} 80042c0: 40023800 .word 0x40023800 80042c4: 0800aacc .word 0x0800aacc 080042c8 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 80042c8: b580 push {r7, lr} 80042ca: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 80042cc: f7ff ffdc bl 8004288 80042d0: 4602 mov r2, r0 80042d2: 4b05 ldr r3, [pc, #20] @ (80042e8 ) 80042d4: 689b ldr r3, [r3, #8] 80042d6: 0b5b lsrs r3, r3, #13 80042d8: f003 0307 and.w r3, r3, #7 80042dc: 4903 ldr r1, [pc, #12] @ (80042ec ) 80042de: 5ccb ldrb r3, [r1, r3] 80042e0: fa22 f303 lsr.w r3, r2, r3 } 80042e4: 4618 mov r0, r3 80042e6: bd80 pop {r7, pc} 80042e8: 40023800 .word 0x40023800 80042ec: 0800aacc .word 0x0800aacc 080042f0 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80042f0: b580 push {r7, lr} 80042f2: b08c sub sp, #48 @ 0x30 80042f4: af00 add r7, sp, #0 80042f6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80042f8: 2300 movs r3, #0 80042fa: 627b str r3, [r7, #36] @ 0x24 uint32_t tmpreg1 = 0U; 80042fc: 2300 movs r3, #0 80042fe: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 8004300: 2300 movs r3, #0 8004302: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 8004304: 2300 movs r3, #0 8004306: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 8004308: 2300 movs r3, #0 800430a: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 800430c: 2300 movs r3, #0 800430e: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 8004310: 2300 movs r3, #0 8004312: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 8004314: 2300 movs r3, #0 8004316: 62fb str r3, [r7, #44] @ 0x2c uint32_t pllsaiused = 0U; 8004318: 2300 movs r3, #0 800431a: 62bb str r3, [r7, #40] @ 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 800431c: 687b ldr r3, [r7, #4] 800431e: 681b ldr r3, [r3, #0] 8004320: f003 0301 and.w r3, r3, #1 8004324: 2b00 cmp r3, #0 8004326: d010 beq.n 800434a { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 8004328: 4b6f ldr r3, [pc, #444] @ (80044e8 ) 800432a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800432e: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 8004332: 687b ldr r3, [r7, #4] 8004334: 6b9b ldr r3, [r3, #56] @ 0x38 8004336: 496c ldr r1, [pc, #432] @ (80044e8 ) 8004338: 4313 orrs r3, r2 800433a: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 800433e: 687b ldr r3, [r7, #4] 8004340: 6b9b ldr r3, [r3, #56] @ 0x38 8004342: 2b00 cmp r3, #0 8004344: d101 bne.n 800434a { plli2sused = 1U; 8004346: 2301 movs r3, #1 8004348: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 800434a: 687b ldr r3, [r7, #4] 800434c: 681b ldr r3, [r3, #0] 800434e: f003 0302 and.w r3, r3, #2 8004352: 2b00 cmp r3, #0 8004354: d010 beq.n 8004378 { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 8004356: 4b64 ldr r3, [pc, #400] @ (80044e8 ) 8004358: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800435c: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 8004360: 687b ldr r3, [r7, #4] 8004362: 6bdb ldr r3, [r3, #60] @ 0x3c 8004364: 4960 ldr r1, [pc, #384] @ (80044e8 ) 8004366: 4313 orrs r3, r2 8004368: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 800436c: 687b ldr r3, [r7, #4] 800436e: 6bdb ldr r3, [r3, #60] @ 0x3c 8004370: 2b00 cmp r3, #0 8004372: d101 bne.n 8004378 { plli2sused = 1U; 8004374: 2301 movs r3, #1 8004376: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 8004378: 687b ldr r3, [r7, #4] 800437a: 681b ldr r3, [r3, #0] 800437c: f003 0304 and.w r3, r3, #4 8004380: 2b00 cmp r3, #0 8004382: d017 beq.n 80043b4 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8004384: 4b58 ldr r3, [pc, #352] @ (80044e8 ) 8004386: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800438a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 800438e: 687b ldr r3, [r7, #4] 8004390: 6b1b ldr r3, [r3, #48] @ 0x30 8004392: 4955 ldr r1, [pc, #340] @ (80044e8 ) 8004394: 4313 orrs r3, r2 8004396: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 800439a: 687b ldr r3, [r7, #4] 800439c: 6b1b ldr r3, [r3, #48] @ 0x30 800439e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80043a2: d101 bne.n 80043a8 { plli2sused = 1U; 80043a4: 2301 movs r3, #1 80043a6: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 80043a8: 687b ldr r3, [r7, #4] 80043aa: 6b1b ldr r3, [r3, #48] @ 0x30 80043ac: 2b00 cmp r3, #0 80043ae: d101 bne.n 80043b4 { pllsaiused = 1U; 80043b0: 2301 movs r3, #1 80043b2: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 80043b4: 687b ldr r3, [r7, #4] 80043b6: 681b ldr r3, [r3, #0] 80043b8: f003 0308 and.w r3, r3, #8 80043bc: 2b00 cmp r3, #0 80043be: d017 beq.n 80043f0 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 80043c0: 4b49 ldr r3, [pc, #292] @ (80044e8 ) 80043c2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80043c6: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80043ca: 687b ldr r3, [r7, #4] 80043cc: 6b5b ldr r3, [r3, #52] @ 0x34 80043ce: 4946 ldr r1, [pc, #280] @ (80044e8 ) 80043d0: 4313 orrs r3, r2 80043d2: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 80043d6: 687b ldr r3, [r7, #4] 80043d8: 6b5b ldr r3, [r3, #52] @ 0x34 80043da: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80043de: d101 bne.n 80043e4 { plli2sused = 1U; 80043e0: 2301 movs r3, #1 80043e2: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 80043e4: 687b ldr r3, [r7, #4] 80043e6: 6b5b ldr r3, [r3, #52] @ 0x34 80043e8: 2b00 cmp r3, #0 80043ea: d101 bne.n 80043f0 { pllsaiused = 1U; 80043ec: 2301 movs r3, #1 80043ee: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 80043f0: 687b ldr r3, [r7, #4] 80043f2: 681b ldr r3, [r3, #0] 80043f4: f003 0320 and.w r3, r3, #32 80043f8: 2b00 cmp r3, #0 80043fa: f000 808a beq.w 8004512 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 80043fe: 2300 movs r3, #0 8004400: 60bb str r3, [r7, #8] 8004402: 4b39 ldr r3, [pc, #228] @ (80044e8 ) 8004404: 6c1b ldr r3, [r3, #64] @ 0x40 8004406: 4a38 ldr r2, [pc, #224] @ (80044e8 ) 8004408: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800440c: 6413 str r3, [r2, #64] @ 0x40 800440e: 4b36 ldr r3, [pc, #216] @ (80044e8 ) 8004410: 6c1b ldr r3, [r3, #64] @ 0x40 8004412: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004416: 60bb str r3, [r7, #8] 8004418: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 800441a: 4b34 ldr r3, [pc, #208] @ (80044ec ) 800441c: 681b ldr r3, [r3, #0] 800441e: 4a33 ldr r2, [pc, #204] @ (80044ec ) 8004420: f443 7380 orr.w r3, r3, #256 @ 0x100 8004424: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004426: f7fd fb75 bl 8001b14 800442a: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR & PWR_CR_DBP) == RESET) 800442c: e008 b.n 8004440 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800442e: f7fd fb71 bl 8001b14 8004432: 4602 mov r2, r0 8004434: 6a7b ldr r3, [r7, #36] @ 0x24 8004436: 1ad3 subs r3, r2, r3 8004438: 2b02 cmp r3, #2 800443a: d901 bls.n 8004440 { return HAL_TIMEOUT; 800443c: 2303 movs r3, #3 800443e: e278 b.n 8004932 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004440: 4b2a ldr r3, [pc, #168] @ (80044ec ) 8004442: 681b ldr r3, [r3, #0] 8004444: f403 7380 and.w r3, r3, #256 @ 0x100 8004448: 2b00 cmp r3, #0 800444a: d0f0 beq.n 800442e } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 800444c: 4b26 ldr r3, [pc, #152] @ (80044e8 ) 800444e: 6f1b ldr r3, [r3, #112] @ 0x70 8004450: f403 7340 and.w r3, r3, #768 @ 0x300 8004454: 623b str r3, [r7, #32] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8004456: 6a3b ldr r3, [r7, #32] 8004458: 2b00 cmp r3, #0 800445a: d02f beq.n 80044bc 800445c: 687b ldr r3, [r7, #4] 800445e: 6c1b ldr r3, [r3, #64] @ 0x40 8004460: f403 7340 and.w r3, r3, #768 @ 0x300 8004464: 6a3a ldr r2, [r7, #32] 8004466: 429a cmp r2, r3 8004468: d028 beq.n 80044bc { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800446a: 4b1f ldr r3, [pc, #124] @ (80044e8 ) 800446c: 6f1b ldr r3, [r3, #112] @ 0x70 800446e: f423 7340 bic.w r3, r3, #768 @ 0x300 8004472: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004474: 4b1e ldr r3, [pc, #120] @ (80044f0 ) 8004476: 2201 movs r2, #1 8004478: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 800447a: 4b1d ldr r3, [pc, #116] @ (80044f0 ) 800447c: 2200 movs r2, #0 800447e: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 8004480: 4a19 ldr r2, [pc, #100] @ (80044e8 ) 8004482: 6a3b ldr r3, [r7, #32] 8004484: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 8004486: 4b18 ldr r3, [pc, #96] @ (80044e8 ) 8004488: 6f1b ldr r3, [r3, #112] @ 0x70 800448a: f003 0301 and.w r3, r3, #1 800448e: 2b01 cmp r3, #1 8004490: d114 bne.n 80044bc { /* Get tick */ tickstart = HAL_GetTick(); 8004492: f7fd fb3f bl 8001b14 8004496: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004498: e00a b.n 80044b0 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800449a: f7fd fb3b bl 8001b14 800449e: 4602 mov r2, r0 80044a0: 6a7b ldr r3, [r7, #36] @ 0x24 80044a2: 1ad3 subs r3, r2, r3 80044a4: f241 3288 movw r2, #5000 @ 0x1388 80044a8: 4293 cmp r3, r2 80044aa: d901 bls.n 80044b0 { return HAL_TIMEOUT; 80044ac: 2303 movs r3, #3 80044ae: e240 b.n 8004932 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80044b0: 4b0d ldr r3, [pc, #52] @ (80044e8 ) 80044b2: 6f1b ldr r3, [r3, #112] @ 0x70 80044b4: f003 0302 and.w r3, r3, #2 80044b8: 2b00 cmp r3, #0 80044ba: d0ee beq.n 800449a } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80044bc: 687b ldr r3, [r7, #4] 80044be: 6c1b ldr r3, [r3, #64] @ 0x40 80044c0: f403 7340 and.w r3, r3, #768 @ 0x300 80044c4: f5b3 7f40 cmp.w r3, #768 @ 0x300 80044c8: d114 bne.n 80044f4 80044ca: 4b07 ldr r3, [pc, #28] @ (80044e8 ) 80044cc: 689b ldr r3, [r3, #8] 80044ce: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 80044d2: 687b ldr r3, [r7, #4] 80044d4: 6c1b ldr r3, [r3, #64] @ 0x40 80044d6: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 80044da: f423 7340 bic.w r3, r3, #768 @ 0x300 80044de: 4902 ldr r1, [pc, #8] @ (80044e8 ) 80044e0: 4313 orrs r3, r2 80044e2: 608b str r3, [r1, #8] 80044e4: e00c b.n 8004500 80044e6: bf00 nop 80044e8: 40023800 .word 0x40023800 80044ec: 40007000 .word 0x40007000 80044f0: 42470e40 .word 0x42470e40 80044f4: 4b4a ldr r3, [pc, #296] @ (8004620 ) 80044f6: 689b ldr r3, [r3, #8] 80044f8: 4a49 ldr r2, [pc, #292] @ (8004620 ) 80044fa: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 80044fe: 6093 str r3, [r2, #8] 8004500: 4b47 ldr r3, [pc, #284] @ (8004620 ) 8004502: 6f1a ldr r2, [r3, #112] @ 0x70 8004504: 687b ldr r3, [r7, #4] 8004506: 6c1b ldr r3, [r3, #64] @ 0x40 8004508: f3c3 030b ubfx r3, r3, #0, #12 800450c: 4944 ldr r1, [pc, #272] @ (8004620 ) 800450e: 4313 orrs r3, r2 8004510: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 8004512: 687b ldr r3, [r7, #4] 8004514: 681b ldr r3, [r3, #0] 8004516: f003 0310 and.w r3, r3, #16 800451a: 2b00 cmp r3, #0 800451c: d004 beq.n 8004528 { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800451e: 687b ldr r3, [r7, #4] 8004520: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 8004524: 4b3f ldr r3, [pc, #252] @ (8004624 ) 8004526: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 8004528: 687b ldr r3, [r7, #4] 800452a: 681b ldr r3, [r3, #0] 800452c: f003 0380 and.w r3, r3, #128 @ 0x80 8004530: 2b00 cmp r3, #0 8004532: d00a beq.n 800454a { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 8004534: 4b3a ldr r3, [pc, #232] @ (8004620 ) 8004536: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800453a: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 800453e: 687b ldr r3, [r7, #4] 8004540: 6cdb ldr r3, [r3, #76] @ 0x4c 8004542: 4937 ldr r1, [pc, #220] @ (8004620 ) 8004544: 4313 orrs r3, r2 8004546: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800454a: 687b ldr r3, [r7, #4] 800454c: 681b ldr r3, [r3, #0] 800454e: f003 0340 and.w r3, r3, #64 @ 0x40 8004552: 2b00 cmp r3, #0 8004554: d00a beq.n 800456c { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8004556: 4b32 ldr r3, [pc, #200] @ (8004620 ) 8004558: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800455c: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 8004560: 687b ldr r3, [r7, #4] 8004562: 6c9b ldr r3, [r3, #72] @ 0x48 8004564: 492e ldr r1, [pc, #184] @ (8004620 ) 8004566: 4313 orrs r3, r2 8004568: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 800456c: 687b ldr r3, [r7, #4] 800456e: 681b ldr r3, [r3, #0] 8004570: f403 7380 and.w r3, r3, #256 @ 0x100 8004574: 2b00 cmp r3, #0 8004576: d011 beq.n 800459c { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 8004578: 4b29 ldr r3, [pc, #164] @ (8004620 ) 800457a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800457e: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 8004582: 687b ldr r3, [r7, #4] 8004584: 6d5b ldr r3, [r3, #84] @ 0x54 8004586: 4926 ldr r1, [pc, #152] @ (8004620 ) 8004588: 4313 orrs r3, r2 800458a: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 800458e: 687b ldr r3, [r7, #4] 8004590: 6d5b ldr r3, [r3, #84] @ 0x54 8004592: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004596: d101 bne.n 800459c { pllsaiused = 1U; 8004598: 2301 movs r3, #1 800459a: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 800459c: 687b ldr r3, [r7, #4] 800459e: 681b ldr r3, [r3, #0] 80045a0: f403 7300 and.w r3, r3, #512 @ 0x200 80045a4: 2b00 cmp r3, #0 80045a6: d00a beq.n 80045be { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 80045a8: 4b1d ldr r3, [pc, #116] @ (8004620 ) 80045aa: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80045ae: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 80045b2: 687b ldr r3, [r7, #4] 80045b4: 6c5b ldr r3, [r3, #68] @ 0x44 80045b6: 491a ldr r1, [pc, #104] @ (8004620 ) 80045b8: 4313 orrs r3, r2 80045ba: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80045be: 687b ldr r3, [r7, #4] 80045c0: 681b ldr r3, [r3, #0] 80045c2: f403 6380 and.w r3, r3, #1024 @ 0x400 80045c6: 2b00 cmp r3, #0 80045c8: d011 beq.n 80045ee { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 80045ca: 4b15 ldr r3, [pc, #84] @ (8004620 ) 80045cc: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80045d0: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 80045d4: 687b ldr r3, [r7, #4] 80045d6: 6d1b ldr r3, [r3, #80] @ 0x50 80045d8: 4911 ldr r1, [pc, #68] @ (8004620 ) 80045da: 4313 orrs r3, r2 80045dc: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 80045e0: 687b ldr r3, [r7, #4] 80045e2: 6d1b ldr r3, [r3, #80] @ 0x50 80045e4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80045e8: d101 bne.n 80045ee { plli2sused = 1U; 80045ea: 2301 movs r3, #1 80045ec: 62fb str r3, [r7, #44] @ 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 80045ee: 6afb ldr r3, [r7, #44] @ 0x2c 80045f0: 2b01 cmp r3, #1 80045f2: d005 beq.n 8004600 80045f4: 687b ldr r3, [r7, #4] 80045f6: 681b ldr r3, [r3, #0] 80045f8: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80045fc: f040 80ff bne.w 80047fe { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8004600: 4b09 ldr r3, [pc, #36] @ (8004628 ) 8004602: 2200 movs r2, #0 8004604: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004606: f7fd fa85 bl 8001b14 800460a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 800460c: e00e b.n 800462c { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 800460e: f7fd fa81 bl 8001b14 8004612: 4602 mov r2, r0 8004614: 6a7b ldr r3, [r7, #36] @ 0x24 8004616: 1ad3 subs r3, r2, r3 8004618: 2b02 cmp r3, #2 800461a: d907 bls.n 800462c { /* return in case of Timeout detected */ return HAL_TIMEOUT; 800461c: 2303 movs r3, #3 800461e: e188 b.n 8004932 8004620: 40023800 .word 0x40023800 8004624: 424711e0 .word 0x424711e0 8004628: 42470068 .word 0x42470068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 800462c: 4b7e ldr r3, [pc, #504] @ (8004828 ) 800462e: 681b ldr r3, [r3, #0] 8004630: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004634: 2b00 cmp r3, #0 8004636: d1ea bne.n 800460e /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) 8004638: 687b ldr r3, [r7, #4] 800463a: 681b ldr r3, [r3, #0] 800463c: f003 0301 and.w r3, r3, #1 8004640: 2b00 cmp r3, #0 8004642: d003 beq.n 800464c && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004644: 687b ldr r3, [r7, #4] 8004646: 6b9b ldr r3, [r3, #56] @ 0x38 8004648: 2b00 cmp r3, #0 800464a: d009 beq.n 8004660 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 800464c: 687b ldr r3, [r7, #4] 800464e: 681b ldr r3, [r3, #0] 8004650: f003 0302 and.w r3, r3, #2 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004654: 2b00 cmp r3, #0 8004656: d028 beq.n 80046aa ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8004658: 687b ldr r3, [r7, #4] 800465a: 6bdb ldr r3, [r3, #60] @ 0x3c 800465c: 2b00 cmp r3, #0 800465e: d124 bne.n 80046aa { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004660: 4b71 ldr r3, [pc, #452] @ (8004828 ) 8004662: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004666: 0c1b lsrs r3, r3, #16 8004668: f003 0303 and.w r3, r3, #3 800466c: 3301 adds r3, #1 800466e: 005b lsls r3, r3, #1 8004670: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8004672: 4b6d ldr r3, [pc, #436] @ (8004828 ) 8004674: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004678: 0e1b lsrs r3, r3, #24 800467a: f003 030f and.w r3, r3, #15 800467e: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, 8004680: 687b ldr r3, [r7, #4] 8004682: 685a ldr r2, [r3, #4] 8004684: 687b ldr r3, [r7, #4] 8004686: 689b ldr r3, [r3, #8] 8004688: 019b lsls r3, r3, #6 800468a: 431a orrs r2, r3 800468c: 69fb ldr r3, [r7, #28] 800468e: 085b lsrs r3, r3, #1 8004690: 3b01 subs r3, #1 8004692: 041b lsls r3, r3, #16 8004694: 431a orrs r2, r3 8004696: 69bb ldr r3, [r7, #24] 8004698: 061b lsls r3, r3, #24 800469a: 431a orrs r2, r3 800469c: 687b ldr r3, [r7, #4] 800469e: 695b ldr r3, [r3, #20] 80046a0: 071b lsls r3, r3, #28 80046a2: 4961 ldr r1, [pc, #388] @ (8004828 ) 80046a4: 4313 orrs r3, r2 80046a6: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80046aa: 687b ldr r3, [r7, #4] 80046ac: 681b ldr r3, [r3, #0] 80046ae: f003 0304 and.w r3, r3, #4 80046b2: 2b00 cmp r3, #0 80046b4: d004 beq.n 80046c0 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 80046b6: 687b ldr r3, [r7, #4] 80046b8: 6b1b ldr r3, [r3, #48] @ 0x30 80046ba: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80046be: d00a beq.n 80046d6 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 80046c0: 687b ldr r3, [r7, #4] 80046c2: 681b ldr r3, [r3, #0] 80046c4: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 80046c8: 2b00 cmp r3, #0 80046ca: d035 beq.n 8004738 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 80046cc: 687b ldr r3, [r7, #4] 80046ce: 6b5b ldr r3, [r3, #52] @ 0x34 80046d0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80046d4: d130 bne.n 8004738 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 80046d6: 4b54 ldr r3, [pc, #336] @ (8004828 ) 80046d8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80046dc: 0c1b lsrs r3, r3, #16 80046de: f003 0303 and.w r3, r3, #3 80046e2: 3301 adds r3, #1 80046e4: 005b lsls r3, r3, #1 80046e6: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 80046e8: 4b4f ldr r3, [pc, #316] @ (8004828 ) 80046ea: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80046ee: 0f1b lsrs r3, r3, #28 80046f0: f003 0307 and.w r3, r3, #7 80046f4: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, 80046f6: 687b ldr r3, [r7, #4] 80046f8: 685a ldr r2, [r3, #4] 80046fa: 687b ldr r3, [r7, #4] 80046fc: 689b ldr r3, [r3, #8] 80046fe: 019b lsls r3, r3, #6 8004700: 431a orrs r2, r3 8004702: 69fb ldr r3, [r7, #28] 8004704: 085b lsrs r3, r3, #1 8004706: 3b01 subs r3, #1 8004708: 041b lsls r3, r3, #16 800470a: 431a orrs r2, r3 800470c: 687b ldr r3, [r7, #4] 800470e: 691b ldr r3, [r3, #16] 8004710: 061b lsls r3, r3, #24 8004712: 431a orrs r2, r3 8004714: 697b ldr r3, [r7, #20] 8004716: 071b lsls r3, r3, #28 8004718: 4943 ldr r1, [pc, #268] @ (8004828 ) 800471a: 4313 orrs r3, r2 800471c: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004720: 4b41 ldr r3, [pc, #260] @ (8004828 ) 8004722: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004726: f023 021f bic.w r2, r3, #31 800472a: 687b ldr r3, [r7, #4] 800472c: 6a9b ldr r3, [r3, #40] @ 0x28 800472e: 3b01 subs r3, #1 8004730: 493d ldr r1, [pc, #244] @ (8004828 ) 8004732: 4313 orrs r3, r2 8004734: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004738: 687b ldr r3, [r7, #4] 800473a: 681b ldr r3, [r3, #0] 800473c: f403 6380 and.w r3, r3, #1024 @ 0x400 8004740: 2b00 cmp r3, #0 8004742: d029 beq.n 8004798 && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 8004744: 687b ldr r3, [r7, #4] 8004746: 6d1b ldr r3, [r3, #80] @ 0x50 8004748: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800474c: d124 bne.n 8004798 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 800474e: 4b36 ldr r3, [pc, #216] @ (8004828 ) 8004750: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004754: 0c1b lsrs r3, r3, #16 8004756: f003 0303 and.w r3, r3, #3 800475a: 3301 adds r3, #1 800475c: 005b lsls r3, r3, #1 800475e: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004760: 4b31 ldr r3, [pc, #196] @ (8004828 ) 8004762: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004766: 0f1b lsrs r3, r3, #28 8004768: f003 0307 and.w r3, r3, #7 800476c: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 800476e: 687b ldr r3, [r7, #4] 8004770: 685a ldr r2, [r3, #4] 8004772: 687b ldr r3, [r7, #4] 8004774: 689b ldr r3, [r3, #8] 8004776: 019b lsls r3, r3, #6 8004778: 431a orrs r2, r3 800477a: 687b ldr r3, [r7, #4] 800477c: 68db ldr r3, [r3, #12] 800477e: 085b lsrs r3, r3, #1 8004780: 3b01 subs r3, #1 8004782: 041b lsls r3, r3, #16 8004784: 431a orrs r2, r3 8004786: 69bb ldr r3, [r7, #24] 8004788: 061b lsls r3, r3, #24 800478a: 431a orrs r2, r3 800478c: 697b ldr r3, [r7, #20] 800478e: 071b lsls r3, r3, #28 8004790: 4925 ldr r1, [pc, #148] @ (8004828 ) 8004792: 4313 orrs r3, r2 8004794: f8c1 3084 str.w r3, [r1, #132] @ 0x84 plli2sq, plli2sr); } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 8004798: 687b ldr r3, [r7, #4] 800479a: 681b ldr r3, [r3, #0] 800479c: f403 6300 and.w r3, r3, #2048 @ 0x800 80047a0: 2b00 cmp r3, #0 80047a2: d016 beq.n 80047d2 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 80047a4: 687b ldr r3, [r7, #4] 80047a6: 685a ldr r2, [r3, #4] 80047a8: 687b ldr r3, [r7, #4] 80047aa: 689b ldr r3, [r3, #8] 80047ac: 019b lsls r3, r3, #6 80047ae: 431a orrs r2, r3 80047b0: 687b ldr r3, [r7, #4] 80047b2: 68db ldr r3, [r3, #12] 80047b4: 085b lsrs r3, r3, #1 80047b6: 3b01 subs r3, #1 80047b8: 041b lsls r3, r3, #16 80047ba: 431a orrs r2, r3 80047bc: 687b ldr r3, [r7, #4] 80047be: 691b ldr r3, [r3, #16] 80047c0: 061b lsls r3, r3, #24 80047c2: 431a orrs r2, r3 80047c4: 687b ldr r3, [r7, #4] 80047c6: 695b ldr r3, [r3, #20] 80047c8: 071b lsls r3, r3, #28 80047ca: 4917 ldr r1, [pc, #92] @ (8004828 ) 80047cc: 4313 orrs r3, r2 80047ce: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 80047d2: 4b16 ldr r3, [pc, #88] @ (800482c ) 80047d4: 2201 movs r2, #1 80047d6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80047d8: f7fd f99c bl 8001b14 80047dc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80047de: e008 b.n 80047f2 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 80047e0: f7fd f998 bl 8001b14 80047e4: 4602 mov r2, r0 80047e6: 6a7b ldr r3, [r7, #36] @ 0x24 80047e8: 1ad3 subs r3, r2, r3 80047ea: 2b02 cmp r3, #2 80047ec: d901 bls.n 80047f2 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 80047ee: 2303 movs r3, #3 80047f0: e09f b.n 8004932 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80047f2: 4b0d ldr r3, [pc, #52] @ (8004828 ) 80047f4: 681b ldr r3, [r3, #0] 80047f6: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80047fa: 2b00 cmp r3, #0 80047fc: d0f0 beq.n 80047e0 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if (pllsaiused == 1U) 80047fe: 6abb ldr r3, [r7, #40] @ 0x28 8004800: 2b01 cmp r3, #1 8004802: f040 8095 bne.w 8004930 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 8004806: 4b0a ldr r3, [pc, #40] @ (8004830 ) 8004808: 2200 movs r2, #0 800480a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800480c: f7fd f982 bl 8001b14 8004810: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004812: e00f b.n 8004834 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004814: f7fd f97e bl 8001b14 8004818: 4602 mov r2, r0 800481a: 6a7b ldr r3, [r7, #36] @ 0x24 800481c: 1ad3 subs r3, r2, r3 800481e: 2b02 cmp r3, #2 8004820: d908 bls.n 8004834 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004822: 2303 movs r3, #3 8004824: e085 b.n 8004932 8004826: bf00 nop 8004828: 40023800 .word 0x40023800 800482c: 42470068 .word 0x42470068 8004830: 42470070 .word 0x42470070 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004834: 4b41 ldr r3, [pc, #260] @ (800493c ) 8004836: 681b ldr r3, [r3, #0] 8004838: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800483c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004840: d0e8 beq.n 8004814 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004842: 687b ldr r3, [r7, #4] 8004844: 681b ldr r3, [r3, #0] 8004846: f003 0304 and.w r3, r3, #4 800484a: 2b00 cmp r3, #0 800484c: d003 beq.n 8004856 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 800484e: 687b ldr r3, [r7, #4] 8004850: 6b1b ldr r3, [r3, #48] @ 0x30 8004852: 2b00 cmp r3, #0 8004854: d009 beq.n 800486a ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004856: 687b ldr r3, [r7, #4] 8004858: 681b ldr r3, [r3, #0] 800485a: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 800485e: 2b00 cmp r3, #0 8004860: d02b beq.n 80048ba ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004862: 687b ldr r3, [r7, #4] 8004864: 6b5b ldr r3, [r3, #52] @ 0x34 8004866: 2b00 cmp r3, #0 8004868: d127 bne.n 80048ba assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 800486a: 4b34 ldr r3, [pc, #208] @ (800493c ) 800486c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004870: 0c1b lsrs r3, r3, #16 8004872: f003 0303 and.w r3, r3, #3 8004876: 3301 adds r3, #1 8004878: 005b lsls r3, r3, #1 800487a: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, 800487c: 687b ldr r3, [r7, #4] 800487e: 699a ldr r2, [r3, #24] 8004880: 687b ldr r3, [r7, #4] 8004882: 69db ldr r3, [r3, #28] 8004884: 019b lsls r3, r3, #6 8004886: 431a orrs r2, r3 8004888: 693b ldr r3, [r7, #16] 800488a: 085b lsrs r3, r3, #1 800488c: 3b01 subs r3, #1 800488e: 041b lsls r3, r3, #16 8004890: 431a orrs r2, r3 8004892: 687b ldr r3, [r7, #4] 8004894: 6a5b ldr r3, [r3, #36] @ 0x24 8004896: 061b lsls r3, r3, #24 8004898: 4928 ldr r1, [pc, #160] @ (800493c ) 800489a: 4313 orrs r3, r2 800489c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 PeriphClkInit->PLLSAI.PLLSAIQ, 0U); /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 80048a0: 4b26 ldr r3, [pc, #152] @ (800493c ) 80048a2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80048a6: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 80048aa: 687b ldr r3, [r7, #4] 80048ac: 6adb ldr r3, [r3, #44] @ 0x2c 80048ae: 3b01 subs r3, #1 80048b0: 021b lsls r3, r3, #8 80048b2: 4922 ldr r1, [pc, #136] @ (800493c ) 80048b4: 4313 orrs r3, r2 80048b6: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 80048ba: 687b ldr r3, [r7, #4] 80048bc: 681b ldr r3, [r3, #0] 80048be: f403 7380 and.w r3, r3, #256 @ 0x100 80048c2: 2b00 cmp r3, #0 80048c4: d01d beq.n 8004902 && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 80048c6: 687b ldr r3, [r7, #4] 80048c8: 6d5b ldr r3, [r3, #84] @ 0x54 80048ca: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80048ce: d118 bne.n 8004902 { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 80048d0: 4b1a ldr r3, [pc, #104] @ (800493c ) 80048d2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80048d6: 0e1b lsrs r3, r3, #24 80048d8: f003 030f and.w r3, r3, #15 80048dc: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, 80048de: 687b ldr r3, [r7, #4] 80048e0: 699a ldr r2, [r3, #24] 80048e2: 687b ldr r3, [r7, #4] 80048e4: 69db ldr r3, [r3, #28] 80048e6: 019b lsls r3, r3, #6 80048e8: 431a orrs r2, r3 80048ea: 687b ldr r3, [r7, #4] 80048ec: 6a1b ldr r3, [r3, #32] 80048ee: 085b lsrs r3, r3, #1 80048f0: 3b01 subs r3, #1 80048f2: 041b lsls r3, r3, #16 80048f4: 431a orrs r2, r3 80048f6: 68fb ldr r3, [r7, #12] 80048f8: 061b lsls r3, r3, #24 80048fa: 4910 ldr r1, [pc, #64] @ (800493c ) 80048fc: 4313 orrs r3, r2 80048fe: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pllsaiq, 0U); } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 8004902: 4b0f ldr r3, [pc, #60] @ (8004940 ) 8004904: 2201 movs r2, #1 8004906: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004908: f7fd f904 bl 8001b14 800490c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 800490e: e008 b.n 8004922 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004910: f7fd f900 bl 8001b14 8004914: 4602 mov r2, r0 8004916: 6a7b ldr r3, [r7, #36] @ 0x24 8004918: 1ad3 subs r3, r2, r3 800491a: 2b02 cmp r3, #2 800491c: d901 bls.n 8004922 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 800491e: 2303 movs r3, #3 8004920: e007 b.n 8004932 while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004922: 4b06 ldr r3, [pc, #24] @ (800493c ) 8004924: 681b ldr r3, [r3, #0] 8004926: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800492a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800492e: d1ef bne.n 8004910 } } } return HAL_OK; 8004930: 2300 movs r3, #0 } 8004932: 4618 mov r0, r3 8004934: 3730 adds r7, #48 @ 0x30 8004936: 46bd mov sp, r7 8004938: bd80 pop {r7, pc} 800493a: bf00 nop 800493c: 40023800 .word 0x40023800 8004940: 42470070 .word 0x42470070 08004944 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8004944: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8004948: b0ae sub sp, #184 @ 0xb8 800494a: af00 add r7, sp, #0 uint32_t pllm = 0U; 800494c: 2300 movs r3, #0 800494e: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t pllvco = 0U; 8004952: 2300 movs r3, #0 8004954: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t pllp = 0U; 8004958: 2300 movs r3, #0 800495a: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 uint32_t pllr = 0U; 800495e: 2300 movs r3, #0 8004960: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t sysclockfreq = 0U; 8004964: 2300 movs r3, #0 8004966: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800496a: 4bcb ldr r3, [pc, #812] @ (8004c98 ) 800496c: 689b ldr r3, [r3, #8] 800496e: f003 030c and.w r3, r3, #12 8004972: 2b0c cmp r3, #12 8004974: f200 8206 bhi.w 8004d84 8004978: a201 add r2, pc, #4 @ (adr r2, 8004980 ) 800497a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800497e: bf00 nop 8004980: 080049b5 .word 0x080049b5 8004984: 08004d85 .word 0x08004d85 8004988: 08004d85 .word 0x08004d85 800498c: 08004d85 .word 0x08004d85 8004990: 080049bd .word 0x080049bd 8004994: 08004d85 .word 0x08004d85 8004998: 08004d85 .word 0x08004d85 800499c: 08004d85 .word 0x08004d85 80049a0: 080049c5 .word 0x080049c5 80049a4: 08004d85 .word 0x08004d85 80049a8: 08004d85 .word 0x08004d85 80049ac: 08004d85 .word 0x08004d85 80049b0: 08004bb5 .word 0x08004bb5 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 80049b4: 4bb9 ldr r3, [pc, #740] @ (8004c9c ) 80049b6: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80049ba: e1e7 b.n 8004d8c } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 80049bc: 4bb8 ldr r3, [pc, #736] @ (8004ca0 ) 80049be: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80049c2: e1e3 b.n 8004d8c } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 80049c4: 4bb4 ldr r3, [pc, #720] @ (8004c98 ) 80049c6: 685b ldr r3, [r3, #4] 80049c8: f003 033f and.w r3, r3, #63 @ 0x3f 80049cc: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 80049d0: 4bb1 ldr r3, [pc, #708] @ (8004c98 ) 80049d2: 685b ldr r3, [r3, #4] 80049d4: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80049d8: 2b00 cmp r3, #0 80049da: d071 beq.n 8004ac0 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 80049dc: 4bae ldr r3, [pc, #696] @ (8004c98 ) 80049de: 685b ldr r3, [r3, #4] 80049e0: 099b lsrs r3, r3, #6 80049e2: 2200 movs r2, #0 80049e4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 80049e8: f8c7 209c str.w r2, [r7, #156] @ 0x9c 80049ec: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80049f0: f3c3 0308 ubfx r3, r3, #0, #9 80049f4: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80049f8: 2300 movs r3, #0 80049fa: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80049fe: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8004a02: 4622 mov r2, r4 8004a04: 462b mov r3, r5 8004a06: f04f 0000 mov.w r0, #0 8004a0a: f04f 0100 mov.w r1, #0 8004a0e: 0159 lsls r1, r3, #5 8004a10: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004a14: 0150 lsls r0, r2, #5 8004a16: 4602 mov r2, r0 8004a18: 460b mov r3, r1 8004a1a: 4621 mov r1, r4 8004a1c: 1a51 subs r1, r2, r1 8004a1e: 6439 str r1, [r7, #64] @ 0x40 8004a20: 4629 mov r1, r5 8004a22: eb63 0301 sbc.w r3, r3, r1 8004a26: 647b str r3, [r7, #68] @ 0x44 8004a28: f04f 0200 mov.w r2, #0 8004a2c: f04f 0300 mov.w r3, #0 8004a30: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 8004a34: 4649 mov r1, r9 8004a36: 018b lsls r3, r1, #6 8004a38: 4641 mov r1, r8 8004a3a: ea43 6391 orr.w r3, r3, r1, lsr #26 8004a3e: 4641 mov r1, r8 8004a40: 018a lsls r2, r1, #6 8004a42: 4641 mov r1, r8 8004a44: 1a51 subs r1, r2, r1 8004a46: 63b9 str r1, [r7, #56] @ 0x38 8004a48: 4649 mov r1, r9 8004a4a: eb63 0301 sbc.w r3, r3, r1 8004a4e: 63fb str r3, [r7, #60] @ 0x3c 8004a50: f04f 0200 mov.w r2, #0 8004a54: f04f 0300 mov.w r3, #0 8004a58: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 8004a5c: 4649 mov r1, r9 8004a5e: 00cb lsls r3, r1, #3 8004a60: 4641 mov r1, r8 8004a62: ea43 7351 orr.w r3, r3, r1, lsr #29 8004a66: 4641 mov r1, r8 8004a68: 00ca lsls r2, r1, #3 8004a6a: 4610 mov r0, r2 8004a6c: 4619 mov r1, r3 8004a6e: 4603 mov r3, r0 8004a70: 4622 mov r2, r4 8004a72: 189b adds r3, r3, r2 8004a74: 633b str r3, [r7, #48] @ 0x30 8004a76: 462b mov r3, r5 8004a78: 460a mov r2, r1 8004a7a: eb42 0303 adc.w r3, r2, r3 8004a7e: 637b str r3, [r7, #52] @ 0x34 8004a80: f04f 0200 mov.w r2, #0 8004a84: f04f 0300 mov.w r3, #0 8004a88: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 8004a8c: 4629 mov r1, r5 8004a8e: 024b lsls r3, r1, #9 8004a90: 4621 mov r1, r4 8004a92: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004a96: 4621 mov r1, r4 8004a98: 024a lsls r2, r1, #9 8004a9a: 4610 mov r0, r2 8004a9c: 4619 mov r1, r3 8004a9e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004aa2: 2200 movs r2, #0 8004aa4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8004aa8: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8004aac: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 8004ab0: f7fb fba8 bl 8000204 <__aeabi_uldivmod> 8004ab4: 4602 mov r2, r0 8004ab6: 460b mov r3, r1 8004ab8: 4613 mov r3, r2 8004aba: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004abe: e067 b.n 8004b90 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004ac0: 4b75 ldr r3, [pc, #468] @ (8004c98 ) 8004ac2: 685b ldr r3, [r3, #4] 8004ac4: 099b lsrs r3, r3, #6 8004ac6: 2200 movs r2, #0 8004ac8: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004acc: f8c7 2084 str.w r2, [r7, #132] @ 0x84 8004ad0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004ad4: f3c3 0308 ubfx r3, r3, #0, #9 8004ad8: 67bb str r3, [r7, #120] @ 0x78 8004ada: 2300 movs r3, #0 8004adc: 67fb str r3, [r7, #124] @ 0x7c 8004ade: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 8004ae2: 4622 mov r2, r4 8004ae4: 462b mov r3, r5 8004ae6: f04f 0000 mov.w r0, #0 8004aea: f04f 0100 mov.w r1, #0 8004aee: 0159 lsls r1, r3, #5 8004af0: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004af4: 0150 lsls r0, r2, #5 8004af6: 4602 mov r2, r0 8004af8: 460b mov r3, r1 8004afa: 4621 mov r1, r4 8004afc: 1a51 subs r1, r2, r1 8004afe: 62b9 str r1, [r7, #40] @ 0x28 8004b00: 4629 mov r1, r5 8004b02: eb63 0301 sbc.w r3, r3, r1 8004b06: 62fb str r3, [r7, #44] @ 0x2c 8004b08: f04f 0200 mov.w r2, #0 8004b0c: f04f 0300 mov.w r3, #0 8004b10: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 8004b14: 4649 mov r1, r9 8004b16: 018b lsls r3, r1, #6 8004b18: 4641 mov r1, r8 8004b1a: ea43 6391 orr.w r3, r3, r1, lsr #26 8004b1e: 4641 mov r1, r8 8004b20: 018a lsls r2, r1, #6 8004b22: 4641 mov r1, r8 8004b24: ebb2 0a01 subs.w sl, r2, r1 8004b28: 4649 mov r1, r9 8004b2a: eb63 0b01 sbc.w fp, r3, r1 8004b2e: f04f 0200 mov.w r2, #0 8004b32: f04f 0300 mov.w r3, #0 8004b36: ea4f 03cb mov.w r3, fp, lsl #3 8004b3a: ea43 735a orr.w r3, r3, sl, lsr #29 8004b3e: ea4f 02ca mov.w r2, sl, lsl #3 8004b42: 4692 mov sl, r2 8004b44: 469b mov fp, r3 8004b46: 4623 mov r3, r4 8004b48: eb1a 0303 adds.w r3, sl, r3 8004b4c: 623b str r3, [r7, #32] 8004b4e: 462b mov r3, r5 8004b50: eb4b 0303 adc.w r3, fp, r3 8004b54: 627b str r3, [r7, #36] @ 0x24 8004b56: f04f 0200 mov.w r2, #0 8004b5a: f04f 0300 mov.w r3, #0 8004b5e: e9d7 4508 ldrd r4, r5, [r7, #32] 8004b62: 4629 mov r1, r5 8004b64: 028b lsls r3, r1, #10 8004b66: 4621 mov r1, r4 8004b68: ea43 5391 orr.w r3, r3, r1, lsr #22 8004b6c: 4621 mov r1, r4 8004b6e: 028a lsls r2, r1, #10 8004b70: 4610 mov r0, r2 8004b72: 4619 mov r1, r3 8004b74: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004b78: 2200 movs r2, #0 8004b7a: 673b str r3, [r7, #112] @ 0x70 8004b7c: 677a str r2, [r7, #116] @ 0x74 8004b7e: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 8004b82: f7fb fb3f bl 8000204 <__aeabi_uldivmod> 8004b86: 4602 mov r2, r0 8004b88: 460b mov r3, r1 8004b8a: 4613 mov r3, r2 8004b8c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004b90: 4b41 ldr r3, [pc, #260] @ (8004c98 ) 8004b92: 685b ldr r3, [r3, #4] 8004b94: 0c1b lsrs r3, r3, #16 8004b96: f003 0303 and.w r3, r3, #3 8004b9a: 3301 adds r3, #1 8004b9c: 005b lsls r3, r3, #1 8004b9e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 sysclockfreq = pllvco / pllp; 8004ba2: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004ba6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8004baa: fbb2 f3f3 udiv r3, r2, r3 8004bae: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004bb2: e0eb b.n 8004d8c } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004bb4: 4b38 ldr r3, [pc, #224] @ (8004c98 ) 8004bb6: 685b ldr r3, [r3, #4] 8004bb8: f003 033f and.w r3, r3, #63 @ 0x3f 8004bbc: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004bc0: 4b35 ldr r3, [pc, #212] @ (8004c98 ) 8004bc2: 685b ldr r3, [r3, #4] 8004bc4: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004bc8: 2b00 cmp r3, #0 8004bca: d06b beq.n 8004ca4 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004bcc: 4b32 ldr r3, [pc, #200] @ (8004c98 ) 8004bce: 685b ldr r3, [r3, #4] 8004bd0: 099b lsrs r3, r3, #6 8004bd2: 2200 movs r2, #0 8004bd4: 66bb str r3, [r7, #104] @ 0x68 8004bd6: 66fa str r2, [r7, #108] @ 0x6c 8004bd8: 6ebb ldr r3, [r7, #104] @ 0x68 8004bda: f3c3 0308 ubfx r3, r3, #0, #9 8004bde: 663b str r3, [r7, #96] @ 0x60 8004be0: 2300 movs r3, #0 8004be2: 667b str r3, [r7, #100] @ 0x64 8004be4: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 8004be8: 4622 mov r2, r4 8004bea: 462b mov r3, r5 8004bec: f04f 0000 mov.w r0, #0 8004bf0: f04f 0100 mov.w r1, #0 8004bf4: 0159 lsls r1, r3, #5 8004bf6: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004bfa: 0150 lsls r0, r2, #5 8004bfc: 4602 mov r2, r0 8004bfe: 460b mov r3, r1 8004c00: 4621 mov r1, r4 8004c02: 1a51 subs r1, r2, r1 8004c04: 61b9 str r1, [r7, #24] 8004c06: 4629 mov r1, r5 8004c08: eb63 0301 sbc.w r3, r3, r1 8004c0c: 61fb str r3, [r7, #28] 8004c0e: f04f 0200 mov.w r2, #0 8004c12: f04f 0300 mov.w r3, #0 8004c16: e9d7 ab06 ldrd sl, fp, [r7, #24] 8004c1a: 4659 mov r1, fp 8004c1c: 018b lsls r3, r1, #6 8004c1e: 4651 mov r1, sl 8004c20: ea43 6391 orr.w r3, r3, r1, lsr #26 8004c24: 4651 mov r1, sl 8004c26: 018a lsls r2, r1, #6 8004c28: 4651 mov r1, sl 8004c2a: ebb2 0801 subs.w r8, r2, r1 8004c2e: 4659 mov r1, fp 8004c30: eb63 0901 sbc.w r9, r3, r1 8004c34: f04f 0200 mov.w r2, #0 8004c38: f04f 0300 mov.w r3, #0 8004c3c: ea4f 03c9 mov.w r3, r9, lsl #3 8004c40: ea43 7358 orr.w r3, r3, r8, lsr #29 8004c44: ea4f 02c8 mov.w r2, r8, lsl #3 8004c48: 4690 mov r8, r2 8004c4a: 4699 mov r9, r3 8004c4c: 4623 mov r3, r4 8004c4e: eb18 0303 adds.w r3, r8, r3 8004c52: 613b str r3, [r7, #16] 8004c54: 462b mov r3, r5 8004c56: eb49 0303 adc.w r3, r9, r3 8004c5a: 617b str r3, [r7, #20] 8004c5c: f04f 0200 mov.w r2, #0 8004c60: f04f 0300 mov.w r3, #0 8004c64: e9d7 4504 ldrd r4, r5, [r7, #16] 8004c68: 4629 mov r1, r5 8004c6a: 024b lsls r3, r1, #9 8004c6c: 4621 mov r1, r4 8004c6e: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004c72: 4621 mov r1, r4 8004c74: 024a lsls r2, r1, #9 8004c76: 4610 mov r0, r2 8004c78: 4619 mov r1, r3 8004c7a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004c7e: 2200 movs r2, #0 8004c80: 65bb str r3, [r7, #88] @ 0x58 8004c82: 65fa str r2, [r7, #92] @ 0x5c 8004c84: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8004c88: f7fb fabc bl 8000204 <__aeabi_uldivmod> 8004c8c: 4602 mov r2, r0 8004c8e: 460b mov r3, r1 8004c90: 4613 mov r3, r2 8004c92: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004c96: e065 b.n 8004d64 8004c98: 40023800 .word 0x40023800 8004c9c: 00f42400 .word 0x00f42400 8004ca0: 007a1200 .word 0x007a1200 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004ca4: 4b3d ldr r3, [pc, #244] @ (8004d9c ) 8004ca6: 685b ldr r3, [r3, #4] 8004ca8: 099b lsrs r3, r3, #6 8004caa: 2200 movs r2, #0 8004cac: 4618 mov r0, r3 8004cae: 4611 mov r1, r2 8004cb0: f3c0 0308 ubfx r3, r0, #0, #9 8004cb4: 653b str r3, [r7, #80] @ 0x50 8004cb6: 2300 movs r3, #0 8004cb8: 657b str r3, [r7, #84] @ 0x54 8004cba: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 8004cbe: 4642 mov r2, r8 8004cc0: 464b mov r3, r9 8004cc2: f04f 0000 mov.w r0, #0 8004cc6: f04f 0100 mov.w r1, #0 8004cca: 0159 lsls r1, r3, #5 8004ccc: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004cd0: 0150 lsls r0, r2, #5 8004cd2: 4602 mov r2, r0 8004cd4: 460b mov r3, r1 8004cd6: 4641 mov r1, r8 8004cd8: 1a51 subs r1, r2, r1 8004cda: 60b9 str r1, [r7, #8] 8004cdc: 4649 mov r1, r9 8004cde: eb63 0301 sbc.w r3, r3, r1 8004ce2: 60fb str r3, [r7, #12] 8004ce4: f04f 0200 mov.w r2, #0 8004ce8: f04f 0300 mov.w r3, #0 8004cec: e9d7 ab02 ldrd sl, fp, [r7, #8] 8004cf0: 4659 mov r1, fp 8004cf2: 018b lsls r3, r1, #6 8004cf4: 4651 mov r1, sl 8004cf6: ea43 6391 orr.w r3, r3, r1, lsr #26 8004cfa: 4651 mov r1, sl 8004cfc: 018a lsls r2, r1, #6 8004cfe: 4651 mov r1, sl 8004d00: 1a54 subs r4, r2, r1 8004d02: 4659 mov r1, fp 8004d04: eb63 0501 sbc.w r5, r3, r1 8004d08: f04f 0200 mov.w r2, #0 8004d0c: f04f 0300 mov.w r3, #0 8004d10: 00eb lsls r3, r5, #3 8004d12: ea43 7354 orr.w r3, r3, r4, lsr #29 8004d16: 00e2 lsls r2, r4, #3 8004d18: 4614 mov r4, r2 8004d1a: 461d mov r5, r3 8004d1c: 4643 mov r3, r8 8004d1e: 18e3 adds r3, r4, r3 8004d20: 603b str r3, [r7, #0] 8004d22: 464b mov r3, r9 8004d24: eb45 0303 adc.w r3, r5, r3 8004d28: 607b str r3, [r7, #4] 8004d2a: f04f 0200 mov.w r2, #0 8004d2e: f04f 0300 mov.w r3, #0 8004d32: e9d7 4500 ldrd r4, r5, [r7] 8004d36: 4629 mov r1, r5 8004d38: 028b lsls r3, r1, #10 8004d3a: 4621 mov r1, r4 8004d3c: ea43 5391 orr.w r3, r3, r1, lsr #22 8004d40: 4621 mov r1, r4 8004d42: 028a lsls r2, r1, #10 8004d44: 4610 mov r0, r2 8004d46: 4619 mov r1, r3 8004d48: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004d4c: 2200 movs r2, #0 8004d4e: 64bb str r3, [r7, #72] @ 0x48 8004d50: 64fa str r2, [r7, #76] @ 0x4c 8004d52: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8004d56: f7fb fa55 bl 8000204 <__aeabi_uldivmod> 8004d5a: 4602 mov r2, r0 8004d5c: 460b mov r3, r1 8004d5e: 4613 mov r3, r2 8004d60: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 8004d64: 4b0d ldr r3, [pc, #52] @ (8004d9c ) 8004d66: 685b ldr r3, [r3, #4] 8004d68: 0f1b lsrs r3, r3, #28 8004d6a: f003 0307 and.w r3, r3, #7 8004d6e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 sysclockfreq = pllvco / pllr; 8004d72: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004d76: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8004d7a: fbb2 f3f3 udiv r3, r2, r3 8004d7e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004d82: e003 b.n 8004d8c } default: { sysclockfreq = HSI_VALUE; 8004d84: 4b06 ldr r3, [pc, #24] @ (8004da0 ) 8004d86: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004d8a: bf00 nop } } return sysclockfreq; 8004d8c: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 } 8004d90: 4618 mov r0, r3 8004d92: 37b8 adds r7, #184 @ 0xb8 8004d94: 46bd mov sp, r7 8004d96: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8004d9a: bf00 nop 8004d9c: 40023800 .word 0x40023800 8004da0: 00f42400 .word 0x00f42400 08004da4 : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004da4: b580 push {r7, lr} 8004da6: b086 sub sp, #24 8004da8: af00 add r7, sp, #0 8004daa: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8004dac: 687b ldr r3, [r7, #4] 8004dae: 2b00 cmp r3, #0 8004db0: d101 bne.n 8004db6 { return HAL_ERROR; 8004db2: 2301 movs r3, #1 8004db4: e28d b.n 80052d2 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004db6: 687b ldr r3, [r7, #4] 8004db8: 681b ldr r3, [r3, #0] 8004dba: f003 0301 and.w r3, r3, #1 8004dbe: 2b00 cmp r3, #0 8004dc0: f000 8083 beq.w 8004eca { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8004dc4: 4b94 ldr r3, [pc, #592] @ (8005018 ) 8004dc6: 689b ldr r3, [r3, #8] 8004dc8: f003 030c and.w r3, r3, #12 8004dcc: 2b04 cmp r3, #4 8004dce: d019 beq.n 8004e04 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004dd0: 4b91 ldr r3, [pc, #580] @ (8005018 ) 8004dd2: 689b ldr r3, [r3, #8] 8004dd4: f003 030c and.w r3, r3, #12 || \ 8004dd8: 2b08 cmp r3, #8 8004dda: d106 bne.n 8004dea ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004ddc: 4b8e ldr r3, [pc, #568] @ (8005018 ) 8004dde: 685b ldr r3, [r3, #4] 8004de0: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004de4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004de8: d00c beq.n 8004e04 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004dea: 4b8b ldr r3, [pc, #556] @ (8005018 ) 8004dec: 689b ldr r3, [r3, #8] 8004dee: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004df2: 2b0c cmp r3, #12 8004df4: d112 bne.n 8004e1c ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004df6: 4b88 ldr r3, [pc, #544] @ (8005018 ) 8004df8: 685b ldr r3, [r3, #4] 8004dfa: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004dfe: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004e02: d10b bne.n 8004e1c if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004e04: 4b84 ldr r3, [pc, #528] @ (8005018 ) 8004e06: 681b ldr r3, [r3, #0] 8004e08: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004e0c: 2b00 cmp r3, #0 8004e0e: d05b beq.n 8004ec8 8004e10: 687b ldr r3, [r7, #4] 8004e12: 685b ldr r3, [r3, #4] 8004e14: 2b00 cmp r3, #0 8004e16: d157 bne.n 8004ec8 { return HAL_ERROR; 8004e18: 2301 movs r3, #1 8004e1a: e25a b.n 80052d2 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004e1c: 687b ldr r3, [r7, #4] 8004e1e: 685b ldr r3, [r3, #4] 8004e20: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004e24: d106 bne.n 8004e34 8004e26: 4b7c ldr r3, [pc, #496] @ (8005018 ) 8004e28: 681b ldr r3, [r3, #0] 8004e2a: 4a7b ldr r2, [pc, #492] @ (8005018 ) 8004e2c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004e30: 6013 str r3, [r2, #0] 8004e32: e01d b.n 8004e70 8004e34: 687b ldr r3, [r7, #4] 8004e36: 685b ldr r3, [r3, #4] 8004e38: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004e3c: d10c bne.n 8004e58 8004e3e: 4b76 ldr r3, [pc, #472] @ (8005018 ) 8004e40: 681b ldr r3, [r3, #0] 8004e42: 4a75 ldr r2, [pc, #468] @ (8005018 ) 8004e44: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8004e48: 6013 str r3, [r2, #0] 8004e4a: 4b73 ldr r3, [pc, #460] @ (8005018 ) 8004e4c: 681b ldr r3, [r3, #0] 8004e4e: 4a72 ldr r2, [pc, #456] @ (8005018 ) 8004e50: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004e54: 6013 str r3, [r2, #0] 8004e56: e00b b.n 8004e70 8004e58: 4b6f ldr r3, [pc, #444] @ (8005018 ) 8004e5a: 681b ldr r3, [r3, #0] 8004e5c: 4a6e ldr r2, [pc, #440] @ (8005018 ) 8004e5e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004e62: 6013 str r3, [r2, #0] 8004e64: 4b6c ldr r3, [pc, #432] @ (8005018 ) 8004e66: 681b ldr r3, [r3, #0] 8004e68: 4a6b ldr r2, [pc, #428] @ (8005018 ) 8004e6a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004e6e: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8004e70: 687b ldr r3, [r7, #4] 8004e72: 685b ldr r3, [r3, #4] 8004e74: 2b00 cmp r3, #0 8004e76: d013 beq.n 8004ea0 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e78: f7fc fe4c bl 8001b14 8004e7c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004e7e: e008 b.n 8004e92 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004e80: f7fc fe48 bl 8001b14 8004e84: 4602 mov r2, r0 8004e86: 693b ldr r3, [r7, #16] 8004e88: 1ad3 subs r3, r2, r3 8004e8a: 2b64 cmp r3, #100 @ 0x64 8004e8c: d901 bls.n 8004e92 { return HAL_TIMEOUT; 8004e8e: 2303 movs r3, #3 8004e90: e21f b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004e92: 4b61 ldr r3, [pc, #388] @ (8005018 ) 8004e94: 681b ldr r3, [r3, #0] 8004e96: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004e9a: 2b00 cmp r3, #0 8004e9c: d0f0 beq.n 8004e80 8004e9e: e014 b.n 8004eca } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004ea0: f7fc fe38 bl 8001b14 8004ea4: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004ea6: e008 b.n 8004eba { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004ea8: f7fc fe34 bl 8001b14 8004eac: 4602 mov r2, r0 8004eae: 693b ldr r3, [r7, #16] 8004eb0: 1ad3 subs r3, r2, r3 8004eb2: 2b64 cmp r3, #100 @ 0x64 8004eb4: d901 bls.n 8004eba { return HAL_TIMEOUT; 8004eb6: 2303 movs r3, #3 8004eb8: e20b b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004eba: 4b57 ldr r3, [pc, #348] @ (8005018 ) 8004ebc: 681b ldr r3, [r3, #0] 8004ebe: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004ec2: 2b00 cmp r3, #0 8004ec4: d1f0 bne.n 8004ea8 8004ec6: e000 b.n 8004eca if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004ec8: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004eca: 687b ldr r3, [r7, #4] 8004ecc: 681b ldr r3, [r3, #0] 8004ece: f003 0302 and.w r3, r3, #2 8004ed2: 2b00 cmp r3, #0 8004ed4: d06f beq.n 8004fb6 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8004ed6: 4b50 ldr r3, [pc, #320] @ (8005018 ) 8004ed8: 689b ldr r3, [r3, #8] 8004eda: f003 030c and.w r3, r3, #12 8004ede: 2b00 cmp r3, #0 8004ee0: d017 beq.n 8004f12 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004ee2: 4b4d ldr r3, [pc, #308] @ (8005018 ) 8004ee4: 689b ldr r3, [r3, #8] 8004ee6: f003 030c and.w r3, r3, #12 || \ 8004eea: 2b08 cmp r3, #8 8004eec: d105 bne.n 8004efa ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004eee: 4b4a ldr r3, [pc, #296] @ (8005018 ) 8004ef0: 685b ldr r3, [r3, #4] 8004ef2: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004ef6: 2b00 cmp r3, #0 8004ef8: d00b beq.n 8004f12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004efa: 4b47 ldr r3, [pc, #284] @ (8005018 ) 8004efc: 689b ldr r3, [r3, #8] 8004efe: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004f02: 2b0c cmp r3, #12 8004f04: d11c bne.n 8004f40 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004f06: 4b44 ldr r3, [pc, #272] @ (8005018 ) 8004f08: 685b ldr r3, [r3, #4] 8004f0a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004f0e: 2b00 cmp r3, #0 8004f10: d116 bne.n 8004f40 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004f12: 4b41 ldr r3, [pc, #260] @ (8005018 ) 8004f14: 681b ldr r3, [r3, #0] 8004f16: f003 0302 and.w r3, r3, #2 8004f1a: 2b00 cmp r3, #0 8004f1c: d005 beq.n 8004f2a 8004f1e: 687b ldr r3, [r7, #4] 8004f20: 68db ldr r3, [r3, #12] 8004f22: 2b01 cmp r3, #1 8004f24: d001 beq.n 8004f2a { return HAL_ERROR; 8004f26: 2301 movs r3, #1 8004f28: e1d3 b.n 80052d2 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004f2a: 4b3b ldr r3, [pc, #236] @ (8005018 ) 8004f2c: 681b ldr r3, [r3, #0] 8004f2e: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004f32: 687b ldr r3, [r7, #4] 8004f34: 691b ldr r3, [r3, #16] 8004f36: 00db lsls r3, r3, #3 8004f38: 4937 ldr r1, [pc, #220] @ (8005018 ) 8004f3a: 4313 orrs r3, r2 8004f3c: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004f3e: e03a b.n 8004fb6 } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8004f40: 687b ldr r3, [r7, #4] 8004f42: 68db ldr r3, [r3, #12] 8004f44: 2b00 cmp r3, #0 8004f46: d020 beq.n 8004f8a { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8004f48: 4b34 ldr r3, [pc, #208] @ (800501c ) 8004f4a: 2201 movs r2, #1 8004f4c: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004f4e: f7fc fde1 bl 8001b14 8004f52: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004f54: e008 b.n 8004f68 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004f56: f7fc fddd bl 8001b14 8004f5a: 4602 mov r2, r0 8004f5c: 693b ldr r3, [r7, #16] 8004f5e: 1ad3 subs r3, r2, r3 8004f60: 2b02 cmp r3, #2 8004f62: d901 bls.n 8004f68 { return HAL_TIMEOUT; 8004f64: 2303 movs r3, #3 8004f66: e1b4 b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004f68: 4b2b ldr r3, [pc, #172] @ (8005018 ) 8004f6a: 681b ldr r3, [r3, #0] 8004f6c: f003 0302 and.w r3, r3, #2 8004f70: 2b00 cmp r3, #0 8004f72: d0f0 beq.n 8004f56 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004f74: 4b28 ldr r3, [pc, #160] @ (8005018 ) 8004f76: 681b ldr r3, [r3, #0] 8004f78: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004f7c: 687b ldr r3, [r7, #4] 8004f7e: 691b ldr r3, [r3, #16] 8004f80: 00db lsls r3, r3, #3 8004f82: 4925 ldr r1, [pc, #148] @ (8005018 ) 8004f84: 4313 orrs r3, r2 8004f86: 600b str r3, [r1, #0] 8004f88: e015 b.n 8004fb6 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8004f8a: 4b24 ldr r3, [pc, #144] @ (800501c ) 8004f8c: 2200 movs r2, #0 8004f8e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004f90: f7fc fdc0 bl 8001b14 8004f94: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004f96: e008 b.n 8004faa { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004f98: f7fc fdbc bl 8001b14 8004f9c: 4602 mov r2, r0 8004f9e: 693b ldr r3, [r7, #16] 8004fa0: 1ad3 subs r3, r2, r3 8004fa2: 2b02 cmp r3, #2 8004fa4: d901 bls.n 8004faa { return HAL_TIMEOUT; 8004fa6: 2303 movs r3, #3 8004fa8: e193 b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004faa: 4b1b ldr r3, [pc, #108] @ (8005018 ) 8004fac: 681b ldr r3, [r3, #0] 8004fae: f003 0302 and.w r3, r3, #2 8004fb2: 2b00 cmp r3, #0 8004fb4: d1f0 bne.n 8004f98 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004fb6: 687b ldr r3, [r7, #4] 8004fb8: 681b ldr r3, [r3, #0] 8004fba: f003 0308 and.w r3, r3, #8 8004fbe: 2b00 cmp r3, #0 8004fc0: d036 beq.n 8005030 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 8004fc2: 687b ldr r3, [r7, #4] 8004fc4: 695b ldr r3, [r3, #20] 8004fc6: 2b00 cmp r3, #0 8004fc8: d016 beq.n 8004ff8 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8004fca: 4b15 ldr r3, [pc, #84] @ (8005020 ) 8004fcc: 2201 movs r2, #1 8004fce: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004fd0: f7fc fda0 bl 8001b14 8004fd4: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004fd6: e008 b.n 8004fea { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004fd8: f7fc fd9c bl 8001b14 8004fdc: 4602 mov r2, r0 8004fde: 693b ldr r3, [r7, #16] 8004fe0: 1ad3 subs r3, r2, r3 8004fe2: 2b02 cmp r3, #2 8004fe4: d901 bls.n 8004fea { return HAL_TIMEOUT; 8004fe6: 2303 movs r3, #3 8004fe8: e173 b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004fea: 4b0b ldr r3, [pc, #44] @ (8005018 ) 8004fec: 6f5b ldr r3, [r3, #116] @ 0x74 8004fee: f003 0302 and.w r3, r3, #2 8004ff2: 2b00 cmp r3, #0 8004ff4: d0f0 beq.n 8004fd8 8004ff6: e01b b.n 8005030 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8004ff8: 4b09 ldr r3, [pc, #36] @ (8005020 ) 8004ffa: 2200 movs r2, #0 8004ffc: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004ffe: f7fc fd89 bl 8001b14 8005002: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8005004: e00e b.n 8005024 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8005006: f7fc fd85 bl 8001b14 800500a: 4602 mov r2, r0 800500c: 693b ldr r3, [r7, #16] 800500e: 1ad3 subs r3, r2, r3 8005010: 2b02 cmp r3, #2 8005012: d907 bls.n 8005024 { return HAL_TIMEOUT; 8005014: 2303 movs r3, #3 8005016: e15c b.n 80052d2 8005018: 40023800 .word 0x40023800 800501c: 42470000 .word 0x42470000 8005020: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8005024: 4b8a ldr r3, [pc, #552] @ (8005250 ) 8005026: 6f5b ldr r3, [r3, #116] @ 0x74 8005028: f003 0302 and.w r3, r3, #2 800502c: 2b00 cmp r3, #0 800502e: d1ea bne.n 8005006 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8005030: 687b ldr r3, [r7, #4] 8005032: 681b ldr r3, [r3, #0] 8005034: f003 0304 and.w r3, r3, #4 8005038: 2b00 cmp r3, #0 800503a: f000 8097 beq.w 800516c { FlagStatus pwrclkchanged = RESET; 800503e: 2300 movs r3, #0 8005040: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8005042: 4b83 ldr r3, [pc, #524] @ (8005250 ) 8005044: 6c1b ldr r3, [r3, #64] @ 0x40 8005046: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800504a: 2b00 cmp r3, #0 800504c: d10f bne.n 800506e { __HAL_RCC_PWR_CLK_ENABLE(); 800504e: 2300 movs r3, #0 8005050: 60bb str r3, [r7, #8] 8005052: 4b7f ldr r3, [pc, #508] @ (8005250 ) 8005054: 6c1b ldr r3, [r3, #64] @ 0x40 8005056: 4a7e ldr r2, [pc, #504] @ (8005250 ) 8005058: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800505c: 6413 str r3, [r2, #64] @ 0x40 800505e: 4b7c ldr r3, [pc, #496] @ (8005250 ) 8005060: 6c1b ldr r3, [r3, #64] @ 0x40 8005062: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005066: 60bb str r3, [r7, #8] 8005068: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800506a: 2301 movs r3, #1 800506c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800506e: 4b79 ldr r3, [pc, #484] @ (8005254 ) 8005070: 681b ldr r3, [r3, #0] 8005072: f403 7380 and.w r3, r3, #256 @ 0x100 8005076: 2b00 cmp r3, #0 8005078: d118 bne.n 80050ac { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800507a: 4b76 ldr r3, [pc, #472] @ (8005254 ) 800507c: 681b ldr r3, [r3, #0] 800507e: 4a75 ldr r2, [pc, #468] @ (8005254 ) 8005080: f443 7380 orr.w r3, r3, #256 @ 0x100 8005084: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8005086: f7fc fd45 bl 8001b14 800508a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800508c: e008 b.n 80050a0 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800508e: f7fc fd41 bl 8001b14 8005092: 4602 mov r2, r0 8005094: 693b ldr r3, [r7, #16] 8005096: 1ad3 subs r3, r2, r3 8005098: 2b02 cmp r3, #2 800509a: d901 bls.n 80050a0 { return HAL_TIMEOUT; 800509c: 2303 movs r3, #3 800509e: e118 b.n 80052d2 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80050a0: 4b6c ldr r3, [pc, #432] @ (8005254 ) 80050a2: 681b ldr r3, [r3, #0] 80050a4: f403 7380 and.w r3, r3, #256 @ 0x100 80050a8: 2b00 cmp r3, #0 80050aa: d0f0 beq.n 800508e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80050ac: 687b ldr r3, [r7, #4] 80050ae: 689b ldr r3, [r3, #8] 80050b0: 2b01 cmp r3, #1 80050b2: d106 bne.n 80050c2 80050b4: 4b66 ldr r3, [pc, #408] @ (8005250 ) 80050b6: 6f1b ldr r3, [r3, #112] @ 0x70 80050b8: 4a65 ldr r2, [pc, #404] @ (8005250 ) 80050ba: f043 0301 orr.w r3, r3, #1 80050be: 6713 str r3, [r2, #112] @ 0x70 80050c0: e01c b.n 80050fc 80050c2: 687b ldr r3, [r7, #4] 80050c4: 689b ldr r3, [r3, #8] 80050c6: 2b05 cmp r3, #5 80050c8: d10c bne.n 80050e4 80050ca: 4b61 ldr r3, [pc, #388] @ (8005250 ) 80050cc: 6f1b ldr r3, [r3, #112] @ 0x70 80050ce: 4a60 ldr r2, [pc, #384] @ (8005250 ) 80050d0: f043 0304 orr.w r3, r3, #4 80050d4: 6713 str r3, [r2, #112] @ 0x70 80050d6: 4b5e ldr r3, [pc, #376] @ (8005250 ) 80050d8: 6f1b ldr r3, [r3, #112] @ 0x70 80050da: 4a5d ldr r2, [pc, #372] @ (8005250 ) 80050dc: f043 0301 orr.w r3, r3, #1 80050e0: 6713 str r3, [r2, #112] @ 0x70 80050e2: e00b b.n 80050fc 80050e4: 4b5a ldr r3, [pc, #360] @ (8005250 ) 80050e6: 6f1b ldr r3, [r3, #112] @ 0x70 80050e8: 4a59 ldr r2, [pc, #356] @ (8005250 ) 80050ea: f023 0301 bic.w r3, r3, #1 80050ee: 6713 str r3, [r2, #112] @ 0x70 80050f0: 4b57 ldr r3, [pc, #348] @ (8005250 ) 80050f2: 6f1b ldr r3, [r3, #112] @ 0x70 80050f4: 4a56 ldr r2, [pc, #344] @ (8005250 ) 80050f6: f023 0304 bic.w r3, r3, #4 80050fa: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 80050fc: 687b ldr r3, [r7, #4] 80050fe: 689b ldr r3, [r3, #8] 8005100: 2b00 cmp r3, #0 8005102: d015 beq.n 8005130 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005104: f7fc fd06 bl 8001b14 8005108: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800510a: e00a b.n 8005122 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800510c: f7fc fd02 bl 8001b14 8005110: 4602 mov r2, r0 8005112: 693b ldr r3, [r7, #16] 8005114: 1ad3 subs r3, r2, r3 8005116: f241 3288 movw r2, #5000 @ 0x1388 800511a: 4293 cmp r3, r2 800511c: d901 bls.n 8005122 { return HAL_TIMEOUT; 800511e: 2303 movs r3, #3 8005120: e0d7 b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005122: 4b4b ldr r3, [pc, #300] @ (8005250 ) 8005124: 6f1b ldr r3, [r3, #112] @ 0x70 8005126: f003 0302 and.w r3, r3, #2 800512a: 2b00 cmp r3, #0 800512c: d0ee beq.n 800510c 800512e: e014 b.n 800515a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005130: f7fc fcf0 bl 8001b14 8005134: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8005136: e00a b.n 800514e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005138: f7fc fcec bl 8001b14 800513c: 4602 mov r2, r0 800513e: 693b ldr r3, [r7, #16] 8005140: 1ad3 subs r3, r2, r3 8005142: f241 3288 movw r2, #5000 @ 0x1388 8005146: 4293 cmp r3, r2 8005148: d901 bls.n 800514e { return HAL_TIMEOUT; 800514a: 2303 movs r3, #3 800514c: e0c1 b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800514e: 4b40 ldr r3, [pc, #256] @ (8005250 ) 8005150: 6f1b ldr r3, [r3, #112] @ 0x70 8005152: f003 0302 and.w r3, r3, #2 8005156: 2b00 cmp r3, #0 8005158: d1ee bne.n 8005138 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 800515a: 7dfb ldrb r3, [r7, #23] 800515c: 2b01 cmp r3, #1 800515e: d105 bne.n 800516c { __HAL_RCC_PWR_CLK_DISABLE(); 8005160: 4b3b ldr r3, [pc, #236] @ (8005250 ) 8005162: 6c1b ldr r3, [r3, #64] @ 0x40 8005164: 4a3a ldr r2, [pc, #232] @ (8005250 ) 8005166: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800516a: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800516c: 687b ldr r3, [r7, #4] 800516e: 699b ldr r3, [r3, #24] 8005170: 2b00 cmp r3, #0 8005172: f000 80ad beq.w 80052d0 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8005176: 4b36 ldr r3, [pc, #216] @ (8005250 ) 8005178: 689b ldr r3, [r3, #8] 800517a: f003 030c and.w r3, r3, #12 800517e: 2b08 cmp r3, #8 8005180: d060 beq.n 8005244 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8005182: 687b ldr r3, [r7, #4] 8005184: 699b ldr r3, [r3, #24] 8005186: 2b02 cmp r3, #2 8005188: d145 bne.n 8005216 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800518a: 4b33 ldr r3, [pc, #204] @ (8005258 ) 800518c: 2200 movs r2, #0 800518e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005190: f7fc fcc0 bl 8001b14 8005194: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005196: e008 b.n 80051aa { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005198: f7fc fcbc bl 8001b14 800519c: 4602 mov r2, r0 800519e: 693b ldr r3, [r7, #16] 80051a0: 1ad3 subs r3, r2, r3 80051a2: 2b02 cmp r3, #2 80051a4: d901 bls.n 80051aa { return HAL_TIMEOUT; 80051a6: 2303 movs r3, #3 80051a8: e093 b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80051aa: 4b29 ldr r3, [pc, #164] @ (8005250 ) 80051ac: 681b ldr r3, [r3, #0] 80051ae: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80051b2: 2b00 cmp r3, #0 80051b4: d1f0 bne.n 8005198 } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 80051b6: 687b ldr r3, [r7, #4] 80051b8: 69da ldr r2, [r3, #28] 80051ba: 687b ldr r3, [r7, #4] 80051bc: 6a1b ldr r3, [r3, #32] 80051be: 431a orrs r2, r3 80051c0: 687b ldr r3, [r7, #4] 80051c2: 6a5b ldr r3, [r3, #36] @ 0x24 80051c4: 019b lsls r3, r3, #6 80051c6: 431a orrs r2, r3 80051c8: 687b ldr r3, [r7, #4] 80051ca: 6a9b ldr r3, [r3, #40] @ 0x28 80051cc: 085b lsrs r3, r3, #1 80051ce: 3b01 subs r3, #1 80051d0: 041b lsls r3, r3, #16 80051d2: 431a orrs r2, r3 80051d4: 687b ldr r3, [r7, #4] 80051d6: 6adb ldr r3, [r3, #44] @ 0x2c 80051d8: 061b lsls r3, r3, #24 80051da: 431a orrs r2, r3 80051dc: 687b ldr r3, [r7, #4] 80051de: 6b1b ldr r3, [r3, #48] @ 0x30 80051e0: 071b lsls r3, r3, #28 80051e2: 491b ldr r1, [pc, #108] @ (8005250 ) 80051e4: 4313 orrs r3, r2 80051e6: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80051e8: 4b1b ldr r3, [pc, #108] @ (8005258 ) 80051ea: 2201 movs r2, #1 80051ec: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80051ee: f7fc fc91 bl 8001b14 80051f2: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80051f4: e008 b.n 8005208 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80051f6: f7fc fc8d bl 8001b14 80051fa: 4602 mov r2, r0 80051fc: 693b ldr r3, [r7, #16] 80051fe: 1ad3 subs r3, r2, r3 8005200: 2b02 cmp r3, #2 8005202: d901 bls.n 8005208 { return HAL_TIMEOUT; 8005204: 2303 movs r3, #3 8005206: e064 b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005208: 4b11 ldr r3, [pc, #68] @ (8005250 ) 800520a: 681b ldr r3, [r3, #0] 800520c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005210: 2b00 cmp r3, #0 8005212: d0f0 beq.n 80051f6 8005214: e05c b.n 80052d0 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8005216: 4b10 ldr r3, [pc, #64] @ (8005258 ) 8005218: 2200 movs r2, #0 800521a: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800521c: f7fc fc7a bl 8001b14 8005220: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005222: e008 b.n 8005236 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005224: f7fc fc76 bl 8001b14 8005228: 4602 mov r2, r0 800522a: 693b ldr r3, [r7, #16] 800522c: 1ad3 subs r3, r2, r3 800522e: 2b02 cmp r3, #2 8005230: d901 bls.n 8005236 { return HAL_TIMEOUT; 8005232: 2303 movs r3, #3 8005234: e04d b.n 80052d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005236: 4b06 ldr r3, [pc, #24] @ (8005250 ) 8005238: 681b ldr r3, [r3, #0] 800523a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800523e: 2b00 cmp r3, #0 8005240: d1f0 bne.n 8005224 8005242: e045 b.n 80052d0 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8005244: 687b ldr r3, [r7, #4] 8005246: 699b ldr r3, [r3, #24] 8005248: 2b01 cmp r3, #1 800524a: d107 bne.n 800525c { return HAL_ERROR; 800524c: 2301 movs r3, #1 800524e: e040 b.n 80052d2 8005250: 40023800 .word 0x40023800 8005254: 40007000 .word 0x40007000 8005258: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 800525c: 4b1f ldr r3, [pc, #124] @ (80052dc ) 800525e: 685b ldr r3, [r3, #4] 8005260: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005262: 687b ldr r3, [r7, #4] 8005264: 699b ldr r3, [r3, #24] 8005266: 2b01 cmp r3, #1 8005268: d030 beq.n 80052cc (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800526a: 68fb ldr r3, [r7, #12] 800526c: f403 0280 and.w r2, r3, #4194304 @ 0x400000 8005270: 687b ldr r3, [r7, #4] 8005272: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005274: 429a cmp r2, r3 8005276: d129 bne.n 80052cc (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8005278: 68fb ldr r3, [r7, #12] 800527a: f003 023f and.w r2, r3, #63 @ 0x3f 800527e: 687b ldr r3, [r7, #4] 8005280: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8005282: 429a cmp r2, r3 8005284: d122 bne.n 80052cc (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8005286: 68fa ldr r2, [r7, #12] 8005288: f647 73c0 movw r3, #32704 @ 0x7fc0 800528c: 4013 ands r3, r2 800528e: 687a ldr r2, [r7, #4] 8005290: 6a52 ldr r2, [r2, #36] @ 0x24 8005292: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8005294: 4293 cmp r3, r2 8005296: d119 bne.n 80052cc (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8005298: 68fb ldr r3, [r7, #12] 800529a: f403 3240 and.w r2, r3, #196608 @ 0x30000 800529e: 687b ldr r3, [r7, #4] 80052a0: 6a9b ldr r3, [r3, #40] @ 0x28 80052a2: 085b lsrs r3, r3, #1 80052a4: 3b01 subs r3, #1 80052a6: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80052a8: 429a cmp r2, r3 80052aa: d10f bne.n 80052cc (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 80052ac: 68fb ldr r3, [r7, #12] 80052ae: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 80052b2: 687b ldr r3, [r7, #4] 80052b4: 6adb ldr r3, [r3, #44] @ 0x2c 80052b6: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80052b8: 429a cmp r2, r3 80052ba: d107 bne.n 80052cc (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 80052bc: 68fb ldr r3, [r7, #12] 80052be: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 80052c2: 687b ldr r3, [r7, #4] 80052c4: 6b1b ldr r3, [r3, #48] @ 0x30 80052c6: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 80052c8: 429a cmp r2, r3 80052ca: d001 beq.n 80052d0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 80052cc: 2301 movs r3, #1 80052ce: e000 b.n 80052d2 } } } } return HAL_OK; 80052d0: 2300 movs r3, #0 } 80052d2: 4618 mov r0, r3 80052d4: 3718 adds r7, #24 80052d6: 46bd mov sp, r7 80052d8: bd80 pop {r7, pc} 80052da: bf00 nop 80052dc: 40023800 .word 0x40023800 080052e0 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 80052e0: b580 push {r7, lr} 80052e2: b082 sub sp, #8 80052e4: af00 add r7, sp, #0 80052e6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80052e8: 687b ldr r3, [r7, #4] 80052ea: 2b00 cmp r3, #0 80052ec: d101 bne.n 80052f2 { return HAL_ERROR; 80052ee: 2301 movs r3, #1 80052f0: e041 b.n 8005376 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80052f2: 687b ldr r3, [r7, #4] 80052f4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80052f8: b2db uxtb r3, r3 80052fa: 2b00 cmp r3, #0 80052fc: d106 bne.n 800530c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80052fe: 687b ldr r3, [r7, #4] 8005300: 2200 movs r2, #0 8005302: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 8005306: 6878 ldr r0, [r7, #4] 8005308: f7fb ff6a bl 80011e0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800530c: 687b ldr r3, [r7, #4] 800530e: 2202 movs r2, #2 8005310: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005314: 687b ldr r3, [r7, #4] 8005316: 681a ldr r2, [r3, #0] 8005318: 687b ldr r3, [r7, #4] 800531a: 3304 adds r3, #4 800531c: 4619 mov r1, r3 800531e: 4610 mov r0, r2 8005320: f000 f930 bl 8005584 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005324: 687b ldr r3, [r7, #4] 8005326: 2201 movs r2, #1 8005328: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800532c: 687b ldr r3, [r7, #4] 800532e: 2201 movs r2, #1 8005330: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005334: 687b ldr r3, [r7, #4] 8005336: 2201 movs r2, #1 8005338: f883 203f strb.w r2, [r3, #63] @ 0x3f 800533c: 687b ldr r3, [r7, #4] 800533e: 2201 movs r2, #1 8005340: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005344: 687b ldr r3, [r7, #4] 8005346: 2201 movs r2, #1 8005348: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800534c: 687b ldr r3, [r7, #4] 800534e: 2201 movs r2, #1 8005350: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005354: 687b ldr r3, [r7, #4] 8005356: 2201 movs r2, #1 8005358: f883 2043 strb.w r2, [r3, #67] @ 0x43 800535c: 687b ldr r3, [r7, #4] 800535e: 2201 movs r2, #1 8005360: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005364: 687b ldr r3, [r7, #4] 8005366: 2201 movs r2, #1 8005368: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800536c: 687b ldr r3, [r7, #4] 800536e: 2201 movs r2, #1 8005370: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005374: 2300 movs r3, #0 } 8005376: 4618 mov r0, r3 8005378: 3708 adds r7, #8 800537a: 46bd mov sp, r7 800537c: bd80 pop {r7, pc} 0800537e : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 800537e: b580 push {r7, lr} 8005380: b086 sub sp, #24 8005382: af00 add r7, sp, #0 8005384: 6078 str r0, [r7, #4] 8005386: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 8005388: 687b ldr r3, [r7, #4] 800538a: 2b00 cmp r3, #0 800538c: d101 bne.n 8005392 { return HAL_ERROR; 800538e: 2301 movs r3, #1 8005390: e097 b.n 80054c2 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 8005392: 687b ldr r3, [r7, #4] 8005394: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8005398: b2db uxtb r3, r3 800539a: 2b00 cmp r3, #0 800539c: d106 bne.n 80053ac { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800539e: 687b ldr r3, [r7, #4] 80053a0: 2200 movs r2, #0 80053a2: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 80053a6: 6878 ldr r0, [r7, #4] 80053a8: f7fb ff3a bl 8001220 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80053ac: 687b ldr r3, [r7, #4] 80053ae: 2202 movs r2, #2 80053b0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 80053b4: 687b ldr r3, [r7, #4] 80053b6: 681b ldr r3, [r3, #0] 80053b8: 689b ldr r3, [r3, #8] 80053ba: 687a ldr r2, [r7, #4] 80053bc: 6812 ldr r2, [r2, #0] 80053be: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80053c2: f023 0307 bic.w r3, r3, #7 80053c6: 6093 str r3, [r2, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80053c8: 687b ldr r3, [r7, #4] 80053ca: 681a ldr r2, [r3, #0] 80053cc: 687b ldr r3, [r7, #4] 80053ce: 3304 adds r3, #4 80053d0: 4619 mov r1, r3 80053d2: 4610 mov r0, r2 80053d4: f000 f8d6 bl 8005584 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80053d8: 687b ldr r3, [r7, #4] 80053da: 681b ldr r3, [r3, #0] 80053dc: 689b ldr r3, [r3, #8] 80053de: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 80053e0: 687b ldr r3, [r7, #4] 80053e2: 681b ldr r3, [r3, #0] 80053e4: 699b ldr r3, [r3, #24] 80053e6: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 80053e8: 687b ldr r3, [r7, #4] 80053ea: 681b ldr r3, [r3, #0] 80053ec: 6a1b ldr r3, [r3, #32] 80053ee: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 80053f0: 683b ldr r3, [r7, #0] 80053f2: 681b ldr r3, [r3, #0] 80053f4: 697a ldr r2, [r7, #20] 80053f6: 4313 orrs r3, r2 80053f8: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 80053fa: 693b ldr r3, [r7, #16] 80053fc: f423 7340 bic.w r3, r3, #768 @ 0x300 8005400: f023 0303 bic.w r3, r3, #3 8005404: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 8005406: 683b ldr r3, [r7, #0] 8005408: 689a ldr r2, [r3, #8] 800540a: 683b ldr r3, [r7, #0] 800540c: 699b ldr r3, [r3, #24] 800540e: 021b lsls r3, r3, #8 8005410: 4313 orrs r3, r2 8005412: 693a ldr r2, [r7, #16] 8005414: 4313 orrs r3, r2 8005416: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 8005418: 693b ldr r3, [r7, #16] 800541a: f423 6340 bic.w r3, r3, #3072 @ 0xc00 800541e: f023 030c bic.w r3, r3, #12 8005422: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 8005424: 693b ldr r3, [r7, #16] 8005426: f423 4370 bic.w r3, r3, #61440 @ 0xf000 800542a: f023 03f0 bic.w r3, r3, #240 @ 0xf0 800542e: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 8005430: 683b ldr r3, [r7, #0] 8005432: 68da ldr r2, [r3, #12] 8005434: 683b ldr r3, [r7, #0] 8005436: 69db ldr r3, [r3, #28] 8005438: 021b lsls r3, r3, #8 800543a: 4313 orrs r3, r2 800543c: 693a ldr r2, [r7, #16] 800543e: 4313 orrs r3, r2 8005440: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 8005442: 683b ldr r3, [r7, #0] 8005444: 691b ldr r3, [r3, #16] 8005446: 011a lsls r2, r3, #4 8005448: 683b ldr r3, [r7, #0] 800544a: 6a1b ldr r3, [r3, #32] 800544c: 031b lsls r3, r3, #12 800544e: 4313 orrs r3, r2 8005450: 693a ldr r2, [r7, #16] 8005452: 4313 orrs r3, r2 8005454: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 8005456: 68fb ldr r3, [r7, #12] 8005458: f023 0322 bic.w r3, r3, #34 @ 0x22 800545c: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 800545e: 68fb ldr r3, [r7, #12] 8005460: f023 0388 bic.w r3, r3, #136 @ 0x88 8005464: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 8005466: 683b ldr r3, [r7, #0] 8005468: 685a ldr r2, [r3, #4] 800546a: 683b ldr r3, [r7, #0] 800546c: 695b ldr r3, [r3, #20] 800546e: 011b lsls r3, r3, #4 8005470: 4313 orrs r3, r2 8005472: 68fa ldr r2, [r7, #12] 8005474: 4313 orrs r3, r2 8005476: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005478: 687b ldr r3, [r7, #4] 800547a: 681b ldr r3, [r3, #0] 800547c: 697a ldr r2, [r7, #20] 800547e: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 8005480: 687b ldr r3, [r7, #4] 8005482: 681b ldr r3, [r3, #0] 8005484: 693a ldr r2, [r7, #16] 8005486: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 8005488: 687b ldr r3, [r7, #4] 800548a: 681b ldr r3, [r3, #0] 800548c: 68fa ldr r2, [r7, #12] 800548e: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005490: 687b ldr r3, [r7, #4] 8005492: 2201 movs r2, #1 8005494: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005498: 687b ldr r3, [r7, #4] 800549a: 2201 movs r2, #1 800549c: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 80054a0: 687b ldr r3, [r7, #4] 80054a2: 2201 movs r2, #1 80054a4: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 80054a8: 687b ldr r3, [r7, #4] 80054aa: 2201 movs r2, #1 80054ac: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 80054b0: 687b ldr r3, [r7, #4] 80054b2: 2201 movs r2, #1 80054b4: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80054b8: 687b ldr r3, [r7, #4] 80054ba: 2201 movs r2, #1 80054bc: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80054c0: 2300 movs r3, #0 } 80054c2: 4618 mov r0, r3 80054c4: 3718 adds r7, #24 80054c6: 46bd mov sp, r7 80054c8: bd80 pop {r7, pc} ... 080054cc : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80054cc: b580 push {r7, lr} 80054ce: b086 sub sp, #24 80054d0: af00 add r7, sp, #0 80054d2: 60f8 str r0, [r7, #12] 80054d4: 60b9 str r1, [r7, #8] 80054d6: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80054d8: 2300 movs r3, #0 80054da: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 80054dc: 68fb ldr r3, [r7, #12] 80054de: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80054e2: 2b01 cmp r3, #1 80054e4: d101 bne.n 80054ea 80054e6: 2302 movs r3, #2 80054e8: e048 b.n 800557c 80054ea: 68fb ldr r3, [r7, #12] 80054ec: 2201 movs r2, #1 80054ee: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80054f2: 687b ldr r3, [r7, #4] 80054f4: 2b0c cmp r3, #12 80054f6: d839 bhi.n 800556c 80054f8: a201 add r2, pc, #4 @ (adr r2, 8005500 ) 80054fa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80054fe: bf00 nop 8005500: 08005535 .word 0x08005535 8005504: 0800556d .word 0x0800556d 8005508: 0800556d .word 0x0800556d 800550c: 0800556d .word 0x0800556d 8005510: 08005543 .word 0x08005543 8005514: 0800556d .word 0x0800556d 8005518: 0800556d .word 0x0800556d 800551c: 0800556d .word 0x0800556d 8005520: 08005551 .word 0x08005551 8005524: 0800556d .word 0x0800556d 8005528: 0800556d .word 0x0800556d 800552c: 0800556d .word 0x0800556d 8005530: 0800555f .word 0x0800555f { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8005534: 68fb ldr r3, [r7, #12] 8005536: 681b ldr r3, [r3, #0] 8005538: 68b9 ldr r1, [r7, #8] 800553a: 4618 mov r0, r3 800553c: f000 f8c8 bl 80056d0 break; 8005540: e017 b.n 8005572 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8005542: 68fb ldr r3, [r7, #12] 8005544: 681b ldr r3, [r3, #0] 8005546: 68b9 ldr r1, [r7, #8] 8005548: 4618 mov r0, r3 800554a: f000 f931 bl 80057b0 break; 800554e: e010 b.n 8005572 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8005550: 68fb ldr r3, [r7, #12] 8005552: 681b ldr r3, [r3, #0] 8005554: 68b9 ldr r1, [r7, #8] 8005556: 4618 mov r0, r3 8005558: f000 f9a0 bl 800589c break; 800555c: e009 b.n 8005572 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800555e: 68fb ldr r3, [r7, #12] 8005560: 681b ldr r3, [r3, #0] 8005562: 68b9 ldr r1, [r7, #8] 8005564: 4618 mov r0, r3 8005566: f000 fa0d bl 8005984 break; 800556a: e002 b.n 8005572 } default: status = HAL_ERROR; 800556c: 2301 movs r3, #1 800556e: 75fb strb r3, [r7, #23] break; 8005570: bf00 nop } __HAL_UNLOCK(htim); 8005572: 68fb ldr r3, [r7, #12] 8005574: 2200 movs r2, #0 8005576: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800557a: 7dfb ldrb r3, [r7, #23] } 800557c: 4618 mov r0, r3 800557e: 3718 adds r7, #24 8005580: 46bd mov sp, r7 8005582: bd80 pop {r7, pc} 08005584 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8005584: b480 push {r7} 8005586: b085 sub sp, #20 8005588: af00 add r7, sp, #0 800558a: 6078 str r0, [r7, #4] 800558c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800558e: 687b ldr r3, [r7, #4] 8005590: 681b ldr r3, [r3, #0] 8005592: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8005594: 687b ldr r3, [r7, #4] 8005596: 4a43 ldr r2, [pc, #268] @ (80056a4 ) 8005598: 4293 cmp r3, r2 800559a: d013 beq.n 80055c4 800559c: 687b ldr r3, [r7, #4] 800559e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80055a2: d00f beq.n 80055c4 80055a4: 687b ldr r3, [r7, #4] 80055a6: 4a40 ldr r2, [pc, #256] @ (80056a8 ) 80055a8: 4293 cmp r3, r2 80055aa: d00b beq.n 80055c4 80055ac: 687b ldr r3, [r7, #4] 80055ae: 4a3f ldr r2, [pc, #252] @ (80056ac ) 80055b0: 4293 cmp r3, r2 80055b2: d007 beq.n 80055c4 80055b4: 687b ldr r3, [r7, #4] 80055b6: 4a3e ldr r2, [pc, #248] @ (80056b0 ) 80055b8: 4293 cmp r3, r2 80055ba: d003 beq.n 80055c4 80055bc: 687b ldr r3, [r7, #4] 80055be: 4a3d ldr r2, [pc, #244] @ (80056b4 ) 80055c0: 4293 cmp r3, r2 80055c2: d108 bne.n 80055d6 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80055c4: 68fb ldr r3, [r7, #12] 80055c6: f023 0370 bic.w r3, r3, #112 @ 0x70 80055ca: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80055cc: 683b ldr r3, [r7, #0] 80055ce: 685b ldr r3, [r3, #4] 80055d0: 68fa ldr r2, [r7, #12] 80055d2: 4313 orrs r3, r2 80055d4: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80055d6: 687b ldr r3, [r7, #4] 80055d8: 4a32 ldr r2, [pc, #200] @ (80056a4 ) 80055da: 4293 cmp r3, r2 80055dc: d02b beq.n 8005636 80055de: 687b ldr r3, [r7, #4] 80055e0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80055e4: d027 beq.n 8005636 80055e6: 687b ldr r3, [r7, #4] 80055e8: 4a2f ldr r2, [pc, #188] @ (80056a8 ) 80055ea: 4293 cmp r3, r2 80055ec: d023 beq.n 8005636 80055ee: 687b ldr r3, [r7, #4] 80055f0: 4a2e ldr r2, [pc, #184] @ (80056ac ) 80055f2: 4293 cmp r3, r2 80055f4: d01f beq.n 8005636 80055f6: 687b ldr r3, [r7, #4] 80055f8: 4a2d ldr r2, [pc, #180] @ (80056b0 ) 80055fa: 4293 cmp r3, r2 80055fc: d01b beq.n 8005636 80055fe: 687b ldr r3, [r7, #4] 8005600: 4a2c ldr r2, [pc, #176] @ (80056b4 ) 8005602: 4293 cmp r3, r2 8005604: d017 beq.n 8005636 8005606: 687b ldr r3, [r7, #4] 8005608: 4a2b ldr r2, [pc, #172] @ (80056b8 ) 800560a: 4293 cmp r3, r2 800560c: d013 beq.n 8005636 800560e: 687b ldr r3, [r7, #4] 8005610: 4a2a ldr r2, [pc, #168] @ (80056bc ) 8005612: 4293 cmp r3, r2 8005614: d00f beq.n 8005636 8005616: 687b ldr r3, [r7, #4] 8005618: 4a29 ldr r2, [pc, #164] @ (80056c0 ) 800561a: 4293 cmp r3, r2 800561c: d00b beq.n 8005636 800561e: 687b ldr r3, [r7, #4] 8005620: 4a28 ldr r2, [pc, #160] @ (80056c4 ) 8005622: 4293 cmp r3, r2 8005624: d007 beq.n 8005636 8005626: 687b ldr r3, [r7, #4] 8005628: 4a27 ldr r2, [pc, #156] @ (80056c8 ) 800562a: 4293 cmp r3, r2 800562c: d003 beq.n 8005636 800562e: 687b ldr r3, [r7, #4] 8005630: 4a26 ldr r2, [pc, #152] @ (80056cc ) 8005632: 4293 cmp r3, r2 8005634: d108 bne.n 8005648 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8005636: 68fb ldr r3, [r7, #12] 8005638: f423 7340 bic.w r3, r3, #768 @ 0x300 800563c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800563e: 683b ldr r3, [r7, #0] 8005640: 68db ldr r3, [r3, #12] 8005642: 68fa ldr r2, [r7, #12] 8005644: 4313 orrs r3, r2 8005646: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8005648: 68fb ldr r3, [r7, #12] 800564a: f023 0280 bic.w r2, r3, #128 @ 0x80 800564e: 683b ldr r3, [r7, #0] 8005650: 695b ldr r3, [r3, #20] 8005652: 4313 orrs r3, r2 8005654: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8005656: 683b ldr r3, [r7, #0] 8005658: 689a ldr r2, [r3, #8] 800565a: 687b ldr r3, [r7, #4] 800565c: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800565e: 683b ldr r3, [r7, #0] 8005660: 681a ldr r2, [r3, #0] 8005662: 687b ldr r3, [r7, #4] 8005664: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8005666: 687b ldr r3, [r7, #4] 8005668: 4a0e ldr r2, [pc, #56] @ (80056a4 ) 800566a: 4293 cmp r3, r2 800566c: d003 beq.n 8005676 800566e: 687b ldr r3, [r7, #4] 8005670: 4a10 ldr r2, [pc, #64] @ (80056b4 ) 8005672: 4293 cmp r3, r2 8005674: d103 bne.n 800567e { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8005676: 683b ldr r3, [r7, #0] 8005678: 691a ldr r2, [r3, #16] 800567a: 687b ldr r3, [r7, #4] 800567c: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 800567e: 687b ldr r3, [r7, #4] 8005680: 681b ldr r3, [r3, #0] 8005682: f043 0204 orr.w r2, r3, #4 8005686: 687b ldr r3, [r7, #4] 8005688: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800568a: 687b ldr r3, [r7, #4] 800568c: 2201 movs r2, #1 800568e: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 8005690: 687b ldr r3, [r7, #4] 8005692: 68fa ldr r2, [r7, #12] 8005694: 601a str r2, [r3, #0] } 8005696: bf00 nop 8005698: 3714 adds r7, #20 800569a: 46bd mov sp, r7 800569c: f85d 7b04 ldr.w r7, [sp], #4 80056a0: 4770 bx lr 80056a2: bf00 nop 80056a4: 40010000 .word 0x40010000 80056a8: 40000400 .word 0x40000400 80056ac: 40000800 .word 0x40000800 80056b0: 40000c00 .word 0x40000c00 80056b4: 40010400 .word 0x40010400 80056b8: 40014000 .word 0x40014000 80056bc: 40014400 .word 0x40014400 80056c0: 40014800 .word 0x40014800 80056c4: 40001800 .word 0x40001800 80056c8: 40001c00 .word 0x40001c00 80056cc: 40002000 .word 0x40002000 080056d0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80056d0: b480 push {r7} 80056d2: b087 sub sp, #28 80056d4: af00 add r7, sp, #0 80056d6: 6078 str r0, [r7, #4] 80056d8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80056da: 687b ldr r3, [r7, #4] 80056dc: 6a1b ldr r3, [r3, #32] 80056de: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80056e0: 687b ldr r3, [r7, #4] 80056e2: 6a1b ldr r3, [r3, #32] 80056e4: f023 0201 bic.w r2, r3, #1 80056e8: 687b ldr r3, [r7, #4] 80056ea: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80056ec: 687b ldr r3, [r7, #4] 80056ee: 685b ldr r3, [r3, #4] 80056f0: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80056f2: 687b ldr r3, [r7, #4] 80056f4: 699b ldr r3, [r3, #24] 80056f6: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80056f8: 68fb ldr r3, [r7, #12] 80056fa: f023 0370 bic.w r3, r3, #112 @ 0x70 80056fe: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8005700: 68fb ldr r3, [r7, #12] 8005702: f023 0303 bic.w r3, r3, #3 8005706: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8005708: 683b ldr r3, [r7, #0] 800570a: 681b ldr r3, [r3, #0] 800570c: 68fa ldr r2, [r7, #12] 800570e: 4313 orrs r3, r2 8005710: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8005712: 697b ldr r3, [r7, #20] 8005714: f023 0302 bic.w r3, r3, #2 8005718: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800571a: 683b ldr r3, [r7, #0] 800571c: 689b ldr r3, [r3, #8] 800571e: 697a ldr r2, [r7, #20] 8005720: 4313 orrs r3, r2 8005722: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8005724: 687b ldr r3, [r7, #4] 8005726: 4a20 ldr r2, [pc, #128] @ (80057a8 ) 8005728: 4293 cmp r3, r2 800572a: d003 beq.n 8005734 800572c: 687b ldr r3, [r7, #4] 800572e: 4a1f ldr r2, [pc, #124] @ (80057ac ) 8005730: 4293 cmp r3, r2 8005732: d10c bne.n 800574e { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8005734: 697b ldr r3, [r7, #20] 8005736: f023 0308 bic.w r3, r3, #8 800573a: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 800573c: 683b ldr r3, [r7, #0] 800573e: 68db ldr r3, [r3, #12] 8005740: 697a ldr r2, [r7, #20] 8005742: 4313 orrs r3, r2 8005744: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8005746: 697b ldr r3, [r7, #20] 8005748: f023 0304 bic.w r3, r3, #4 800574c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800574e: 687b ldr r3, [r7, #4] 8005750: 4a15 ldr r2, [pc, #84] @ (80057a8 ) 8005752: 4293 cmp r3, r2 8005754: d003 beq.n 800575e 8005756: 687b ldr r3, [r7, #4] 8005758: 4a14 ldr r2, [pc, #80] @ (80057ac ) 800575a: 4293 cmp r3, r2 800575c: d111 bne.n 8005782 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800575e: 693b ldr r3, [r7, #16] 8005760: f423 7380 bic.w r3, r3, #256 @ 0x100 8005764: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8005766: 693b ldr r3, [r7, #16] 8005768: f423 7300 bic.w r3, r3, #512 @ 0x200 800576c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 800576e: 683b ldr r3, [r7, #0] 8005770: 695b ldr r3, [r3, #20] 8005772: 693a ldr r2, [r7, #16] 8005774: 4313 orrs r3, r2 8005776: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8005778: 683b ldr r3, [r7, #0] 800577a: 699b ldr r3, [r3, #24] 800577c: 693a ldr r2, [r7, #16] 800577e: 4313 orrs r3, r2 8005780: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005782: 687b ldr r3, [r7, #4] 8005784: 693a ldr r2, [r7, #16] 8005786: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8005788: 687b ldr r3, [r7, #4] 800578a: 68fa ldr r2, [r7, #12] 800578c: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800578e: 683b ldr r3, [r7, #0] 8005790: 685a ldr r2, [r3, #4] 8005792: 687b ldr r3, [r7, #4] 8005794: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005796: 687b ldr r3, [r7, #4] 8005798: 697a ldr r2, [r7, #20] 800579a: 621a str r2, [r3, #32] } 800579c: bf00 nop 800579e: 371c adds r7, #28 80057a0: 46bd mov sp, r7 80057a2: f85d 7b04 ldr.w r7, [sp], #4 80057a6: 4770 bx lr 80057a8: 40010000 .word 0x40010000 80057ac: 40010400 .word 0x40010400 080057b0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80057b0: b480 push {r7} 80057b2: b087 sub sp, #28 80057b4: af00 add r7, sp, #0 80057b6: 6078 str r0, [r7, #4] 80057b8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80057ba: 687b ldr r3, [r7, #4] 80057bc: 6a1b ldr r3, [r3, #32] 80057be: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80057c0: 687b ldr r3, [r7, #4] 80057c2: 6a1b ldr r3, [r3, #32] 80057c4: f023 0210 bic.w r2, r3, #16 80057c8: 687b ldr r3, [r7, #4] 80057ca: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80057cc: 687b ldr r3, [r7, #4] 80057ce: 685b ldr r3, [r3, #4] 80057d0: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80057d2: 687b ldr r3, [r7, #4] 80057d4: 699b ldr r3, [r3, #24] 80057d6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80057d8: 68fb ldr r3, [r7, #12] 80057da: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80057de: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80057e0: 68fb ldr r3, [r7, #12] 80057e2: f423 7340 bic.w r3, r3, #768 @ 0x300 80057e6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80057e8: 683b ldr r3, [r7, #0] 80057ea: 681b ldr r3, [r3, #0] 80057ec: 021b lsls r3, r3, #8 80057ee: 68fa ldr r2, [r7, #12] 80057f0: 4313 orrs r3, r2 80057f2: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80057f4: 697b ldr r3, [r7, #20] 80057f6: f023 0320 bic.w r3, r3, #32 80057fa: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80057fc: 683b ldr r3, [r7, #0] 80057fe: 689b ldr r3, [r3, #8] 8005800: 011b lsls r3, r3, #4 8005802: 697a ldr r2, [r7, #20] 8005804: 4313 orrs r3, r2 8005806: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8005808: 687b ldr r3, [r7, #4] 800580a: 4a22 ldr r2, [pc, #136] @ (8005894 ) 800580c: 4293 cmp r3, r2 800580e: d003 beq.n 8005818 8005810: 687b ldr r3, [r7, #4] 8005812: 4a21 ldr r2, [pc, #132] @ (8005898 ) 8005814: 4293 cmp r3, r2 8005816: d10d bne.n 8005834 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8005818: 697b ldr r3, [r7, #20] 800581a: f023 0380 bic.w r3, r3, #128 @ 0x80 800581e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8005820: 683b ldr r3, [r7, #0] 8005822: 68db ldr r3, [r3, #12] 8005824: 011b lsls r3, r3, #4 8005826: 697a ldr r2, [r7, #20] 8005828: 4313 orrs r3, r2 800582a: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 800582c: 697b ldr r3, [r7, #20] 800582e: f023 0340 bic.w r3, r3, #64 @ 0x40 8005832: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005834: 687b ldr r3, [r7, #4] 8005836: 4a17 ldr r2, [pc, #92] @ (8005894 ) 8005838: 4293 cmp r3, r2 800583a: d003 beq.n 8005844 800583c: 687b ldr r3, [r7, #4] 800583e: 4a16 ldr r2, [pc, #88] @ (8005898 ) 8005840: 4293 cmp r3, r2 8005842: d113 bne.n 800586c /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8005844: 693b ldr r3, [r7, #16] 8005846: f423 6380 bic.w r3, r3, #1024 @ 0x400 800584a: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 800584c: 693b ldr r3, [r7, #16] 800584e: f423 6300 bic.w r3, r3, #2048 @ 0x800 8005852: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8005854: 683b ldr r3, [r7, #0] 8005856: 695b ldr r3, [r3, #20] 8005858: 009b lsls r3, r3, #2 800585a: 693a ldr r2, [r7, #16] 800585c: 4313 orrs r3, r2 800585e: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8005860: 683b ldr r3, [r7, #0] 8005862: 699b ldr r3, [r3, #24] 8005864: 009b lsls r3, r3, #2 8005866: 693a ldr r2, [r7, #16] 8005868: 4313 orrs r3, r2 800586a: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800586c: 687b ldr r3, [r7, #4] 800586e: 693a ldr r2, [r7, #16] 8005870: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8005872: 687b ldr r3, [r7, #4] 8005874: 68fa ldr r2, [r7, #12] 8005876: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8005878: 683b ldr r3, [r7, #0] 800587a: 685a ldr r2, [r3, #4] 800587c: 687b ldr r3, [r7, #4] 800587e: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005880: 687b ldr r3, [r7, #4] 8005882: 697a ldr r2, [r7, #20] 8005884: 621a str r2, [r3, #32] } 8005886: bf00 nop 8005888: 371c adds r7, #28 800588a: 46bd mov sp, r7 800588c: f85d 7b04 ldr.w r7, [sp], #4 8005890: 4770 bx lr 8005892: bf00 nop 8005894: 40010000 .word 0x40010000 8005898: 40010400 .word 0x40010400 0800589c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800589c: b480 push {r7} 800589e: b087 sub sp, #28 80058a0: af00 add r7, sp, #0 80058a2: 6078 str r0, [r7, #4] 80058a4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80058a6: 687b ldr r3, [r7, #4] 80058a8: 6a1b ldr r3, [r3, #32] 80058aa: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 80058ac: 687b ldr r3, [r7, #4] 80058ae: 6a1b ldr r3, [r3, #32] 80058b0: f423 7280 bic.w r2, r3, #256 @ 0x100 80058b4: 687b ldr r3, [r7, #4] 80058b6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80058b8: 687b ldr r3, [r7, #4] 80058ba: 685b ldr r3, [r3, #4] 80058bc: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80058be: 687b ldr r3, [r7, #4] 80058c0: 69db ldr r3, [r3, #28] 80058c2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 80058c4: 68fb ldr r3, [r7, #12] 80058c6: f023 0370 bic.w r3, r3, #112 @ 0x70 80058ca: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 80058cc: 68fb ldr r3, [r7, #12] 80058ce: f023 0303 bic.w r3, r3, #3 80058d2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80058d4: 683b ldr r3, [r7, #0] 80058d6: 681b ldr r3, [r3, #0] 80058d8: 68fa ldr r2, [r7, #12] 80058da: 4313 orrs r3, r2 80058dc: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80058de: 697b ldr r3, [r7, #20] 80058e0: f423 7300 bic.w r3, r3, #512 @ 0x200 80058e4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80058e6: 683b ldr r3, [r7, #0] 80058e8: 689b ldr r3, [r3, #8] 80058ea: 021b lsls r3, r3, #8 80058ec: 697a ldr r2, [r7, #20] 80058ee: 4313 orrs r3, r2 80058f0: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80058f2: 687b ldr r3, [r7, #4] 80058f4: 4a21 ldr r2, [pc, #132] @ (800597c ) 80058f6: 4293 cmp r3, r2 80058f8: d003 beq.n 8005902 80058fa: 687b ldr r3, [r7, #4] 80058fc: 4a20 ldr r2, [pc, #128] @ (8005980 ) 80058fe: 4293 cmp r3, r2 8005900: d10d bne.n 800591e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8005902: 697b ldr r3, [r7, #20] 8005904: f423 6300 bic.w r3, r3, #2048 @ 0x800 8005908: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 800590a: 683b ldr r3, [r7, #0] 800590c: 68db ldr r3, [r3, #12] 800590e: 021b lsls r3, r3, #8 8005910: 697a ldr r2, [r7, #20] 8005912: 4313 orrs r3, r2 8005914: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8005916: 697b ldr r3, [r7, #20] 8005918: f423 6380 bic.w r3, r3, #1024 @ 0x400 800591c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800591e: 687b ldr r3, [r7, #4] 8005920: 4a16 ldr r2, [pc, #88] @ (800597c ) 8005922: 4293 cmp r3, r2 8005924: d003 beq.n 800592e 8005926: 687b ldr r3, [r7, #4] 8005928: 4a15 ldr r2, [pc, #84] @ (8005980 ) 800592a: 4293 cmp r3, r2 800592c: d113 bne.n 8005956 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 800592e: 693b ldr r3, [r7, #16] 8005930: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8005934: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8005936: 693b ldr r3, [r7, #16] 8005938: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800593c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 800593e: 683b ldr r3, [r7, #0] 8005940: 695b ldr r3, [r3, #20] 8005942: 011b lsls r3, r3, #4 8005944: 693a ldr r2, [r7, #16] 8005946: 4313 orrs r3, r2 8005948: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800594a: 683b ldr r3, [r7, #0] 800594c: 699b ldr r3, [r3, #24] 800594e: 011b lsls r3, r3, #4 8005950: 693a ldr r2, [r7, #16] 8005952: 4313 orrs r3, r2 8005954: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005956: 687b ldr r3, [r7, #4] 8005958: 693a ldr r2, [r7, #16] 800595a: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800595c: 687b ldr r3, [r7, #4] 800595e: 68fa ldr r2, [r7, #12] 8005960: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8005962: 683b ldr r3, [r7, #0] 8005964: 685a ldr r2, [r3, #4] 8005966: 687b ldr r3, [r7, #4] 8005968: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800596a: 687b ldr r3, [r7, #4] 800596c: 697a ldr r2, [r7, #20] 800596e: 621a str r2, [r3, #32] } 8005970: bf00 nop 8005972: 371c adds r7, #28 8005974: 46bd mov sp, r7 8005976: f85d 7b04 ldr.w r7, [sp], #4 800597a: 4770 bx lr 800597c: 40010000 .word 0x40010000 8005980: 40010400 .word 0x40010400 08005984 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005984: b480 push {r7} 8005986: b087 sub sp, #28 8005988: af00 add r7, sp, #0 800598a: 6078 str r0, [r7, #4] 800598c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800598e: 687b ldr r3, [r7, #4] 8005990: 6a1b ldr r3, [r3, #32] 8005992: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8005994: 687b ldr r3, [r7, #4] 8005996: 6a1b ldr r3, [r3, #32] 8005998: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800599c: 687b ldr r3, [r7, #4] 800599e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80059a0: 687b ldr r3, [r7, #4] 80059a2: 685b ldr r3, [r3, #4] 80059a4: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80059a6: 687b ldr r3, [r7, #4] 80059a8: 69db ldr r3, [r3, #28] 80059aa: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 80059ac: 68fb ldr r3, [r7, #12] 80059ae: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80059b2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 80059b4: 68fb ldr r3, [r7, #12] 80059b6: f423 7340 bic.w r3, r3, #768 @ 0x300 80059ba: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80059bc: 683b ldr r3, [r7, #0] 80059be: 681b ldr r3, [r3, #0] 80059c0: 021b lsls r3, r3, #8 80059c2: 68fa ldr r2, [r7, #12] 80059c4: 4313 orrs r3, r2 80059c6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 80059c8: 693b ldr r3, [r7, #16] 80059ca: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80059ce: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 80059d0: 683b ldr r3, [r7, #0] 80059d2: 689b ldr r3, [r3, #8] 80059d4: 031b lsls r3, r3, #12 80059d6: 693a ldr r2, [r7, #16] 80059d8: 4313 orrs r3, r2 80059da: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 80059dc: 687b ldr r3, [r7, #4] 80059de: 4a12 ldr r2, [pc, #72] @ (8005a28 ) 80059e0: 4293 cmp r3, r2 80059e2: d003 beq.n 80059ec 80059e4: 687b ldr r3, [r7, #4] 80059e6: 4a11 ldr r2, [pc, #68] @ (8005a2c ) 80059e8: 4293 cmp r3, r2 80059ea: d109 bne.n 8005a00 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 80059ec: 697b ldr r3, [r7, #20] 80059ee: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80059f2: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 80059f4: 683b ldr r3, [r7, #0] 80059f6: 695b ldr r3, [r3, #20] 80059f8: 019b lsls r3, r3, #6 80059fa: 697a ldr r2, [r7, #20] 80059fc: 4313 orrs r3, r2 80059fe: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005a00: 687b ldr r3, [r7, #4] 8005a02: 697a ldr r2, [r7, #20] 8005a04: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8005a06: 687b ldr r3, [r7, #4] 8005a08: 68fa ldr r2, [r7, #12] 8005a0a: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8005a0c: 683b ldr r3, [r7, #0] 8005a0e: 685a ldr r2, [r3, #4] 8005a10: 687b ldr r3, [r7, #4] 8005a12: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005a14: 687b ldr r3, [r7, #4] 8005a16: 693a ldr r2, [r7, #16] 8005a18: 621a str r2, [r3, #32] } 8005a1a: bf00 nop 8005a1c: 371c adds r7, #28 8005a1e: 46bd mov sp, r7 8005a20: f85d 7b04 ldr.w r7, [sp], #4 8005a24: 4770 bx lr 8005a26: bf00 nop 8005a28: 40010000 .word 0x40010000 8005a2c: 40010400 .word 0x40010400 08005a30 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8005a30: b480 push {r7} 8005a32: b085 sub sp, #20 8005a34: af00 add r7, sp, #0 8005a36: 6078 str r0, [r7, #4] 8005a38: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8005a3a: 687b ldr r3, [r7, #4] 8005a3c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005a40: 2b01 cmp r3, #1 8005a42: d101 bne.n 8005a48 8005a44: 2302 movs r3, #2 8005a46: e05a b.n 8005afe 8005a48: 687b ldr r3, [r7, #4] 8005a4a: 2201 movs r2, #1 8005a4c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005a50: 687b ldr r3, [r7, #4] 8005a52: 2202 movs r2, #2 8005a54: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8005a58: 687b ldr r3, [r7, #4] 8005a5a: 681b ldr r3, [r3, #0] 8005a5c: 685b ldr r3, [r3, #4] 8005a5e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005a60: 687b ldr r3, [r7, #4] 8005a62: 681b ldr r3, [r3, #0] 8005a64: 689b ldr r3, [r3, #8] 8005a66: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8005a68: 68fb ldr r3, [r7, #12] 8005a6a: f023 0370 bic.w r3, r3, #112 @ 0x70 8005a6e: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005a70: 683b ldr r3, [r7, #0] 8005a72: 681b ldr r3, [r3, #0] 8005a74: 68fa ldr r2, [r7, #12] 8005a76: 4313 orrs r3, r2 8005a78: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8005a7a: 687b ldr r3, [r7, #4] 8005a7c: 681b ldr r3, [r3, #0] 8005a7e: 68fa ldr r2, [r7, #12] 8005a80: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005a82: 687b ldr r3, [r7, #4] 8005a84: 681b ldr r3, [r3, #0] 8005a86: 4a21 ldr r2, [pc, #132] @ (8005b0c ) 8005a88: 4293 cmp r3, r2 8005a8a: d022 beq.n 8005ad2 8005a8c: 687b ldr r3, [r7, #4] 8005a8e: 681b ldr r3, [r3, #0] 8005a90: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005a94: d01d beq.n 8005ad2 8005a96: 687b ldr r3, [r7, #4] 8005a98: 681b ldr r3, [r3, #0] 8005a9a: 4a1d ldr r2, [pc, #116] @ (8005b10 ) 8005a9c: 4293 cmp r3, r2 8005a9e: d018 beq.n 8005ad2 8005aa0: 687b ldr r3, [r7, #4] 8005aa2: 681b ldr r3, [r3, #0] 8005aa4: 4a1b ldr r2, [pc, #108] @ (8005b14 ) 8005aa6: 4293 cmp r3, r2 8005aa8: d013 beq.n 8005ad2 8005aaa: 687b ldr r3, [r7, #4] 8005aac: 681b ldr r3, [r3, #0] 8005aae: 4a1a ldr r2, [pc, #104] @ (8005b18 ) 8005ab0: 4293 cmp r3, r2 8005ab2: d00e beq.n 8005ad2 8005ab4: 687b ldr r3, [r7, #4] 8005ab6: 681b ldr r3, [r3, #0] 8005ab8: 4a18 ldr r2, [pc, #96] @ (8005b1c ) 8005aba: 4293 cmp r3, r2 8005abc: d009 beq.n 8005ad2 8005abe: 687b ldr r3, [r7, #4] 8005ac0: 681b ldr r3, [r3, #0] 8005ac2: 4a17 ldr r2, [pc, #92] @ (8005b20 ) 8005ac4: 4293 cmp r3, r2 8005ac6: d004 beq.n 8005ad2 8005ac8: 687b ldr r3, [r7, #4] 8005aca: 681b ldr r3, [r3, #0] 8005acc: 4a15 ldr r2, [pc, #84] @ (8005b24 ) 8005ace: 4293 cmp r3, r2 8005ad0: d10c bne.n 8005aec { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8005ad2: 68bb ldr r3, [r7, #8] 8005ad4: f023 0380 bic.w r3, r3, #128 @ 0x80 8005ad8: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8005ada: 683b ldr r3, [r7, #0] 8005adc: 685b ldr r3, [r3, #4] 8005ade: 68ba ldr r2, [r7, #8] 8005ae0: 4313 orrs r3, r2 8005ae2: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005ae4: 687b ldr r3, [r7, #4] 8005ae6: 681b ldr r3, [r3, #0] 8005ae8: 68ba ldr r2, [r7, #8] 8005aea: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8005aec: 687b ldr r3, [r7, #4] 8005aee: 2201 movs r2, #1 8005af0: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8005af4: 687b ldr r3, [r7, #4] 8005af6: 2200 movs r2, #0 8005af8: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8005afc: 2300 movs r3, #0 } 8005afe: 4618 mov r0, r3 8005b00: 3714 adds r7, #20 8005b02: 46bd mov sp, r7 8005b04: f85d 7b04 ldr.w r7, [sp], #4 8005b08: 4770 bx lr 8005b0a: bf00 nop 8005b0c: 40010000 .word 0x40010000 8005b10: 40000400 .word 0x40000400 8005b14: 40000800 .word 0x40000800 8005b18: 40000c00 .word 0x40000c00 8005b1c: 40010400 .word 0x40010400 8005b20: 40014000 .word 0x40014000 8005b24: 40001800 .word 0x40001800 08005b28 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8005b28: b580 push {r7, lr} 8005b2a: b082 sub sp, #8 8005b2c: af00 add r7, sp, #0 8005b2e: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8005b30: 687b ldr r3, [r7, #4] 8005b32: 2b00 cmp r3, #0 8005b34: d101 bne.n 8005b3a { return HAL_ERROR; 8005b36: 2301 movs r3, #1 8005b38: e042 b.n 8005bc0 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 8005b3a: 687b ldr r3, [r7, #4] 8005b3c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005b40: b2db uxtb r3, r3 8005b42: 2b00 cmp r3, #0 8005b44: d106 bne.n 8005b54 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8005b46: 687b ldr r3, [r7, #4] 8005b48: 2200 movs r2, #0 8005b4a: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005b4e: 6878 ldr r0, [r7, #4] 8005b50: f7fb fc8e bl 8001470 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005b54: 687b ldr r3, [r7, #4] 8005b56: 2224 movs r2, #36 @ 0x24 8005b58: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005b5c: 687b ldr r3, [r7, #4] 8005b5e: 681b ldr r3, [r3, #0] 8005b60: 68da ldr r2, [r3, #12] 8005b62: 687b ldr r3, [r7, #4] 8005b64: 681b ldr r3, [r3, #0] 8005b66: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8005b6a: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005b6c: 6878 ldr r0, [r7, #4] 8005b6e: f000 ff63 bl 8006a38 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005b72: 687b ldr r3, [r7, #4] 8005b74: 681b ldr r3, [r3, #0] 8005b76: 691a ldr r2, [r3, #16] 8005b78: 687b ldr r3, [r7, #4] 8005b7a: 681b ldr r3, [r3, #0] 8005b7c: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8005b80: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005b82: 687b ldr r3, [r7, #4] 8005b84: 681b ldr r3, [r3, #0] 8005b86: 695a ldr r2, [r3, #20] 8005b88: 687b ldr r3, [r7, #4] 8005b8a: 681b ldr r3, [r3, #0] 8005b8c: f022 022a bic.w r2, r2, #42 @ 0x2a 8005b90: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005b92: 687b ldr r3, [r7, #4] 8005b94: 681b ldr r3, [r3, #0] 8005b96: 68da ldr r2, [r3, #12] 8005b98: 687b ldr r3, [r7, #4] 8005b9a: 681b ldr r3, [r3, #0] 8005b9c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8005ba0: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005ba2: 687b ldr r3, [r7, #4] 8005ba4: 2200 movs r2, #0 8005ba6: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 2220 movs r2, #32 8005bac: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8005bb0: 687b ldr r3, [r7, #4] 8005bb2: 2220 movs r2, #32 8005bb4: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8005bb8: 687b ldr r3, [r7, #4] 8005bba: 2200 movs r2, #0 8005bbc: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8005bbe: 2300 movs r3, #0 } 8005bc0: 4618 mov r0, r3 8005bc2: 3708 adds r7, #8 8005bc4: 46bd mov sp, r7 8005bc6: bd80 pop {r7, pc} 08005bc8 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8005bc8: b580 push {r7, lr} 8005bca: b08c sub sp, #48 @ 0x30 8005bcc: af00 add r7, sp, #0 8005bce: 60f8 str r0, [r7, #12] 8005bd0: 60b9 str r1, [r7, #8] 8005bd2: 4613 mov r3, r2 8005bd4: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8005bd6: 68fb ldr r3, [r7, #12] 8005bd8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005bdc: b2db uxtb r3, r3 8005bde: 2b20 cmp r3, #32 8005be0: d162 bne.n 8005ca8 { if ((pData == NULL) || (Size == 0U)) 8005be2: 68bb ldr r3, [r7, #8] 8005be4: 2b00 cmp r3, #0 8005be6: d002 beq.n 8005bee 8005be8: 88fb ldrh r3, [r7, #6] 8005bea: 2b00 cmp r3, #0 8005bec: d101 bne.n 8005bf2 { return HAL_ERROR; 8005bee: 2301 movs r3, #1 8005bf0: e05b b.n 8005caa } huart->pTxBuffPtr = pData; 8005bf2: 68ba ldr r2, [r7, #8] 8005bf4: 68fb ldr r3, [r7, #12] 8005bf6: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8005bf8: 68fb ldr r3, [r7, #12] 8005bfa: 88fa ldrh r2, [r7, #6] 8005bfc: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8005bfe: 68fb ldr r3, [r7, #12] 8005c00: 88fa ldrh r2, [r7, #6] 8005c02: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8005c04: 68fb ldr r3, [r7, #12] 8005c06: 2200 movs r2, #0 8005c08: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8005c0a: 68fb ldr r3, [r7, #12] 8005c0c: 2221 movs r2, #33 @ 0x21 8005c0e: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8005c12: 68fb ldr r3, [r7, #12] 8005c14: 6b9b ldr r3, [r3, #56] @ 0x38 8005c16: 4a27 ldr r2, [pc, #156] @ (8005cb4 ) 8005c18: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8005c1a: 68fb ldr r3, [r7, #12] 8005c1c: 6b9b ldr r3, [r3, #56] @ 0x38 8005c1e: 4a26 ldr r2, [pc, #152] @ (8005cb8 ) 8005c20: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8005c22: 68fb ldr r3, [r7, #12] 8005c24: 6b9b ldr r3, [r3, #56] @ 0x38 8005c26: 4a25 ldr r2, [pc, #148] @ (8005cbc ) 8005c28: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8005c2a: 68fb ldr r3, [r7, #12] 8005c2c: 6b9b ldr r3, [r3, #56] @ 0x38 8005c2e: 2200 movs r2, #0 8005c30: 651a str r2, [r3, #80] @ 0x50 /* Enable the UART transmit DMA stream */ tmp = (const uint32_t *)&pData; 8005c32: f107 0308 add.w r3, r7, #8 8005c36: 62fb str r3, [r7, #44] @ 0x2c if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) 8005c38: 68fb ldr r3, [r7, #12] 8005c3a: 6b98 ldr r0, [r3, #56] @ 0x38 8005c3c: 6afb ldr r3, [r7, #44] @ 0x2c 8005c3e: 6819 ldr r1, [r3, #0] 8005c40: 68fb ldr r3, [r7, #12] 8005c42: 681b ldr r3, [r3, #0] 8005c44: 3304 adds r3, #4 8005c46: 461a mov r2, r3 8005c48: 88fb ldrh r3, [r7, #6] 8005c4a: f7fc f953 bl 8001ef4 8005c4e: 4603 mov r3, r0 8005c50: 2b00 cmp r3, #0 8005c52: d008 beq.n 8005c66 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8005c54: 68fb ldr r3, [r7, #12] 8005c56: 2210 movs r2, #16 8005c58: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 8005c5a: 68fb ldr r3, [r7, #12] 8005c5c: 2220 movs r2, #32 8005c5e: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_ERROR; 8005c62: 2301 movs r3, #1 8005c64: e021 b.n 8005caa } /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8005c66: 68fb ldr r3, [r7, #12] 8005c68: 681b ldr r3, [r3, #0] 8005c6a: f06f 0240 mvn.w r2, #64 @ 0x40 8005c6e: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8005c70: 68fb ldr r3, [r7, #12] 8005c72: 681b ldr r3, [r3, #0] 8005c74: 3314 adds r3, #20 8005c76: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005c78: 69bb ldr r3, [r7, #24] 8005c7a: e853 3f00 ldrex r3, [r3] 8005c7e: 617b str r3, [r7, #20] return(result); 8005c80: 697b ldr r3, [r7, #20] 8005c82: f043 0380 orr.w r3, r3, #128 @ 0x80 8005c86: 62bb str r3, [r7, #40] @ 0x28 8005c88: 68fb ldr r3, [r7, #12] 8005c8a: 681b ldr r3, [r3, #0] 8005c8c: 3314 adds r3, #20 8005c8e: 6aba ldr r2, [r7, #40] @ 0x28 8005c90: 627a str r2, [r7, #36] @ 0x24 8005c92: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005c94: 6a39 ldr r1, [r7, #32] 8005c96: 6a7a ldr r2, [r7, #36] @ 0x24 8005c98: e841 2300 strex r3, r2, [r1] 8005c9c: 61fb str r3, [r7, #28] return(result); 8005c9e: 69fb ldr r3, [r7, #28] 8005ca0: 2b00 cmp r3, #0 8005ca2: d1e5 bne.n 8005c70 return HAL_OK; 8005ca4: 2300 movs r3, #0 8005ca6: e000 b.n 8005caa } else { return HAL_BUSY; 8005ca8: 2302 movs r3, #2 } } 8005caa: 4618 mov r0, r3 8005cac: 3730 adds r7, #48 @ 0x30 8005cae: 46bd mov sp, r7 8005cb0: bd80 pop {r7, pc} 8005cb2: bf00 nop 8005cb4: 080062b5 .word 0x080062b5 8005cb8: 0800634f .word 0x0800634f 8005cbc: 080064d3 .word 0x080064d3 08005cc0 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8005cc0: b580 push {r7, lr} 8005cc2: b084 sub sp, #16 8005cc4: af00 add r7, sp, #0 8005cc6: 60f8 str r0, [r7, #12] 8005cc8: 60b9 str r1, [r7, #8] 8005cca: 4613 mov r3, r2 8005ccc: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8005cce: 68fb ldr r3, [r7, #12] 8005cd0: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8005cd4: b2db uxtb r3, r3 8005cd6: 2b20 cmp r3, #32 8005cd8: d112 bne.n 8005d00 { if ((pData == NULL) || (Size == 0U)) 8005cda: 68bb ldr r3, [r7, #8] 8005cdc: 2b00 cmp r3, #0 8005cde: d002 beq.n 8005ce6 8005ce0: 88fb ldrh r3, [r7, #6] 8005ce2: 2b00 cmp r3, #0 8005ce4: d101 bne.n 8005cea { return HAL_ERROR; 8005ce6: 2301 movs r3, #1 8005ce8: e00b b.n 8005d02 } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005cea: 68fb ldr r3, [r7, #12] 8005cec: 2200 movs r2, #0 8005cee: 631a str r2, [r3, #48] @ 0x30 return (UART_Start_Receive_DMA(huart, pData, Size)); 8005cf0: 88fb ldrh r3, [r7, #6] 8005cf2: 461a mov r2, r3 8005cf4: 68b9 ldr r1, [r7, #8] 8005cf6: 68f8 ldr r0, [r7, #12] 8005cf8: f000 fc36 bl 8006568 8005cfc: 4603 mov r3, r0 8005cfe: e000 b.n 8005d02 } else { return HAL_BUSY; 8005d00: 2302 movs r3, #2 } } 8005d02: 4618 mov r0, r3 8005d04: 3710 adds r7, #16 8005d06: 46bd mov sp, r7 8005d08: bd80 pop {r7, pc} ... 08005d0c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8005d0c: b580 push {r7, lr} 8005d0e: b0ba sub sp, #232 @ 0xe8 8005d10: af00 add r7, sp, #0 8005d12: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8005d14: 687b ldr r3, [r7, #4] 8005d16: 681b ldr r3, [r3, #0] 8005d18: 681b ldr r3, [r3, #0] 8005d1a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8005d1e: 687b ldr r3, [r7, #4] 8005d20: 681b ldr r3, [r3, #0] 8005d22: 68db ldr r3, [r3, #12] 8005d24: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8005d28: 687b ldr r3, [r7, #4] 8005d2a: 681b ldr r3, [r3, #0] 8005d2c: 695b ldr r3, [r3, #20] 8005d2e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8005d32: 2300 movs r3, #0 8005d34: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8005d38: 2300 movs r3, #0 8005d3a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8005d3e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d42: f003 030f and.w r3, r3, #15 8005d46: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8005d4a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005d4e: 2b00 cmp r3, #0 8005d50: d10f bne.n 8005d72 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005d52: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d56: f003 0320 and.w r3, r3, #32 8005d5a: 2b00 cmp r3, #0 8005d5c: d009 beq.n 8005d72 8005d5e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005d62: f003 0320 and.w r3, r3, #32 8005d66: 2b00 cmp r3, #0 8005d68: d003 beq.n 8005d72 { UART_Receive_IT(huart); 8005d6a: 6878 ldr r0, [r7, #4] 8005d6c: f000 fda6 bl 80068bc return; 8005d70: e273 b.n 800625a } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8005d72: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005d76: 2b00 cmp r3, #0 8005d78: f000 80de beq.w 8005f38 8005d7c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005d80: f003 0301 and.w r3, r3, #1 8005d84: 2b00 cmp r3, #0 8005d86: d106 bne.n 8005d96 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8005d88: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005d8c: f403 7390 and.w r3, r3, #288 @ 0x120 8005d90: 2b00 cmp r3, #0 8005d92: f000 80d1 beq.w 8005f38 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8005d96: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d9a: f003 0301 and.w r3, r3, #1 8005d9e: 2b00 cmp r3, #0 8005da0: d00b beq.n 8005dba 8005da2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005da6: f403 7380 and.w r3, r3, #256 @ 0x100 8005daa: 2b00 cmp r3, #0 8005dac: d005 beq.n 8005dba { huart->ErrorCode |= HAL_UART_ERROR_PE; 8005dae: 687b ldr r3, [r7, #4] 8005db0: 6c5b ldr r3, [r3, #68] @ 0x44 8005db2: f043 0201 orr.w r2, r3, #1 8005db6: 687b ldr r3, [r7, #4] 8005db8: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005dba: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005dbe: f003 0304 and.w r3, r3, #4 8005dc2: 2b00 cmp r3, #0 8005dc4: d00b beq.n 8005dde 8005dc6: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005dca: f003 0301 and.w r3, r3, #1 8005dce: 2b00 cmp r3, #0 8005dd0: d005 beq.n 8005dde { huart->ErrorCode |= HAL_UART_ERROR_NE; 8005dd2: 687b ldr r3, [r7, #4] 8005dd4: 6c5b ldr r3, [r3, #68] @ 0x44 8005dd6: f043 0202 orr.w r2, r3, #2 8005dda: 687b ldr r3, [r7, #4] 8005ddc: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005dde: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005de2: f003 0302 and.w r3, r3, #2 8005de6: 2b00 cmp r3, #0 8005de8: d00b beq.n 8005e02 8005dea: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005dee: f003 0301 and.w r3, r3, #1 8005df2: 2b00 cmp r3, #0 8005df4: d005 beq.n 8005e02 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8005df6: 687b ldr r3, [r7, #4] 8005df8: 6c5b ldr r3, [r3, #68] @ 0x44 8005dfa: f043 0204 orr.w r2, r3, #4 8005dfe: 687b ldr r3, [r7, #4] 8005e00: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8005e02: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e06: f003 0308 and.w r3, r3, #8 8005e0a: 2b00 cmp r3, #0 8005e0c: d011 beq.n 8005e32 8005e0e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005e12: f003 0320 and.w r3, r3, #32 8005e16: 2b00 cmp r3, #0 8005e18: d105 bne.n 8005e26 || ((cr3its & USART_CR3_EIE) != RESET))) 8005e1a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005e1e: f003 0301 and.w r3, r3, #1 8005e22: 2b00 cmp r3, #0 8005e24: d005 beq.n 8005e32 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8005e26: 687b ldr r3, [r7, #4] 8005e28: 6c5b ldr r3, [r3, #68] @ 0x44 8005e2a: f043 0208 orr.w r2, r3, #8 8005e2e: 687b ldr r3, [r7, #4] 8005e30: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8005e32: 687b ldr r3, [r7, #4] 8005e34: 6c5b ldr r3, [r3, #68] @ 0x44 8005e36: 2b00 cmp r3, #0 8005e38: f000 820a beq.w 8006250 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005e3c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e40: f003 0320 and.w r3, r3, #32 8005e44: 2b00 cmp r3, #0 8005e46: d008 beq.n 8005e5a 8005e48: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005e4c: f003 0320 and.w r3, r3, #32 8005e50: 2b00 cmp r3, #0 8005e52: d002 beq.n 8005e5a { UART_Receive_IT(huart); 8005e54: 6878 ldr r0, [r7, #4] 8005e56: f000 fd31 bl 80068bc } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8005e5a: 687b ldr r3, [r7, #4] 8005e5c: 681b ldr r3, [r3, #0] 8005e5e: 695b ldr r3, [r3, #20] 8005e60: f003 0340 and.w r3, r3, #64 @ 0x40 8005e64: 2b40 cmp r3, #64 @ 0x40 8005e66: bf0c ite eq 8005e68: 2301 moveq r3, #1 8005e6a: 2300 movne r3, #0 8005e6c: b2db uxtb r3, r3 8005e6e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8005e72: 687b ldr r3, [r7, #4] 8005e74: 6c5b ldr r3, [r3, #68] @ 0x44 8005e76: f003 0308 and.w r3, r3, #8 8005e7a: 2b00 cmp r3, #0 8005e7c: d103 bne.n 8005e86 8005e7e: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8005e82: 2b00 cmp r3, #0 8005e84: d04f beq.n 8005f26 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8005e86: 6878 ldr r0, [r7, #4] 8005e88: f000 fc3c bl 8006704 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005e8c: 687b ldr r3, [r7, #4] 8005e8e: 681b ldr r3, [r3, #0] 8005e90: 695b ldr r3, [r3, #20] 8005e92: f003 0340 and.w r3, r3, #64 @ 0x40 8005e96: 2b40 cmp r3, #64 @ 0x40 8005e98: d141 bne.n 8005f1e { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005e9a: 687b ldr r3, [r7, #4] 8005e9c: 681b ldr r3, [r3, #0] 8005e9e: 3314 adds r3, #20 8005ea0: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005ea4: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8005ea8: e853 3f00 ldrex r3, [r3] 8005eac: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8005eb0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8005eb4: f023 0340 bic.w r3, r3, #64 @ 0x40 8005eb8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8005ebc: 687b ldr r3, [r7, #4] 8005ebe: 681b ldr r3, [r3, #0] 8005ec0: 3314 adds r3, #20 8005ec2: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8005ec6: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8005eca: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005ece: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8005ed2: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8005ed6: e841 2300 strex r3, r2, [r1] 8005eda: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8005ede: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8005ee2: 2b00 cmp r3, #0 8005ee4: d1d9 bne.n 8005e9a /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) 8005ee6: 687b ldr r3, [r7, #4] 8005ee8: 6bdb ldr r3, [r3, #60] @ 0x3c 8005eea: 2b00 cmp r3, #0 8005eec: d013 beq.n 8005f16 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8005eee: 687b ldr r3, [r7, #4] 8005ef0: 6bdb ldr r3, [r3, #60] @ 0x3c 8005ef2: 4a8a ldr r2, [pc, #552] @ (800611c ) 8005ef4: 651a str r2, [r3, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8005ef6: 687b ldr r3, [r7, #4] 8005ef8: 6bdb ldr r3, [r3, #60] @ 0x3c 8005efa: 4618 mov r0, r3 8005efc: f7fc f8c2 bl 8002084 8005f00: 4603 mov r3, r0 8005f02: 2b00 cmp r3, #0 8005f04: d016 beq.n 8005f34 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8005f06: 687b ldr r3, [r7, #4] 8005f08: 6bdb ldr r3, [r3, #60] @ 0x3c 8005f0a: 6d1b ldr r3, [r3, #80] @ 0x50 8005f0c: 687a ldr r2, [r7, #4] 8005f0e: 6bd2 ldr r2, [r2, #60] @ 0x3c 8005f10: 4610 mov r0, r2 8005f12: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f14: e00e b.n 8005f34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005f16: 6878 ldr r0, [r7, #4] 8005f18: f7fa fe1e bl 8000b58 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f1c: e00a b.n 8005f34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005f1e: 6878 ldr r0, [r7, #4] 8005f20: f7fa fe1a bl 8000b58 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f24: e006 b.n 8005f34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005f26: 6878 ldr r0, [r7, #4] 8005f28: f7fa fe16 bl 8000b58 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005f2c: 687b ldr r3, [r7, #4] 8005f2e: 2200 movs r2, #0 8005f30: 645a str r2, [r3, #68] @ 0x44 } } return; 8005f32: e18d b.n 8006250 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f34: bf00 nop return; 8005f36: e18b b.n 8006250 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005f38: 687b ldr r3, [r7, #4] 8005f3a: 6b1b ldr r3, [r3, #48] @ 0x30 8005f3c: 2b01 cmp r3, #1 8005f3e: f040 8167 bne.w 8006210 && ((isrflags & USART_SR_IDLE) != 0U) 8005f42: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005f46: f003 0310 and.w r3, r3, #16 8005f4a: 2b00 cmp r3, #0 8005f4c: f000 8160 beq.w 8006210 && ((cr1its & USART_CR1_IDLEIE) != 0U)) 8005f50: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005f54: f003 0310 and.w r3, r3, #16 8005f58: 2b00 cmp r3, #0 8005f5a: f000 8159 beq.w 8006210 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8005f5e: 2300 movs r3, #0 8005f60: 60bb str r3, [r7, #8] 8005f62: 687b ldr r3, [r7, #4] 8005f64: 681b ldr r3, [r3, #0] 8005f66: 681b ldr r3, [r3, #0] 8005f68: 60bb str r3, [r7, #8] 8005f6a: 687b ldr r3, [r7, #4] 8005f6c: 681b ldr r3, [r3, #0] 8005f6e: 685b ldr r3, [r3, #4] 8005f70: 60bb str r3, [r7, #8] 8005f72: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f74: 687b ldr r3, [r7, #4] 8005f76: 681b ldr r3, [r3, #0] 8005f78: 695b ldr r3, [r3, #20] 8005f7a: f003 0340 and.w r3, r3, #64 @ 0x40 8005f7e: 2b40 cmp r3, #64 @ 0x40 8005f80: f040 80ce bne.w 8006120 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8005f84: 687b ldr r3, [r7, #4] 8005f86: 6bdb ldr r3, [r3, #60] @ 0x3c 8005f88: 681b ldr r3, [r3, #0] 8005f8a: 685b ldr r3, [r3, #4] 8005f8c: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8005f90: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8005f94: 2b00 cmp r3, #0 8005f96: f000 80a9 beq.w 80060ec && (nb_remaining_rx_data < huart->RxXferSize)) 8005f9a: 687b ldr r3, [r7, #4] 8005f9c: 8d9b ldrh r3, [r3, #44] @ 0x2c 8005f9e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005fa2: 429a cmp r2, r3 8005fa4: f080 80a2 bcs.w 80060ec { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8005fa8: 687b ldr r3, [r7, #4] 8005faa: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005fae: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8005fb0: 687b ldr r3, [r7, #4] 8005fb2: 6bdb ldr r3, [r3, #60] @ 0x3c 8005fb4: 69db ldr r3, [r3, #28] 8005fb6: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005fba: f000 8088 beq.w 80060ce { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005fbe: 687b ldr r3, [r7, #4] 8005fc0: 681b ldr r3, [r3, #0] 8005fc2: 330c adds r3, #12 8005fc4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005fc8: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005fcc: e853 3f00 ldrex r3, [r3] 8005fd0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8005fd4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005fd8: f423 7380 bic.w r3, r3, #256 @ 0x100 8005fdc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8005fe0: 687b ldr r3, [r7, #4] 8005fe2: 681b ldr r3, [r3, #0] 8005fe4: 330c adds r3, #12 8005fe6: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8005fea: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8005fee: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005ff2: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8005ff6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8005ffa: e841 2300 strex r3, r2, [r1] 8005ffe: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8006002: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8006006: 2b00 cmp r3, #0 8006008: d1d9 bne.n 8005fbe ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800600a: 687b ldr r3, [r7, #4] 800600c: 681b ldr r3, [r3, #0] 800600e: 3314 adds r3, #20 8006010: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006012: 6f7b ldr r3, [r7, #116] @ 0x74 8006014: e853 3f00 ldrex r3, [r3] 8006018: 673b str r3, [r7, #112] @ 0x70 return(result); 800601a: 6f3b ldr r3, [r7, #112] @ 0x70 800601c: f023 0301 bic.w r3, r3, #1 8006020: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006024: 687b ldr r3, [r7, #4] 8006026: 681b ldr r3, [r3, #0] 8006028: 3314 adds r3, #20 800602a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 800602e: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8006032: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006034: 6ff9 ldr r1, [r7, #124] @ 0x7c 8006036: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 800603a: e841 2300 strex r3, r2, [r1] 800603e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8006040: 6fbb ldr r3, [r7, #120] @ 0x78 8006042: 2b00 cmp r3, #0 8006044: d1e1 bne.n 800600a /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006046: 687b ldr r3, [r7, #4] 8006048: 681b ldr r3, [r3, #0] 800604a: 3314 adds r3, #20 800604c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800604e: 6e3b ldr r3, [r7, #96] @ 0x60 8006050: e853 3f00 ldrex r3, [r3] 8006054: 65fb str r3, [r7, #92] @ 0x5c return(result); 8006056: 6dfb ldr r3, [r7, #92] @ 0x5c 8006058: f023 0340 bic.w r3, r3, #64 @ 0x40 800605c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8006060: 687b ldr r3, [r7, #4] 8006062: 681b ldr r3, [r3, #0] 8006064: 3314 adds r3, #20 8006066: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 800606a: 66fa str r2, [r7, #108] @ 0x6c 800606c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800606e: 6eb9 ldr r1, [r7, #104] @ 0x68 8006070: 6efa ldr r2, [r7, #108] @ 0x6c 8006072: e841 2300 strex r3, r2, [r1] 8006076: 667b str r3, [r7, #100] @ 0x64 return(result); 8006078: 6e7b ldr r3, [r7, #100] @ 0x64 800607a: 2b00 cmp r3, #0 800607c: d1e3 bne.n 8006046 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800607e: 687b ldr r3, [r7, #4] 8006080: 2220 movs r2, #32 8006082: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006086: 687b ldr r3, [r7, #4] 8006088: 2200 movs r2, #0 800608a: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800608c: 687b ldr r3, [r7, #4] 800608e: 681b ldr r3, [r3, #0] 8006090: 330c adds r3, #12 8006092: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006094: 6cfb ldr r3, [r7, #76] @ 0x4c 8006096: e853 3f00 ldrex r3, [r3] 800609a: 64bb str r3, [r7, #72] @ 0x48 return(result); 800609c: 6cbb ldr r3, [r7, #72] @ 0x48 800609e: f023 0310 bic.w r3, r3, #16 80060a2: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80060a6: 687b ldr r3, [r7, #4] 80060a8: 681b ldr r3, [r3, #0] 80060aa: 330c adds r3, #12 80060ac: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 80060b0: 65ba str r2, [r7, #88] @ 0x58 80060b2: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80060b4: 6d79 ldr r1, [r7, #84] @ 0x54 80060b6: 6dba ldr r2, [r7, #88] @ 0x58 80060b8: e841 2300 strex r3, r2, [r1] 80060bc: 653b str r3, [r7, #80] @ 0x50 return(result); 80060be: 6d3b ldr r3, [r7, #80] @ 0x50 80060c0: 2b00 cmp r3, #0 80060c2: d1e3 bne.n 800608c /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 80060c4: 687b ldr r3, [r7, #4] 80060c6: 6bdb ldr r3, [r3, #60] @ 0x3c 80060c8: 4618 mov r0, r3 80060ca: f7fb ff6b bl 8001fa4 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80060ce: 687b ldr r3, [r7, #4] 80060d0: 2202 movs r2, #2 80060d2: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 80060d4: 687b ldr r3, [r7, #4] 80060d6: 8d9a ldrh r2, [r3, #44] @ 0x2c 80060d8: 687b ldr r3, [r7, #4] 80060da: 8ddb ldrh r3, [r3, #46] @ 0x2e 80060dc: b29b uxth r3, r3 80060de: 1ad3 subs r3, r2, r3 80060e0: b29b uxth r3, r3 80060e2: 4619 mov r1, r3 80060e4: 6878 ldr r0, [r7, #4] 80060e6: f000 f8d9 bl 800629c HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 80060ea: e0b3 b.n 8006254 if (nb_remaining_rx_data == huart->RxXferSize) 80060ec: 687b ldr r3, [r7, #4] 80060ee: 8d9b ldrh r3, [r3, #44] @ 0x2c 80060f0: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80060f4: 429a cmp r2, r3 80060f6: f040 80ad bne.w 8006254 if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 80060fa: 687b ldr r3, [r7, #4] 80060fc: 6bdb ldr r3, [r3, #60] @ 0x3c 80060fe: 69db ldr r3, [r3, #28] 8006100: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006104: f040 80a6 bne.w 8006254 huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006108: 687b ldr r3, [r7, #4] 800610a: 2202 movs r2, #2 800610c: 635a str r2, [r3, #52] @ 0x34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800610e: 687b ldr r3, [r7, #4] 8006110: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006112: 4619 mov r1, r3 8006114: 6878 ldr r0, [r7, #4] 8006116: f000 f8c1 bl 800629c return; 800611a: e09b b.n 8006254 800611c: 080067cb .word 0x080067cb else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8006120: 687b ldr r3, [r7, #4] 8006122: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006124: 687b ldr r3, [r7, #4] 8006126: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006128: b29b uxth r3, r3 800612a: 1ad3 subs r3, r2, r3 800612c: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8006130: 687b ldr r3, [r7, #4] 8006132: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006134: b29b uxth r3, r3 8006136: 2b00 cmp r3, #0 8006138: f000 808e beq.w 8006258 && (nb_rx_data > 0U)) 800613c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006140: 2b00 cmp r3, #0 8006142: f000 8089 beq.w 8006258 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006146: 687b ldr r3, [r7, #4] 8006148: 681b ldr r3, [r3, #0] 800614a: 330c adds r3, #12 800614c: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800614e: 6bbb ldr r3, [r7, #56] @ 0x38 8006150: e853 3f00 ldrex r3, [r3] 8006154: 637b str r3, [r7, #52] @ 0x34 return(result); 8006156: 6b7b ldr r3, [r7, #52] @ 0x34 8006158: f423 7390 bic.w r3, r3, #288 @ 0x120 800615c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006160: 687b ldr r3, [r7, #4] 8006162: 681b ldr r3, [r3, #0] 8006164: 330c adds r3, #12 8006166: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 800616a: 647a str r2, [r7, #68] @ 0x44 800616c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800616e: 6c39 ldr r1, [r7, #64] @ 0x40 8006170: 6c7a ldr r2, [r7, #68] @ 0x44 8006172: e841 2300 strex r3, r2, [r1] 8006176: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006178: 6bfb ldr r3, [r7, #60] @ 0x3c 800617a: 2b00 cmp r3, #0 800617c: d1e3 bne.n 8006146 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800617e: 687b ldr r3, [r7, #4] 8006180: 681b ldr r3, [r3, #0] 8006182: 3314 adds r3, #20 8006184: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006186: 6a7b ldr r3, [r7, #36] @ 0x24 8006188: e853 3f00 ldrex r3, [r3] 800618c: 623b str r3, [r7, #32] return(result); 800618e: 6a3b ldr r3, [r7, #32] 8006190: f023 0301 bic.w r3, r3, #1 8006194: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8006198: 687b ldr r3, [r7, #4] 800619a: 681b ldr r3, [r3, #0] 800619c: 3314 adds r3, #20 800619e: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80061a2: 633a str r2, [r7, #48] @ 0x30 80061a4: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80061a6: 6af9 ldr r1, [r7, #44] @ 0x2c 80061a8: 6b3a ldr r2, [r7, #48] @ 0x30 80061aa: e841 2300 strex r3, r2, [r1] 80061ae: 62bb str r3, [r7, #40] @ 0x28 return(result); 80061b0: 6abb ldr r3, [r7, #40] @ 0x28 80061b2: 2b00 cmp r3, #0 80061b4: d1e3 bne.n 800617e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80061b6: 687b ldr r3, [r7, #4] 80061b8: 2220 movs r2, #32 80061ba: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80061be: 687b ldr r3, [r7, #4] 80061c0: 2200 movs r2, #0 80061c2: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80061c4: 687b ldr r3, [r7, #4] 80061c6: 681b ldr r3, [r3, #0] 80061c8: 330c adds r3, #12 80061ca: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80061cc: 693b ldr r3, [r7, #16] 80061ce: e853 3f00 ldrex r3, [r3] 80061d2: 60fb str r3, [r7, #12] return(result); 80061d4: 68fb ldr r3, [r7, #12] 80061d6: f023 0310 bic.w r3, r3, #16 80061da: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 80061de: 687b ldr r3, [r7, #4] 80061e0: 681b ldr r3, [r3, #0] 80061e2: 330c adds r3, #12 80061e4: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 80061e8: 61fa str r2, [r7, #28] 80061ea: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80061ec: 69b9 ldr r1, [r7, #24] 80061ee: 69fa ldr r2, [r7, #28] 80061f0: e841 2300 strex r3, r2, [r1] 80061f4: 617b str r3, [r7, #20] return(result); 80061f6: 697b ldr r3, [r7, #20] 80061f8: 2b00 cmp r3, #0 80061fa: d1e3 bne.n 80061c4 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80061fc: 687b ldr r3, [r7, #4] 80061fe: 2202 movs r2, #2 8006200: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8006202: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006206: 4619 mov r1, r3 8006208: 6878 ldr r0, [r7, #4] 800620a: f000 f847 bl 800629c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 800620e: e023 b.n 8006258 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8006210: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006214: f003 0380 and.w r3, r3, #128 @ 0x80 8006218: 2b00 cmp r3, #0 800621a: d009 beq.n 8006230 800621c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006220: f003 0380 and.w r3, r3, #128 @ 0x80 8006224: 2b00 cmp r3, #0 8006226: d003 beq.n 8006230 { UART_Transmit_IT(huart); 8006228: 6878 ldr r0, [r7, #4] 800622a: f000 fadf bl 80067ec return; 800622e: e014 b.n 800625a } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8006230: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006234: f003 0340 and.w r3, r3, #64 @ 0x40 8006238: 2b00 cmp r3, #0 800623a: d00e beq.n 800625a 800623c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006240: f003 0340 and.w r3, r3, #64 @ 0x40 8006244: 2b00 cmp r3, #0 8006246: d008 beq.n 800625a { UART_EndTransmit_IT(huart); 8006248: 6878 ldr r0, [r7, #4] 800624a: f000 fb1f bl 800688c return; 800624e: e004 b.n 800625a return; 8006250: bf00 nop 8006252: e002 b.n 800625a return; 8006254: bf00 nop 8006256: e000 b.n 800625a return; 8006258: bf00 nop } } 800625a: 37e8 adds r7, #232 @ 0xe8 800625c: 46bd mov sp, r7 800625e: bd80 pop {r7, pc} 08006260 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8006260: b480 push {r7} 8006262: b083 sub sp, #12 8006264: af00 add r7, sp, #0 8006266: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8006268: bf00 nop 800626a: 370c adds r7, #12 800626c: 46bd mov sp, r7 800626e: f85d 7b04 ldr.w r7, [sp], #4 8006272: 4770 bx lr 08006274 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006274: b480 push {r7} 8006276: b083 sub sp, #12 8006278: af00 add r7, sp, #0 800627a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 800627c: bf00 nop 800627e: 370c adds r7, #12 8006280: 46bd mov sp, r7 8006282: f85d 7b04 ldr.w r7, [sp], #4 8006286: 4770 bx lr 08006288 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006288: b480 push {r7} 800628a: b083 sub sp, #12 800628c: af00 add r7, sp, #0 800628e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 8006290: bf00 nop 8006292: 370c adds r7, #12 8006294: 46bd mov sp, r7 8006296: f85d 7b04 ldr.w r7, [sp], #4 800629a: 4770 bx lr 0800629c : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800629c: b480 push {r7} 800629e: b083 sub sp, #12 80062a0: af00 add r7, sp, #0 80062a2: 6078 str r0, [r7, #4] 80062a4: 460b mov r3, r1 80062a6: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 80062a8: bf00 nop 80062aa: 370c adds r7, #12 80062ac: 46bd mov sp, r7 80062ae: f85d 7b04 ldr.w r7, [sp], #4 80062b2: 4770 bx lr 080062b4 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 80062b4: b580 push {r7, lr} 80062b6: b090 sub sp, #64 @ 0x40 80062b8: af00 add r7, sp, #0 80062ba: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80062bc: 687b ldr r3, [r7, #4] 80062be: 6b9b ldr r3, [r3, #56] @ 0x38 80062c0: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 80062c2: 687b ldr r3, [r7, #4] 80062c4: 681b ldr r3, [r3, #0] 80062c6: 681b ldr r3, [r3, #0] 80062c8: f403 7380 and.w r3, r3, #256 @ 0x100 80062cc: 2b00 cmp r3, #0 80062ce: d137 bne.n 8006340 { huart->TxXferCount = 0x00U; 80062d0: 6bfb ldr r3, [r7, #60] @ 0x3c 80062d2: 2200 movs r2, #0 80062d4: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80062d6: 6bfb ldr r3, [r7, #60] @ 0x3c 80062d8: 681b ldr r3, [r3, #0] 80062da: 3314 adds r3, #20 80062dc: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80062de: 6a7b ldr r3, [r7, #36] @ 0x24 80062e0: e853 3f00 ldrex r3, [r3] 80062e4: 623b str r3, [r7, #32] return(result); 80062e6: 6a3b ldr r3, [r7, #32] 80062e8: f023 0380 bic.w r3, r3, #128 @ 0x80 80062ec: 63bb str r3, [r7, #56] @ 0x38 80062ee: 6bfb ldr r3, [r7, #60] @ 0x3c 80062f0: 681b ldr r3, [r3, #0] 80062f2: 3314 adds r3, #20 80062f4: 6bba ldr r2, [r7, #56] @ 0x38 80062f6: 633a str r2, [r7, #48] @ 0x30 80062f8: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80062fa: 6af9 ldr r1, [r7, #44] @ 0x2c 80062fc: 6b3a ldr r2, [r7, #48] @ 0x30 80062fe: e841 2300 strex r3, r2, [r1] 8006302: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006304: 6abb ldr r3, [r7, #40] @ 0x28 8006306: 2b00 cmp r3, #0 8006308: d1e5 bne.n 80062d6 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800630a: 6bfb ldr r3, [r7, #60] @ 0x3c 800630c: 681b ldr r3, [r3, #0] 800630e: 330c adds r3, #12 8006310: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006312: 693b ldr r3, [r7, #16] 8006314: e853 3f00 ldrex r3, [r3] 8006318: 60fb str r3, [r7, #12] return(result); 800631a: 68fb ldr r3, [r7, #12] 800631c: f043 0340 orr.w r3, r3, #64 @ 0x40 8006320: 637b str r3, [r7, #52] @ 0x34 8006322: 6bfb ldr r3, [r7, #60] @ 0x3c 8006324: 681b ldr r3, [r3, #0] 8006326: 330c adds r3, #12 8006328: 6b7a ldr r2, [r7, #52] @ 0x34 800632a: 61fa str r2, [r7, #28] 800632c: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800632e: 69b9 ldr r1, [r7, #24] 8006330: 69fa ldr r2, [r7, #28] 8006332: e841 2300 strex r3, r2, [r1] 8006336: 617b str r3, [r7, #20] return(result); 8006338: 697b ldr r3, [r7, #20] 800633a: 2b00 cmp r3, #0 800633c: d1e5 bne.n 800630a #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 800633e: e002 b.n 8006346 HAL_UART_TxCpltCallback(huart); 8006340: 6bf8 ldr r0, [r7, #60] @ 0x3c 8006342: f7ff ff8d bl 8006260 } 8006346: bf00 nop 8006348: 3740 adds r7, #64 @ 0x40 800634a: 46bd mov sp, r7 800634c: bd80 pop {r7, pc} 0800634e : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 800634e: b580 push {r7, lr} 8006350: b084 sub sp, #16 8006352: af00 add r7, sp, #0 8006354: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006356: 687b ldr r3, [r7, #4] 8006358: 6b9b ldr r3, [r3, #56] @ 0x38 800635a: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 800635c: 68f8 ldr r0, [r7, #12] 800635e: f7ff ff89 bl 8006274 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006362: bf00 nop 8006364: 3710 adds r7, #16 8006366: 46bd mov sp, r7 8006368: bd80 pop {r7, pc} 0800636a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 800636a: b580 push {r7, lr} 800636c: b09c sub sp, #112 @ 0x70 800636e: af00 add r7, sp, #0 8006370: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006372: 687b ldr r3, [r7, #4] 8006374: 6b9b ldr r3, [r3, #56] @ 0x38 8006376: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8006378: 687b ldr r3, [r7, #4] 800637a: 681b ldr r3, [r3, #0] 800637c: 681b ldr r3, [r3, #0] 800637e: f403 7380 and.w r3, r3, #256 @ 0x100 8006382: 2b00 cmp r3, #0 8006384: d172 bne.n 800646c { huart->RxXferCount = 0U; 8006386: 6efb ldr r3, [r7, #108] @ 0x6c 8006388: 2200 movs r2, #0 800638a: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800638c: 6efb ldr r3, [r7, #108] @ 0x6c 800638e: 681b ldr r3, [r3, #0] 8006390: 330c adds r3, #12 8006392: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006394: 6cfb ldr r3, [r7, #76] @ 0x4c 8006396: e853 3f00 ldrex r3, [r3] 800639a: 64bb str r3, [r7, #72] @ 0x48 return(result); 800639c: 6cbb ldr r3, [r7, #72] @ 0x48 800639e: f423 7380 bic.w r3, r3, #256 @ 0x100 80063a2: 66bb str r3, [r7, #104] @ 0x68 80063a4: 6efb ldr r3, [r7, #108] @ 0x6c 80063a6: 681b ldr r3, [r3, #0] 80063a8: 330c adds r3, #12 80063aa: 6eba ldr r2, [r7, #104] @ 0x68 80063ac: 65ba str r2, [r7, #88] @ 0x58 80063ae: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80063b0: 6d79 ldr r1, [r7, #84] @ 0x54 80063b2: 6dba ldr r2, [r7, #88] @ 0x58 80063b4: e841 2300 strex r3, r2, [r1] 80063b8: 653b str r3, [r7, #80] @ 0x50 return(result); 80063ba: 6d3b ldr r3, [r7, #80] @ 0x50 80063bc: 2b00 cmp r3, #0 80063be: d1e5 bne.n 800638c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80063c0: 6efb ldr r3, [r7, #108] @ 0x6c 80063c2: 681b ldr r3, [r3, #0] 80063c4: 3314 adds r3, #20 80063c6: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80063c8: 6bbb ldr r3, [r7, #56] @ 0x38 80063ca: e853 3f00 ldrex r3, [r3] 80063ce: 637b str r3, [r7, #52] @ 0x34 return(result); 80063d0: 6b7b ldr r3, [r7, #52] @ 0x34 80063d2: f023 0301 bic.w r3, r3, #1 80063d6: 667b str r3, [r7, #100] @ 0x64 80063d8: 6efb ldr r3, [r7, #108] @ 0x6c 80063da: 681b ldr r3, [r3, #0] 80063dc: 3314 adds r3, #20 80063de: 6e7a ldr r2, [r7, #100] @ 0x64 80063e0: 647a str r2, [r7, #68] @ 0x44 80063e2: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80063e4: 6c39 ldr r1, [r7, #64] @ 0x40 80063e6: 6c7a ldr r2, [r7, #68] @ 0x44 80063e8: e841 2300 strex r3, r2, [r1] 80063ec: 63fb str r3, [r7, #60] @ 0x3c return(result); 80063ee: 6bfb ldr r3, [r7, #60] @ 0x3c 80063f0: 2b00 cmp r3, #0 80063f2: d1e5 bne.n 80063c0 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80063f4: 6efb ldr r3, [r7, #108] @ 0x6c 80063f6: 681b ldr r3, [r3, #0] 80063f8: 3314 adds r3, #20 80063fa: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80063fc: 6a7b ldr r3, [r7, #36] @ 0x24 80063fe: e853 3f00 ldrex r3, [r3] 8006402: 623b str r3, [r7, #32] return(result); 8006404: 6a3b ldr r3, [r7, #32] 8006406: f023 0340 bic.w r3, r3, #64 @ 0x40 800640a: 663b str r3, [r7, #96] @ 0x60 800640c: 6efb ldr r3, [r7, #108] @ 0x6c 800640e: 681b ldr r3, [r3, #0] 8006410: 3314 adds r3, #20 8006412: 6e3a ldr r2, [r7, #96] @ 0x60 8006414: 633a str r2, [r7, #48] @ 0x30 8006416: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006418: 6af9 ldr r1, [r7, #44] @ 0x2c 800641a: 6b3a ldr r2, [r7, #48] @ 0x30 800641c: e841 2300 strex r3, r2, [r1] 8006420: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006422: 6abb ldr r3, [r7, #40] @ 0x28 8006424: 2b00 cmp r3, #0 8006426: d1e5 bne.n 80063f4 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006428: 6efb ldr r3, [r7, #108] @ 0x6c 800642a: 2220 movs r2, #32 800642c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006430: 6efb ldr r3, [r7, #108] @ 0x6c 8006432: 6b1b ldr r3, [r3, #48] @ 0x30 8006434: 2b01 cmp r3, #1 8006436: d119 bne.n 800646c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006438: 6efb ldr r3, [r7, #108] @ 0x6c 800643a: 681b ldr r3, [r3, #0] 800643c: 330c adds r3, #12 800643e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006440: 693b ldr r3, [r7, #16] 8006442: e853 3f00 ldrex r3, [r3] 8006446: 60fb str r3, [r7, #12] return(result); 8006448: 68fb ldr r3, [r7, #12] 800644a: f023 0310 bic.w r3, r3, #16 800644e: 65fb str r3, [r7, #92] @ 0x5c 8006450: 6efb ldr r3, [r7, #108] @ 0x6c 8006452: 681b ldr r3, [r3, #0] 8006454: 330c adds r3, #12 8006456: 6dfa ldr r2, [r7, #92] @ 0x5c 8006458: 61fa str r2, [r7, #28] 800645a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800645c: 69b9 ldr r1, [r7, #24] 800645e: 69fa ldr r2, [r7, #28] 8006460: e841 2300 strex r3, r2, [r1] 8006464: 617b str r3, [r7, #20] return(result); 8006466: 697b ldr r3, [r7, #20] 8006468: 2b00 cmp r3, #0 800646a: d1e5 bne.n 8006438 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800646c: 6efb ldr r3, [r7, #108] @ 0x6c 800646e: 2200 movs r2, #0 8006470: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006472: 6efb ldr r3, [r7, #108] @ 0x6c 8006474: 6b1b ldr r3, [r3, #48] @ 0x30 8006476: 2b01 cmp r3, #1 8006478: d106 bne.n 8006488 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800647a: 6efb ldr r3, [r7, #108] @ 0x6c 800647c: 8d9b ldrh r3, [r3, #44] @ 0x2c 800647e: 4619 mov r1, r3 8006480: 6ef8 ldr r0, [r7, #108] @ 0x6c 8006482: f7ff ff0b bl 800629c #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006486: e002 b.n 800648e HAL_UART_RxCpltCallback(huart); 8006488: 6ef8 ldr r0, [r7, #108] @ 0x6c 800648a: f7fa fb09 bl 8000aa0 } 800648e: bf00 nop 8006490: 3770 adds r7, #112 @ 0x70 8006492: 46bd mov sp, r7 8006494: bd80 pop {r7, pc} 08006496 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8006496: b580 push {r7, lr} 8006498: b084 sub sp, #16 800649a: af00 add r7, sp, #0 800649c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800649e: 687b ldr r3, [r7, #4] 80064a0: 6b9b ldr r3, [r3, #56] @ 0x38 80064a2: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 80064a4: 68fb ldr r3, [r7, #12] 80064a6: 2201 movs r2, #1 80064a8: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80064aa: 68fb ldr r3, [r7, #12] 80064ac: 6b1b ldr r3, [r3, #48] @ 0x30 80064ae: 2b01 cmp r3, #1 80064b0: d108 bne.n 80064c4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 80064b2: 68fb ldr r3, [r7, #12] 80064b4: 8d9b ldrh r3, [r3, #44] @ 0x2c 80064b6: 085b lsrs r3, r3, #1 80064b8: b29b uxth r3, r3 80064ba: 4619 mov r1, r3 80064bc: 68f8 ldr r0, [r7, #12] 80064be: f7ff feed bl 800629c #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80064c2: e002 b.n 80064ca HAL_UART_RxHalfCpltCallback(huart); 80064c4: 68f8 ldr r0, [r7, #12] 80064c6: f7ff fedf bl 8006288 } 80064ca: bf00 nop 80064cc: 3710 adds r7, #16 80064ce: 46bd mov sp, r7 80064d0: bd80 pop {r7, pc} 080064d2 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 80064d2: b580 push {r7, lr} 80064d4: b084 sub sp, #16 80064d6: af00 add r7, sp, #0 80064d8: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 80064da: 2300 movs r3, #0 80064dc: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80064de: 687b ldr r3, [r7, #4] 80064e0: 6b9b ldr r3, [r3, #56] @ 0x38 80064e2: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 80064e4: 68bb ldr r3, [r7, #8] 80064e6: 681b ldr r3, [r3, #0] 80064e8: 695b ldr r3, [r3, #20] 80064ea: f003 0380 and.w r3, r3, #128 @ 0x80 80064ee: 2b80 cmp r3, #128 @ 0x80 80064f0: bf0c ite eq 80064f2: 2301 moveq r3, #1 80064f4: 2300 movne r3, #0 80064f6: b2db uxtb r3, r3 80064f8: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 80064fa: 68bb ldr r3, [r7, #8] 80064fc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8006500: b2db uxtb r3, r3 8006502: 2b21 cmp r3, #33 @ 0x21 8006504: d108 bne.n 8006518 8006506: 68fb ldr r3, [r7, #12] 8006508: 2b00 cmp r3, #0 800650a: d005 beq.n 8006518 { huart->TxXferCount = 0x00U; 800650c: 68bb ldr r3, [r7, #8] 800650e: 2200 movs r2, #0 8006510: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 8006512: 68b8 ldr r0, [r7, #8] 8006514: f000 f8ce bl 80066b4 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8006518: 68bb ldr r3, [r7, #8] 800651a: 681b ldr r3, [r3, #0] 800651c: 695b ldr r3, [r3, #20] 800651e: f003 0340 and.w r3, r3, #64 @ 0x40 8006522: 2b40 cmp r3, #64 @ 0x40 8006524: bf0c ite eq 8006526: 2301 moveq r3, #1 8006528: 2300 movne r3, #0 800652a: b2db uxtb r3, r3 800652c: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 800652e: 68bb ldr r3, [r7, #8] 8006530: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8006534: b2db uxtb r3, r3 8006536: 2b22 cmp r3, #34 @ 0x22 8006538: d108 bne.n 800654c 800653a: 68fb ldr r3, [r7, #12] 800653c: 2b00 cmp r3, #0 800653e: d005 beq.n 800654c { huart->RxXferCount = 0x00U; 8006540: 68bb ldr r3, [r7, #8] 8006542: 2200 movs r2, #0 8006544: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 8006546: 68b8 ldr r0, [r7, #8] 8006548: f000 f8dc bl 8006704 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 800654c: 68bb ldr r3, [r7, #8] 800654e: 6c5b ldr r3, [r3, #68] @ 0x44 8006550: f043 0210 orr.w r2, r3, #16 8006554: 68bb ldr r3, [r7, #8] 8006556: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006558: 68b8 ldr r0, [r7, #8] 800655a: f7fa fafd bl 8000b58 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800655e: bf00 nop 8006560: 3710 adds r7, #16 8006562: 46bd mov sp, r7 8006564: bd80 pop {r7, pc} ... 08006568 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8006568: b580 push {r7, lr} 800656a: b098 sub sp, #96 @ 0x60 800656c: af00 add r7, sp, #0 800656e: 60f8 str r0, [r7, #12] 8006570: 60b9 str r1, [r7, #8] 8006572: 4613 mov r3, r2 8006574: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 8006576: 68ba ldr r2, [r7, #8] 8006578: 68fb ldr r3, [r7, #12] 800657a: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 800657c: 68fb ldr r3, [r7, #12] 800657e: 88fa ldrh r2, [r7, #6] 8006580: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 8006582: 68fb ldr r3, [r7, #12] 8006584: 2200 movs r2, #0 8006586: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8006588: 68fb ldr r3, [r7, #12] 800658a: 2222 movs r2, #34 @ 0x22 800658c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8006590: 68fb ldr r3, [r7, #12] 8006592: 6bdb ldr r3, [r3, #60] @ 0x3c 8006594: 4a44 ldr r2, [pc, #272] @ (80066a8 ) 8006596: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8006598: 68fb ldr r3, [r7, #12] 800659a: 6bdb ldr r3, [r3, #60] @ 0x3c 800659c: 4a43 ldr r2, [pc, #268] @ (80066ac ) 800659e: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 80065a0: 68fb ldr r3, [r7, #12] 80065a2: 6bdb ldr r3, [r3, #60] @ 0x3c 80065a4: 4a42 ldr r2, [pc, #264] @ (80066b0 ) 80065a6: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 80065a8: 68fb ldr r3, [r7, #12] 80065aa: 6bdb ldr r3, [r3, #60] @ 0x3c 80065ac: 2200 movs r2, #0 80065ae: 651a str r2, [r3, #80] @ 0x50 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 80065b0: f107 0308 add.w r3, r7, #8 80065b4: 65fb str r3, [r7, #92] @ 0x5c if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) 80065b6: 68fb ldr r3, [r7, #12] 80065b8: 6bd8 ldr r0, [r3, #60] @ 0x3c 80065ba: 68fb ldr r3, [r7, #12] 80065bc: 681b ldr r3, [r3, #0] 80065be: 3304 adds r3, #4 80065c0: 4619 mov r1, r3 80065c2: 6dfb ldr r3, [r7, #92] @ 0x5c 80065c4: 681a ldr r2, [r3, #0] 80065c6: 88fb ldrh r3, [r7, #6] 80065c8: f7fb fc94 bl 8001ef4 80065cc: 4603 mov r3, r0 80065ce: 2b00 cmp r3, #0 80065d0: d008 beq.n 80065e4 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 80065d2: 68fb ldr r3, [r7, #12] 80065d4: 2210 movs r2, #16 80065d6: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 80065d8: 68fb ldr r3, [r7, #12] 80065da: 2220 movs r2, #32 80065dc: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_ERROR; 80065e0: 2301 movs r3, #1 80065e2: e05d b.n 80066a0 } /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 80065e4: 2300 movs r3, #0 80065e6: 613b str r3, [r7, #16] 80065e8: 68fb ldr r3, [r7, #12] 80065ea: 681b ldr r3, [r3, #0] 80065ec: 681b ldr r3, [r3, #0] 80065ee: 613b str r3, [r7, #16] 80065f0: 68fb ldr r3, [r7, #12] 80065f2: 681b ldr r3, [r3, #0] 80065f4: 685b ldr r3, [r3, #4] 80065f6: 613b str r3, [r7, #16] 80065f8: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 80065fa: 68fb ldr r3, [r7, #12] 80065fc: 691b ldr r3, [r3, #16] 80065fe: 2b00 cmp r3, #0 8006600: d019 beq.n 8006636 { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006602: 68fb ldr r3, [r7, #12] 8006604: 681b ldr r3, [r3, #0] 8006606: 330c adds r3, #12 8006608: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800660a: 6c3b ldr r3, [r7, #64] @ 0x40 800660c: e853 3f00 ldrex r3, [r3] 8006610: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006612: 6bfb ldr r3, [r7, #60] @ 0x3c 8006614: f443 7380 orr.w r3, r3, #256 @ 0x100 8006618: 65bb str r3, [r7, #88] @ 0x58 800661a: 68fb ldr r3, [r7, #12] 800661c: 681b ldr r3, [r3, #0] 800661e: 330c adds r3, #12 8006620: 6dba ldr r2, [r7, #88] @ 0x58 8006622: 64fa str r2, [r7, #76] @ 0x4c 8006624: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006626: 6cb9 ldr r1, [r7, #72] @ 0x48 8006628: 6cfa ldr r2, [r7, #76] @ 0x4c 800662a: e841 2300 strex r3, r2, [r1] 800662e: 647b str r3, [r7, #68] @ 0x44 return(result); 8006630: 6c7b ldr r3, [r7, #68] @ 0x44 8006632: 2b00 cmp r3, #0 8006634: d1e5 bne.n 8006602 } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006636: 68fb ldr r3, [r7, #12] 8006638: 681b ldr r3, [r3, #0] 800663a: 3314 adds r3, #20 800663c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800663e: 6afb ldr r3, [r7, #44] @ 0x2c 8006640: e853 3f00 ldrex r3, [r3] 8006644: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006646: 6abb ldr r3, [r7, #40] @ 0x28 8006648: f043 0301 orr.w r3, r3, #1 800664c: 657b str r3, [r7, #84] @ 0x54 800664e: 68fb ldr r3, [r7, #12] 8006650: 681b ldr r3, [r3, #0] 8006652: 3314 adds r3, #20 8006654: 6d7a ldr r2, [r7, #84] @ 0x54 8006656: 63ba str r2, [r7, #56] @ 0x38 8006658: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800665a: 6b79 ldr r1, [r7, #52] @ 0x34 800665c: 6bba ldr r2, [r7, #56] @ 0x38 800665e: e841 2300 strex r3, r2, [r1] 8006662: 633b str r3, [r7, #48] @ 0x30 return(result); 8006664: 6b3b ldr r3, [r7, #48] @ 0x30 8006666: 2b00 cmp r3, #0 8006668: d1e5 bne.n 8006636 /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800666a: 68fb ldr r3, [r7, #12] 800666c: 681b ldr r3, [r3, #0] 800666e: 3314 adds r3, #20 8006670: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006672: 69bb ldr r3, [r7, #24] 8006674: e853 3f00 ldrex r3, [r3] 8006678: 617b str r3, [r7, #20] return(result); 800667a: 697b ldr r3, [r7, #20] 800667c: f043 0340 orr.w r3, r3, #64 @ 0x40 8006680: 653b str r3, [r7, #80] @ 0x50 8006682: 68fb ldr r3, [r7, #12] 8006684: 681b ldr r3, [r3, #0] 8006686: 3314 adds r3, #20 8006688: 6d3a ldr r2, [r7, #80] @ 0x50 800668a: 627a str r2, [r7, #36] @ 0x24 800668c: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800668e: 6a39 ldr r1, [r7, #32] 8006690: 6a7a ldr r2, [r7, #36] @ 0x24 8006692: e841 2300 strex r3, r2, [r1] 8006696: 61fb str r3, [r7, #28] return(result); 8006698: 69fb ldr r3, [r7, #28] 800669a: 2b00 cmp r3, #0 800669c: d1e5 bne.n 800666a return HAL_OK; 800669e: 2300 movs r3, #0 } 80066a0: 4618 mov r0, r3 80066a2: 3760 adds r7, #96 @ 0x60 80066a4: 46bd mov sp, r7 80066a6: bd80 pop {r7, pc} 80066a8: 0800636b .word 0x0800636b 80066ac: 08006497 .word 0x08006497 80066b0: 080064d3 .word 0x080064d3 080066b4 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 80066b4: b480 push {r7} 80066b6: b089 sub sp, #36 @ 0x24 80066b8: af00 add r7, sp, #0 80066ba: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 80066bc: 687b ldr r3, [r7, #4] 80066be: 681b ldr r3, [r3, #0] 80066c0: 330c adds r3, #12 80066c2: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80066c4: 68fb ldr r3, [r7, #12] 80066c6: e853 3f00 ldrex r3, [r3] 80066ca: 60bb str r3, [r7, #8] return(result); 80066cc: 68bb ldr r3, [r7, #8] 80066ce: f023 03c0 bic.w r3, r3, #192 @ 0xc0 80066d2: 61fb str r3, [r7, #28] 80066d4: 687b ldr r3, [r7, #4] 80066d6: 681b ldr r3, [r3, #0] 80066d8: 330c adds r3, #12 80066da: 69fa ldr r2, [r7, #28] 80066dc: 61ba str r2, [r7, #24] 80066de: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066e0: 6979 ldr r1, [r7, #20] 80066e2: 69ba ldr r2, [r7, #24] 80066e4: e841 2300 strex r3, r2, [r1] 80066e8: 613b str r3, [r7, #16] return(result); 80066ea: 693b ldr r3, [r7, #16] 80066ec: 2b00 cmp r3, #0 80066ee: d1e5 bne.n 80066bc /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80066f0: 687b ldr r3, [r7, #4] 80066f2: 2220 movs r2, #32 80066f4: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 80066f8: bf00 nop 80066fa: 3724 adds r7, #36 @ 0x24 80066fc: 46bd mov sp, r7 80066fe: f85d 7b04 ldr.w r7, [sp], #4 8006702: 4770 bx lr 08006704 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8006704: b480 push {r7} 8006706: b095 sub sp, #84 @ 0x54 8006708: af00 add r7, sp, #0 800670a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800670c: 687b ldr r3, [r7, #4] 800670e: 681b ldr r3, [r3, #0] 8006710: 330c adds r3, #12 8006712: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006714: 6b7b ldr r3, [r7, #52] @ 0x34 8006716: e853 3f00 ldrex r3, [r3] 800671a: 633b str r3, [r7, #48] @ 0x30 return(result); 800671c: 6b3b ldr r3, [r7, #48] @ 0x30 800671e: f423 7390 bic.w r3, r3, #288 @ 0x120 8006722: 64fb str r3, [r7, #76] @ 0x4c 8006724: 687b ldr r3, [r7, #4] 8006726: 681b ldr r3, [r3, #0] 8006728: 330c adds r3, #12 800672a: 6cfa ldr r2, [r7, #76] @ 0x4c 800672c: 643a str r2, [r7, #64] @ 0x40 800672e: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006730: 6bf9 ldr r1, [r7, #60] @ 0x3c 8006732: 6c3a ldr r2, [r7, #64] @ 0x40 8006734: e841 2300 strex r3, r2, [r1] 8006738: 63bb str r3, [r7, #56] @ 0x38 return(result); 800673a: 6bbb ldr r3, [r7, #56] @ 0x38 800673c: 2b00 cmp r3, #0 800673e: d1e5 bne.n 800670c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006740: 687b ldr r3, [r7, #4] 8006742: 681b ldr r3, [r3, #0] 8006744: 3314 adds r3, #20 8006746: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006748: 6a3b ldr r3, [r7, #32] 800674a: e853 3f00 ldrex r3, [r3] 800674e: 61fb str r3, [r7, #28] return(result); 8006750: 69fb ldr r3, [r7, #28] 8006752: f023 0301 bic.w r3, r3, #1 8006756: 64bb str r3, [r7, #72] @ 0x48 8006758: 687b ldr r3, [r7, #4] 800675a: 681b ldr r3, [r3, #0] 800675c: 3314 adds r3, #20 800675e: 6cba ldr r2, [r7, #72] @ 0x48 8006760: 62fa str r2, [r7, #44] @ 0x2c 8006762: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006764: 6ab9 ldr r1, [r7, #40] @ 0x28 8006766: 6afa ldr r2, [r7, #44] @ 0x2c 8006768: e841 2300 strex r3, r2, [r1] 800676c: 627b str r3, [r7, #36] @ 0x24 return(result); 800676e: 6a7b ldr r3, [r7, #36] @ 0x24 8006770: 2b00 cmp r3, #0 8006772: d1e5 bne.n 8006740 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006774: 687b ldr r3, [r7, #4] 8006776: 6b1b ldr r3, [r3, #48] @ 0x30 8006778: 2b01 cmp r3, #1 800677a: d119 bne.n 80067b0 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800677c: 687b ldr r3, [r7, #4] 800677e: 681b ldr r3, [r3, #0] 8006780: 330c adds r3, #12 8006782: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006784: 68fb ldr r3, [r7, #12] 8006786: e853 3f00 ldrex r3, [r3] 800678a: 60bb str r3, [r7, #8] return(result); 800678c: 68bb ldr r3, [r7, #8] 800678e: f023 0310 bic.w r3, r3, #16 8006792: 647b str r3, [r7, #68] @ 0x44 8006794: 687b ldr r3, [r7, #4] 8006796: 681b ldr r3, [r3, #0] 8006798: 330c adds r3, #12 800679a: 6c7a ldr r2, [r7, #68] @ 0x44 800679c: 61ba str r2, [r7, #24] 800679e: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067a0: 6979 ldr r1, [r7, #20] 80067a2: 69ba ldr r2, [r7, #24] 80067a4: e841 2300 strex r3, r2, [r1] 80067a8: 613b str r3, [r7, #16] return(result); 80067aa: 693b ldr r3, [r7, #16] 80067ac: 2b00 cmp r3, #0 80067ae: d1e5 bne.n 800677c } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80067b0: 687b ldr r3, [r7, #4] 80067b2: 2220 movs r2, #32 80067b4: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80067b8: 687b ldr r3, [r7, #4] 80067ba: 2200 movs r2, #0 80067bc: 631a str r2, [r3, #48] @ 0x30 } 80067be: bf00 nop 80067c0: 3754 adds r7, #84 @ 0x54 80067c2: 46bd mov sp, r7 80067c4: f85d 7b04 ldr.w r7, [sp], #4 80067c8: 4770 bx lr 080067ca : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 80067ca: b580 push {r7, lr} 80067cc: b084 sub sp, #16 80067ce: af00 add r7, sp, #0 80067d0: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80067d2: 687b ldr r3, [r7, #4] 80067d4: 6b9b ldr r3, [r3, #56] @ 0x38 80067d6: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 80067d8: 68fb ldr r3, [r7, #12] 80067da: 2200 movs r2, #0 80067dc: 85da strh r2, [r3, #46] @ 0x2e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80067de: 68f8 ldr r0, [r7, #12] 80067e0: f7fa f9ba bl 8000b58 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80067e4: bf00 nop 80067e6: 3710 adds r7, #16 80067e8: 46bd mov sp, r7 80067ea: bd80 pop {r7, pc} 080067ec : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 80067ec: b480 push {r7} 80067ee: b085 sub sp, #20 80067f0: af00 add r7, sp, #0 80067f2: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80067f4: 687b ldr r3, [r7, #4] 80067f6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80067fa: b2db uxtb r3, r3 80067fc: 2b21 cmp r3, #33 @ 0x21 80067fe: d13e bne.n 800687e { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006800: 687b ldr r3, [r7, #4] 8006802: 689b ldr r3, [r3, #8] 8006804: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006808: d114 bne.n 8006834 800680a: 687b ldr r3, [r7, #4] 800680c: 691b ldr r3, [r3, #16] 800680e: 2b00 cmp r3, #0 8006810: d110 bne.n 8006834 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8006812: 687b ldr r3, [r7, #4] 8006814: 6a1b ldr r3, [r3, #32] 8006816: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8006818: 68fb ldr r3, [r7, #12] 800681a: 881b ldrh r3, [r3, #0] 800681c: 461a mov r2, r3 800681e: 687b ldr r3, [r7, #4] 8006820: 681b ldr r3, [r3, #0] 8006822: f3c2 0208 ubfx r2, r2, #0, #9 8006826: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8006828: 687b ldr r3, [r7, #4] 800682a: 6a1b ldr r3, [r3, #32] 800682c: 1c9a adds r2, r3, #2 800682e: 687b ldr r3, [r7, #4] 8006830: 621a str r2, [r3, #32] 8006832: e008 b.n 8006846 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8006834: 687b ldr r3, [r7, #4] 8006836: 6a1b ldr r3, [r3, #32] 8006838: 1c59 adds r1, r3, #1 800683a: 687a ldr r2, [r7, #4] 800683c: 6211 str r1, [r2, #32] 800683e: 781a ldrb r2, [r3, #0] 8006840: 687b ldr r3, [r7, #4] 8006842: 681b ldr r3, [r3, #0] 8006844: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8006846: 687b ldr r3, [r7, #4] 8006848: 8cdb ldrh r3, [r3, #38] @ 0x26 800684a: b29b uxth r3, r3 800684c: 3b01 subs r3, #1 800684e: b29b uxth r3, r3 8006850: 687a ldr r2, [r7, #4] 8006852: 4619 mov r1, r3 8006854: 84d1 strh r1, [r2, #38] @ 0x26 8006856: 2b00 cmp r3, #0 8006858: d10f bne.n 800687a { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 800685a: 687b ldr r3, [r7, #4] 800685c: 681b ldr r3, [r3, #0] 800685e: 68da ldr r2, [r3, #12] 8006860: 687b ldr r3, [r7, #4] 8006862: 681b ldr r3, [r3, #0] 8006864: f022 0280 bic.w r2, r2, #128 @ 0x80 8006868: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 800686a: 687b ldr r3, [r7, #4] 800686c: 681b ldr r3, [r3, #0] 800686e: 68da ldr r2, [r3, #12] 8006870: 687b ldr r3, [r7, #4] 8006872: 681b ldr r3, [r3, #0] 8006874: f042 0240 orr.w r2, r2, #64 @ 0x40 8006878: 60da str r2, [r3, #12] } return HAL_OK; 800687a: 2300 movs r3, #0 800687c: e000 b.n 8006880 } else { return HAL_BUSY; 800687e: 2302 movs r3, #2 } } 8006880: 4618 mov r0, r3 8006882: 3714 adds r7, #20 8006884: 46bd mov sp, r7 8006886: f85d 7b04 ldr.w r7, [sp], #4 800688a: 4770 bx lr 0800688c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 800688c: b580 push {r7, lr} 800688e: b082 sub sp, #8 8006890: af00 add r7, sp, #0 8006892: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8006894: 687b ldr r3, [r7, #4] 8006896: 681b ldr r3, [r3, #0] 8006898: 68da ldr r2, [r3, #12] 800689a: 687b ldr r3, [r7, #4] 800689c: 681b ldr r3, [r3, #0] 800689e: f022 0240 bic.w r2, r2, #64 @ 0x40 80068a2: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80068a4: 687b ldr r3, [r7, #4] 80068a6: 2220 movs r2, #32 80068a8: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80068ac: 6878 ldr r0, [r7, #4] 80068ae: f7ff fcd7 bl 8006260 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 80068b2: 2300 movs r3, #0 } 80068b4: 4618 mov r0, r3 80068b6: 3708 adds r7, #8 80068b8: 46bd mov sp, r7 80068ba: bd80 pop {r7, pc} 080068bc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 80068bc: b580 push {r7, lr} 80068be: b08c sub sp, #48 @ 0x30 80068c0: af00 add r7, sp, #0 80068c2: 6078 str r0, [r7, #4] uint8_t *pdata8bits = NULL; 80068c4: 2300 movs r3, #0 80068c6: 62fb str r3, [r7, #44] @ 0x2c uint16_t *pdata16bits = NULL; 80068c8: 2300 movs r3, #0 80068ca: 62bb str r3, [r7, #40] @ 0x28 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80068cc: 687b ldr r3, [r7, #4] 80068ce: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80068d2: b2db uxtb r3, r3 80068d4: 2b22 cmp r3, #34 @ 0x22 80068d6: f040 80aa bne.w 8006a2e { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80068da: 687b ldr r3, [r7, #4] 80068dc: 689b ldr r3, [r3, #8] 80068de: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80068e2: d115 bne.n 8006910 80068e4: 687b ldr r3, [r7, #4] 80068e6: 691b ldr r3, [r3, #16] 80068e8: 2b00 cmp r3, #0 80068ea: d111 bne.n 8006910 { /* Unused pdata8bits */ UNUSED(pdata8bits); pdata16bits = (uint16_t *) huart->pRxBuffPtr; 80068ec: 687b ldr r3, [r7, #4] 80068ee: 6a9b ldr r3, [r3, #40] @ 0x28 80068f0: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 80068f2: 687b ldr r3, [r7, #4] 80068f4: 681b ldr r3, [r3, #0] 80068f6: 685b ldr r3, [r3, #4] 80068f8: b29b uxth r3, r3 80068fa: f3c3 0308 ubfx r3, r3, #0, #9 80068fe: b29a uxth r2, r3 8006900: 6abb ldr r3, [r7, #40] @ 0x28 8006902: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8006904: 687b ldr r3, [r7, #4] 8006906: 6a9b ldr r3, [r3, #40] @ 0x28 8006908: 1c9a adds r2, r3, #2 800690a: 687b ldr r3, [r7, #4] 800690c: 629a str r2, [r3, #40] @ 0x28 800690e: e024 b.n 800695a } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8006910: 687b ldr r3, [r7, #4] 8006912: 6a9b ldr r3, [r3, #40] @ 0x28 8006914: 62fb str r3, [r7, #44] @ 0x2c /* Unused pdata16bits */ UNUSED(pdata16bits); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8006916: 687b ldr r3, [r7, #4] 8006918: 689b ldr r3, [r3, #8] 800691a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800691e: d007 beq.n 8006930 8006920: 687b ldr r3, [r7, #4] 8006922: 689b ldr r3, [r3, #8] 8006924: 2b00 cmp r3, #0 8006926: d10a bne.n 800693e 8006928: 687b ldr r3, [r7, #4] 800692a: 691b ldr r3, [r3, #16] 800692c: 2b00 cmp r3, #0 800692e: d106 bne.n 800693e { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8006930: 687b ldr r3, [r7, #4] 8006932: 681b ldr r3, [r3, #0] 8006934: 685b ldr r3, [r3, #4] 8006936: b2da uxtb r2, r3 8006938: 6afb ldr r3, [r7, #44] @ 0x2c 800693a: 701a strb r2, [r3, #0] 800693c: e008 b.n 8006950 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 800693e: 687b ldr r3, [r7, #4] 8006940: 681b ldr r3, [r3, #0] 8006942: 685b ldr r3, [r3, #4] 8006944: b2db uxtb r3, r3 8006946: f003 037f and.w r3, r3, #127 @ 0x7f 800694a: b2da uxtb r2, r3 800694c: 6afb ldr r3, [r7, #44] @ 0x2c 800694e: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8006950: 687b ldr r3, [r7, #4] 8006952: 6a9b ldr r3, [r3, #40] @ 0x28 8006954: 1c5a adds r2, r3, #1 8006956: 687b ldr r3, [r7, #4] 8006958: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 800695a: 687b ldr r3, [r7, #4] 800695c: 8ddb ldrh r3, [r3, #46] @ 0x2e 800695e: b29b uxth r3, r3 8006960: 3b01 subs r3, #1 8006962: b29b uxth r3, r3 8006964: 687a ldr r2, [r7, #4] 8006966: 4619 mov r1, r3 8006968: 85d1 strh r1, [r2, #46] @ 0x2e 800696a: 2b00 cmp r3, #0 800696c: d15d bne.n 8006a2a { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 800696e: 687b ldr r3, [r7, #4] 8006970: 681b ldr r3, [r3, #0] 8006972: 68da ldr r2, [r3, #12] 8006974: 687b ldr r3, [r7, #4] 8006976: 681b ldr r3, [r3, #0] 8006978: f022 0220 bic.w r2, r2, #32 800697c: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 800697e: 687b ldr r3, [r7, #4] 8006980: 681b ldr r3, [r3, #0] 8006982: 68da ldr r2, [r3, #12] 8006984: 687b ldr r3, [r7, #4] 8006986: 681b ldr r3, [r3, #0] 8006988: f422 7280 bic.w r2, r2, #256 @ 0x100 800698c: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 800698e: 687b ldr r3, [r7, #4] 8006990: 681b ldr r3, [r3, #0] 8006992: 695a ldr r2, [r3, #20] 8006994: 687b ldr r3, [r7, #4] 8006996: 681b ldr r3, [r3, #0] 8006998: f022 0201 bic.w r2, r2, #1 800699c: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800699e: 687b ldr r3, [r7, #4] 80069a0: 2220 movs r2, #32 80069a2: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80069a6: 687b ldr r3, [r7, #4] 80069a8: 2200 movs r2, #0 80069aa: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80069ac: 687b ldr r3, [r7, #4] 80069ae: 6b1b ldr r3, [r3, #48] @ 0x30 80069b0: 2b01 cmp r3, #1 80069b2: d135 bne.n 8006a20 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80069b4: 687b ldr r3, [r7, #4] 80069b6: 2200 movs r2, #0 80069b8: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80069ba: 687b ldr r3, [r7, #4] 80069bc: 681b ldr r3, [r3, #0] 80069be: 330c adds r3, #12 80069c0: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80069c2: 697b ldr r3, [r7, #20] 80069c4: e853 3f00 ldrex r3, [r3] 80069c8: 613b str r3, [r7, #16] return(result); 80069ca: 693b ldr r3, [r7, #16] 80069cc: f023 0310 bic.w r3, r3, #16 80069d0: 627b str r3, [r7, #36] @ 0x24 80069d2: 687b ldr r3, [r7, #4] 80069d4: 681b ldr r3, [r3, #0] 80069d6: 330c adds r3, #12 80069d8: 6a7a ldr r2, [r7, #36] @ 0x24 80069da: 623a str r2, [r7, #32] 80069dc: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80069de: 69f9 ldr r1, [r7, #28] 80069e0: 6a3a ldr r2, [r7, #32] 80069e2: e841 2300 strex r3, r2, [r1] 80069e6: 61bb str r3, [r7, #24] return(result); 80069e8: 69bb ldr r3, [r7, #24] 80069ea: 2b00 cmp r3, #0 80069ec: d1e5 bne.n 80069ba /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 80069ee: 687b ldr r3, [r7, #4] 80069f0: 681b ldr r3, [r3, #0] 80069f2: 681b ldr r3, [r3, #0] 80069f4: f003 0310 and.w r3, r3, #16 80069f8: 2b10 cmp r3, #16 80069fa: d10a bne.n 8006a12 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 80069fc: 2300 movs r3, #0 80069fe: 60fb str r3, [r7, #12] 8006a00: 687b ldr r3, [r7, #4] 8006a02: 681b ldr r3, [r3, #0] 8006a04: 681b ldr r3, [r3, #0] 8006a06: 60fb str r3, [r7, #12] 8006a08: 687b ldr r3, [r7, #4] 8006a0a: 681b ldr r3, [r3, #0] 8006a0c: 685b ldr r3, [r3, #4] 8006a0e: 60fb str r3, [r7, #12] 8006a10: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006a12: 687b ldr r3, [r7, #4] 8006a14: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006a16: 4619 mov r1, r3 8006a18: 6878 ldr r0, [r7, #4] 8006a1a: f7ff fc3f bl 800629c 8006a1e: e002 b.n 8006a26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8006a20: 6878 ldr r0, [r7, #4] 8006a22: f7fa f83d bl 8000aa0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8006a26: 2300 movs r3, #0 8006a28: e002 b.n 8006a30 } return HAL_OK; 8006a2a: 2300 movs r3, #0 8006a2c: e000 b.n 8006a30 } else { return HAL_BUSY; 8006a2e: 2302 movs r3, #2 } } 8006a30: 4618 mov r0, r3 8006a32: 3730 adds r7, #48 @ 0x30 8006a34: 46bd mov sp, r7 8006a36: bd80 pop {r7, pc} 08006a38 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8006a38: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8006a3c: b0c0 sub sp, #256 @ 0x100 8006a3e: af00 add r7, sp, #0 8006a40: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8006a44: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a48: 681b ldr r3, [r3, #0] 8006a4a: 691b ldr r3, [r3, #16] 8006a4c: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8006a50: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a54: 68d9 ldr r1, [r3, #12] 8006a56: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a5a: 681a ldr r2, [r3, #0] 8006a5c: ea40 0301 orr.w r3, r0, r1 8006a60: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8006a62: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a66: 689a ldr r2, [r3, #8] 8006a68: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a6c: 691b ldr r3, [r3, #16] 8006a6e: 431a orrs r2, r3 8006a70: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a74: 695b ldr r3, [r3, #20] 8006a76: 431a orrs r2, r3 8006a78: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a7c: 69db ldr r3, [r3, #28] 8006a7e: 4313 orrs r3, r2 8006a80: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 8006a84: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a88: 681b ldr r3, [r3, #0] 8006a8a: 68db ldr r3, [r3, #12] 8006a8c: f423 4116 bic.w r1, r3, #38400 @ 0x9600 8006a90: f021 010c bic.w r1, r1, #12 8006a94: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a98: 681a ldr r2, [r3, #0] 8006a9a: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 8006a9e: 430b orrs r3, r1 8006aa0: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8006aa2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006aa6: 681b ldr r3, [r3, #0] 8006aa8: 695b ldr r3, [r3, #20] 8006aaa: f423 7040 bic.w r0, r3, #768 @ 0x300 8006aae: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ab2: 6999 ldr r1, [r3, #24] 8006ab4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ab8: 681a ldr r2, [r3, #0] 8006aba: ea40 0301 orr.w r3, r0, r1 8006abe: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 8006ac0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ac4: 681a ldr r2, [r3, #0] 8006ac6: 4b8f ldr r3, [pc, #572] @ (8006d04 ) 8006ac8: 429a cmp r2, r3 8006aca: d005 beq.n 8006ad8 8006acc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ad0: 681a ldr r2, [r3, #0] 8006ad2: 4b8d ldr r3, [pc, #564] @ (8006d08 ) 8006ad4: 429a cmp r2, r3 8006ad6: d104 bne.n 8006ae2 { pclk = HAL_RCC_GetPCLK2Freq(); 8006ad8: f7fd fbf6 bl 80042c8 8006adc: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8006ae0: e003 b.n 8006aea pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8006ae2: f7fd fbdd bl 80042a0 8006ae6: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8006aea: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006aee: 69db ldr r3, [r3, #28] 8006af0: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8006af4: f040 810c bne.w 8006d10 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8006af8: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006afc: 2200 movs r2, #0 8006afe: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8006b02: f8c7 20ec str.w r2, [r7, #236] @ 0xec 8006b06: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 8006b0a: 4622 mov r2, r4 8006b0c: 462b mov r3, r5 8006b0e: 1891 adds r1, r2, r2 8006b10: 65b9 str r1, [r7, #88] @ 0x58 8006b12: 415b adcs r3, r3 8006b14: 65fb str r3, [r7, #92] @ 0x5c 8006b16: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8006b1a: 4621 mov r1, r4 8006b1c: eb12 0801 adds.w r8, r2, r1 8006b20: 4629 mov r1, r5 8006b22: eb43 0901 adc.w r9, r3, r1 8006b26: f04f 0200 mov.w r2, #0 8006b2a: f04f 0300 mov.w r3, #0 8006b2e: ea4f 03c9 mov.w r3, r9, lsl #3 8006b32: ea43 7358 orr.w r3, r3, r8, lsr #29 8006b36: ea4f 02c8 mov.w r2, r8, lsl #3 8006b3a: 4690 mov r8, r2 8006b3c: 4699 mov r9, r3 8006b3e: 4623 mov r3, r4 8006b40: eb18 0303 adds.w r3, r8, r3 8006b44: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 8006b48: 462b mov r3, r5 8006b4a: eb49 0303 adc.w r3, r9, r3 8006b4e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8006b52: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b56: 685b ldr r3, [r3, #4] 8006b58: 2200 movs r2, #0 8006b5a: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8006b5e: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 8006b62: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 8006b66: 460b mov r3, r1 8006b68: 18db adds r3, r3, r3 8006b6a: 653b str r3, [r7, #80] @ 0x50 8006b6c: 4613 mov r3, r2 8006b6e: eb42 0303 adc.w r3, r2, r3 8006b72: 657b str r3, [r7, #84] @ 0x54 8006b74: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 8006b78: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 8006b7c: f7f9 fb42 bl 8000204 <__aeabi_uldivmod> 8006b80: 4602 mov r2, r0 8006b82: 460b mov r3, r1 8006b84: 4b61 ldr r3, [pc, #388] @ (8006d0c ) 8006b86: fba3 2302 umull r2, r3, r3, r2 8006b8a: 095b lsrs r3, r3, #5 8006b8c: 011c lsls r4, r3, #4 8006b8e: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006b92: 2200 movs r2, #0 8006b94: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8006b98: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 8006b9c: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8006ba0: 4642 mov r2, r8 8006ba2: 464b mov r3, r9 8006ba4: 1891 adds r1, r2, r2 8006ba6: 64b9 str r1, [r7, #72] @ 0x48 8006ba8: 415b adcs r3, r3 8006baa: 64fb str r3, [r7, #76] @ 0x4c 8006bac: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8006bb0: 4641 mov r1, r8 8006bb2: eb12 0a01 adds.w sl, r2, r1 8006bb6: 4649 mov r1, r9 8006bb8: eb43 0b01 adc.w fp, r3, r1 8006bbc: f04f 0200 mov.w r2, #0 8006bc0: f04f 0300 mov.w r3, #0 8006bc4: ea4f 03cb mov.w r3, fp, lsl #3 8006bc8: ea43 735a orr.w r3, r3, sl, lsr #29 8006bcc: ea4f 02ca mov.w r2, sl, lsl #3 8006bd0: 4692 mov sl, r2 8006bd2: 469b mov fp, r3 8006bd4: 4643 mov r3, r8 8006bd6: eb1a 0303 adds.w r3, sl, r3 8006bda: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006bde: 464b mov r3, r9 8006be0: eb4b 0303 adc.w r3, fp, r3 8006be4: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8006be8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bec: 685b ldr r3, [r3, #4] 8006bee: 2200 movs r2, #0 8006bf0: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006bf4: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 8006bf8: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8006bfc: 460b mov r3, r1 8006bfe: 18db adds r3, r3, r3 8006c00: 643b str r3, [r7, #64] @ 0x40 8006c02: 4613 mov r3, r2 8006c04: eb42 0303 adc.w r3, r2, r3 8006c08: 647b str r3, [r7, #68] @ 0x44 8006c0a: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 8006c0e: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 8006c12: f7f9 faf7 bl 8000204 <__aeabi_uldivmod> 8006c16: 4602 mov r2, r0 8006c18: 460b mov r3, r1 8006c1a: 4611 mov r1, r2 8006c1c: 4b3b ldr r3, [pc, #236] @ (8006d0c ) 8006c1e: fba3 2301 umull r2, r3, r3, r1 8006c22: 095b lsrs r3, r3, #5 8006c24: 2264 movs r2, #100 @ 0x64 8006c26: fb02 f303 mul.w r3, r2, r3 8006c2a: 1acb subs r3, r1, r3 8006c2c: 00db lsls r3, r3, #3 8006c2e: f103 0232 add.w r2, r3, #50 @ 0x32 8006c32: 4b36 ldr r3, [pc, #216] @ (8006d0c ) 8006c34: fba3 2302 umull r2, r3, r3, r2 8006c38: 095b lsrs r3, r3, #5 8006c3a: 005b lsls r3, r3, #1 8006c3c: f403 73f8 and.w r3, r3, #496 @ 0x1f0 8006c40: 441c add r4, r3 8006c42: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006c46: 2200 movs r2, #0 8006c48: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006c4c: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8006c50: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 8006c54: 4642 mov r2, r8 8006c56: 464b mov r3, r9 8006c58: 1891 adds r1, r2, r2 8006c5a: 63b9 str r1, [r7, #56] @ 0x38 8006c5c: 415b adcs r3, r3 8006c5e: 63fb str r3, [r7, #60] @ 0x3c 8006c60: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 8006c64: 4641 mov r1, r8 8006c66: 1851 adds r1, r2, r1 8006c68: 6339 str r1, [r7, #48] @ 0x30 8006c6a: 4649 mov r1, r9 8006c6c: 414b adcs r3, r1 8006c6e: 637b str r3, [r7, #52] @ 0x34 8006c70: f04f 0200 mov.w r2, #0 8006c74: f04f 0300 mov.w r3, #0 8006c78: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 8006c7c: 4659 mov r1, fp 8006c7e: 00cb lsls r3, r1, #3 8006c80: 4651 mov r1, sl 8006c82: ea43 7351 orr.w r3, r3, r1, lsr #29 8006c86: 4651 mov r1, sl 8006c88: 00ca lsls r2, r1, #3 8006c8a: 4610 mov r0, r2 8006c8c: 4619 mov r1, r3 8006c8e: 4603 mov r3, r0 8006c90: 4642 mov r2, r8 8006c92: 189b adds r3, r3, r2 8006c94: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8006c98: 464b mov r3, r9 8006c9a: 460a mov r2, r1 8006c9c: eb42 0303 adc.w r3, r2, r3 8006ca0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006ca4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ca8: 685b ldr r3, [r3, #4] 8006caa: 2200 movs r2, #0 8006cac: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8006cb0: f8c7 20ac str.w r2, [r7, #172] @ 0xac 8006cb4: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8006cb8: 460b mov r3, r1 8006cba: 18db adds r3, r3, r3 8006cbc: 62bb str r3, [r7, #40] @ 0x28 8006cbe: 4613 mov r3, r2 8006cc0: eb42 0303 adc.w r3, r2, r3 8006cc4: 62fb str r3, [r7, #44] @ 0x2c 8006cc6: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 8006cca: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 8006cce: f7f9 fa99 bl 8000204 <__aeabi_uldivmod> 8006cd2: 4602 mov r2, r0 8006cd4: 460b mov r3, r1 8006cd6: 4b0d ldr r3, [pc, #52] @ (8006d0c ) 8006cd8: fba3 1302 umull r1, r3, r3, r2 8006cdc: 095b lsrs r3, r3, #5 8006cde: 2164 movs r1, #100 @ 0x64 8006ce0: fb01 f303 mul.w r3, r1, r3 8006ce4: 1ad3 subs r3, r2, r3 8006ce6: 00db lsls r3, r3, #3 8006ce8: 3332 adds r3, #50 @ 0x32 8006cea: 4a08 ldr r2, [pc, #32] @ (8006d0c ) 8006cec: fba2 2303 umull r2, r3, r2, r3 8006cf0: 095b lsrs r3, r3, #5 8006cf2: f003 0207 and.w r2, r3, #7 8006cf6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006cfa: 681b ldr r3, [r3, #0] 8006cfc: 4422 add r2, r4 8006cfe: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8006d00: e106 b.n 8006f10 8006d02: bf00 nop 8006d04: 40011000 .word 0x40011000 8006d08: 40011400 .word 0x40011400 8006d0c: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8006d10: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006d14: 2200 movs r2, #0 8006d16: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8006d1a: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 8006d1e: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8006d22: 4642 mov r2, r8 8006d24: 464b mov r3, r9 8006d26: 1891 adds r1, r2, r2 8006d28: 6239 str r1, [r7, #32] 8006d2a: 415b adcs r3, r3 8006d2c: 627b str r3, [r7, #36] @ 0x24 8006d2e: e9d7 2308 ldrd r2, r3, [r7, #32] 8006d32: 4641 mov r1, r8 8006d34: 1854 adds r4, r2, r1 8006d36: 4649 mov r1, r9 8006d38: eb43 0501 adc.w r5, r3, r1 8006d3c: f04f 0200 mov.w r2, #0 8006d40: f04f 0300 mov.w r3, #0 8006d44: 00eb lsls r3, r5, #3 8006d46: ea43 7354 orr.w r3, r3, r4, lsr #29 8006d4a: 00e2 lsls r2, r4, #3 8006d4c: 4614 mov r4, r2 8006d4e: 461d mov r5, r3 8006d50: 4643 mov r3, r8 8006d52: 18e3 adds r3, r4, r3 8006d54: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8006d58: 464b mov r3, r9 8006d5a: eb45 0303 adc.w r3, r5, r3 8006d5e: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8006d62: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006d66: 685b ldr r3, [r3, #4] 8006d68: 2200 movs r2, #0 8006d6a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8006d6e: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8006d72: f04f 0200 mov.w r2, #0 8006d76: f04f 0300 mov.w r3, #0 8006d7a: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8006d7e: 4629 mov r1, r5 8006d80: 008b lsls r3, r1, #2 8006d82: 4621 mov r1, r4 8006d84: ea43 7391 orr.w r3, r3, r1, lsr #30 8006d88: 4621 mov r1, r4 8006d8a: 008a lsls r2, r1, #2 8006d8c: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 8006d90: f7f9 fa38 bl 8000204 <__aeabi_uldivmod> 8006d94: 4602 mov r2, r0 8006d96: 460b mov r3, r1 8006d98: 4b60 ldr r3, [pc, #384] @ (8006f1c ) 8006d9a: fba3 2302 umull r2, r3, r3, r2 8006d9e: 095b lsrs r3, r3, #5 8006da0: 011c lsls r4, r3, #4 8006da2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006da6: 2200 movs r2, #0 8006da8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8006dac: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8006db0: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 8006db4: 4642 mov r2, r8 8006db6: 464b mov r3, r9 8006db8: 1891 adds r1, r2, r2 8006dba: 61b9 str r1, [r7, #24] 8006dbc: 415b adcs r3, r3 8006dbe: 61fb str r3, [r7, #28] 8006dc0: e9d7 2306 ldrd r2, r3, [r7, #24] 8006dc4: 4641 mov r1, r8 8006dc6: 1851 adds r1, r2, r1 8006dc8: 6139 str r1, [r7, #16] 8006dca: 4649 mov r1, r9 8006dcc: 414b adcs r3, r1 8006dce: 617b str r3, [r7, #20] 8006dd0: f04f 0200 mov.w r2, #0 8006dd4: f04f 0300 mov.w r3, #0 8006dd8: e9d7 ab04 ldrd sl, fp, [r7, #16] 8006ddc: 4659 mov r1, fp 8006dde: 00cb lsls r3, r1, #3 8006de0: 4651 mov r1, sl 8006de2: ea43 7351 orr.w r3, r3, r1, lsr #29 8006de6: 4651 mov r1, sl 8006de8: 00ca lsls r2, r1, #3 8006dea: 4610 mov r0, r2 8006dec: 4619 mov r1, r3 8006dee: 4603 mov r3, r0 8006df0: 4642 mov r2, r8 8006df2: 189b adds r3, r3, r2 8006df4: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8006df8: 464b mov r3, r9 8006dfa: 460a mov r2, r1 8006dfc: eb42 0303 adc.w r3, r2, r3 8006e00: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006e04: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006e08: 685b ldr r3, [r3, #4] 8006e0a: 2200 movs r2, #0 8006e0c: 67bb str r3, [r7, #120] @ 0x78 8006e0e: 67fa str r2, [r7, #124] @ 0x7c 8006e10: f04f 0200 mov.w r2, #0 8006e14: f04f 0300 mov.w r3, #0 8006e18: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 8006e1c: 4649 mov r1, r9 8006e1e: 008b lsls r3, r1, #2 8006e20: 4641 mov r1, r8 8006e22: ea43 7391 orr.w r3, r3, r1, lsr #30 8006e26: 4641 mov r1, r8 8006e28: 008a lsls r2, r1, #2 8006e2a: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 8006e2e: f7f9 f9e9 bl 8000204 <__aeabi_uldivmod> 8006e32: 4602 mov r2, r0 8006e34: 460b mov r3, r1 8006e36: 4611 mov r1, r2 8006e38: 4b38 ldr r3, [pc, #224] @ (8006f1c ) 8006e3a: fba3 2301 umull r2, r3, r3, r1 8006e3e: 095b lsrs r3, r3, #5 8006e40: 2264 movs r2, #100 @ 0x64 8006e42: fb02 f303 mul.w r3, r2, r3 8006e46: 1acb subs r3, r1, r3 8006e48: 011b lsls r3, r3, #4 8006e4a: 3332 adds r3, #50 @ 0x32 8006e4c: 4a33 ldr r2, [pc, #204] @ (8006f1c ) 8006e4e: fba2 2303 umull r2, r3, r2, r3 8006e52: 095b lsrs r3, r3, #5 8006e54: f003 03f0 and.w r3, r3, #240 @ 0xf0 8006e58: 441c add r4, r3 8006e5a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006e5e: 2200 movs r2, #0 8006e60: 673b str r3, [r7, #112] @ 0x70 8006e62: 677a str r2, [r7, #116] @ 0x74 8006e64: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 8006e68: 4642 mov r2, r8 8006e6a: 464b mov r3, r9 8006e6c: 1891 adds r1, r2, r2 8006e6e: 60b9 str r1, [r7, #8] 8006e70: 415b adcs r3, r3 8006e72: 60fb str r3, [r7, #12] 8006e74: e9d7 2302 ldrd r2, r3, [r7, #8] 8006e78: 4641 mov r1, r8 8006e7a: 1851 adds r1, r2, r1 8006e7c: 6039 str r1, [r7, #0] 8006e7e: 4649 mov r1, r9 8006e80: 414b adcs r3, r1 8006e82: 607b str r3, [r7, #4] 8006e84: f04f 0200 mov.w r2, #0 8006e88: f04f 0300 mov.w r3, #0 8006e8c: e9d7 ab00 ldrd sl, fp, [r7] 8006e90: 4659 mov r1, fp 8006e92: 00cb lsls r3, r1, #3 8006e94: 4651 mov r1, sl 8006e96: ea43 7351 orr.w r3, r3, r1, lsr #29 8006e9a: 4651 mov r1, sl 8006e9c: 00ca lsls r2, r1, #3 8006e9e: 4610 mov r0, r2 8006ea0: 4619 mov r1, r3 8006ea2: 4603 mov r3, r0 8006ea4: 4642 mov r2, r8 8006ea6: 189b adds r3, r3, r2 8006ea8: 66bb str r3, [r7, #104] @ 0x68 8006eaa: 464b mov r3, r9 8006eac: 460a mov r2, r1 8006eae: eb42 0303 adc.w r3, r2, r3 8006eb2: 66fb str r3, [r7, #108] @ 0x6c 8006eb4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006eb8: 685b ldr r3, [r3, #4] 8006eba: 2200 movs r2, #0 8006ebc: 663b str r3, [r7, #96] @ 0x60 8006ebe: 667a str r2, [r7, #100] @ 0x64 8006ec0: f04f 0200 mov.w r2, #0 8006ec4: f04f 0300 mov.w r3, #0 8006ec8: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 8006ecc: 4649 mov r1, r9 8006ece: 008b lsls r3, r1, #2 8006ed0: 4641 mov r1, r8 8006ed2: ea43 7391 orr.w r3, r3, r1, lsr #30 8006ed6: 4641 mov r1, r8 8006ed8: 008a lsls r2, r1, #2 8006eda: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 8006ede: f7f9 f991 bl 8000204 <__aeabi_uldivmod> 8006ee2: 4602 mov r2, r0 8006ee4: 460b mov r3, r1 8006ee6: 4b0d ldr r3, [pc, #52] @ (8006f1c ) 8006ee8: fba3 1302 umull r1, r3, r3, r2 8006eec: 095b lsrs r3, r3, #5 8006eee: 2164 movs r1, #100 @ 0x64 8006ef0: fb01 f303 mul.w r3, r1, r3 8006ef4: 1ad3 subs r3, r2, r3 8006ef6: 011b lsls r3, r3, #4 8006ef8: 3332 adds r3, #50 @ 0x32 8006efa: 4a08 ldr r2, [pc, #32] @ (8006f1c ) 8006efc: fba2 2303 umull r2, r3, r2, r3 8006f00: 095b lsrs r3, r3, #5 8006f02: f003 020f and.w r2, r3, #15 8006f06: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006f0a: 681b ldr r3, [r3, #0] 8006f0c: 4422 add r2, r4 8006f0e: 609a str r2, [r3, #8] } 8006f10: bf00 nop 8006f12: f507 7780 add.w r7, r7, #256 @ 0x100 8006f16: 46bd mov sp, r7 8006f18: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8006f1c: 51eb851f .word 0x51eb851f 08006f20 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8006f20: b084 sub sp, #16 8006f22: b580 push {r7, lr} 8006f24: b084 sub sp, #16 8006f26: af00 add r7, sp, #0 8006f28: 6078 str r0, [r7, #4] 8006f2a: f107 001c add.w r0, r7, #28 8006f2e: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8006f32: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 8006f36: 2b01 cmp r3, #1 8006f38: d123 bne.n 8006f82 { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8006f3a: 687b ldr r3, [r7, #4] 8006f3c: 6b9b ldr r3, [r3, #56] @ 0x38 8006f3e: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8006f42: 687b ldr r3, [r7, #4] 8006f44: 639a str r2, [r3, #56] @ 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 8006f46: 687b ldr r3, [r7, #4] 8006f48: 68db ldr r3, [r3, #12] 8006f4a: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 8006f4e: f023 0340 bic.w r3, r3, #64 @ 0x40 8006f52: 687a ldr r2, [r7, #4] 8006f54: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 8006f56: 687b ldr r3, [r7, #4] 8006f58: 68db ldr r3, [r3, #12] 8006f5a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8006f5e: 687b ldr r3, [r7, #4] 8006f60: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8006f62: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8006f66: 2b01 cmp r3, #1 8006f68: d105 bne.n 8006f76 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 8006f6a: 687b ldr r3, [r7, #4] 8006f6c: 68db ldr r3, [r3, #12] 8006f6e: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8006f72: 687b ldr r3, [r7, #4] 8006f74: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8006f76: 6878 ldr r0, [r7, #4] 8006f78: f001 fae2 bl 8008540 8006f7c: 4603 mov r3, r0 8006f7e: 73fb strb r3, [r7, #15] 8006f80: e01b b.n 8006fba } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8006f82: 687b ldr r3, [r7, #4] 8006f84: 68db ldr r3, [r3, #12] 8006f86: f043 0240 orr.w r2, r3, #64 @ 0x40 8006f8a: 687b ldr r3, [r7, #4] 8006f8c: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8006f8e: 6878 ldr r0, [r7, #4] 8006f90: f001 fad6 bl 8008540 8006f94: 4603 mov r3, r0 8006f96: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 8006f98: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 8006f9c: 2b00 cmp r3, #0 8006f9e: d106 bne.n 8006fae { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8006fa0: 687b ldr r3, [r7, #4] 8006fa2: 6b9b ldr r3, [r3, #56] @ 0x38 8006fa4: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8006fa8: 687b ldr r3, [r7, #4] 8006faa: 639a str r2, [r3, #56] @ 0x38 8006fac: e005 b.n 8006fba } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8006fae: 687b ldr r3, [r7, #4] 8006fb0: 6b9b ldr r3, [r3, #56] @ 0x38 8006fb2: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8006fb6: 687b ldr r3, [r7, #4] 8006fb8: 639a str r2, [r3, #56] @ 0x38 } } if (cfg.dma_enable == 1U) 8006fba: 7fbb ldrb r3, [r7, #30] 8006fbc: 2b01 cmp r3, #1 8006fbe: d10b bne.n 8006fd8 { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8006fc0: 687b ldr r3, [r7, #4] 8006fc2: 689b ldr r3, [r3, #8] 8006fc4: f043 0206 orr.w r2, r3, #6 8006fc8: 687b ldr r3, [r7, #4] 8006fca: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 8006fcc: 687b ldr r3, [r7, #4] 8006fce: 689b ldr r3, [r3, #8] 8006fd0: f043 0220 orr.w r2, r3, #32 8006fd4: 687b ldr r3, [r7, #4] 8006fd6: 609a str r2, [r3, #8] } return ret; 8006fd8: 7bfb ldrb r3, [r7, #15] } 8006fda: 4618 mov r0, r3 8006fdc: 3710 adds r7, #16 8006fde: 46bd mov sp, r7 8006fe0: e8bd 4080 ldmia.w sp!, {r7, lr} 8006fe4: b004 add sp, #16 8006fe6: 4770 bx lr 08006fe8 : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8006fe8: b480 push {r7} 8006fea: b087 sub sp, #28 8006fec: af00 add r7, sp, #0 8006fee: 60f8 str r0, [r7, #12] 8006ff0: 60b9 str r1, [r7, #8] 8006ff2: 4613 mov r3, r2 8006ff4: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 8006ff6: 79fb ldrb r3, [r7, #7] 8006ff8: 2b02 cmp r3, #2 8006ffa: d165 bne.n 80070c8 { if ((hclk >= 14200000U) && (hclk < 15000000U)) 8006ffc: 68bb ldr r3, [r7, #8] 8006ffe: 4a41 ldr r2, [pc, #260] @ (8007104 ) 8007000: 4293 cmp r3, r2 8007002: d906 bls.n 8007012 8007004: 68bb ldr r3, [r7, #8] 8007006: 4a40 ldr r2, [pc, #256] @ (8007108 ) 8007008: 4293 cmp r3, r2 800700a: d202 bcs.n 8007012 { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 800700c: 230f movs r3, #15 800700e: 617b str r3, [r7, #20] 8007010: e062 b.n 80070d8 } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 8007012: 68bb ldr r3, [r7, #8] 8007014: 4a3c ldr r2, [pc, #240] @ (8007108 ) 8007016: 4293 cmp r3, r2 8007018: d306 bcc.n 8007028 800701a: 68bb ldr r3, [r7, #8] 800701c: 4a3b ldr r2, [pc, #236] @ (800710c ) 800701e: 4293 cmp r3, r2 8007020: d202 bcs.n 8007028 { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8007022: 230e movs r3, #14 8007024: 617b str r3, [r7, #20] 8007026: e057 b.n 80070d8 } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 8007028: 68bb ldr r3, [r7, #8] 800702a: 4a38 ldr r2, [pc, #224] @ (800710c ) 800702c: 4293 cmp r3, r2 800702e: d306 bcc.n 800703e 8007030: 68bb ldr r3, [r7, #8] 8007032: 4a37 ldr r2, [pc, #220] @ (8007110 ) 8007034: 4293 cmp r3, r2 8007036: d202 bcs.n 800703e { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 8007038: 230d movs r3, #13 800703a: 617b str r3, [r7, #20] 800703c: e04c b.n 80070d8 } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 800703e: 68bb ldr r3, [r7, #8] 8007040: 4a33 ldr r2, [pc, #204] @ (8007110 ) 8007042: 4293 cmp r3, r2 8007044: d306 bcc.n 8007054 8007046: 68bb ldr r3, [r7, #8] 8007048: 4a32 ldr r2, [pc, #200] @ (8007114 ) 800704a: 4293 cmp r3, r2 800704c: d802 bhi.n 8007054 { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 800704e: 230c movs r3, #12 8007050: 617b str r3, [r7, #20] 8007052: e041 b.n 80070d8 } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 8007054: 68bb ldr r3, [r7, #8] 8007056: 4a2f ldr r2, [pc, #188] @ (8007114 ) 8007058: 4293 cmp r3, r2 800705a: d906 bls.n 800706a 800705c: 68bb ldr r3, [r7, #8] 800705e: 4a2e ldr r2, [pc, #184] @ (8007118 ) 8007060: 4293 cmp r3, r2 8007062: d802 bhi.n 800706a { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 8007064: 230b movs r3, #11 8007066: 617b str r3, [r7, #20] 8007068: e036 b.n 80070d8 } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 800706a: 68bb ldr r3, [r7, #8] 800706c: 4a2a ldr r2, [pc, #168] @ (8007118 ) 800706e: 4293 cmp r3, r2 8007070: d906 bls.n 8007080 8007072: 68bb ldr r3, [r7, #8] 8007074: 4a29 ldr r2, [pc, #164] @ (800711c ) 8007076: 4293 cmp r3, r2 8007078: d802 bhi.n 8007080 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 800707a: 230a movs r3, #10 800707c: 617b str r3, [r7, #20] 800707e: e02b b.n 80070d8 } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 8007080: 68bb ldr r3, [r7, #8] 8007082: 4a26 ldr r2, [pc, #152] @ (800711c ) 8007084: 4293 cmp r3, r2 8007086: d906 bls.n 8007096 8007088: 68bb ldr r3, [r7, #8] 800708a: 4a25 ldr r2, [pc, #148] @ (8007120 ) 800708c: 4293 cmp r3, r2 800708e: d202 bcs.n 8007096 { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 8007090: 2309 movs r3, #9 8007092: 617b str r3, [r7, #20] 8007094: e020 b.n 80070d8 } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 8007096: 68bb ldr r3, [r7, #8] 8007098: 4a21 ldr r2, [pc, #132] @ (8007120 ) 800709a: 4293 cmp r3, r2 800709c: d306 bcc.n 80070ac 800709e: 68bb ldr r3, [r7, #8] 80070a0: 4a20 ldr r2, [pc, #128] @ (8007124 ) 80070a2: 4293 cmp r3, r2 80070a4: d802 bhi.n 80070ac { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 80070a6: 2308 movs r3, #8 80070a8: 617b str r3, [r7, #20] 80070aa: e015 b.n 80070d8 } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 80070ac: 68bb ldr r3, [r7, #8] 80070ae: 4a1d ldr r2, [pc, #116] @ (8007124 ) 80070b0: 4293 cmp r3, r2 80070b2: d906 bls.n 80070c2 80070b4: 68bb ldr r3, [r7, #8] 80070b6: 4a1c ldr r2, [pc, #112] @ (8007128 ) 80070b8: 4293 cmp r3, r2 80070ba: d202 bcs.n 80070c2 { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 80070bc: 2307 movs r3, #7 80070be: 617b str r3, [r7, #20] 80070c0: e00a b.n 80070d8 } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 80070c2: 2306 movs r3, #6 80070c4: 617b str r3, [r7, #20] 80070c6: e007 b.n 80070d8 } } else if (speed == USBD_HS_SPEED) 80070c8: 79fb ldrb r3, [r7, #7] 80070ca: 2b00 cmp r3, #0 80070cc: d102 bne.n 80070d4 { UsbTrd = USBD_HS_TRDT_VALUE; 80070ce: 2309 movs r3, #9 80070d0: 617b str r3, [r7, #20] 80070d2: e001 b.n 80070d8 } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 80070d4: 2309 movs r3, #9 80070d6: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 80070d8: 68fb ldr r3, [r7, #12] 80070da: 68db ldr r3, [r3, #12] 80070dc: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 80070e0: 68fb ldr r3, [r7, #12] 80070e2: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 80070e4: 68fb ldr r3, [r7, #12] 80070e6: 68da ldr r2, [r3, #12] 80070e8: 697b ldr r3, [r7, #20] 80070ea: 029b lsls r3, r3, #10 80070ec: f403 5370 and.w r3, r3, #15360 @ 0x3c00 80070f0: 431a orrs r2, r3 80070f2: 68fb ldr r3, [r7, #12] 80070f4: 60da str r2, [r3, #12] return HAL_OK; 80070f6: 2300 movs r3, #0 } 80070f8: 4618 mov r0, r3 80070fa: 371c adds r7, #28 80070fc: 46bd mov sp, r7 80070fe: f85d 7b04 ldr.w r7, [sp], #4 8007102: 4770 bx lr 8007104: 00d8acbf .word 0x00d8acbf 8007108: 00e4e1c0 .word 0x00e4e1c0 800710c: 00f42400 .word 0x00f42400 8007110: 01067380 .word 0x01067380 8007114: 011a499f .word 0x011a499f 8007118: 01312cff .word 0x01312cff 800711c: 014ca43f .word 0x014ca43f 8007120: 016e3600 .word 0x016e3600 8007124: 01a6ab1f .word 0x01a6ab1f 8007128: 01e84800 .word 0x01e84800 0800712c : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 800712c: b480 push {r7} 800712e: b083 sub sp, #12 8007130: af00 add r7, sp, #0 8007132: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8007134: 687b ldr r3, [r7, #4] 8007136: 689b ldr r3, [r3, #8] 8007138: f043 0201 orr.w r2, r3, #1 800713c: 687b ldr r3, [r7, #4] 800713e: 609a str r2, [r3, #8] return HAL_OK; 8007140: 2300 movs r3, #0 } 8007142: 4618 mov r0, r3 8007144: 370c adds r7, #12 8007146: 46bd mov sp, r7 8007148: f85d 7b04 ldr.w r7, [sp], #4 800714c: 4770 bx lr 0800714e : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 800714e: b480 push {r7} 8007150: b083 sub sp, #12 8007152: af00 add r7, sp, #0 8007154: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 8007156: 687b ldr r3, [r7, #4] 8007158: 689b ldr r3, [r3, #8] 800715a: f023 0201 bic.w r2, r3, #1 800715e: 687b ldr r3, [r7, #4] 8007160: 609a str r2, [r3, #8] return HAL_OK; 8007162: 2300 movs r3, #0 } 8007164: 4618 mov r0, r3 8007166: 370c adds r7, #12 8007168: 46bd mov sp, r7 800716a: f85d 7b04 ldr.w r7, [sp], #4 800716e: 4770 bx lr 08007170 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8007170: b580 push {r7, lr} 8007172: b084 sub sp, #16 8007174: af00 add r7, sp, #0 8007176: 6078 str r0, [r7, #4] 8007178: 460b mov r3, r1 800717a: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 800717c: 2300 movs r3, #0 800717e: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8007180: 687b ldr r3, [r7, #4] 8007182: 68db ldr r3, [r3, #12] 8007184: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 8007188: 687b ldr r3, [r7, #4] 800718a: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 800718c: 78fb ldrb r3, [r7, #3] 800718e: 2b01 cmp r3, #1 8007190: d115 bne.n 80071be { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8007192: 687b ldr r3, [r7, #4] 8007194: 68db ldr r3, [r3, #12] 8007196: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 800719a: 687b ldr r3, [r7, #4] 800719c: 60da str r2, [r3, #12] do { HAL_Delay(10U); 800719e: 200a movs r0, #10 80071a0: f7fa fcc4 bl 8001b2c ms += 10U; 80071a4: 68fb ldr r3, [r7, #12] 80071a6: 330a adds r3, #10 80071a8: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 80071aa: 6878 ldr r0, [r7, #4] 80071ac: f001 f939 bl 8008422 80071b0: 4603 mov r3, r0 80071b2: 2b01 cmp r3, #1 80071b4: d01e beq.n 80071f4 80071b6: 68fb ldr r3, [r7, #12] 80071b8: 2bc7 cmp r3, #199 @ 0xc7 80071ba: d9f0 bls.n 800719e 80071bc: e01a b.n 80071f4 } else if (mode == USB_DEVICE_MODE) 80071be: 78fb ldrb r3, [r7, #3] 80071c0: 2b00 cmp r3, #0 80071c2: d115 bne.n 80071f0 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 80071c4: 687b ldr r3, [r7, #4] 80071c6: 68db ldr r3, [r3, #12] 80071c8: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 80071cc: 687b ldr r3, [r7, #4] 80071ce: 60da str r2, [r3, #12] do { HAL_Delay(10U); 80071d0: 200a movs r0, #10 80071d2: f7fa fcab bl 8001b2c ms += 10U; 80071d6: 68fb ldr r3, [r7, #12] 80071d8: 330a adds r3, #10 80071da: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 80071dc: 6878 ldr r0, [r7, #4] 80071de: f001 f920 bl 8008422 80071e2: 4603 mov r3, r0 80071e4: 2b00 cmp r3, #0 80071e6: d005 beq.n 80071f4 80071e8: 68fb ldr r3, [r7, #12] 80071ea: 2bc7 cmp r3, #199 @ 0xc7 80071ec: d9f0 bls.n 80071d0 80071ee: e001 b.n 80071f4 } else { return HAL_ERROR; 80071f0: 2301 movs r3, #1 80071f2: e005 b.n 8007200 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 80071f4: 68fb ldr r3, [r7, #12] 80071f6: 2bc8 cmp r3, #200 @ 0xc8 80071f8: d101 bne.n 80071fe { return HAL_ERROR; 80071fa: 2301 movs r3, #1 80071fc: e000 b.n 8007200 } return HAL_OK; 80071fe: 2300 movs r3, #0 } 8007200: 4618 mov r0, r3 8007202: 3710 adds r7, #16 8007204: 46bd mov sp, r7 8007206: bd80 pop {r7, pc} 08007208 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007208: b084 sub sp, #16 800720a: b580 push {r7, lr} 800720c: b086 sub sp, #24 800720e: af00 add r7, sp, #0 8007210: 6078 str r0, [r7, #4] 8007212: f107 0024 add.w r0, r7, #36 @ 0x24 8007216: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 800721a: 2300 movs r3, #0 800721c: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 800721e: 687b ldr r3, [r7, #4] 8007220: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 8007222: 2300 movs r3, #0 8007224: 613b str r3, [r7, #16] 8007226: e009 b.n 800723c { USBx->DIEPTXF[i] = 0U; 8007228: 687a ldr r2, [r7, #4] 800722a: 693b ldr r3, [r7, #16] 800722c: 3340 adds r3, #64 @ 0x40 800722e: 009b lsls r3, r3, #2 8007230: 4413 add r3, r2 8007232: 2200 movs r2, #0 8007234: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 8007236: 693b ldr r3, [r7, #16] 8007238: 3301 adds r3, #1 800723a: 613b str r3, [r7, #16] 800723c: 693b ldr r3, [r7, #16] 800723e: 2b0e cmp r3, #14 8007240: d9f2 bls.n 8007228 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 8007242: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8007246: 2b00 cmp r3, #0 8007248: d11c bne.n 8007284 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 800724a: 68fb ldr r3, [r7, #12] 800724c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007250: 685b ldr r3, [r3, #4] 8007252: 68fa ldr r2, [r7, #12] 8007254: f502 6200 add.w r2, r2, #2048 @ 0x800 8007258: f043 0302 orr.w r3, r3, #2 800725c: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 800725e: 687b ldr r3, [r7, #4] 8007260: 6b9b ldr r3, [r3, #56] @ 0x38 8007262: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 8007266: 687b ldr r3, [r7, #4] 8007268: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 800726a: 687b ldr r3, [r7, #4] 800726c: 681b ldr r3, [r3, #0] 800726e: f043 0240 orr.w r2, r3, #64 @ 0x40 8007272: 687b ldr r3, [r7, #4] 8007274: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8007276: 687b ldr r3, [r7, #4] 8007278: 681b ldr r3, [r3, #0] 800727a: f043 0280 orr.w r2, r3, #128 @ 0x80 800727e: 687b ldr r3, [r7, #4] 8007280: 601a str r2, [r3, #0] 8007282: e005 b.n 8007290 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 8007284: 687b ldr r3, [r7, #4] 8007286: 6b9b ldr r3, [r3, #56] @ 0x38 8007288: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800728c: 687b ldr r3, [r7, #4] 800728e: 639a str r2, [r3, #56] @ 0x38 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 8007290: 68fb ldr r3, [r7, #12] 8007292: f503 6360 add.w r3, r3, #3584 @ 0xe00 8007296: 461a mov r2, r3 8007298: 2300 movs r3, #0 800729a: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 800729c: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 80072a0: 2b01 cmp r3, #1 80072a2: d10d bne.n 80072c0 { if (cfg.speed == USBD_HS_SPEED) 80072a4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80072a8: 2b00 cmp r3, #0 80072aa: d104 bne.n 80072b6 { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 80072ac: 2100 movs r1, #0 80072ae: 6878 ldr r0, [r7, #4] 80072b0: f000 f968 bl 8007584 80072b4: e008 b.n 80072c8 } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 80072b6: 2101 movs r1, #1 80072b8: 6878 ldr r0, [r7, #4] 80072ba: f000 f963 bl 8007584 80072be: e003 b.n 80072c8 } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 80072c0: 2103 movs r1, #3 80072c2: 6878 ldr r0, [r7, #4] 80072c4: f000 f95e bl 8007584 } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 80072c8: 2110 movs r1, #16 80072ca: 6878 ldr r0, [r7, #4] 80072cc: f000 f8fa bl 80074c4 80072d0: 4603 mov r3, r0 80072d2: 2b00 cmp r3, #0 80072d4: d001 beq.n 80072da { ret = HAL_ERROR; 80072d6: 2301 movs r3, #1 80072d8: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 80072da: 6878 ldr r0, [r7, #4] 80072dc: f000 f924 bl 8007528 80072e0: 4603 mov r3, r0 80072e2: 2b00 cmp r3, #0 80072e4: d001 beq.n 80072ea { ret = HAL_ERROR; 80072e6: 2301 movs r3, #1 80072e8: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 80072ea: 68fb ldr r3, [r7, #12] 80072ec: f503 6300 add.w r3, r3, #2048 @ 0x800 80072f0: 461a mov r2, r3 80072f2: 2300 movs r3, #0 80072f4: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 80072f6: 68fb ldr r3, [r7, #12] 80072f8: f503 6300 add.w r3, r3, #2048 @ 0x800 80072fc: 461a mov r2, r3 80072fe: 2300 movs r3, #0 8007300: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 8007302: 68fb ldr r3, [r7, #12] 8007304: f503 6300 add.w r3, r3, #2048 @ 0x800 8007308: 461a mov r2, r3 800730a: 2300 movs r3, #0 800730c: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 800730e: 2300 movs r3, #0 8007310: 613b str r3, [r7, #16] 8007312: e043 b.n 800739c { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007314: 693b ldr r3, [r7, #16] 8007316: 015a lsls r2, r3, #5 8007318: 68fb ldr r3, [r7, #12] 800731a: 4413 add r3, r2 800731c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007320: 681b ldr r3, [r3, #0] 8007322: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007326: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800732a: d118 bne.n 800735e { if (i == 0U) 800732c: 693b ldr r3, [r7, #16] 800732e: 2b00 cmp r3, #0 8007330: d10a bne.n 8007348 { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 8007332: 693b ldr r3, [r7, #16] 8007334: 015a lsls r2, r3, #5 8007336: 68fb ldr r3, [r7, #12] 8007338: 4413 add r3, r2 800733a: f503 6310 add.w r3, r3, #2304 @ 0x900 800733e: 461a mov r2, r3 8007340: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007344: 6013 str r3, [r2, #0] 8007346: e013 b.n 8007370 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 8007348: 693b ldr r3, [r7, #16] 800734a: 015a lsls r2, r3, #5 800734c: 68fb ldr r3, [r7, #12] 800734e: 4413 add r3, r2 8007350: f503 6310 add.w r3, r3, #2304 @ 0x900 8007354: 461a mov r2, r3 8007356: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 800735a: 6013 str r3, [r2, #0] 800735c: e008 b.n 8007370 } } else { USBx_INEP(i)->DIEPCTL = 0U; 800735e: 693b ldr r3, [r7, #16] 8007360: 015a lsls r2, r3, #5 8007362: 68fb ldr r3, [r7, #12] 8007364: 4413 add r3, r2 8007366: f503 6310 add.w r3, r3, #2304 @ 0x900 800736a: 461a mov r2, r3 800736c: 2300 movs r3, #0 800736e: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8007370: 693b ldr r3, [r7, #16] 8007372: 015a lsls r2, r3, #5 8007374: 68fb ldr r3, [r7, #12] 8007376: 4413 add r3, r2 8007378: f503 6310 add.w r3, r3, #2304 @ 0x900 800737c: 461a mov r2, r3 800737e: 2300 movs r3, #0 8007380: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 8007382: 693b ldr r3, [r7, #16] 8007384: 015a lsls r2, r3, #5 8007386: 68fb ldr r3, [r7, #12] 8007388: 4413 add r3, r2 800738a: f503 6310 add.w r3, r3, #2304 @ 0x900 800738e: 461a mov r2, r3 8007390: f64f 337f movw r3, #64383 @ 0xfb7f 8007394: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8007396: 693b ldr r3, [r7, #16] 8007398: 3301 adds r3, #1 800739a: 613b str r3, [r7, #16] 800739c: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 80073a0: 461a mov r2, r3 80073a2: 693b ldr r3, [r7, #16] 80073a4: 4293 cmp r3, r2 80073a6: d3b5 bcc.n 8007314 } for (i = 0U; i < cfg.dev_endpoints; i++) 80073a8: 2300 movs r3, #0 80073aa: 613b str r3, [r7, #16] 80073ac: e043 b.n 8007436 { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80073ae: 693b ldr r3, [r7, #16] 80073b0: 015a lsls r2, r3, #5 80073b2: 68fb ldr r3, [r7, #12] 80073b4: 4413 add r3, r2 80073b6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80073ba: 681b ldr r3, [r3, #0] 80073bc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80073c0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80073c4: d118 bne.n 80073f8 { if (i == 0U) 80073c6: 693b ldr r3, [r7, #16] 80073c8: 2b00 cmp r3, #0 80073ca: d10a bne.n 80073e2 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 80073cc: 693b ldr r3, [r7, #16] 80073ce: 015a lsls r2, r3, #5 80073d0: 68fb ldr r3, [r7, #12] 80073d2: 4413 add r3, r2 80073d4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80073d8: 461a mov r2, r3 80073da: f04f 6300 mov.w r3, #134217728 @ 0x8000000 80073de: 6013 str r3, [r2, #0] 80073e0: e013 b.n 800740a } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 80073e2: 693b ldr r3, [r7, #16] 80073e4: 015a lsls r2, r3, #5 80073e6: 68fb ldr r3, [r7, #12] 80073e8: 4413 add r3, r2 80073ea: f503 6330 add.w r3, r3, #2816 @ 0xb00 80073ee: 461a mov r2, r3 80073f0: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 80073f4: 6013 str r3, [r2, #0] 80073f6: e008 b.n 800740a } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 80073f8: 693b ldr r3, [r7, #16] 80073fa: 015a lsls r2, r3, #5 80073fc: 68fb ldr r3, [r7, #12] 80073fe: 4413 add r3, r2 8007400: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007404: 461a mov r2, r3 8007406: 2300 movs r3, #0 8007408: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 800740a: 693b ldr r3, [r7, #16] 800740c: 015a lsls r2, r3, #5 800740e: 68fb ldr r3, [r7, #12] 8007410: 4413 add r3, r2 8007412: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007416: 461a mov r2, r3 8007418: 2300 movs r3, #0 800741a: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 800741c: 693b ldr r3, [r7, #16] 800741e: 015a lsls r2, r3, #5 8007420: 68fb ldr r3, [r7, #12] 8007422: 4413 add r3, r2 8007424: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007428: 461a mov r2, r3 800742a: f64f 337f movw r3, #64383 @ 0xfb7f 800742e: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8007430: 693b ldr r3, [r7, #16] 8007432: 3301 adds r3, #1 8007434: 613b str r3, [r7, #16] 8007436: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 800743a: 461a mov r2, r3 800743c: 693b ldr r3, [r7, #16] 800743e: 4293 cmp r3, r2 8007440: d3b5 bcc.n 80073ae } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 8007442: 68fb ldr r3, [r7, #12] 8007444: f503 6300 add.w r3, r3, #2048 @ 0x800 8007448: 691b ldr r3, [r3, #16] 800744a: 68fa ldr r2, [r7, #12] 800744c: f502 6200 add.w r2, r2, #2048 @ 0x800 8007450: f423 7380 bic.w r3, r3, #256 @ 0x100 8007454: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 8007456: 687b ldr r3, [r7, #4] 8007458: 2200 movs r2, #0 800745a: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 800745c: 687b ldr r3, [r7, #4] 800745e: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 8007462: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 8007464: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8007468: 2b00 cmp r3, #0 800746a: d105 bne.n 8007478 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 800746c: 687b ldr r3, [r7, #4] 800746e: 699b ldr r3, [r3, #24] 8007470: f043 0210 orr.w r2, r3, #16 8007474: 687b ldr r3, [r7, #4] 8007476: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8007478: 687b ldr r3, [r7, #4] 800747a: 699a ldr r2, [r3, #24] 800747c: 4b10 ldr r3, [pc, #64] @ (80074c0 ) 800747e: 4313 orrs r3, r2 8007480: 687a ldr r2, [r7, #4] 8007482: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 8007484: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 8007488: 2b00 cmp r3, #0 800748a: d005 beq.n 8007498 { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 800748c: 687b ldr r3, [r7, #4] 800748e: 699b ldr r3, [r3, #24] 8007490: f043 0208 orr.w r2, r3, #8 8007494: 687b ldr r3, [r7, #4] 8007496: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 8007498: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800749c: 2b01 cmp r3, #1 800749e: d107 bne.n 80074b0 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 80074a0: 687b ldr r3, [r7, #4] 80074a2: 699b ldr r3, [r3, #24] 80074a4: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80074a8: f043 0304 orr.w r3, r3, #4 80074ac: 687a ldr r2, [r7, #4] 80074ae: 6193 str r3, [r2, #24] } return ret; 80074b0: 7dfb ldrb r3, [r7, #23] } 80074b2: 4618 mov r0, r3 80074b4: 3718 adds r7, #24 80074b6: 46bd mov sp, r7 80074b8: e8bd 4080 ldmia.w sp!, {r7, lr} 80074bc: b004 add sp, #16 80074be: 4770 bx lr 80074c0: 803c3800 .word 0x803c3800 080074c4 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 80074c4: b480 push {r7} 80074c6: b085 sub sp, #20 80074c8: af00 add r7, sp, #0 80074ca: 6078 str r0, [r7, #4] 80074cc: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 80074ce: 2300 movs r3, #0 80074d0: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80074d2: 68fb ldr r3, [r7, #12] 80074d4: 3301 adds r3, #1 80074d6: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80074d8: 68fb ldr r3, [r7, #12] 80074da: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80074de: d901 bls.n 80074e4 { return HAL_TIMEOUT; 80074e0: 2303 movs r3, #3 80074e2: e01b b.n 800751c } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80074e4: 687b ldr r3, [r7, #4] 80074e6: 691b ldr r3, [r3, #16] 80074e8: 2b00 cmp r3, #0 80074ea: daf2 bge.n 80074d2 /* Flush TX Fifo */ count = 0U; 80074ec: 2300 movs r3, #0 80074ee: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 80074f0: 683b ldr r3, [r7, #0] 80074f2: 019b lsls r3, r3, #6 80074f4: f043 0220 orr.w r2, r3, #32 80074f8: 687b ldr r3, [r7, #4] 80074fa: 611a str r2, [r3, #16] do { count++; 80074fc: 68fb ldr r3, [r7, #12] 80074fe: 3301 adds r3, #1 8007500: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007502: 68fb ldr r3, [r7, #12] 8007504: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007508: d901 bls.n 800750e { return HAL_TIMEOUT; 800750a: 2303 movs r3, #3 800750c: e006 b.n 800751c } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 800750e: 687b ldr r3, [r7, #4] 8007510: 691b ldr r3, [r3, #16] 8007512: f003 0320 and.w r3, r3, #32 8007516: 2b20 cmp r3, #32 8007518: d0f0 beq.n 80074fc return HAL_OK; 800751a: 2300 movs r3, #0 } 800751c: 4618 mov r0, r3 800751e: 3714 adds r7, #20 8007520: 46bd mov sp, r7 8007522: f85d 7b04 ldr.w r7, [sp], #4 8007526: 4770 bx lr 08007528 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 8007528: b480 push {r7} 800752a: b085 sub sp, #20 800752c: af00 add r7, sp, #0 800752e: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8007530: 2300 movs r3, #0 8007532: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8007534: 68fb ldr r3, [r7, #12] 8007536: 3301 adds r3, #1 8007538: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800753a: 68fb ldr r3, [r7, #12] 800753c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007540: d901 bls.n 8007546 { return HAL_TIMEOUT; 8007542: 2303 movs r3, #3 8007544: e018 b.n 8007578 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8007546: 687b ldr r3, [r7, #4] 8007548: 691b ldr r3, [r3, #16] 800754a: 2b00 cmp r3, #0 800754c: daf2 bge.n 8007534 /* Flush RX Fifo */ count = 0U; 800754e: 2300 movs r3, #0 8007550: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 8007552: 687b ldr r3, [r7, #4] 8007554: 2210 movs r2, #16 8007556: 611a str r2, [r3, #16] do { count++; 8007558: 68fb ldr r3, [r7, #12] 800755a: 3301 adds r3, #1 800755c: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800755e: 68fb ldr r3, [r7, #12] 8007560: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007564: d901 bls.n 800756a { return HAL_TIMEOUT; 8007566: 2303 movs r3, #3 8007568: e006 b.n 8007578 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 800756a: 687b ldr r3, [r7, #4] 800756c: 691b ldr r3, [r3, #16] 800756e: f003 0310 and.w r3, r3, #16 8007572: 2b10 cmp r3, #16 8007574: d0f0 beq.n 8007558 return HAL_OK; 8007576: 2300 movs r3, #0 } 8007578: 4618 mov r0, r3 800757a: 3714 adds r7, #20 800757c: 46bd mov sp, r7 800757e: f85d 7b04 ldr.w r7, [sp], #4 8007582: 4770 bx lr 08007584 : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 8007584: b480 push {r7} 8007586: b085 sub sp, #20 8007588: af00 add r7, sp, #0 800758a: 6078 str r0, [r7, #4] 800758c: 460b mov r3, r1 800758e: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8007590: 687b ldr r3, [r7, #4] 8007592: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 8007594: 68fb ldr r3, [r7, #12] 8007596: f503 6300 add.w r3, r3, #2048 @ 0x800 800759a: 681a ldr r2, [r3, #0] 800759c: 78fb ldrb r3, [r7, #3] 800759e: 68f9 ldr r1, [r7, #12] 80075a0: f501 6100 add.w r1, r1, #2048 @ 0x800 80075a4: 4313 orrs r3, r2 80075a6: 600b str r3, [r1, #0] return HAL_OK; 80075a8: 2300 movs r3, #0 } 80075aa: 4618 mov r0, r3 80075ac: 3714 adds r7, #20 80075ae: 46bd mov sp, r7 80075b0: f85d 7b04 ldr.w r7, [sp], #4 80075b4: 4770 bx lr 080075b6 : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { 80075b6: b480 push {r7} 80075b8: b087 sub sp, #28 80075ba: af00 add r7, sp, #0 80075bc: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80075be: 687b ldr r3, [r7, #4] 80075c0: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 80075c2: 693b ldr r3, [r7, #16] 80075c4: f503 6300 add.w r3, r3, #2048 @ 0x800 80075c8: 689b ldr r3, [r3, #8] 80075ca: f003 0306 and.w r3, r3, #6 80075ce: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 80075d0: 68fb ldr r3, [r7, #12] 80075d2: 2b00 cmp r3, #0 80075d4: d102 bne.n 80075dc { speed = USBD_HS_SPEED; 80075d6: 2300 movs r3, #0 80075d8: 75fb strb r3, [r7, #23] 80075da: e00a b.n 80075f2 } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 80075dc: 68fb ldr r3, [r7, #12] 80075de: 2b02 cmp r3, #2 80075e0: d002 beq.n 80075e8 80075e2: 68fb ldr r3, [r7, #12] 80075e4: 2b06 cmp r3, #6 80075e6: d102 bne.n 80075ee (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 80075e8: 2302 movs r3, #2 80075ea: 75fb strb r3, [r7, #23] 80075ec: e001 b.n 80075f2 } else { speed = 0xFU; 80075ee: 230f movs r3, #15 80075f0: 75fb strb r3, [r7, #23] } return speed; 80075f2: 7dfb ldrb r3, [r7, #23] } 80075f4: 4618 mov r0, r3 80075f6: 371c adds r7, #28 80075f8: 46bd mov sp, r7 80075fa: f85d 7b04 ldr.w r7, [sp], #4 80075fe: 4770 bx lr 08007600 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007600: b480 push {r7} 8007602: b085 sub sp, #20 8007604: af00 add r7, sp, #0 8007606: 6078 str r0, [r7, #4] 8007608: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800760a: 687b ldr r3, [r7, #4] 800760c: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 800760e: 683b ldr r3, [r7, #0] 8007610: 781b ldrb r3, [r3, #0] 8007612: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007614: 683b ldr r3, [r7, #0] 8007616: 785b ldrb r3, [r3, #1] 8007618: 2b01 cmp r3, #1 800761a: d13a bne.n 8007692 { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 800761c: 68fb ldr r3, [r7, #12] 800761e: f503 6300 add.w r3, r3, #2048 @ 0x800 8007622: 69da ldr r2, [r3, #28] 8007624: 683b ldr r3, [r7, #0] 8007626: 781b ldrb r3, [r3, #0] 8007628: f003 030f and.w r3, r3, #15 800762c: 2101 movs r1, #1 800762e: fa01 f303 lsl.w r3, r1, r3 8007632: b29b uxth r3, r3 8007634: 68f9 ldr r1, [r7, #12] 8007636: f501 6100 add.w r1, r1, #2048 @ 0x800 800763a: 4313 orrs r3, r2 800763c: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 800763e: 68bb ldr r3, [r7, #8] 8007640: 015a lsls r2, r3, #5 8007642: 68fb ldr r3, [r7, #12] 8007644: 4413 add r3, r2 8007646: f503 6310 add.w r3, r3, #2304 @ 0x900 800764a: 681b ldr r3, [r3, #0] 800764c: f403 4300 and.w r3, r3, #32768 @ 0x8000 8007650: 2b00 cmp r3, #0 8007652: d155 bne.n 8007700 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007654: 68bb ldr r3, [r7, #8] 8007656: 015a lsls r2, r3, #5 8007658: 68fb ldr r3, [r7, #12] 800765a: 4413 add r3, r2 800765c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007660: 681a ldr r2, [r3, #0] 8007662: 683b ldr r3, [r7, #0] 8007664: 689b ldr r3, [r3, #8] 8007666: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 800766a: 683b ldr r3, [r7, #0] 800766c: 791b ldrb r3, [r3, #4] 800766e: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007670: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 8007672: 68bb ldr r3, [r7, #8] 8007674: 059b lsls r3, r3, #22 8007676: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007678: 4313 orrs r3, r2 800767a: 68ba ldr r2, [r7, #8] 800767c: 0151 lsls r1, r2, #5 800767e: 68fa ldr r2, [r7, #12] 8007680: 440a add r2, r1 8007682: f502 6210 add.w r2, r2, #2304 @ 0x900 8007686: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800768a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800768e: 6013 str r3, [r2, #0] 8007690: e036 b.n 8007700 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 8007692: 68fb ldr r3, [r7, #12] 8007694: f503 6300 add.w r3, r3, #2048 @ 0x800 8007698: 69da ldr r2, [r3, #28] 800769a: 683b ldr r3, [r7, #0] 800769c: 781b ldrb r3, [r3, #0] 800769e: f003 030f and.w r3, r3, #15 80076a2: 2101 movs r1, #1 80076a4: fa01 f303 lsl.w r3, r1, r3 80076a8: 041b lsls r3, r3, #16 80076aa: 68f9 ldr r1, [r7, #12] 80076ac: f501 6100 add.w r1, r1, #2048 @ 0x800 80076b0: 4313 orrs r3, r2 80076b2: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 80076b4: 68bb ldr r3, [r7, #8] 80076b6: 015a lsls r2, r3, #5 80076b8: 68fb ldr r3, [r7, #12] 80076ba: 4413 add r3, r2 80076bc: f503 6330 add.w r3, r3, #2816 @ 0xb00 80076c0: 681b ldr r3, [r3, #0] 80076c2: f403 4300 and.w r3, r3, #32768 @ 0x8000 80076c6: 2b00 cmp r3, #0 80076c8: d11a bne.n 8007700 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 80076ca: 68bb ldr r3, [r7, #8] 80076cc: 015a lsls r2, r3, #5 80076ce: 68fb ldr r3, [r7, #12] 80076d0: 4413 add r3, r2 80076d2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80076d6: 681a ldr r2, [r3, #0] 80076d8: 683b ldr r3, [r7, #0] 80076da: 689b ldr r3, [r3, #8] 80076dc: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 80076e0: 683b ldr r3, [r7, #0] 80076e2: 791b ldrb r3, [r3, #4] 80076e4: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 80076e6: 430b orrs r3, r1 80076e8: 4313 orrs r3, r2 80076ea: 68ba ldr r2, [r7, #8] 80076ec: 0151 lsls r1, r2, #5 80076ee: 68fa ldr r2, [r7, #12] 80076f0: 440a add r2, r1 80076f2: f502 6230 add.w r2, r2, #2816 @ 0xb00 80076f6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80076fa: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80076fe: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 8007700: 2300 movs r3, #0 } 8007702: 4618 mov r0, r3 8007704: 3714 adds r7, #20 8007706: 46bd mov sp, r7 8007708: f85d 7b04 ldr.w r7, [sp], #4 800770c: 4770 bx lr ... 08007710 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007710: b480 push {r7} 8007712: b085 sub sp, #20 8007714: af00 add r7, sp, #0 8007716: 6078 str r0, [r7, #4] 8007718: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800771a: 687b ldr r3, [r7, #4] 800771c: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 800771e: 683b ldr r3, [r7, #0] 8007720: 781b ldrb r3, [r3, #0] 8007722: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 8007724: 683b ldr r3, [r7, #0] 8007726: 785b ldrb r3, [r3, #1] 8007728: 2b01 cmp r3, #1 800772a: d161 bne.n 80077f0 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 800772c: 68bb ldr r3, [r7, #8] 800772e: 015a lsls r2, r3, #5 8007730: 68fb ldr r3, [r7, #12] 8007732: 4413 add r3, r2 8007734: f503 6310 add.w r3, r3, #2304 @ 0x900 8007738: 681b ldr r3, [r3, #0] 800773a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800773e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007742: d11f bne.n 8007784 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 8007744: 68bb ldr r3, [r7, #8] 8007746: 015a lsls r2, r3, #5 8007748: 68fb ldr r3, [r7, #12] 800774a: 4413 add r3, r2 800774c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007750: 681b ldr r3, [r3, #0] 8007752: 68ba ldr r2, [r7, #8] 8007754: 0151 lsls r1, r2, #5 8007756: 68fa ldr r2, [r7, #12] 8007758: 440a add r2, r1 800775a: f502 6210 add.w r2, r2, #2304 @ 0x900 800775e: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007762: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 8007764: 68bb ldr r3, [r7, #8] 8007766: 015a lsls r2, r3, #5 8007768: 68fb ldr r3, [r7, #12] 800776a: 4413 add r3, r2 800776c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007770: 681b ldr r3, [r3, #0] 8007772: 68ba ldr r2, [r7, #8] 8007774: 0151 lsls r1, r2, #5 8007776: 68fa ldr r2, [r7, #12] 8007778: 440a add r2, r1 800777a: f502 6210 add.w r2, r2, #2304 @ 0x900 800777e: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007782: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8007784: 68fb ldr r3, [r7, #12] 8007786: f503 6300 add.w r3, r3, #2048 @ 0x800 800778a: 6bda ldr r2, [r3, #60] @ 0x3c 800778c: 683b ldr r3, [r7, #0] 800778e: 781b ldrb r3, [r3, #0] 8007790: f003 030f and.w r3, r3, #15 8007794: 2101 movs r1, #1 8007796: fa01 f303 lsl.w r3, r1, r3 800779a: b29b uxth r3, r3 800779c: 43db mvns r3, r3 800779e: 68f9 ldr r1, [r7, #12] 80077a0: f501 6100 add.w r1, r1, #2048 @ 0x800 80077a4: 4013 ands r3, r2 80077a6: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80077a8: 68fb ldr r3, [r7, #12] 80077aa: f503 6300 add.w r3, r3, #2048 @ 0x800 80077ae: 69da ldr r2, [r3, #28] 80077b0: 683b ldr r3, [r7, #0] 80077b2: 781b ldrb r3, [r3, #0] 80077b4: f003 030f and.w r3, r3, #15 80077b8: 2101 movs r1, #1 80077ba: fa01 f303 lsl.w r3, r1, r3 80077be: b29b uxth r3, r3 80077c0: 43db mvns r3, r3 80077c2: 68f9 ldr r1, [r7, #12] 80077c4: f501 6100 add.w r1, r1, #2048 @ 0x800 80077c8: 4013 ands r3, r2 80077ca: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 80077cc: 68bb ldr r3, [r7, #8] 80077ce: 015a lsls r2, r3, #5 80077d0: 68fb ldr r3, [r7, #12] 80077d2: 4413 add r3, r2 80077d4: f503 6310 add.w r3, r3, #2304 @ 0x900 80077d8: 681a ldr r2, [r3, #0] 80077da: 68bb ldr r3, [r7, #8] 80077dc: 0159 lsls r1, r3, #5 80077de: 68fb ldr r3, [r7, #12] 80077e0: 440b add r3, r1 80077e2: f503 6310 add.w r3, r3, #2304 @ 0x900 80077e6: 4619 mov r1, r3 80077e8: 4b35 ldr r3, [pc, #212] @ (80078c0 ) 80077ea: 4013 ands r3, r2 80077ec: 600b str r3, [r1, #0] 80077ee: e060 b.n 80078b2 USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80077f0: 68bb ldr r3, [r7, #8] 80077f2: 015a lsls r2, r3, #5 80077f4: 68fb ldr r3, [r7, #12] 80077f6: 4413 add r3, r2 80077f8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80077fc: 681b ldr r3, [r3, #0] 80077fe: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007802: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007806: d11f bne.n 8007848 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8007808: 68bb ldr r3, [r7, #8] 800780a: 015a lsls r2, r3, #5 800780c: 68fb ldr r3, [r7, #12] 800780e: 4413 add r3, r2 8007810: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007814: 681b ldr r3, [r3, #0] 8007816: 68ba ldr r2, [r7, #8] 8007818: 0151 lsls r1, r2, #5 800781a: 68fa ldr r2, [r7, #12] 800781c: 440a add r2, r1 800781e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007822: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007826: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 8007828: 68bb ldr r3, [r7, #8] 800782a: 015a lsls r2, r3, #5 800782c: 68fb ldr r3, [r7, #12] 800782e: 4413 add r3, r2 8007830: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007834: 681b ldr r3, [r3, #0] 8007836: 68ba ldr r2, [r7, #8] 8007838: 0151 lsls r1, r2, #5 800783a: 68fa ldr r2, [r7, #12] 800783c: 440a add r2, r1 800783e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007842: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007846: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8007848: 68fb ldr r3, [r7, #12] 800784a: f503 6300 add.w r3, r3, #2048 @ 0x800 800784e: 6bda ldr r2, [r3, #60] @ 0x3c 8007850: 683b ldr r3, [r7, #0] 8007852: 781b ldrb r3, [r3, #0] 8007854: f003 030f and.w r3, r3, #15 8007858: 2101 movs r1, #1 800785a: fa01 f303 lsl.w r3, r1, r3 800785e: 041b lsls r3, r3, #16 8007860: 43db mvns r3, r3 8007862: 68f9 ldr r1, [r7, #12] 8007864: f501 6100 add.w r1, r1, #2048 @ 0x800 8007868: 4013 ands r3, r2 800786a: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 800786c: 68fb ldr r3, [r7, #12] 800786e: f503 6300 add.w r3, r3, #2048 @ 0x800 8007872: 69da ldr r2, [r3, #28] 8007874: 683b ldr r3, [r7, #0] 8007876: 781b ldrb r3, [r3, #0] 8007878: f003 030f and.w r3, r3, #15 800787c: 2101 movs r1, #1 800787e: fa01 f303 lsl.w r3, r1, r3 8007882: 041b lsls r3, r3, #16 8007884: 43db mvns r3, r3 8007886: 68f9 ldr r1, [r7, #12] 8007888: f501 6100 add.w r1, r1, #2048 @ 0x800 800788c: 4013 ands r3, r2 800788e: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 8007890: 68bb ldr r3, [r7, #8] 8007892: 015a lsls r2, r3, #5 8007894: 68fb ldr r3, [r7, #12] 8007896: 4413 add r3, r2 8007898: f503 6330 add.w r3, r3, #2816 @ 0xb00 800789c: 681a ldr r2, [r3, #0] 800789e: 68bb ldr r3, [r7, #8] 80078a0: 0159 lsls r1, r3, #5 80078a2: 68fb ldr r3, [r7, #12] 80078a4: 440b add r3, r1 80078a6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80078aa: 4619 mov r1, r3 80078ac: 4b05 ldr r3, [pc, #20] @ (80078c4 ) 80078ae: 4013 ands r3, r2 80078b0: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 80078b2: 2300 movs r3, #0 } 80078b4: 4618 mov r0, r3 80078b6: 3714 adds r7, #20 80078b8: 46bd mov sp, r7 80078ba: f85d 7b04 ldr.w r7, [sp], #4 80078be: 4770 bx lr 80078c0: ec337800 .word 0xec337800 80078c4: eff37800 .word 0xeff37800 080078c8 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 80078c8: b580 push {r7, lr} 80078ca: b08a sub sp, #40 @ 0x28 80078cc: af02 add r7, sp, #8 80078ce: 60f8 str r0, [r7, #12] 80078d0: 60b9 str r1, [r7, #8] 80078d2: 4613 mov r3, r2 80078d4: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 80078d6: 68fb ldr r3, [r7, #12] 80078d8: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 80078da: 68bb ldr r3, [r7, #8] 80078dc: 781b ldrb r3, [r3, #0] 80078de: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 80078e0: 68bb ldr r3, [r7, #8] 80078e2: 785b ldrb r3, [r3, #1] 80078e4: 2b01 cmp r3, #1 80078e6: f040 817f bne.w 8007be8 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 80078ea: 68bb ldr r3, [r7, #8] 80078ec: 691b ldr r3, [r3, #16] 80078ee: 2b00 cmp r3, #0 80078f0: d132 bne.n 8007958 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 80078f2: 69bb ldr r3, [r7, #24] 80078f4: 015a lsls r2, r3, #5 80078f6: 69fb ldr r3, [r7, #28] 80078f8: 4413 add r3, r2 80078fa: f503 6310 add.w r3, r3, #2304 @ 0x900 80078fe: 691b ldr r3, [r3, #16] 8007900: 69ba ldr r2, [r7, #24] 8007902: 0151 lsls r1, r2, #5 8007904: 69fa ldr r2, [r7, #28] 8007906: 440a add r2, r1 8007908: f502 6210 add.w r2, r2, #2304 @ 0x900 800790c: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007910: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007914: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8007916: 69bb ldr r3, [r7, #24] 8007918: 015a lsls r2, r3, #5 800791a: 69fb ldr r3, [r7, #28] 800791c: 4413 add r3, r2 800791e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007922: 691b ldr r3, [r3, #16] 8007924: 69ba ldr r2, [r7, #24] 8007926: 0151 lsls r1, r2, #5 8007928: 69fa ldr r2, [r7, #28] 800792a: 440a add r2, r1 800792c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007930: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007934: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8007936: 69bb ldr r3, [r7, #24] 8007938: 015a lsls r2, r3, #5 800793a: 69fb ldr r3, [r7, #28] 800793c: 4413 add r3, r2 800793e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007942: 691b ldr r3, [r3, #16] 8007944: 69ba ldr r2, [r7, #24] 8007946: 0151 lsls r1, r2, #5 8007948: 69fa ldr r2, [r7, #28] 800794a: 440a add r2, r1 800794c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007950: 0cdb lsrs r3, r3, #19 8007952: 04db lsls r3, r3, #19 8007954: 6113 str r3, [r2, #16] 8007956: e097 b.n 8007a88 /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8007958: 69bb ldr r3, [r7, #24] 800795a: 015a lsls r2, r3, #5 800795c: 69fb ldr r3, [r7, #28] 800795e: 4413 add r3, r2 8007960: f503 6310 add.w r3, r3, #2304 @ 0x900 8007964: 691b ldr r3, [r3, #16] 8007966: 69ba ldr r2, [r7, #24] 8007968: 0151 lsls r1, r2, #5 800796a: 69fa ldr r2, [r7, #28] 800796c: 440a add r2, r1 800796e: f502 6210 add.w r2, r2, #2304 @ 0x900 8007972: 0cdb lsrs r3, r3, #19 8007974: 04db lsls r3, r3, #19 8007976: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8007978: 69bb ldr r3, [r7, #24] 800797a: 015a lsls r2, r3, #5 800797c: 69fb ldr r3, [r7, #28] 800797e: 4413 add r3, r2 8007980: f503 6310 add.w r3, r3, #2304 @ 0x900 8007984: 691b ldr r3, [r3, #16] 8007986: 69ba ldr r2, [r7, #24] 8007988: 0151 lsls r1, r2, #5 800798a: 69fa ldr r2, [r7, #28] 800798c: 440a add r2, r1 800798e: f502 6210 add.w r2, r2, #2304 @ 0x900 8007992: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007996: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 800799a: 6113 str r3, [r2, #16] if (epnum == 0U) 800799c: 69bb ldr r3, [r7, #24] 800799e: 2b00 cmp r3, #0 80079a0: d11a bne.n 80079d8 { if (ep->xfer_len > ep->maxpacket) 80079a2: 68bb ldr r3, [r7, #8] 80079a4: 691a ldr r2, [r3, #16] 80079a6: 68bb ldr r3, [r7, #8] 80079a8: 689b ldr r3, [r3, #8] 80079aa: 429a cmp r2, r3 80079ac: d903 bls.n 80079b6 { ep->xfer_len = ep->maxpacket; 80079ae: 68bb ldr r3, [r7, #8] 80079b0: 689a ldr r2, [r3, #8] 80079b2: 68bb ldr r3, [r7, #8] 80079b4: 611a str r2, [r3, #16] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 80079b6: 69bb ldr r3, [r7, #24] 80079b8: 015a lsls r2, r3, #5 80079ba: 69fb ldr r3, [r7, #28] 80079bc: 4413 add r3, r2 80079be: f503 6310 add.w r3, r3, #2304 @ 0x900 80079c2: 691b ldr r3, [r3, #16] 80079c4: 69ba ldr r2, [r7, #24] 80079c6: 0151 lsls r1, r2, #5 80079c8: 69fa ldr r2, [r7, #28] 80079ca: 440a add r2, r1 80079cc: f502 6210 add.w r2, r2, #2304 @ 0x900 80079d0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80079d4: 6113 str r3, [r2, #16] 80079d6: e044 b.n 8007a62 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 80079d8: 68bb ldr r3, [r7, #8] 80079da: 691a ldr r2, [r3, #16] 80079dc: 68bb ldr r3, [r7, #8] 80079de: 689b ldr r3, [r3, #8] 80079e0: 4413 add r3, r2 80079e2: 1e5a subs r2, r3, #1 80079e4: 68bb ldr r3, [r7, #8] 80079e6: 689b ldr r3, [r3, #8] 80079e8: fbb2 f3f3 udiv r3, r2, r3 80079ec: 82fb strh r3, [r7, #22] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); 80079ee: 69bb ldr r3, [r7, #24] 80079f0: 015a lsls r2, r3, #5 80079f2: 69fb ldr r3, [r7, #28] 80079f4: 4413 add r3, r2 80079f6: f503 6310 add.w r3, r3, #2304 @ 0x900 80079fa: 691a ldr r2, [r3, #16] 80079fc: 8afb ldrh r3, [r7, #22] 80079fe: 04d9 lsls r1, r3, #19 8007a00: 4ba4 ldr r3, [pc, #656] @ (8007c94 ) 8007a02: 400b ands r3, r1 8007a04: 69b9 ldr r1, [r7, #24] 8007a06: 0148 lsls r0, r1, #5 8007a08: 69f9 ldr r1, [r7, #28] 8007a0a: 4401 add r1, r0 8007a0c: f501 6110 add.w r1, r1, #2304 @ 0x900 8007a10: 4313 orrs r3, r2 8007a12: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 8007a14: 68bb ldr r3, [r7, #8] 8007a16: 791b ldrb r3, [r3, #4] 8007a18: 2b01 cmp r3, #1 8007a1a: d122 bne.n 8007a62 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 8007a1c: 69bb ldr r3, [r7, #24] 8007a1e: 015a lsls r2, r3, #5 8007a20: 69fb ldr r3, [r7, #28] 8007a22: 4413 add r3, r2 8007a24: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a28: 691b ldr r3, [r3, #16] 8007a2a: 69ba ldr r2, [r7, #24] 8007a2c: 0151 lsls r1, r2, #5 8007a2e: 69fa ldr r2, [r7, #28] 8007a30: 440a add r2, r1 8007a32: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a36: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 8007a3a: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); 8007a3c: 69bb ldr r3, [r7, #24] 8007a3e: 015a lsls r2, r3, #5 8007a40: 69fb ldr r3, [r7, #28] 8007a42: 4413 add r3, r2 8007a44: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a48: 691a ldr r2, [r3, #16] 8007a4a: 8afb ldrh r3, [r7, #22] 8007a4c: 075b lsls r3, r3, #29 8007a4e: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 8007a52: 69b9 ldr r1, [r7, #24] 8007a54: 0148 lsls r0, r1, #5 8007a56: 69f9 ldr r1, [r7, #28] 8007a58: 4401 add r1, r0 8007a5a: f501 6110 add.w r1, r1, #2304 @ 0x900 8007a5e: 4313 orrs r3, r2 8007a60: 610b str r3, [r1, #16] } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8007a62: 69bb ldr r3, [r7, #24] 8007a64: 015a lsls r2, r3, #5 8007a66: 69fb ldr r3, [r7, #28] 8007a68: 4413 add r3, r2 8007a6a: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a6e: 691a ldr r2, [r3, #16] 8007a70: 68bb ldr r3, [r7, #8] 8007a72: 691b ldr r3, [r3, #16] 8007a74: f3c3 0312 ubfx r3, r3, #0, #19 8007a78: 69b9 ldr r1, [r7, #24] 8007a7a: 0148 lsls r0, r1, #5 8007a7c: 69f9 ldr r1, [r7, #28] 8007a7e: 4401 add r1, r0 8007a80: f501 6110 add.w r1, r1, #2304 @ 0x900 8007a84: 4313 orrs r3, r2 8007a86: 610b str r3, [r1, #16] } if (dma == 1U) 8007a88: 79fb ldrb r3, [r7, #7] 8007a8a: 2b01 cmp r3, #1 8007a8c: d14b bne.n 8007b26 { if ((uint32_t)ep->dma_addr != 0U) 8007a8e: 68bb ldr r3, [r7, #8] 8007a90: 69db ldr r3, [r3, #28] 8007a92: 2b00 cmp r3, #0 8007a94: d009 beq.n 8007aaa { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8007a96: 69bb ldr r3, [r7, #24] 8007a98: 015a lsls r2, r3, #5 8007a9a: 69fb ldr r3, [r7, #28] 8007a9c: 4413 add r3, r2 8007a9e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007aa2: 461a mov r2, r3 8007aa4: 68bb ldr r3, [r7, #8] 8007aa6: 69db ldr r3, [r3, #28] 8007aa8: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 8007aaa: 68bb ldr r3, [r7, #8] 8007aac: 791b ldrb r3, [r3, #4] 8007aae: 2b01 cmp r3, #1 8007ab0: d128 bne.n 8007b04 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007ab2: 69fb ldr r3, [r7, #28] 8007ab4: f503 6300 add.w r3, r3, #2048 @ 0x800 8007ab8: 689b ldr r3, [r3, #8] 8007aba: f403 7380 and.w r3, r3, #256 @ 0x100 8007abe: 2b00 cmp r3, #0 8007ac0: d110 bne.n 8007ae4 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8007ac2: 69bb ldr r3, [r7, #24] 8007ac4: 015a lsls r2, r3, #5 8007ac6: 69fb ldr r3, [r7, #28] 8007ac8: 4413 add r3, r2 8007aca: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ace: 681b ldr r3, [r3, #0] 8007ad0: 69ba ldr r2, [r7, #24] 8007ad2: 0151 lsls r1, r2, #5 8007ad4: 69fa ldr r2, [r7, #28] 8007ad6: 440a add r2, r1 8007ad8: f502 6210 add.w r2, r2, #2304 @ 0x900 8007adc: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007ae0: 6013 str r3, [r2, #0] 8007ae2: e00f b.n 8007b04 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007ae4: 69bb ldr r3, [r7, #24] 8007ae6: 015a lsls r2, r3, #5 8007ae8: 69fb ldr r3, [r7, #28] 8007aea: 4413 add r3, r2 8007aec: f503 6310 add.w r3, r3, #2304 @ 0x900 8007af0: 681b ldr r3, [r3, #0] 8007af2: 69ba ldr r2, [r7, #24] 8007af4: 0151 lsls r1, r2, #5 8007af6: 69fa ldr r2, [r7, #28] 8007af8: 440a add r2, r1 8007afa: f502 6210 add.w r2, r2, #2304 @ 0x900 8007afe: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007b02: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007b04: 69bb ldr r3, [r7, #24] 8007b06: 015a lsls r2, r3, #5 8007b08: 69fb ldr r3, [r7, #28] 8007b0a: 4413 add r3, r2 8007b0c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b10: 681b ldr r3, [r3, #0] 8007b12: 69ba ldr r2, [r7, #24] 8007b14: 0151 lsls r1, r2, #5 8007b16: 69fa ldr r2, [r7, #28] 8007b18: 440a add r2, r1 8007b1a: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b1e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007b22: 6013 str r3, [r2, #0] 8007b24: e166 b.n 8007df4 } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007b26: 69bb ldr r3, [r7, #24] 8007b28: 015a lsls r2, r3, #5 8007b2a: 69fb ldr r3, [r7, #28] 8007b2c: 4413 add r3, r2 8007b2e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b32: 681b ldr r3, [r3, #0] 8007b34: 69ba ldr r2, [r7, #24] 8007b36: 0151 lsls r1, r2, #5 8007b38: 69fa ldr r2, [r7, #28] 8007b3a: 440a add r2, r1 8007b3c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b40: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007b44: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 8007b46: 68bb ldr r3, [r7, #8] 8007b48: 791b ldrb r3, [r3, #4] 8007b4a: 2b01 cmp r3, #1 8007b4c: d015 beq.n 8007b7a { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8007b4e: 68bb ldr r3, [r7, #8] 8007b50: 691b ldr r3, [r3, #16] 8007b52: 2b00 cmp r3, #0 8007b54: f000 814e beq.w 8007df4 { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8007b58: 69fb ldr r3, [r7, #28] 8007b5a: f503 6300 add.w r3, r3, #2048 @ 0x800 8007b5e: 6b5a ldr r2, [r3, #52] @ 0x34 8007b60: 68bb ldr r3, [r7, #8] 8007b62: 781b ldrb r3, [r3, #0] 8007b64: f003 030f and.w r3, r3, #15 8007b68: 2101 movs r1, #1 8007b6a: fa01 f303 lsl.w r3, r1, r3 8007b6e: 69f9 ldr r1, [r7, #28] 8007b70: f501 6100 add.w r1, r1, #2048 @ 0x800 8007b74: 4313 orrs r3, r2 8007b76: 634b str r3, [r1, #52] @ 0x34 8007b78: e13c b.n 8007df4 } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007b7a: 69fb ldr r3, [r7, #28] 8007b7c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007b80: 689b ldr r3, [r3, #8] 8007b82: f403 7380 and.w r3, r3, #256 @ 0x100 8007b86: 2b00 cmp r3, #0 8007b88: d110 bne.n 8007bac { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8007b8a: 69bb ldr r3, [r7, #24] 8007b8c: 015a lsls r2, r3, #5 8007b8e: 69fb ldr r3, [r7, #28] 8007b90: 4413 add r3, r2 8007b92: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b96: 681b ldr r3, [r3, #0] 8007b98: 69ba ldr r2, [r7, #24] 8007b9a: 0151 lsls r1, r2, #5 8007b9c: 69fa ldr r2, [r7, #28] 8007b9e: 440a add r2, r1 8007ba0: f502 6210 add.w r2, r2, #2304 @ 0x900 8007ba4: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007ba8: 6013 str r3, [r2, #0] 8007baa: e00f b.n 8007bcc } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007bac: 69bb ldr r3, [r7, #24] 8007bae: 015a lsls r2, r3, #5 8007bb0: 69fb ldr r3, [r7, #28] 8007bb2: 4413 add r3, r2 8007bb4: f503 6310 add.w r3, r3, #2304 @ 0x900 8007bb8: 681b ldr r3, [r3, #0] 8007bba: 69ba ldr r2, [r7, #24] 8007bbc: 0151 lsls r1, r2, #5 8007bbe: 69fa ldr r2, [r7, #28] 8007bc0: 440a add r2, r1 8007bc2: f502 6210 add.w r2, r2, #2304 @ 0x900 8007bc6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007bca: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 8007bcc: 68bb ldr r3, [r7, #8] 8007bce: 68d9 ldr r1, [r3, #12] 8007bd0: 68bb ldr r3, [r7, #8] 8007bd2: 781a ldrb r2, [r3, #0] 8007bd4: 68bb ldr r3, [r7, #8] 8007bd6: 691b ldr r3, [r3, #16] 8007bd8: b298 uxth r0, r3 8007bda: 79fb ldrb r3, [r7, #7] 8007bdc: 9300 str r3, [sp, #0] 8007bde: 4603 mov r3, r0 8007be0: 68f8 ldr r0, [r7, #12] 8007be2: f000 f9b9 bl 8007f58 8007be6: e105 b.n 8007df4 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8007be8: 69bb ldr r3, [r7, #24] 8007bea: 015a lsls r2, r3, #5 8007bec: 69fb ldr r3, [r7, #28] 8007bee: 4413 add r3, r2 8007bf0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007bf4: 691b ldr r3, [r3, #16] 8007bf6: 69ba ldr r2, [r7, #24] 8007bf8: 0151 lsls r1, r2, #5 8007bfa: 69fa ldr r2, [r7, #28] 8007bfc: 440a add r2, r1 8007bfe: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007c02: 0cdb lsrs r3, r3, #19 8007c04: 04db lsls r3, r3, #19 8007c06: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8007c08: 69bb ldr r3, [r7, #24] 8007c0a: 015a lsls r2, r3, #5 8007c0c: 69fb ldr r3, [r7, #28] 8007c0e: 4413 add r3, r2 8007c10: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c14: 691b ldr r3, [r3, #16] 8007c16: 69ba ldr r2, [r7, #24] 8007c18: 0151 lsls r1, r2, #5 8007c1a: 69fa ldr r2, [r7, #28] 8007c1c: 440a add r2, r1 8007c1e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007c22: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007c26: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007c2a: 6113 str r3, [r2, #16] if (epnum == 0U) 8007c2c: 69bb ldr r3, [r7, #24] 8007c2e: 2b00 cmp r3, #0 8007c30: d132 bne.n 8007c98 { if (ep->xfer_len > 0U) 8007c32: 68bb ldr r3, [r7, #8] 8007c34: 691b ldr r3, [r3, #16] 8007c36: 2b00 cmp r3, #0 8007c38: d003 beq.n 8007c42 { ep->xfer_len = ep->maxpacket; 8007c3a: 68bb ldr r3, [r7, #8] 8007c3c: 689a ldr r2, [r3, #8] 8007c3e: 68bb ldr r3, [r7, #8] 8007c40: 611a str r2, [r3, #16] } /* Store transfer size, for EP0 this is equal to endpoint max packet size */ ep->xfer_size = ep->maxpacket; 8007c42: 68bb ldr r3, [r7, #8] 8007c44: 689a ldr r2, [r3, #8] 8007c46: 68bb ldr r3, [r7, #8] 8007c48: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); 8007c4a: 69bb ldr r3, [r7, #24] 8007c4c: 015a lsls r2, r3, #5 8007c4e: 69fb ldr r3, [r7, #28] 8007c50: 4413 add r3, r2 8007c52: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c56: 691a ldr r2, [r3, #16] 8007c58: 68bb ldr r3, [r7, #8] 8007c5a: 6a1b ldr r3, [r3, #32] 8007c5c: f3c3 0312 ubfx r3, r3, #0, #19 8007c60: 69b9 ldr r1, [r7, #24] 8007c62: 0148 lsls r0, r1, #5 8007c64: 69f9 ldr r1, [r7, #28] 8007c66: 4401 add r1, r0 8007c68: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007c6c: 4313 orrs r3, r2 8007c6e: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007c70: 69bb ldr r3, [r7, #24] 8007c72: 015a lsls r2, r3, #5 8007c74: 69fb ldr r3, [r7, #28] 8007c76: 4413 add r3, r2 8007c78: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c7c: 691b ldr r3, [r3, #16] 8007c7e: 69ba ldr r2, [r7, #24] 8007c80: 0151 lsls r1, r2, #5 8007c82: 69fa ldr r2, [r7, #28] 8007c84: 440a add r2, r1 8007c86: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007c8a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007c8e: 6113 str r3, [r2, #16] 8007c90: e062 b.n 8007d58 8007c92: bf00 nop 8007c94: 1ff80000 .word 0x1ff80000 } else { if (ep->xfer_len == 0U) 8007c98: 68bb ldr r3, [r7, #8] 8007c9a: 691b ldr r3, [r3, #16] 8007c9c: 2b00 cmp r3, #0 8007c9e: d123 bne.n 8007ce8 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8007ca0: 69bb ldr r3, [r7, #24] 8007ca2: 015a lsls r2, r3, #5 8007ca4: 69fb ldr r3, [r7, #28] 8007ca6: 4413 add r3, r2 8007ca8: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007cac: 691a ldr r2, [r3, #16] 8007cae: 68bb ldr r3, [r7, #8] 8007cb0: 689b ldr r3, [r3, #8] 8007cb2: f3c3 0312 ubfx r3, r3, #0, #19 8007cb6: 69b9 ldr r1, [r7, #24] 8007cb8: 0148 lsls r0, r1, #5 8007cba: 69f9 ldr r1, [r7, #28] 8007cbc: 4401 add r1, r0 8007cbe: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007cc2: 4313 orrs r3, r2 8007cc4: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007cc6: 69bb ldr r3, [r7, #24] 8007cc8: 015a lsls r2, r3, #5 8007cca: 69fb ldr r3, [r7, #28] 8007ccc: 4413 add r3, r2 8007cce: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007cd2: 691b ldr r3, [r3, #16] 8007cd4: 69ba ldr r2, [r7, #24] 8007cd6: 0151 lsls r1, r2, #5 8007cd8: 69fa ldr r2, [r7, #28] 8007cda: 440a add r2, r1 8007cdc: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007ce0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007ce4: 6113 str r3, [r2, #16] 8007ce6: e037 b.n 8007d58 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8007ce8: 68bb ldr r3, [r7, #8] 8007cea: 691a ldr r2, [r3, #16] 8007cec: 68bb ldr r3, [r7, #8] 8007cee: 689b ldr r3, [r3, #8] 8007cf0: 4413 add r3, r2 8007cf2: 1e5a subs r2, r3, #1 8007cf4: 68bb ldr r3, [r7, #8] 8007cf6: 689b ldr r3, [r3, #8] 8007cf8: fbb2 f3f3 udiv r3, r2, r3 8007cfc: 82fb strh r3, [r7, #22] ep->xfer_size = ep->maxpacket * pktcnt; 8007cfe: 68bb ldr r3, [r7, #8] 8007d00: 689b ldr r3, [r3, #8] 8007d02: 8afa ldrh r2, [r7, #22] 8007d04: fb03 f202 mul.w r2, r3, r2 8007d08: 68bb ldr r3, [r7, #8] 8007d0a: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8007d0c: 69bb ldr r3, [r7, #24] 8007d0e: 015a lsls r2, r3, #5 8007d10: 69fb ldr r3, [r7, #28] 8007d12: 4413 add r3, r2 8007d14: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d18: 691a ldr r2, [r3, #16] 8007d1a: 8afb ldrh r3, [r7, #22] 8007d1c: 04d9 lsls r1, r3, #19 8007d1e: 4b38 ldr r3, [pc, #224] @ (8007e00 ) 8007d20: 400b ands r3, r1 8007d22: 69b9 ldr r1, [r7, #24] 8007d24: 0148 lsls r0, r1, #5 8007d26: 69f9 ldr r1, [r7, #28] 8007d28: 4401 add r1, r0 8007d2a: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007d2e: 4313 orrs r3, r2 8007d30: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; 8007d32: 69bb ldr r3, [r7, #24] 8007d34: 015a lsls r2, r3, #5 8007d36: 69fb ldr r3, [r7, #28] 8007d38: 4413 add r3, r2 8007d3a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d3e: 691a ldr r2, [r3, #16] 8007d40: 68bb ldr r3, [r7, #8] 8007d42: 6a1b ldr r3, [r3, #32] 8007d44: f3c3 0312 ubfx r3, r3, #0, #19 8007d48: 69b9 ldr r1, [r7, #24] 8007d4a: 0148 lsls r0, r1, #5 8007d4c: 69f9 ldr r1, [r7, #28] 8007d4e: 4401 add r1, r0 8007d50: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007d54: 4313 orrs r3, r2 8007d56: 610b str r3, [r1, #16] } } if (dma == 1U) 8007d58: 79fb ldrb r3, [r7, #7] 8007d5a: 2b01 cmp r3, #1 8007d5c: d10d bne.n 8007d7a { if ((uint32_t)ep->xfer_buff != 0U) 8007d5e: 68bb ldr r3, [r7, #8] 8007d60: 68db ldr r3, [r3, #12] 8007d62: 2b00 cmp r3, #0 8007d64: d009 beq.n 8007d7a { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8007d66: 68bb ldr r3, [r7, #8] 8007d68: 68d9 ldr r1, [r3, #12] 8007d6a: 69bb ldr r3, [r7, #24] 8007d6c: 015a lsls r2, r3, #5 8007d6e: 69fb ldr r3, [r7, #28] 8007d70: 4413 add r3, r2 8007d72: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d76: 460a mov r2, r1 8007d78: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8007d7a: 68bb ldr r3, [r7, #8] 8007d7c: 791b ldrb r3, [r3, #4] 8007d7e: 2b01 cmp r3, #1 8007d80: d128 bne.n 8007dd4 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007d82: 69fb ldr r3, [r7, #28] 8007d84: f503 6300 add.w r3, r3, #2048 @ 0x800 8007d88: 689b ldr r3, [r3, #8] 8007d8a: f403 7380 and.w r3, r3, #256 @ 0x100 8007d8e: 2b00 cmp r3, #0 8007d90: d110 bne.n 8007db4 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 8007d92: 69bb ldr r3, [r7, #24] 8007d94: 015a lsls r2, r3, #5 8007d96: 69fb ldr r3, [r7, #28] 8007d98: 4413 add r3, r2 8007d9a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d9e: 681b ldr r3, [r3, #0] 8007da0: 69ba ldr r2, [r7, #24] 8007da2: 0151 lsls r1, r2, #5 8007da4: 69fa ldr r2, [r7, #28] 8007da6: 440a add r2, r1 8007da8: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007dac: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007db0: 6013 str r3, [r2, #0] 8007db2: e00f b.n 8007dd4 } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8007db4: 69bb ldr r3, [r7, #24] 8007db6: 015a lsls r2, r3, #5 8007db8: 69fb ldr r3, [r7, #28] 8007dba: 4413 add r3, r2 8007dbc: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007dc0: 681b ldr r3, [r3, #0] 8007dc2: 69ba ldr r2, [r7, #24] 8007dc4: 0151 lsls r1, r2, #5 8007dc6: 69fa ldr r2, [r7, #28] 8007dc8: 440a add r2, r1 8007dca: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007dce: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007dd2: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8007dd4: 69bb ldr r3, [r7, #24] 8007dd6: 015a lsls r2, r3, #5 8007dd8: 69fb ldr r3, [r7, #28] 8007dda: 4413 add r3, r2 8007ddc: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007de0: 681b ldr r3, [r3, #0] 8007de2: 69ba ldr r2, [r7, #24] 8007de4: 0151 lsls r1, r2, #5 8007de6: 69fa ldr r2, [r7, #28] 8007de8: 440a add r2, r1 8007dea: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007dee: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007df2: 6013 str r3, [r2, #0] } return HAL_OK; 8007df4: 2300 movs r3, #0 } 8007df6: 4618 mov r0, r3 8007df8: 3720 adds r7, #32 8007dfa: 46bd mov sp, r7 8007dfc: bd80 pop {r7, pc} 8007dfe: bf00 nop 8007e00: 1ff80000 .word 0x1ff80000 08007e04 : * @param USBx usb device instance * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8007e04: b480 push {r7} 8007e06: b087 sub sp, #28 8007e08: af00 add r7, sp, #0 8007e0a: 6078 str r0, [r7, #4] 8007e0c: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8007e0e: 2300 movs r3, #0 8007e10: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; 8007e12: 2300 movs r3, #0 8007e14: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007e16: 687b ldr r3, [r7, #4] 8007e18: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8007e1a: 683b ldr r3, [r7, #0] 8007e1c: 785b ldrb r3, [r3, #1] 8007e1e: 2b01 cmp r3, #1 8007e20: d14a bne.n 8007eb8 { /* EP enable, IN data in FIFO */ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007e22: 683b ldr r3, [r7, #0] 8007e24: 781b ldrb r3, [r3, #0] 8007e26: 015a lsls r2, r3, #5 8007e28: 693b ldr r3, [r7, #16] 8007e2a: 4413 add r3, r2 8007e2c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007e30: 681b ldr r3, [r3, #0] 8007e32: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007e36: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007e3a: f040 8086 bne.w 8007f4a { USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); 8007e3e: 683b ldr r3, [r7, #0] 8007e40: 781b ldrb r3, [r3, #0] 8007e42: 015a lsls r2, r3, #5 8007e44: 693b ldr r3, [r7, #16] 8007e46: 4413 add r3, r2 8007e48: f503 6310 add.w r3, r3, #2304 @ 0x900 8007e4c: 681b ldr r3, [r3, #0] 8007e4e: 683a ldr r2, [r7, #0] 8007e50: 7812 ldrb r2, [r2, #0] 8007e52: 0151 lsls r1, r2, #5 8007e54: 693a ldr r2, [r7, #16] 8007e56: 440a add r2, r1 8007e58: f502 6210 add.w r2, r2, #2304 @ 0x900 8007e5c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007e60: 6013 str r3, [r2, #0] USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); 8007e62: 683b ldr r3, [r7, #0] 8007e64: 781b ldrb r3, [r3, #0] 8007e66: 015a lsls r2, r3, #5 8007e68: 693b ldr r3, [r7, #16] 8007e6a: 4413 add r3, r2 8007e6c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007e70: 681b ldr r3, [r3, #0] 8007e72: 683a ldr r2, [r7, #0] 8007e74: 7812 ldrb r2, [r2, #0] 8007e76: 0151 lsls r1, r2, #5 8007e78: 693a ldr r2, [r7, #16] 8007e7a: 440a add r2, r1 8007e7c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007e80: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007e84: 6013 str r3, [r2, #0] do { count++; 8007e86: 68fb ldr r3, [r7, #12] 8007e88: 3301 adds r3, #1 8007e8a: 60fb str r3, [r7, #12] if (count > 10000U) 8007e8c: 68fb ldr r3, [r7, #12] 8007e8e: f242 7210 movw r2, #10000 @ 0x2710 8007e92: 4293 cmp r3, r2 8007e94: d902 bls.n 8007e9c { ret = HAL_ERROR; 8007e96: 2301 movs r3, #1 8007e98: 75fb strb r3, [r7, #23] break; 8007e9a: e056 b.n 8007f4a } } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); 8007e9c: 683b ldr r3, [r7, #0] 8007e9e: 781b ldrb r3, [r3, #0] 8007ea0: 015a lsls r2, r3, #5 8007ea2: 693b ldr r3, [r7, #16] 8007ea4: 4413 add r3, r2 8007ea6: f503 6310 add.w r3, r3, #2304 @ 0x900 8007eaa: 681b ldr r3, [r3, #0] 8007eac: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007eb0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007eb4: d0e7 beq.n 8007e86 8007eb6: e048 b.n 8007f4a } } else /* OUT endpoint */ { if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007eb8: 683b ldr r3, [r7, #0] 8007eba: 781b ldrb r3, [r3, #0] 8007ebc: 015a lsls r2, r3, #5 8007ebe: 693b ldr r3, [r7, #16] 8007ec0: 4413 add r3, r2 8007ec2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ec6: 681b ldr r3, [r3, #0] 8007ec8: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007ecc: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007ed0: d13b bne.n 8007f4a { USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); 8007ed2: 683b ldr r3, [r7, #0] 8007ed4: 781b ldrb r3, [r3, #0] 8007ed6: 015a lsls r2, r3, #5 8007ed8: 693b ldr r3, [r7, #16] 8007eda: 4413 add r3, r2 8007edc: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ee0: 681b ldr r3, [r3, #0] 8007ee2: 683a ldr r2, [r7, #0] 8007ee4: 7812 ldrb r2, [r2, #0] 8007ee6: 0151 lsls r1, r2, #5 8007ee8: 693a ldr r2, [r7, #16] 8007eea: 440a add r2, r1 8007eec: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007ef0: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007ef4: 6013 str r3, [r2, #0] USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); 8007ef6: 683b ldr r3, [r7, #0] 8007ef8: 781b ldrb r3, [r3, #0] 8007efa: 015a lsls r2, r3, #5 8007efc: 693b ldr r3, [r7, #16] 8007efe: 4413 add r3, r2 8007f00: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f04: 681b ldr r3, [r3, #0] 8007f06: 683a ldr r2, [r7, #0] 8007f08: 7812 ldrb r2, [r2, #0] 8007f0a: 0151 lsls r1, r2, #5 8007f0c: 693a ldr r2, [r7, #16] 8007f0e: 440a add r2, r1 8007f10: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f14: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007f18: 6013 str r3, [r2, #0] do { count++; 8007f1a: 68fb ldr r3, [r7, #12] 8007f1c: 3301 adds r3, #1 8007f1e: 60fb str r3, [r7, #12] if (count > 10000U) 8007f20: 68fb ldr r3, [r7, #12] 8007f22: f242 7210 movw r2, #10000 @ 0x2710 8007f26: 4293 cmp r3, r2 8007f28: d902 bls.n 8007f30 { ret = HAL_ERROR; 8007f2a: 2301 movs r3, #1 8007f2c: 75fb strb r3, [r7, #23] break; 8007f2e: e00c b.n 8007f4a } } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); 8007f30: 683b ldr r3, [r7, #0] 8007f32: 781b ldrb r3, [r3, #0] 8007f34: 015a lsls r2, r3, #5 8007f36: 693b ldr r3, [r7, #16] 8007f38: 4413 add r3, r2 8007f3a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f3e: 681b ldr r3, [r3, #0] 8007f40: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007f44: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007f48: d0e7 beq.n 8007f1a } } return ret; 8007f4a: 7dfb ldrb r3, [r7, #23] } 8007f4c: 4618 mov r0, r3 8007f4e: 371c adds r7, #28 8007f50: 46bd mov sp, r7 8007f52: f85d 7b04 ldr.w r7, [sp], #4 8007f56: 4770 bx lr 08007f58 : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 8007f58: b480 push {r7} 8007f5a: b089 sub sp, #36 @ 0x24 8007f5c: af00 add r7, sp, #0 8007f5e: 60f8 str r0, [r7, #12] 8007f60: 60b9 str r1, [r7, #8] 8007f62: 4611 mov r1, r2 8007f64: 461a mov r2, r3 8007f66: 460b mov r3, r1 8007f68: 71fb strb r3, [r7, #7] 8007f6a: 4613 mov r3, r2 8007f6c: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007f6e: 68fb ldr r3, [r7, #12] 8007f70: 617b str r3, [r7, #20] uint8_t *pSrc = src; 8007f72: 68bb ldr r3, [r7, #8] 8007f74: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 8007f76: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8007f7a: 2b00 cmp r3, #0 8007f7c: d123 bne.n 8007fc6 { count32b = ((uint32_t)len + 3U) / 4U; 8007f7e: 88bb ldrh r3, [r7, #4] 8007f80: 3303 adds r3, #3 8007f82: 089b lsrs r3, r3, #2 8007f84: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 8007f86: 2300 movs r3, #0 8007f88: 61bb str r3, [r7, #24] 8007f8a: e018 b.n 8007fbe { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 8007f8c: 79fb ldrb r3, [r7, #7] 8007f8e: 031a lsls r2, r3, #12 8007f90: 697b ldr r3, [r7, #20] 8007f92: 4413 add r3, r2 8007f94: f503 5380 add.w r3, r3, #4096 @ 0x1000 8007f98: 461a mov r2, r3 8007f9a: 69fb ldr r3, [r7, #28] 8007f9c: 681b ldr r3, [r3, #0] 8007f9e: 6013 str r3, [r2, #0] pSrc++; 8007fa0: 69fb ldr r3, [r7, #28] 8007fa2: 3301 adds r3, #1 8007fa4: 61fb str r3, [r7, #28] pSrc++; 8007fa6: 69fb ldr r3, [r7, #28] 8007fa8: 3301 adds r3, #1 8007faa: 61fb str r3, [r7, #28] pSrc++; 8007fac: 69fb ldr r3, [r7, #28] 8007fae: 3301 adds r3, #1 8007fb0: 61fb str r3, [r7, #28] pSrc++; 8007fb2: 69fb ldr r3, [r7, #28] 8007fb4: 3301 adds r3, #1 8007fb6: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8007fb8: 69bb ldr r3, [r7, #24] 8007fba: 3301 adds r3, #1 8007fbc: 61bb str r3, [r7, #24] 8007fbe: 69ba ldr r2, [r7, #24] 8007fc0: 693b ldr r3, [r7, #16] 8007fc2: 429a cmp r2, r3 8007fc4: d3e2 bcc.n 8007f8c } } return HAL_OK; 8007fc6: 2300 movs r3, #0 } 8007fc8: 4618 mov r0, r3 8007fca: 3724 adds r7, #36 @ 0x24 8007fcc: 46bd mov sp, r7 8007fce: f85d 7b04 ldr.w r7, [sp], #4 8007fd2: 4770 bx lr 08007fd4 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8007fd4: b480 push {r7} 8007fd6: b08b sub sp, #44 @ 0x2c 8007fd8: af00 add r7, sp, #0 8007fda: 60f8 str r0, [r7, #12] 8007fdc: 60b9 str r1, [r7, #8] 8007fde: 4613 mov r3, r2 8007fe0: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8007fe2: 68fb ldr r3, [r7, #12] 8007fe4: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8007fe6: 68bb ldr r3, [r7, #8] 8007fe8: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8007fea: 88fb ldrh r3, [r7, #6] 8007fec: 089b lsrs r3, r3, #2 8007fee: b29b uxth r3, r3 8007ff0: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8007ff2: 88fb ldrh r3, [r7, #6] 8007ff4: f003 0303 and.w r3, r3, #3 8007ff8: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8007ffa: 2300 movs r3, #0 8007ffc: 623b str r3, [r7, #32] 8007ffe: e014 b.n 800802a { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8008000: 69bb ldr r3, [r7, #24] 8008002: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008006: 681a ldr r2, [r3, #0] 8008008: 6a7b ldr r3, [r7, #36] @ 0x24 800800a: 601a str r2, [r3, #0] pDest++; 800800c: 6a7b ldr r3, [r7, #36] @ 0x24 800800e: 3301 adds r3, #1 8008010: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008012: 6a7b ldr r3, [r7, #36] @ 0x24 8008014: 3301 adds r3, #1 8008016: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008018: 6a7b ldr r3, [r7, #36] @ 0x24 800801a: 3301 adds r3, #1 800801c: 627b str r3, [r7, #36] @ 0x24 pDest++; 800801e: 6a7b ldr r3, [r7, #36] @ 0x24 8008020: 3301 adds r3, #1 8008022: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 8008024: 6a3b ldr r3, [r7, #32] 8008026: 3301 adds r3, #1 8008028: 623b str r3, [r7, #32] 800802a: 6a3a ldr r2, [r7, #32] 800802c: 697b ldr r3, [r7, #20] 800802e: 429a cmp r2, r3 8008030: d3e6 bcc.n 8008000 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8008032: 8bfb ldrh r3, [r7, #30] 8008034: 2b00 cmp r3, #0 8008036: d01e beq.n 8008076 { i = 0U; 8008038: 2300 movs r3, #0 800803a: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 800803c: 69bb ldr r3, [r7, #24] 800803e: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008042: 461a mov r2, r3 8008044: f107 0310 add.w r3, r7, #16 8008048: 6812 ldr r2, [r2, #0] 800804a: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 800804c: 693a ldr r2, [r7, #16] 800804e: 6a3b ldr r3, [r7, #32] 8008050: b2db uxtb r3, r3 8008052: 00db lsls r3, r3, #3 8008054: fa22 f303 lsr.w r3, r2, r3 8008058: b2da uxtb r2, r3 800805a: 6a7b ldr r3, [r7, #36] @ 0x24 800805c: 701a strb r2, [r3, #0] i++; 800805e: 6a3b ldr r3, [r7, #32] 8008060: 3301 adds r3, #1 8008062: 623b str r3, [r7, #32] pDest++; 8008064: 6a7b ldr r3, [r7, #36] @ 0x24 8008066: 3301 adds r3, #1 8008068: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 800806a: 8bfb ldrh r3, [r7, #30] 800806c: 3b01 subs r3, #1 800806e: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 8008070: 8bfb ldrh r3, [r7, #30] 8008072: 2b00 cmp r3, #0 8008074: d1ea bne.n 800804c } return ((void *)pDest); 8008076: 6a7b ldr r3, [r7, #36] @ 0x24 } 8008078: 4618 mov r0, r3 800807a: 372c adds r7, #44 @ 0x2c 800807c: 46bd mov sp, r7 800807e: f85d 7b04 ldr.w r7, [sp], #4 8008082: 4770 bx lr 08008084 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008084: b480 push {r7} 8008086: b085 sub sp, #20 8008088: af00 add r7, sp, #0 800808a: 6078 str r0, [r7, #4] 800808c: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800808e: 687b ldr r3, [r7, #4] 8008090: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008092: 683b ldr r3, [r7, #0] 8008094: 781b ldrb r3, [r3, #0] 8008096: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8008098: 683b ldr r3, [r7, #0] 800809a: 785b ldrb r3, [r3, #1] 800809c: 2b01 cmp r3, #1 800809e: d12c bne.n 80080fa { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 80080a0: 68bb ldr r3, [r7, #8] 80080a2: 015a lsls r2, r3, #5 80080a4: 68fb ldr r3, [r7, #12] 80080a6: 4413 add r3, r2 80080a8: f503 6310 add.w r3, r3, #2304 @ 0x900 80080ac: 681b ldr r3, [r3, #0] 80080ae: 2b00 cmp r3, #0 80080b0: db12 blt.n 80080d8 80080b2: 68bb ldr r3, [r7, #8] 80080b4: 2b00 cmp r3, #0 80080b6: d00f beq.n 80080d8 { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 80080b8: 68bb ldr r3, [r7, #8] 80080ba: 015a lsls r2, r3, #5 80080bc: 68fb ldr r3, [r7, #12] 80080be: 4413 add r3, r2 80080c0: f503 6310 add.w r3, r3, #2304 @ 0x900 80080c4: 681b ldr r3, [r3, #0] 80080c6: 68ba ldr r2, [r7, #8] 80080c8: 0151 lsls r1, r2, #5 80080ca: 68fa ldr r2, [r7, #12] 80080cc: 440a add r2, r1 80080ce: f502 6210 add.w r2, r2, #2304 @ 0x900 80080d2: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 80080d6: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 80080d8: 68bb ldr r3, [r7, #8] 80080da: 015a lsls r2, r3, #5 80080dc: 68fb ldr r3, [r7, #12] 80080de: 4413 add r3, r2 80080e0: f503 6310 add.w r3, r3, #2304 @ 0x900 80080e4: 681b ldr r3, [r3, #0] 80080e6: 68ba ldr r2, [r7, #8] 80080e8: 0151 lsls r1, r2, #5 80080ea: 68fa ldr r2, [r7, #12] 80080ec: 440a add r2, r1 80080ee: f502 6210 add.w r2, r2, #2304 @ 0x900 80080f2: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 80080f6: 6013 str r3, [r2, #0] 80080f8: e02b b.n 8008152 } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 80080fa: 68bb ldr r3, [r7, #8] 80080fc: 015a lsls r2, r3, #5 80080fe: 68fb ldr r3, [r7, #12] 8008100: 4413 add r3, r2 8008102: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008106: 681b ldr r3, [r3, #0] 8008108: 2b00 cmp r3, #0 800810a: db12 blt.n 8008132 800810c: 68bb ldr r3, [r7, #8] 800810e: 2b00 cmp r3, #0 8008110: d00f beq.n 8008132 { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 8008112: 68bb ldr r3, [r7, #8] 8008114: 015a lsls r2, r3, #5 8008116: 68fb ldr r3, [r7, #12] 8008118: 4413 add r3, r2 800811a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800811e: 681b ldr r3, [r3, #0] 8008120: 68ba ldr r2, [r7, #8] 8008122: 0151 lsls r1, r2, #5 8008124: 68fa ldr r2, [r7, #12] 8008126: 440a add r2, r1 8008128: f502 6230 add.w r2, r2, #2816 @ 0xb00 800812c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008130: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 8008132: 68bb ldr r3, [r7, #8] 8008134: 015a lsls r2, r3, #5 8008136: 68fb ldr r3, [r7, #12] 8008138: 4413 add r3, r2 800813a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800813e: 681b ldr r3, [r3, #0] 8008140: 68ba ldr r2, [r7, #8] 8008142: 0151 lsls r1, r2, #5 8008144: 68fa ldr r2, [r7, #12] 8008146: 440a add r2, r1 8008148: f502 6230 add.w r2, r2, #2816 @ 0xb00 800814c: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008150: 6013 str r3, [r2, #0] } return HAL_OK; 8008152: 2300 movs r3, #0 } 8008154: 4618 mov r0, r3 8008156: 3714 adds r7, #20 8008158: 46bd mov sp, r7 800815a: f85d 7b04 ldr.w r7, [sp], #4 800815e: 4770 bx lr 08008160 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008160: b480 push {r7} 8008162: b085 sub sp, #20 8008164: af00 add r7, sp, #0 8008166: 6078 str r0, [r7, #4] 8008168: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800816a: 687b ldr r3, [r7, #4] 800816c: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 800816e: 683b ldr r3, [r7, #0] 8008170: 781b ldrb r3, [r3, #0] 8008172: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8008174: 683b ldr r3, [r7, #0] 8008176: 785b ldrb r3, [r3, #1] 8008178: 2b01 cmp r3, #1 800817a: d128 bne.n 80081ce { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 800817c: 68bb ldr r3, [r7, #8] 800817e: 015a lsls r2, r3, #5 8008180: 68fb ldr r3, [r7, #12] 8008182: 4413 add r3, r2 8008184: f503 6310 add.w r3, r3, #2304 @ 0x900 8008188: 681b ldr r3, [r3, #0] 800818a: 68ba ldr r2, [r7, #8] 800818c: 0151 lsls r1, r2, #5 800818e: 68fa ldr r2, [r7, #12] 8008190: 440a add r2, r1 8008192: f502 6210 add.w r2, r2, #2304 @ 0x900 8008196: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800819a: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 800819c: 683b ldr r3, [r7, #0] 800819e: 791b ldrb r3, [r3, #4] 80081a0: 2b03 cmp r3, #3 80081a2: d003 beq.n 80081ac 80081a4: 683b ldr r3, [r7, #0] 80081a6: 791b ldrb r3, [r3, #4] 80081a8: 2b02 cmp r3, #2 80081aa: d138 bne.n 800821e { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 80081ac: 68bb ldr r3, [r7, #8] 80081ae: 015a lsls r2, r3, #5 80081b0: 68fb ldr r3, [r7, #12] 80081b2: 4413 add r3, r2 80081b4: f503 6310 add.w r3, r3, #2304 @ 0x900 80081b8: 681b ldr r3, [r3, #0] 80081ba: 68ba ldr r2, [r7, #8] 80081bc: 0151 lsls r1, r2, #5 80081be: 68fa ldr r2, [r7, #12] 80081c0: 440a add r2, r1 80081c2: f502 6210 add.w r2, r2, #2304 @ 0x900 80081c6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80081ca: 6013 str r3, [r2, #0] 80081cc: e027 b.n 800821e } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 80081ce: 68bb ldr r3, [r7, #8] 80081d0: 015a lsls r2, r3, #5 80081d2: 68fb ldr r3, [r7, #12] 80081d4: 4413 add r3, r2 80081d6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80081da: 681b ldr r3, [r3, #0] 80081dc: 68ba ldr r2, [r7, #8] 80081de: 0151 lsls r1, r2, #5 80081e0: 68fa ldr r2, [r7, #12] 80081e2: 440a add r2, r1 80081e4: f502 6230 add.w r2, r2, #2816 @ 0xb00 80081e8: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80081ec: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 80081ee: 683b ldr r3, [r7, #0] 80081f0: 791b ldrb r3, [r3, #4] 80081f2: 2b03 cmp r3, #3 80081f4: d003 beq.n 80081fe 80081f6: 683b ldr r3, [r7, #0] 80081f8: 791b ldrb r3, [r3, #4] 80081fa: 2b02 cmp r3, #2 80081fc: d10f bne.n 800821e { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 80081fe: 68bb ldr r3, [r7, #8] 8008200: 015a lsls r2, r3, #5 8008202: 68fb ldr r3, [r7, #12] 8008204: 4413 add r3, r2 8008206: f503 6330 add.w r3, r3, #2816 @ 0xb00 800820a: 681b ldr r3, [r3, #0] 800820c: 68ba ldr r2, [r7, #8] 800820e: 0151 lsls r1, r2, #5 8008210: 68fa ldr r2, [r7, #12] 8008212: 440a add r2, r1 8008214: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008218: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800821c: 6013 str r3, [r2, #0] } } return HAL_OK; 800821e: 2300 movs r3, #0 } 8008220: 4618 mov r0, r3 8008222: 3714 adds r7, #20 8008224: 46bd mov sp, r7 8008226: f85d 7b04 ldr.w r7, [sp], #4 800822a: 4770 bx lr 0800822c : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 800822c: b480 push {r7} 800822e: b085 sub sp, #20 8008230: af00 add r7, sp, #0 8008232: 6078 str r0, [r7, #4] 8008234: 460b mov r3, r1 8008236: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008238: 687b ldr r3, [r7, #4] 800823a: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 800823c: 68fb ldr r3, [r7, #12] 800823e: f503 6300 add.w r3, r3, #2048 @ 0x800 8008242: 681b ldr r3, [r3, #0] 8008244: 68fa ldr r2, [r7, #12] 8008246: f502 6200 add.w r2, r2, #2048 @ 0x800 800824a: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 800824e: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 8008250: 68fb ldr r3, [r7, #12] 8008252: f503 6300 add.w r3, r3, #2048 @ 0x800 8008256: 681a ldr r2, [r3, #0] 8008258: 78fb ldrb r3, [r7, #3] 800825a: 011b lsls r3, r3, #4 800825c: f403 63fe and.w r3, r3, #2032 @ 0x7f0 8008260: 68f9 ldr r1, [r7, #12] 8008262: f501 6100 add.w r1, r1, #2048 @ 0x800 8008266: 4313 orrs r3, r2 8008268: 600b str r3, [r1, #0] return HAL_OK; 800826a: 2300 movs r3, #0 } 800826c: 4618 mov r0, r3 800826e: 3714 adds r7, #20 8008270: 46bd mov sp, r7 8008272: f85d 7b04 ldr.w r7, [sp], #4 8008276: 4770 bx lr 08008278 : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { 8008278: b480 push {r7} 800827a: b085 sub sp, #20 800827c: af00 add r7, sp, #0 800827e: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008280: 687b ldr r3, [r7, #4] 8008282: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8008284: 68fb ldr r3, [r7, #12] 8008286: f503 6360 add.w r3, r3, #3584 @ 0xe00 800828a: 681b ldr r3, [r3, #0] 800828c: 68fa ldr r2, [r7, #12] 800828e: f502 6260 add.w r2, r2, #3584 @ 0xe00 8008292: f023 0303 bic.w r3, r3, #3 8008296: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 8008298: 68fb ldr r3, [r7, #12] 800829a: f503 6300 add.w r3, r3, #2048 @ 0x800 800829e: 685b ldr r3, [r3, #4] 80082a0: 68fa ldr r2, [r7, #12] 80082a2: f502 6200 add.w r2, r2, #2048 @ 0x800 80082a6: f023 0302 bic.w r3, r3, #2 80082aa: 6053 str r3, [r2, #4] return HAL_OK; 80082ac: 2300 movs r3, #0 } 80082ae: 4618 mov r0, r3 80082b0: 3714 adds r7, #20 80082b2: 46bd mov sp, r7 80082b4: f85d 7b04 ldr.w r7, [sp], #4 80082b8: 4770 bx lr 080082ba : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 80082ba: b480 push {r7} 80082bc: b085 sub sp, #20 80082be: af00 add r7, sp, #0 80082c0: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80082c2: 687b ldr r3, [r7, #4] 80082c4: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 80082c6: 68fb ldr r3, [r7, #12] 80082c8: f503 6360 add.w r3, r3, #3584 @ 0xe00 80082cc: 681b ldr r3, [r3, #0] 80082ce: 68fa ldr r2, [r7, #12] 80082d0: f502 6260 add.w r2, r2, #3584 @ 0xe00 80082d4: f023 0303 bic.w r3, r3, #3 80082d8: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 80082da: 68fb ldr r3, [r7, #12] 80082dc: f503 6300 add.w r3, r3, #2048 @ 0x800 80082e0: 685b ldr r3, [r3, #4] 80082e2: 68fa ldr r2, [r7, #12] 80082e4: f502 6200 add.w r2, r2, #2048 @ 0x800 80082e8: f043 0302 orr.w r3, r3, #2 80082ec: 6053 str r3, [r2, #4] return HAL_OK; 80082ee: 2300 movs r3, #0 } 80082f0: 4618 mov r0, r3 80082f2: 3714 adds r7, #20 80082f4: 46bd mov sp, r7 80082f6: f85d 7b04 ldr.w r7, [sp], #4 80082fa: 4770 bx lr 080082fc : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 80082fc: b480 push {r7} 80082fe: b085 sub sp, #20 8008300: af00 add r7, sp, #0 8008302: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 8008304: 687b ldr r3, [r7, #4] 8008306: 695b ldr r3, [r3, #20] 8008308: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 800830a: 687b ldr r3, [r7, #4] 800830c: 699b ldr r3, [r3, #24] 800830e: 68fa ldr r2, [r7, #12] 8008310: 4013 ands r3, r2 8008312: 60fb str r3, [r7, #12] return tmpreg; 8008314: 68fb ldr r3, [r7, #12] } 8008316: 4618 mov r0, r3 8008318: 3714 adds r7, #20 800831a: 46bd mov sp, r7 800831c: f85d 7b04 ldr.w r7, [sp], #4 8008320: 4770 bx lr 08008322 : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 8008322: b480 push {r7} 8008324: b085 sub sp, #20 8008326: af00 add r7, sp, #0 8008328: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800832a: 687b ldr r3, [r7, #4] 800832c: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 800832e: 68fb ldr r3, [r7, #12] 8008330: f503 6300 add.w r3, r3, #2048 @ 0x800 8008334: 699b ldr r3, [r3, #24] 8008336: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8008338: 68fb ldr r3, [r7, #12] 800833a: f503 6300 add.w r3, r3, #2048 @ 0x800 800833e: 69db ldr r3, [r3, #28] 8008340: 68ba ldr r2, [r7, #8] 8008342: 4013 ands r3, r2 8008344: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 8008346: 68bb ldr r3, [r7, #8] 8008348: 0c1b lsrs r3, r3, #16 } 800834a: 4618 mov r0, r3 800834c: 3714 adds r7, #20 800834e: 46bd mov sp, r7 8008350: f85d 7b04 ldr.w r7, [sp], #4 8008354: 4770 bx lr 08008356 : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 8008356: b480 push {r7} 8008358: b085 sub sp, #20 800835a: af00 add r7, sp, #0 800835c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800835e: 687b ldr r3, [r7, #4] 8008360: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8008362: 68fb ldr r3, [r7, #12] 8008364: f503 6300 add.w r3, r3, #2048 @ 0x800 8008368: 699b ldr r3, [r3, #24] 800836a: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 800836c: 68fb ldr r3, [r7, #12] 800836e: f503 6300 add.w r3, r3, #2048 @ 0x800 8008372: 69db ldr r3, [r3, #28] 8008374: 68ba ldr r2, [r7, #8] 8008376: 4013 ands r3, r2 8008378: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 800837a: 68bb ldr r3, [r7, #8] 800837c: b29b uxth r3, r3 } 800837e: 4618 mov r0, r3 8008380: 3714 adds r7, #20 8008382: 46bd mov sp, r7 8008384: f85d 7b04 ldr.w r7, [sp], #4 8008388: 4770 bx lr 0800838a : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 800838a: b480 push {r7} 800838c: b085 sub sp, #20 800838e: af00 add r7, sp, #0 8008390: 6078 str r0, [r7, #4] 8008392: 460b mov r3, r1 8008394: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008396: 687b ldr r3, [r7, #4] 8008398: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 800839a: 78fb ldrb r3, [r7, #3] 800839c: 015a lsls r2, r3, #5 800839e: 68fb ldr r3, [r7, #12] 80083a0: 4413 add r3, r2 80083a2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80083a6: 689b ldr r3, [r3, #8] 80083a8: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 80083aa: 68fb ldr r3, [r7, #12] 80083ac: f503 6300 add.w r3, r3, #2048 @ 0x800 80083b0: 695b ldr r3, [r3, #20] 80083b2: 68ba ldr r2, [r7, #8] 80083b4: 4013 ands r3, r2 80083b6: 60bb str r3, [r7, #8] return tmpreg; 80083b8: 68bb ldr r3, [r7, #8] } 80083ba: 4618 mov r0, r3 80083bc: 3714 adds r7, #20 80083be: 46bd mov sp, r7 80083c0: f85d 7b04 ldr.w r7, [sp], #4 80083c4: 4770 bx lr 080083c6 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 80083c6: b480 push {r7} 80083c8: b087 sub sp, #28 80083ca: af00 add r7, sp, #0 80083cc: 6078 str r0, [r7, #4] 80083ce: 460b mov r3, r1 80083d0: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80083d2: 687b ldr r3, [r7, #4] 80083d4: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 80083d6: 697b ldr r3, [r7, #20] 80083d8: f503 6300 add.w r3, r3, #2048 @ 0x800 80083dc: 691b ldr r3, [r3, #16] 80083de: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 80083e0: 697b ldr r3, [r7, #20] 80083e2: f503 6300 add.w r3, r3, #2048 @ 0x800 80083e6: 6b5b ldr r3, [r3, #52] @ 0x34 80083e8: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 80083ea: 78fb ldrb r3, [r7, #3] 80083ec: f003 030f and.w r3, r3, #15 80083f0: 68fa ldr r2, [r7, #12] 80083f2: fa22 f303 lsr.w r3, r2, r3 80083f6: 01db lsls r3, r3, #7 80083f8: b2db uxtb r3, r3 80083fa: 693a ldr r2, [r7, #16] 80083fc: 4313 orrs r3, r2 80083fe: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 8008400: 78fb ldrb r3, [r7, #3] 8008402: 015a lsls r2, r3, #5 8008404: 697b ldr r3, [r7, #20] 8008406: 4413 add r3, r2 8008408: f503 6310 add.w r3, r3, #2304 @ 0x900 800840c: 689b ldr r3, [r3, #8] 800840e: 693a ldr r2, [r7, #16] 8008410: 4013 ands r3, r2 8008412: 60bb str r3, [r7, #8] return tmpreg; 8008414: 68bb ldr r3, [r7, #8] } 8008416: 4618 mov r0, r3 8008418: 371c adds r7, #28 800841a: 46bd mov sp, r7 800841c: f85d 7b04 ldr.w r7, [sp], #4 8008420: 4770 bx lr 08008422 : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 8008422: b480 push {r7} 8008424: b083 sub sp, #12 8008426: af00 add r7, sp, #0 8008428: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 800842a: 687b ldr r3, [r7, #4] 800842c: 695b ldr r3, [r3, #20] 800842e: f003 0301 and.w r3, r3, #1 } 8008432: 4618 mov r0, r3 8008434: 370c adds r7, #12 8008436: 46bd mov sp, r7 8008438: f85d 7b04 ldr.w r7, [sp], #4 800843c: 4770 bx lr 0800843e : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { 800843e: b480 push {r7} 8008440: b085 sub sp, #20 8008442: af00 add r7, sp, #0 8008444: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008446: 687b ldr r3, [r7, #4] 8008448: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 800844a: 68fb ldr r3, [r7, #12] 800844c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008450: 681b ldr r3, [r3, #0] 8008452: 68fa ldr r2, [r7, #12] 8008454: f502 6210 add.w r2, r2, #2304 @ 0x900 8008458: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 800845c: f023 0307 bic.w r3, r3, #7 8008460: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 8008462: 68fb ldr r3, [r7, #12] 8008464: f503 6300 add.w r3, r3, #2048 @ 0x800 8008468: 685b ldr r3, [r3, #4] 800846a: 68fa ldr r2, [r7, #12] 800846c: f502 6200 add.w r2, r2, #2048 @ 0x800 8008470: f443 7380 orr.w r3, r3, #256 @ 0x100 8008474: 6053 str r3, [r2, #4] return HAL_OK; 8008476: 2300 movs r3, #0 } 8008478: 4618 mov r0, r3 800847a: 3714 adds r7, #20 800847c: 46bd mov sp, r7 800847e: f85d 7b04 ldr.w r7, [sp], #4 8008482: 4770 bx lr 08008484 : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { 8008484: b480 push {r7} 8008486: b087 sub sp, #28 8008488: af00 add r7, sp, #0 800848a: 60f8 str r0, [r7, #12] 800848c: 460b mov r3, r1 800848e: 607a str r2, [r7, #4] 8008490: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 8008492: 68fb ldr r3, [r7, #12] 8008494: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8008496: 68fb ldr r3, [r7, #12] 8008498: 333c adds r3, #60 @ 0x3c 800849a: 3304 adds r3, #4 800849c: 681b ldr r3, [r3, #0] 800849e: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 80084a0: 693b ldr r3, [r7, #16] 80084a2: 4a26 ldr r2, [pc, #152] @ (800853c ) 80084a4: 4293 cmp r3, r2 80084a6: d90a bls.n 80084be { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80084a8: 697b ldr r3, [r7, #20] 80084aa: f503 6330 add.w r3, r3, #2816 @ 0xb00 80084ae: 681b ldr r3, [r3, #0] 80084b0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80084b4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80084b8: d101 bne.n 80084be { return HAL_OK; 80084ba: 2300 movs r3, #0 80084bc: e037 b.n 800852e } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 80084be: 697b ldr r3, [r7, #20] 80084c0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80084c4: 461a mov r2, r3 80084c6: 2300 movs r3, #0 80084c8: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 80084ca: 697b ldr r3, [r7, #20] 80084cc: f503 6330 add.w r3, r3, #2816 @ 0xb00 80084d0: 691b ldr r3, [r3, #16] 80084d2: 697a ldr r2, [r7, #20] 80084d4: f502 6230 add.w r2, r2, #2816 @ 0xb00 80084d8: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80084dc: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 80084de: 697b ldr r3, [r7, #20] 80084e0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80084e4: 691b ldr r3, [r3, #16] 80084e6: 697a ldr r2, [r7, #20] 80084e8: f502 6230 add.w r2, r2, #2816 @ 0xb00 80084ec: f043 0318 orr.w r3, r3, #24 80084f0: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 80084f2: 697b ldr r3, [r7, #20] 80084f4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80084f8: 691b ldr r3, [r3, #16] 80084fa: 697a ldr r2, [r7, #20] 80084fc: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008500: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 8008504: 6113 str r3, [r2, #16] if (dma == 1U) 8008506: 7afb ldrb r3, [r7, #11] 8008508: 2b01 cmp r3, #1 800850a: d10f bne.n 800852c { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 800850c: 697b ldr r3, [r7, #20] 800850e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008512: 461a mov r2, r3 8008514: 687b ldr r3, [r7, #4] 8008516: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 8008518: 697b ldr r3, [r7, #20] 800851a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800851e: 681b ldr r3, [r3, #0] 8008520: 697a ldr r2, [r7, #20] 8008522: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008526: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 800852a: 6013 str r3, [r2, #0] } return HAL_OK; 800852c: 2300 movs r3, #0 } 800852e: 4618 mov r0, r3 8008530: 371c adds r7, #28 8008532: 46bd mov sp, r7 8008534: f85d 7b04 ldr.w r7, [sp], #4 8008538: 4770 bx lr 800853a: bf00 nop 800853c: 4f54300a .word 0x4f54300a 08008540 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 8008540: b480 push {r7} 8008542: b085 sub sp, #20 8008544: af00 add r7, sp, #0 8008546: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8008548: 2300 movs r3, #0 800854a: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 800854c: 68fb ldr r3, [r7, #12] 800854e: 3301 adds r3, #1 8008550: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8008552: 68fb ldr r3, [r7, #12] 8008554: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8008558: d901 bls.n 800855e { return HAL_TIMEOUT; 800855a: 2303 movs r3, #3 800855c: e022 b.n 80085a4 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 800855e: 687b ldr r3, [r7, #4] 8008560: 691b ldr r3, [r3, #16] 8008562: 2b00 cmp r3, #0 8008564: daf2 bge.n 800854c count = 10U; 8008566: 230a movs r3, #10 8008568: 60fb str r3, [r7, #12] /* few cycles before setting core reset */ while (count > 0U) 800856a: e002 b.n 8008572 { count--; 800856c: 68fb ldr r3, [r7, #12] 800856e: 3b01 subs r3, #1 8008570: 60fb str r3, [r7, #12] while (count > 0U) 8008572: 68fb ldr r3, [r7, #12] 8008574: 2b00 cmp r3, #0 8008576: d1f9 bne.n 800856c } /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 8008578: 687b ldr r3, [r7, #4] 800857a: 691b ldr r3, [r3, #16] 800857c: f043 0201 orr.w r2, r3, #1 8008580: 687b ldr r3, [r7, #4] 8008582: 611a str r2, [r3, #16] do { count++; 8008584: 68fb ldr r3, [r7, #12] 8008586: 3301 adds r3, #1 8008588: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800858a: 68fb ldr r3, [r7, #12] 800858c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8008590: d901 bls.n 8008596 { return HAL_TIMEOUT; 8008592: 2303 movs r3, #3 8008594: e006 b.n 80085a4 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 8008596: 687b ldr r3, [r7, #4] 8008598: 691b ldr r3, [r3, #16] 800859a: f003 0301 and.w r3, r3, #1 800859e: 2b01 cmp r3, #1 80085a0: d0f0 beq.n 8008584 return HAL_OK; 80085a2: 2300 movs r3, #0 } 80085a4: 4618 mov r0, r3 80085a6: 3714 adds r7, #20 80085a8: 46bd mov sp, r7 80085aa: f85d 7b04 ldr.w r7, [sp], #4 80085ae: 4770 bx lr 080085b0 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80085b0: b580 push {r7, lr} 80085b2: b084 sub sp, #16 80085b4: af00 add r7, sp, #0 80085b6: 6078 str r0, [r7, #4] 80085b8: 460b mov r3, r1 80085ba: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_HID_HandleTypeDef *hhid; hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); 80085bc: 2010 movs r0, #16 80085be: f002 f9e3 bl 800a988 80085c2: 60f8 str r0, [r7, #12] if (hhid == NULL) 80085c4: 68fb ldr r3, [r7, #12] 80085c6: 2b00 cmp r3, #0 80085c8: d109 bne.n 80085de { pdev->pClassDataCmsit[pdev->classId] = NULL; 80085ca: 687b ldr r3, [r7, #4] 80085cc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80085d0: 687b ldr r3, [r7, #4] 80085d2: 32b0 adds r2, #176 @ 0xb0 80085d4: 2100 movs r1, #0 80085d6: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 80085da: 2302 movs r3, #2 80085dc: e048 b.n 8008670 } pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; 80085de: 687b ldr r3, [r7, #4] 80085e0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80085e4: 687b ldr r3, [r7, #4] 80085e6: 32b0 adds r2, #176 @ 0xb0 80085e8: 68f9 ldr r1, [r7, #12] 80085ea: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 80085ee: 687b ldr r3, [r7, #4] 80085f0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80085f4: 687b ldr r3, [r7, #4] 80085f6: 32b0 adds r2, #176 @ 0xb0 80085f8: f853 2022 ldr.w r2, [r3, r2, lsl #2] 80085fc: 687b ldr r3, [r7, #4] 80085fe: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 8008602: 687b ldr r3, [r7, #4] 8008604: 7c1b ldrb r3, [r3, #16] 8008606: 2b00 cmp r3, #0 8008608: d10d bne.n 8008626 { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; 800860a: 4b1b ldr r3, [pc, #108] @ (8008678 ) 800860c: 781b ldrb r3, [r3, #0] 800860e: f003 020f and.w r2, r3, #15 8008612: 6879 ldr r1, [r7, #4] 8008614: 4613 mov r3, r2 8008616: 009b lsls r3, r3, #2 8008618: 4413 add r3, r2 800861a: 009b lsls r3, r3, #2 800861c: 440b add r3, r1 800861e: 331c adds r3, #28 8008620: 2207 movs r2, #7 8008622: 601a str r2, [r3, #0] 8008624: e00c b.n 8008640 } else /* LOW and FULL-speed endpoints */ { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; 8008626: 4b14 ldr r3, [pc, #80] @ (8008678 ) 8008628: 781b ldrb r3, [r3, #0] 800862a: f003 020f and.w r2, r3, #15 800862e: 6879 ldr r1, [r7, #4] 8008630: 4613 mov r3, r2 8008632: 009b lsls r3, r3, #2 8008634: 4413 add r3, r2 8008636: 009b lsls r3, r3, #2 8008638: 440b add r3, r1 800863a: 331c adds r3, #28 800863c: 220a movs r2, #10 800863e: 601a str r2, [r3, #0] } /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); 8008640: 4b0d ldr r3, [pc, #52] @ (8008678 ) 8008642: 7819 ldrb r1, [r3, #0] 8008644: 230e movs r3, #14 8008646: 2203 movs r2, #3 8008648: 6878 ldr r0, [r7, #4] 800864a: f002 f83e bl 800a6ca pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; 800864e: 4b0a ldr r3, [pc, #40] @ (8008678 ) 8008650: 781b ldrb r3, [r3, #0] 8008652: f003 020f and.w r2, r3, #15 8008656: 6879 ldr r1, [r7, #4] 8008658: 4613 mov r3, r2 800865a: 009b lsls r3, r3, #2 800865c: 4413 add r3, r2 800865e: 009b lsls r3, r3, #2 8008660: 440b add r3, r1 8008662: 3323 adds r3, #35 @ 0x23 8008664: 2201 movs r2, #1 8008666: 701a strb r2, [r3, #0] hhid->state = USBD_HID_IDLE; 8008668: 68fb ldr r3, [r7, #12] 800866a: 2200 movs r2, #0 800866c: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 800866e: 2300 movs r3, #0 } 8008670: 4618 mov r0, r3 8008672: 3710 adds r7, #16 8008674: 46bd mov sp, r7 8008676: bd80 pop {r7, pc} 8008678: 2000013d .word 0x2000013d 0800867c : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800867c: b580 push {r7, lr} 800867e: b082 sub sp, #8 8008680: af00 add r7, sp, #0 8008682: 6078 str r0, [r7, #4] 8008684: 460b mov r3, r1 8008686: 70fb strb r3, [r7, #3] /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close HID EPs */ (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); 8008688: 4b1f ldr r3, [pc, #124] @ (8008708 ) 800868a: 781b ldrb r3, [r3, #0] 800868c: 4619 mov r1, r3 800868e: 6878 ldr r0, [r7, #4] 8008690: f002 f841 bl 800a716 pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; 8008694: 4b1c ldr r3, [pc, #112] @ (8008708 ) 8008696: 781b ldrb r3, [r3, #0] 8008698: f003 020f and.w r2, r3, #15 800869c: 6879 ldr r1, [r7, #4] 800869e: 4613 mov r3, r2 80086a0: 009b lsls r3, r3, #2 80086a2: 4413 add r3, r2 80086a4: 009b lsls r3, r3, #2 80086a6: 440b add r3, r1 80086a8: 3323 adds r3, #35 @ 0x23 80086aa: 2200 movs r2, #0 80086ac: 701a strb r2, [r3, #0] pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; 80086ae: 4b16 ldr r3, [pc, #88] @ (8008708 ) 80086b0: 781b ldrb r3, [r3, #0] 80086b2: f003 020f and.w r2, r3, #15 80086b6: 6879 ldr r1, [r7, #4] 80086b8: 4613 mov r3, r2 80086ba: 009b lsls r3, r3, #2 80086bc: 4413 add r3, r2 80086be: 009b lsls r3, r3, #2 80086c0: 440b add r3, r1 80086c2: 331c adds r3, #28 80086c4: 2200 movs r2, #0 80086c6: 601a str r2, [r3, #0] /* Free allocated memory */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 80086c8: 687b ldr r3, [r7, #4] 80086ca: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80086ce: 687b ldr r3, [r7, #4] 80086d0: 32b0 adds r2, #176 @ 0xb0 80086d2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80086d6: 2b00 cmp r3, #0 80086d8: d011 beq.n 80086fe { (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 80086da: 687b ldr r3, [r7, #4] 80086dc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80086e0: 687b ldr r3, [r7, #4] 80086e2: 32b0 adds r2, #176 @ 0xb0 80086e4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80086e8: 4618 mov r0, r3 80086ea: f002 f95b bl 800a9a4 pdev->pClassDataCmsit[pdev->classId] = NULL; 80086ee: 687b ldr r3, [r7, #4] 80086f0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80086f4: 687b ldr r3, [r7, #4] 80086f6: 32b0 adds r2, #176 @ 0xb0 80086f8: 2100 movs r1, #0 80086fa: f843 1022 str.w r1, [r3, r2, lsl #2] } return (uint8_t)USBD_OK; 80086fe: 2300 movs r3, #0 } 8008700: 4618 mov r0, r3 8008702: 3708 adds r7, #8 8008704: 46bd mov sp, r7 8008706: bd80 pop {r7, pc} 8008708: 2000013d .word 0x2000013d 0800870c : * @param pdev: instance * @param req: usb requests * @retval status */ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800870c: b580 push {r7, lr} 800870e: b086 sub sp, #24 8008710: af00 add r7, sp, #0 8008712: 6078 str r0, [r7, #4] 8008714: 6039 str r1, [r7, #0] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8008716: 687b ldr r3, [r7, #4] 8008718: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800871c: 687b ldr r3, [r7, #4] 800871e: 32b0 adds r2, #176 @ 0xb0 8008720: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008724: 60fb str r3, [r7, #12] USBD_StatusTypeDef ret = USBD_OK; 8008726: 2300 movs r3, #0 8008728: 75fb strb r3, [r7, #23] uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; 800872a: 2300 movs r3, #0 800872c: 817b strh r3, [r7, #10] if (hhid == NULL) 800872e: 68fb ldr r3, [r7, #12] 8008730: 2b00 cmp r3, #0 8008732: d101 bne.n 8008738 { return (uint8_t)USBD_FAIL; 8008734: 2303 movs r3, #3 8008736: e0e8 b.n 800890a } switch (req->bmRequest & USB_REQ_TYPE_MASK) 8008738: 683b ldr r3, [r7, #0] 800873a: 781b ldrb r3, [r3, #0] 800873c: f003 0360 and.w r3, r3, #96 @ 0x60 8008740: 2b00 cmp r3, #0 8008742: d046 beq.n 80087d2 8008744: 2b20 cmp r3, #32 8008746: f040 80d8 bne.w 80088fa { case USB_REQ_TYPE_CLASS : switch (req->bRequest) 800874a: 683b ldr r3, [r7, #0] 800874c: 785b ldrb r3, [r3, #1] 800874e: 3b02 subs r3, #2 8008750: 2b09 cmp r3, #9 8008752: d836 bhi.n 80087c2 8008754: a201 add r2, pc, #4 @ (adr r2, 800875c ) 8008756: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800875a: bf00 nop 800875c: 080087b3 .word 0x080087b3 8008760: 08008793 .word 0x08008793 8008764: 080087c3 .word 0x080087c3 8008768: 080087c3 .word 0x080087c3 800876c: 080087c3 .word 0x080087c3 8008770: 080087c3 .word 0x080087c3 8008774: 080087c3 .word 0x080087c3 8008778: 080087c3 .word 0x080087c3 800877c: 080087a1 .word 0x080087a1 8008780: 08008785 .word 0x08008785 { case USBD_HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); 8008784: 683b ldr r3, [r7, #0] 8008786: 885b ldrh r3, [r3, #2] 8008788: b2db uxtb r3, r3 800878a: 461a mov r2, r3 800878c: 68fb ldr r3, [r7, #12] 800878e: 601a str r2, [r3, #0] break; 8008790: e01e b.n 80087d0 case USBD_HID_REQ_GET_PROTOCOL: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); 8008792: 68fb ldr r3, [r7, #12] 8008794: 2201 movs r2, #1 8008796: 4619 mov r1, r3 8008798: 6878 ldr r0, [r7, #4] 800879a: f001 fc25 bl 8009fe8 break; 800879e: e017 b.n 80087d0 case USBD_HID_REQ_SET_IDLE: hhid->IdleState = (uint8_t)(req->wValue >> 8); 80087a0: 683b ldr r3, [r7, #0] 80087a2: 885b ldrh r3, [r3, #2] 80087a4: 0a1b lsrs r3, r3, #8 80087a6: b29b uxth r3, r3 80087a8: b2db uxtb r3, r3 80087aa: 461a mov r2, r3 80087ac: 68fb ldr r3, [r7, #12] 80087ae: 605a str r2, [r3, #4] break; 80087b0: e00e b.n 80087d0 case USBD_HID_REQ_GET_IDLE: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); 80087b2: 68fb ldr r3, [r7, #12] 80087b4: 3304 adds r3, #4 80087b6: 2201 movs r2, #1 80087b8: 4619 mov r1, r3 80087ba: 6878 ldr r0, [r7, #4] 80087bc: f001 fc14 bl 8009fe8 break; 80087c0: e006 b.n 80087d0 default: USBD_CtlError(pdev, req); 80087c2: 6839 ldr r1, [r7, #0] 80087c4: 6878 ldr r0, [r7, #4] 80087c6: f001 fb92 bl 8009eee ret = USBD_FAIL; 80087ca: 2303 movs r3, #3 80087cc: 75fb strb r3, [r7, #23] break; 80087ce: bf00 nop } break; 80087d0: e09a b.n 8008908 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80087d2: 683b ldr r3, [r7, #0] 80087d4: 785b ldrb r3, [r3, #1] 80087d6: 2b0b cmp r3, #11 80087d8: f200 8086 bhi.w 80088e8 80087dc: a201 add r2, pc, #4 @ (adr r2, 80087e4 ) 80087de: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80087e2: bf00 nop 80087e4: 08008815 .word 0x08008815 80087e8: 080088f7 .word 0x080088f7 80087ec: 080088e9 .word 0x080088e9 80087f0: 080088e9 .word 0x080088e9 80087f4: 080088e9 .word 0x080088e9 80087f8: 080088e9 .word 0x080088e9 80087fc: 0800883f .word 0x0800883f 8008800: 080088e9 .word 0x080088e9 8008804: 080088e9 .word 0x080088e9 8008808: 080088e9 .word 0x080088e9 800880c: 08008897 .word 0x08008897 8008810: 080088c1 .word 0x080088c1 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008814: 687b ldr r3, [r7, #4] 8008816: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800881a: b2db uxtb r3, r3 800881c: 2b03 cmp r3, #3 800881e: d107 bne.n 8008830 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 8008820: f107 030a add.w r3, r7, #10 8008824: 2202 movs r2, #2 8008826: 4619 mov r1, r3 8008828: 6878 ldr r0, [r7, #4] 800882a: f001 fbdd bl 8009fe8 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 800882e: e063 b.n 80088f8 USBD_CtlError(pdev, req); 8008830: 6839 ldr r1, [r7, #0] 8008832: 6878 ldr r0, [r7, #4] 8008834: f001 fb5b bl 8009eee ret = USBD_FAIL; 8008838: 2303 movs r3, #3 800883a: 75fb strb r3, [r7, #23] break; 800883c: e05c b.n 80088f8 case USB_REQ_GET_DESCRIPTOR: if ((req->wValue >> 8) == HID_REPORT_DESC) 800883e: 683b ldr r3, [r7, #0] 8008840: 885b ldrh r3, [r3, #2] 8008842: 0a1b lsrs r3, r3, #8 8008844: b29b uxth r3, r3 8008846: 2b22 cmp r3, #34 @ 0x22 8008848: d108 bne.n 800885c { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); 800884a: 683b ldr r3, [r7, #0] 800884c: 88db ldrh r3, [r3, #6] 800884e: 2b2d cmp r3, #45 @ 0x2d 8008850: bf28 it cs 8008852: 232d movcs r3, #45 @ 0x2d 8008854: 82bb strh r3, [r7, #20] pbuf = HID_MOUSE_ReportDesc; 8008856: 4b2f ldr r3, [pc, #188] @ (8008914 ) 8008858: 613b str r3, [r7, #16] 800885a: e015 b.n 8008888 } else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) 800885c: 683b ldr r3, [r7, #0] 800885e: 885b ldrh r3, [r3, #2] 8008860: 0a1b lsrs r3, r3, #8 8008862: b29b uxth r3, r3 8008864: 2b21 cmp r3, #33 @ 0x21 8008866: d108 bne.n 800887a { pbuf = USBD_HID_Desc; 8008868: 4b2b ldr r3, [pc, #172] @ (8008918 ) 800886a: 613b str r3, [r7, #16] len = MIN(USB_HID_DESC_SIZ, req->wLength); 800886c: 683b ldr r3, [r7, #0] 800886e: 88db ldrh r3, [r3, #6] 8008870: 2b09 cmp r3, #9 8008872: bf28 it cs 8008874: 2309 movcs r3, #9 8008876: 82bb strh r3, [r7, #20] 8008878: e006 b.n 8008888 } else { USBD_CtlError(pdev, req); 800887a: 6839 ldr r1, [r7, #0] 800887c: 6878 ldr r0, [r7, #4] 800887e: f001 fb36 bl 8009eee ret = USBD_FAIL; 8008882: 2303 movs r3, #3 8008884: 75fb strb r3, [r7, #23] break; 8008886: e037 b.n 80088f8 } (void)USBD_CtlSendData(pdev, pbuf, len); 8008888: 8abb ldrh r3, [r7, #20] 800888a: 461a mov r2, r3 800888c: 6939 ldr r1, [r7, #16] 800888e: 6878 ldr r0, [r7, #4] 8008890: f001 fbaa bl 8009fe8 break; 8008894: e030 b.n 80088f8 case USB_REQ_GET_INTERFACE : if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008896: 687b ldr r3, [r7, #4] 8008898: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800889c: b2db uxtb r3, r3 800889e: 2b03 cmp r3, #3 80088a0: d107 bne.n 80088b2 { (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); 80088a2: 68fb ldr r3, [r7, #12] 80088a4: 3308 adds r3, #8 80088a6: 2201 movs r2, #1 80088a8: 4619 mov r1, r3 80088aa: 6878 ldr r0, [r7, #4] 80088ac: f001 fb9c bl 8009fe8 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80088b0: e022 b.n 80088f8 USBD_CtlError(pdev, req); 80088b2: 6839 ldr r1, [r7, #0] 80088b4: 6878 ldr r0, [r7, #4] 80088b6: f001 fb1a bl 8009eee ret = USBD_FAIL; 80088ba: 2303 movs r3, #3 80088bc: 75fb strb r3, [r7, #23] break; 80088be: e01b b.n 80088f8 case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 80088c0: 687b ldr r3, [r7, #4] 80088c2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80088c6: b2db uxtb r3, r3 80088c8: 2b03 cmp r3, #3 80088ca: d106 bne.n 80088da { hhid->AltSetting = (uint8_t)(req->wValue); 80088cc: 683b ldr r3, [r7, #0] 80088ce: 885b ldrh r3, [r3, #2] 80088d0: b2db uxtb r3, r3 80088d2: 461a mov r2, r3 80088d4: 68fb ldr r3, [r7, #12] 80088d6: 609a str r2, [r3, #8] else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80088d8: e00e b.n 80088f8 USBD_CtlError(pdev, req); 80088da: 6839 ldr r1, [r7, #0] 80088dc: 6878 ldr r0, [r7, #4] 80088de: f001 fb06 bl 8009eee ret = USBD_FAIL; 80088e2: 2303 movs r3, #3 80088e4: 75fb strb r3, [r7, #23] break; 80088e6: e007 b.n 80088f8 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 80088e8: 6839 ldr r1, [r7, #0] 80088ea: 6878 ldr r0, [r7, #4] 80088ec: f001 faff bl 8009eee ret = USBD_FAIL; 80088f0: 2303 movs r3, #3 80088f2: 75fb strb r3, [r7, #23] break; 80088f4: e000 b.n 80088f8 break; 80088f6: bf00 nop } break; 80088f8: e006 b.n 8008908 default: USBD_CtlError(pdev, req); 80088fa: 6839 ldr r1, [r7, #0] 80088fc: 6878 ldr r0, [r7, #4] 80088fe: f001 faf6 bl 8009eee ret = USBD_FAIL; 8008902: 2303 movs r3, #3 8008904: 75fb strb r3, [r7, #23] break; 8008906: bf00 nop } return (uint8_t)ret; 8008908: 7dfb ldrb r3, [r7, #23] } 800890a: 4618 mov r0, r3 800890c: 3718 adds r7, #24 800890e: 46bd mov sp, r7 8008910: bd80 pop {r7, pc} 8008912: bf00 nop 8008914: 20000110 .word 0x20000110 8008918: 200000f8 .word 0x200000f8 0800891c : uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) { USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { 800891c: b580 push {r7, lr} 800891e: b086 sub sp, #24 8008920: af00 add r7, sp, #0 8008922: 60f8 str r0, [r7, #12] 8008924: 60b9 str r1, [r7, #8] 8008926: 4613 mov r3, r2 8008928: 80fb strh r3, [r7, #6] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 800892a: 68fb ldr r3, [r7, #12] 800892c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008930: 68fb ldr r3, [r7, #12] 8008932: 32b0 adds r2, #176 @ 0xb0 8008934: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008938: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hhid == NULL) 800893a: 697b ldr r3, [r7, #20] 800893c: 2b00 cmp r3, #0 800893e: d101 bne.n 8008944 { return (uint8_t)USBD_FAIL; 8008940: 2303 movs r3, #3 8008942: e014 b.n 800896e #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008944: 68fb ldr r3, [r7, #12] 8008946: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800894a: b2db uxtb r3, r3 800894c: 2b03 cmp r3, #3 800894e: d10d bne.n 800896c { if (hhid->state == USBD_HID_IDLE) 8008950: 697b ldr r3, [r7, #20] 8008952: 7b1b ldrb r3, [r3, #12] 8008954: 2b00 cmp r3, #0 8008956: d109 bne.n 800896c { hhid->state = USBD_HID_BUSY; 8008958: 697b ldr r3, [r7, #20] 800895a: 2201 movs r2, #1 800895c: 731a strb r2, [r3, #12] (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); 800895e: 4b06 ldr r3, [pc, #24] @ (8008978 ) 8008960: 7819 ldrb r1, [r3, #0] 8008962: 88fb ldrh r3, [r7, #6] 8008964: 68ba ldr r2, [r7, #8] 8008966: 68f8 ldr r0, [r7, #12] 8008968: f001 ff7d bl 800a866 } } return (uint8_t)USBD_OK; 800896c: 2300 movs r3, #0 } 800896e: 4618 mov r0, r3 8008970: 3718 adds r7, #24 8008972: 46bd mov sp, r7 8008974: bd80 pop {r7, pc} 8008976: bf00 nop 8008978: 2000013d .word 0x2000013d 0800897c : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { 800897c: b580 push {r7, lr} 800897e: b084 sub sp, #16 8008980: af00 add r7, sp, #0 8008982: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008984: 2181 movs r1, #129 @ 0x81 8008986: 4809 ldr r0, [pc, #36] @ (80089ac ) 8008988: f000 fc4e bl 8009228 800898c: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 800898e: 68fb ldr r3, [r7, #12] 8008990: 2b00 cmp r3, #0 8008992: d002 beq.n 800899a { pEpDesc->bInterval = HID_FS_BINTERVAL; 8008994: 68fb ldr r3, [r7, #12] 8008996: 220a movs r2, #10 8008998: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 800899a: 687b ldr r3, [r7, #4] 800899c: 2222 movs r2, #34 @ 0x22 800899e: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 80089a0: 4b02 ldr r3, [pc, #8] @ (80089ac ) } 80089a2: 4618 mov r0, r3 80089a4: 3710 adds r7, #16 80089a6: 46bd mov sp, r7 80089a8: bd80 pop {r7, pc} 80089aa: bf00 nop 80089ac: 200000d4 .word 0x200000d4 080089b0 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { 80089b0: b580 push {r7, lr} 80089b2: b084 sub sp, #16 80089b4: af00 add r7, sp, #0 80089b6: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80089b8: 2181 movs r1, #129 @ 0x81 80089ba: 4809 ldr r0, [pc, #36] @ (80089e0 ) 80089bc: f000 fc34 bl 8009228 80089c0: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80089c2: 68fb ldr r3, [r7, #12] 80089c4: 2b00 cmp r3, #0 80089c6: d002 beq.n 80089ce { pEpDesc->bInterval = HID_HS_BINTERVAL; 80089c8: 68fb ldr r3, [r7, #12] 80089ca: 2207 movs r2, #7 80089cc: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80089ce: 687b ldr r3, [r7, #4] 80089d0: 2222 movs r2, #34 @ 0x22 80089d2: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 80089d4: 4b02 ldr r3, [pc, #8] @ (80089e0 ) } 80089d6: 4618 mov r0, r3 80089d8: 3710 adds r7, #16 80089da: 46bd mov sp, r7 80089dc: bd80 pop {r7, pc} 80089de: bf00 nop 80089e0: 200000d4 .word 0x200000d4 080089e4 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { 80089e4: b580 push {r7, lr} 80089e6: b084 sub sp, #16 80089e8: af00 add r7, sp, #0 80089ea: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80089ec: 2181 movs r1, #129 @ 0x81 80089ee: 4809 ldr r0, [pc, #36] @ (8008a14 ) 80089f0: f000 fc1a bl 8009228 80089f4: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80089f6: 68fb ldr r3, [r7, #12] 80089f8: 2b00 cmp r3, #0 80089fa: d002 beq.n 8008a02 { pEpDesc->bInterval = HID_FS_BINTERVAL; 80089fc: 68fb ldr r3, [r7, #12] 80089fe: 220a movs r2, #10 8008a00: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008a02: 687b ldr r3, [r7, #4] 8008a04: 2222 movs r2, #34 @ 0x22 8008a06: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008a08: 4b02 ldr r3, [pc, #8] @ (8008a14 ) } 8008a0a: 4618 mov r0, r3 8008a0c: 3710 adds r7, #16 8008a0e: 46bd mov sp, r7 8008a10: bd80 pop {r7, pc} 8008a12: bf00 nop 8008a14: 200000d4 .word 0x200000d4 08008a18 : * @param pdev: device instance * @param epnum: endpoint index * @retval status */ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008a18: b480 push {r7} 8008a1a: b083 sub sp, #12 8008a1c: af00 add r7, sp, #0 8008a1e: 6078 str r0, [r7, #4] 8008a20: 460b mov r3, r1 8008a22: 70fb strb r3, [r7, #3] UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; 8008a24: 687b ldr r3, [r7, #4] 8008a26: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008a2a: 687b ldr r3, [r7, #4] 8008a2c: 32b0 adds r2, #176 @ 0xb0 8008a2e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008a32: 2200 movs r2, #0 8008a34: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 8008a36: 2300 movs r3, #0 } 8008a38: 4618 mov r0, r3 8008a3a: 370c adds r7, #12 8008a3c: 46bd mov sp, r7 8008a3e: f85d 7b04 ldr.w r7, [sp], #4 8008a42: 4770 bx lr 08008a44 : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { 8008a44: b480 push {r7} 8008a46: b083 sub sp, #12 8008a48: af00 add r7, sp, #0 8008a4a: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); 8008a4c: 687b ldr r3, [r7, #4] 8008a4e: 220a movs r2, #10 8008a50: 801a strh r2, [r3, #0] return USBD_HID_DeviceQualifierDesc; 8008a52: 4b03 ldr r3, [pc, #12] @ (8008a60 ) } 8008a54: 4618 mov r0, r3 8008a56: 370c adds r7, #12 8008a58: 46bd mov sp, r7 8008a5a: f85d 7b04 ldr.w r7, [sp], #4 8008a5e: 4770 bx lr 8008a60: 20000104 .word 0x20000104 08008a64 : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 8008a64: b580 push {r7, lr} 8008a66: b086 sub sp, #24 8008a68: af00 add r7, sp, #0 8008a6a: 60f8 str r0, [r7, #12] 8008a6c: 60b9 str r1, [r7, #8] 8008a6e: 4613 mov r3, r2 8008a70: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 8008a72: 68fb ldr r3, [r7, #12] 8008a74: 2b00 cmp r3, #0 8008a76: d101 bne.n 8008a7c { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8008a78: 2303 movs r3, #3 8008a7a: e01f b.n 8008abc pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 8008a7c: 68fb ldr r3, [r7, #12] 8008a7e: 2200 movs r2, #0 8008a80: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 8008a84: 68fb ldr r3, [r7, #12] 8008a86: 2200 movs r2, #0 8008a88: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 8008a8c: 68fb ldr r3, [r7, #12] 8008a8e: 2200 movs r2, #0 8008a90: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 8008a94: 68bb ldr r3, [r7, #8] 8008a96: 2b00 cmp r3, #0 8008a98: d003 beq.n 8008aa2 { pdev->pDesc = pdesc; 8008a9a: 68fb ldr r3, [r7, #12] 8008a9c: 68ba ldr r2, [r7, #8] 8008a9e: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 8008aa2: 68fb ldr r3, [r7, #12] 8008aa4: 2201 movs r2, #1 8008aa6: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 8008aaa: 68fb ldr r3, [r7, #12] 8008aac: 79fa ldrb r2, [r7, #7] 8008aae: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8008ab0: 68f8 ldr r0, [r7, #12] 8008ab2: f001 fda3 bl 800a5fc 8008ab6: 4603 mov r3, r0 8008ab8: 75fb strb r3, [r7, #23] return ret; 8008aba: 7dfb ldrb r3, [r7, #23] } 8008abc: 4618 mov r0, r3 8008abe: 3718 adds r7, #24 8008ac0: 46bd mov sp, r7 8008ac2: bd80 pop {r7, pc} 08008ac4 : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 8008ac4: b580 push {r7, lr} 8008ac6: b084 sub sp, #16 8008ac8: af00 add r7, sp, #0 8008aca: 6078 str r0, [r7, #4] 8008acc: 6039 str r1, [r7, #0] uint16_t len = 0U; 8008ace: 2300 movs r3, #0 8008ad0: 81fb strh r3, [r7, #14] if (pclass == NULL) 8008ad2: 683b ldr r3, [r7, #0] 8008ad4: 2b00 cmp r3, #0 8008ad6: d101 bne.n 8008adc { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8008ad8: 2303 movs r3, #3 8008ada: e025 b.n 8008b28 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 8008adc: 687b ldr r3, [r7, #4] 8008ade: 683a ldr r2, [r7, #0] 8008ae0: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 8008ae4: 687b ldr r3, [r7, #4] 8008ae6: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008aea: 687b ldr r3, [r7, #4] 8008aec: 32ae adds r2, #174 @ 0xae 8008aee: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008af2: 6adb ldr r3, [r3, #44] @ 0x2c 8008af4: 2b00 cmp r3, #0 8008af6: d00f beq.n 8008b18 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 8008af8: 687b ldr r3, [r7, #4] 8008afa: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008afe: 687b ldr r3, [r7, #4] 8008b00: 32ae adds r2, #174 @ 0xae 8008b02: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b06: 6adb ldr r3, [r3, #44] @ 0x2c 8008b08: f107 020e add.w r2, r7, #14 8008b0c: 4610 mov r0, r2 8008b0e: 4798 blx r3 8008b10: 4602 mov r2, r0 8008b12: 687b ldr r3, [r7, #4] 8008b14: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 8008b18: 687b ldr r3, [r7, #4] 8008b1a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8008b1e: 1c5a adds r2, r3, #1 8008b20: 687b ldr r3, [r7, #4] 8008b22: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 8008b26: 2300 movs r3, #0 } 8008b28: 4618 mov r0, r3 8008b2a: 3710 adds r7, #16 8008b2c: 46bd mov sp, r7 8008b2e: bd80 pop {r7, pc} 08008b30 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8008b30: b580 push {r7, lr} 8008b32: b082 sub sp, #8 8008b34: af00 add r7, sp, #0 8008b36: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 8008b38: 6878 ldr r0, [r7, #4] 8008b3a: f001 fdab bl 800a694 8008b3e: 4603 mov r3, r0 } 8008b40: 4618 mov r0, r3 8008b42: 3708 adds r7, #8 8008b44: 46bd mov sp, r7 8008b46: bd80 pop {r7, pc} 08008b48 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8008b48: b480 push {r7} 8008b4a: b083 sub sp, #12 8008b4c: af00 add r7, sp, #0 8008b4e: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8008b50: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 8008b52: 4618 mov r0, r3 8008b54: 370c adds r7, #12 8008b56: 46bd mov sp, r7 8008b58: f85d 7b04 ldr.w r7, [sp], #4 8008b5c: 4770 bx lr 08008b5e : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008b5e: b580 push {r7, lr} 8008b60: b084 sub sp, #16 8008b62: af00 add r7, sp, #0 8008b64: 6078 str r0, [r7, #4] 8008b66: 460b mov r3, r1 8008b68: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008b6a: 2300 movs r3, #0 8008b6c: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 8008b6e: 687b ldr r3, [r7, #4] 8008b70: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008b74: 2b00 cmp r3, #0 8008b76: d009 beq.n 8008b8c { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 8008b78: 687b ldr r3, [r7, #4] 8008b7a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008b7e: 681b ldr r3, [r3, #0] 8008b80: 78fa ldrb r2, [r7, #3] 8008b82: 4611 mov r1, r2 8008b84: 6878 ldr r0, [r7, #4] 8008b86: 4798 blx r3 8008b88: 4603 mov r3, r0 8008b8a: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008b8c: 7bfb ldrb r3, [r7, #15] } 8008b8e: 4618 mov r0, r3 8008b90: 3710 adds r7, #16 8008b92: 46bd mov sp, r7 8008b94: bd80 pop {r7, pc} 08008b96 : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008b96: b580 push {r7, lr} 8008b98: b084 sub sp, #16 8008b9a: af00 add r7, sp, #0 8008b9c: 6078 str r0, [r7, #4] 8008b9e: 460b mov r3, r1 8008ba0: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008ba2: 2300 movs r3, #0 8008ba4: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 8008ba6: 687b ldr r3, [r7, #4] 8008ba8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008bac: 685b ldr r3, [r3, #4] 8008bae: 78fa ldrb r2, [r7, #3] 8008bb0: 4611 mov r1, r2 8008bb2: 6878 ldr r0, [r7, #4] 8008bb4: 4798 blx r3 8008bb6: 4603 mov r3, r0 8008bb8: 2b00 cmp r3, #0 8008bba: d001 beq.n 8008bc0 { ret = USBD_FAIL; 8008bbc: 2303 movs r3, #3 8008bbe: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008bc0: 7bfb ldrb r3, [r7, #15] } 8008bc2: 4618 mov r0, r3 8008bc4: 3710 adds r7, #16 8008bc6: 46bd mov sp, r7 8008bc8: bd80 pop {r7, pc} 08008bca : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 8008bca: b580 push {r7, lr} 8008bcc: b084 sub sp, #16 8008bce: af00 add r7, sp, #0 8008bd0: 6078 str r0, [r7, #4] 8008bd2: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 8008bd4: 687b ldr r3, [r7, #4] 8008bd6: f203 23aa addw r3, r3, #682 @ 0x2aa 8008bda: 6839 ldr r1, [r7, #0] 8008bdc: 4618 mov r0, r3 8008bde: f001 f94c bl 8009e7a pdev->ep0_state = USBD_EP0_SETUP; 8008be2: 687b ldr r3, [r7, #4] 8008be4: 2201 movs r2, #1 8008be6: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 8008bea: 687b ldr r3, [r7, #4] 8008bec: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 8008bf0: 461a mov r2, r3 8008bf2: 687b ldr r3, [r7, #4] 8008bf4: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 8008bf8: 687b ldr r3, [r7, #4] 8008bfa: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008bfe: f003 031f and.w r3, r3, #31 8008c02: 2b02 cmp r3, #2 8008c04: d01a beq.n 8008c3c 8008c06: 2b02 cmp r3, #2 8008c08: d822 bhi.n 8008c50 8008c0a: 2b00 cmp r3, #0 8008c0c: d002 beq.n 8008c14 8008c0e: 2b01 cmp r3, #1 8008c10: d00a beq.n 8008c28 8008c12: e01d b.n 8008c50 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8008c14: 687b ldr r3, [r7, #4] 8008c16: f203 23aa addw r3, r3, #682 @ 0x2aa 8008c1a: 4619 mov r1, r3 8008c1c: 6878 ldr r0, [r7, #4] 8008c1e: f000 fb77 bl 8009310 8008c22: 4603 mov r3, r0 8008c24: 73fb strb r3, [r7, #15] break; 8008c26: e020 b.n 8008c6a case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8008c28: 687b ldr r3, [r7, #4] 8008c2a: f203 23aa addw r3, r3, #682 @ 0x2aa 8008c2e: 4619 mov r1, r3 8008c30: 6878 ldr r0, [r7, #4] 8008c32: f000 fbdf bl 80093f4 8008c36: 4603 mov r3, r0 8008c38: 73fb strb r3, [r7, #15] break; 8008c3a: e016 b.n 8008c6a case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8008c3c: 687b ldr r3, [r7, #4] 8008c3e: f203 23aa addw r3, r3, #682 @ 0x2aa 8008c42: 4619 mov r1, r3 8008c44: 6878 ldr r0, [r7, #4] 8008c46: f000 fc41 bl 80094cc 8008c4a: 4603 mov r3, r0 8008c4c: 73fb strb r3, [r7, #15] break; 8008c4e: e00c b.n 8008c6a default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8008c50: 687b ldr r3, [r7, #4] 8008c52: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008c56: f023 037f bic.w r3, r3, #127 @ 0x7f 8008c5a: b2db uxtb r3, r3 8008c5c: 4619 mov r1, r3 8008c5e: 6878 ldr r0, [r7, #4] 8008c60: f001 fd78 bl 800a754 8008c64: 4603 mov r3, r0 8008c66: 73fb strb r3, [r7, #15] break; 8008c68: bf00 nop } return ret; 8008c6a: 7bfb ldrb r3, [r7, #15] } 8008c6c: 4618 mov r0, r3 8008c6e: 3710 adds r7, #16 8008c70: 46bd mov sp, r7 8008c72: bd80 pop {r7, pc} 08008c74 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008c74: b580 push {r7, lr} 8008c76: b086 sub sp, #24 8008c78: af00 add r7, sp, #0 8008c7a: 60f8 str r0, [r7, #12] 8008c7c: 460b mov r3, r1 8008c7e: 607a str r2, [r7, #4] 8008c80: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 8008c82: 2300 movs r3, #0 8008c84: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008c86: 7afb ldrb r3, [r7, #11] 8008c88: 2b00 cmp r3, #0 8008c8a: d177 bne.n 8008d7c { pep = &pdev->ep_out[0]; 8008c8c: 68fb ldr r3, [r7, #12] 8008c8e: f503 73aa add.w r3, r3, #340 @ 0x154 8008c92: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 8008c94: 68fb ldr r3, [r7, #12] 8008c96: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008c9a: 2b03 cmp r3, #3 8008c9c: f040 80a1 bne.w 8008de2 { if (pep->rem_length > pep->maxpacket) 8008ca0: 693b ldr r3, [r7, #16] 8008ca2: 685b ldr r3, [r3, #4] 8008ca4: 693a ldr r2, [r7, #16] 8008ca6: 8992 ldrh r2, [r2, #12] 8008ca8: 4293 cmp r3, r2 8008caa: d91c bls.n 8008ce6 { pep->rem_length -= pep->maxpacket; 8008cac: 693b ldr r3, [r7, #16] 8008cae: 685b ldr r3, [r3, #4] 8008cb0: 693a ldr r2, [r7, #16] 8008cb2: 8992 ldrh r2, [r2, #12] 8008cb4: 1a9a subs r2, r3, r2 8008cb6: 693b ldr r3, [r7, #16] 8008cb8: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008cba: 693b ldr r3, [r7, #16] 8008cbc: 691b ldr r3, [r3, #16] 8008cbe: 693a ldr r2, [r7, #16] 8008cc0: 8992 ldrh r2, [r2, #12] 8008cc2: 441a add r2, r3 8008cc4: 693b ldr r3, [r7, #16] 8008cc6: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 8008cc8: 693b ldr r3, [r7, #16] 8008cca: 6919 ldr r1, [r3, #16] 8008ccc: 693b ldr r3, [r7, #16] 8008cce: 899b ldrh r3, [r3, #12] 8008cd0: 461a mov r2, r3 8008cd2: 693b ldr r3, [r7, #16] 8008cd4: 685b ldr r3, [r3, #4] 8008cd6: 4293 cmp r3, r2 8008cd8: bf38 it cc 8008cda: 4613 movcc r3, r2 8008cdc: 461a mov r2, r3 8008cde: 68f8 ldr r0, [r7, #12] 8008ce0: f001 f9b1 bl 800a046 8008ce4: e07d b.n 8008de2 } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 8008ce6: 68fb ldr r3, [r7, #12] 8008ce8: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008cec: f003 031f and.w r3, r3, #31 8008cf0: 2b02 cmp r3, #2 8008cf2: d014 beq.n 8008d1e 8008cf4: 2b02 cmp r3, #2 8008cf6: d81d bhi.n 8008d34 8008cf8: 2b00 cmp r3, #0 8008cfa: d002 beq.n 8008d02 8008cfc: 2b01 cmp r3, #1 8008cfe: d003 beq.n 8008d08 8008d00: e018 b.n 8008d34 { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 8008d02: 2300 movs r3, #0 8008d04: 75bb strb r3, [r7, #22] break; 8008d06: e018 b.n 8008d3a case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8008d08: 68fb ldr r3, [r7, #12] 8008d0a: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008d0e: b2db uxtb r3, r3 8008d10: 4619 mov r1, r3 8008d12: 68f8 ldr r0, [r7, #12] 8008d14: f000 fa6e bl 80091f4 8008d18: 4603 mov r3, r0 8008d1a: 75bb strb r3, [r7, #22] break; 8008d1c: e00d b.n 8008d3a case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8008d1e: 68fb ldr r3, [r7, #12] 8008d20: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008d24: b2db uxtb r3, r3 8008d26: 4619 mov r1, r3 8008d28: 68f8 ldr r0, [r7, #12] 8008d2a: f000 fa70 bl 800920e 8008d2e: 4603 mov r3, r0 8008d30: 75bb strb r3, [r7, #22] break; 8008d32: e002 b.n 8008d3a default: /* Back to the first class in case of doubt */ idx = 0U; 8008d34: 2300 movs r3, #0 8008d36: 75bb strb r3, [r7, #22] break; 8008d38: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 8008d3a: 7dbb ldrb r3, [r7, #22] 8008d3c: 2b00 cmp r3, #0 8008d3e: d119 bne.n 8008d74 { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008d40: 68fb ldr r3, [r7, #12] 8008d42: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008d46: b2db uxtb r3, r3 8008d48: 2b03 cmp r3, #3 8008d4a: d113 bne.n 8008d74 { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8008d4c: 7dba ldrb r2, [r7, #22] 8008d4e: 68fb ldr r3, [r7, #12] 8008d50: 32ae adds r2, #174 @ 0xae 8008d52: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008d56: 691b ldr r3, [r3, #16] 8008d58: 2b00 cmp r3, #0 8008d5a: d00b beq.n 8008d74 { pdev->classId = idx; 8008d5c: 7dba ldrb r2, [r7, #22] 8008d5e: 68fb ldr r3, [r7, #12] 8008d60: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 8008d64: 7dba ldrb r2, [r7, #22] 8008d66: 68fb ldr r3, [r7, #12] 8008d68: 32ae adds r2, #174 @ 0xae 8008d6a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008d6e: 691b ldr r3, [r3, #16] 8008d70: 68f8 ldr r0, [r7, #12] 8008d72: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 8008d74: 68f8 ldr r0, [r7, #12] 8008d76: f001 f977 bl 800a068 8008d7a: e032 b.n 8008de2 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 8008d7c: 7afb ldrb r3, [r7, #11] 8008d7e: f003 037f and.w r3, r3, #127 @ 0x7f 8008d82: b2db uxtb r3, r3 8008d84: 4619 mov r1, r3 8008d86: 68f8 ldr r0, [r7, #12] 8008d88: f000 fa41 bl 800920e 8008d8c: 4603 mov r3, r0 8008d8e: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008d90: 7dbb ldrb r3, [r7, #22] 8008d92: 2bff cmp r3, #255 @ 0xff 8008d94: d025 beq.n 8008de2 8008d96: 7dbb ldrb r3, [r7, #22] 8008d98: 2b00 cmp r3, #0 8008d9a: d122 bne.n 8008de2 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008d9c: 68fb ldr r3, [r7, #12] 8008d9e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008da2: b2db uxtb r3, r3 8008da4: 2b03 cmp r3, #3 8008da6: d117 bne.n 8008dd8 { if (pdev->pClass[idx]->DataOut != NULL) 8008da8: 7dba ldrb r2, [r7, #22] 8008daa: 68fb ldr r3, [r7, #12] 8008dac: 32ae adds r2, #174 @ 0xae 8008dae: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008db2: 699b ldr r3, [r3, #24] 8008db4: 2b00 cmp r3, #0 8008db6: d00f beq.n 8008dd8 { pdev->classId = idx; 8008db8: 7dba ldrb r2, [r7, #22] 8008dba: 68fb ldr r3, [r7, #12] 8008dbc: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 8008dc0: 7dba ldrb r2, [r7, #22] 8008dc2: 68fb ldr r3, [r7, #12] 8008dc4: 32ae adds r2, #174 @ 0xae 8008dc6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008dca: 699b ldr r3, [r3, #24] 8008dcc: 7afa ldrb r2, [r7, #11] 8008dce: 4611 mov r1, r2 8008dd0: 68f8 ldr r0, [r7, #12] 8008dd2: 4798 blx r3 8008dd4: 4603 mov r3, r0 8008dd6: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8008dd8: 7dfb ldrb r3, [r7, #23] 8008dda: 2b00 cmp r3, #0 8008ddc: d001 beq.n 8008de2 { return ret; 8008dde: 7dfb ldrb r3, [r7, #23] 8008de0: e000 b.n 8008de4 } } } return USBD_OK; 8008de2: 2300 movs r3, #0 } 8008de4: 4618 mov r0, r3 8008de6: 3718 adds r7, #24 8008de8: 46bd mov sp, r7 8008dea: bd80 pop {r7, pc} 08008dec : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008dec: b580 push {r7, lr} 8008dee: b086 sub sp, #24 8008df0: af00 add r7, sp, #0 8008df2: 60f8 str r0, [r7, #12] 8008df4: 460b mov r3, r1 8008df6: 607a str r2, [r7, #4] 8008df8: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008dfa: 7afb ldrb r3, [r7, #11] 8008dfc: 2b00 cmp r3, #0 8008dfe: d178 bne.n 8008ef2 { pep = &pdev->ep_in[0]; 8008e00: 68fb ldr r3, [r7, #12] 8008e02: 3314 adds r3, #20 8008e04: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8008e06: 68fb ldr r3, [r7, #12] 8008e08: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008e0c: 2b02 cmp r3, #2 8008e0e: d163 bne.n 8008ed8 { if (pep->rem_length > pep->maxpacket) 8008e10: 693b ldr r3, [r7, #16] 8008e12: 685b ldr r3, [r3, #4] 8008e14: 693a ldr r2, [r7, #16] 8008e16: 8992 ldrh r2, [r2, #12] 8008e18: 4293 cmp r3, r2 8008e1a: d91c bls.n 8008e56 { pep->rem_length -= pep->maxpacket; 8008e1c: 693b ldr r3, [r7, #16] 8008e1e: 685b ldr r3, [r3, #4] 8008e20: 693a ldr r2, [r7, #16] 8008e22: 8992 ldrh r2, [r2, #12] 8008e24: 1a9a subs r2, r3, r2 8008e26: 693b ldr r3, [r7, #16] 8008e28: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008e2a: 693b ldr r3, [r7, #16] 8008e2c: 691b ldr r3, [r3, #16] 8008e2e: 693a ldr r2, [r7, #16] 8008e30: 8992 ldrh r2, [r2, #12] 8008e32: 441a add r2, r3 8008e34: 693b ldr r3, [r7, #16] 8008e36: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8008e38: 693b ldr r3, [r7, #16] 8008e3a: 6919 ldr r1, [r3, #16] 8008e3c: 693b ldr r3, [r7, #16] 8008e3e: 685b ldr r3, [r3, #4] 8008e40: 461a mov r2, r3 8008e42: 68f8 ldr r0, [r7, #12] 8008e44: f001 f8ee bl 800a024 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008e48: 2300 movs r3, #0 8008e4a: 2200 movs r2, #0 8008e4c: 2100 movs r1, #0 8008e4e: 68f8 ldr r0, [r7, #12] 8008e50: f001 fd2a bl 800a8a8 8008e54: e040 b.n 8008ed8 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8008e56: 693b ldr r3, [r7, #16] 8008e58: 899b ldrh r3, [r3, #12] 8008e5a: 461a mov r2, r3 8008e5c: 693b ldr r3, [r7, #16] 8008e5e: 685b ldr r3, [r3, #4] 8008e60: 429a cmp r2, r3 8008e62: d11c bne.n 8008e9e (pep->total_length >= pep->maxpacket) && 8008e64: 693b ldr r3, [r7, #16] 8008e66: 681b ldr r3, [r3, #0] 8008e68: 693a ldr r2, [r7, #16] 8008e6a: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 8008e6c: 4293 cmp r3, r2 8008e6e: d316 bcc.n 8008e9e (pep->total_length < pdev->ep0_data_len)) 8008e70: 693b ldr r3, [r7, #16] 8008e72: 681a ldr r2, [r3, #0] 8008e74: 68fb ldr r3, [r7, #12] 8008e76: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 8008e7a: 429a cmp r2, r3 8008e7c: d20f bcs.n 8008e9e { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8008e7e: 2200 movs r2, #0 8008e80: 2100 movs r1, #0 8008e82: 68f8 ldr r0, [r7, #12] 8008e84: f001 f8ce bl 800a024 pdev->ep0_data_len = 0U; 8008e88: 68fb ldr r3, [r7, #12] 8008e8a: 2200 movs r2, #0 8008e8c: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008e90: 2300 movs r3, #0 8008e92: 2200 movs r2, #0 8008e94: 2100 movs r1, #0 8008e96: 68f8 ldr r0, [r7, #12] 8008e98: f001 fd06 bl 800a8a8 8008e9c: e01c b.n 8008ed8 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008e9e: 68fb ldr r3, [r7, #12] 8008ea0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008ea4: b2db uxtb r3, r3 8008ea6: 2b03 cmp r3, #3 8008ea8: d10f bne.n 8008eca { if (pdev->pClass[0]->EP0_TxSent != NULL) 8008eaa: 68fb ldr r3, [r7, #12] 8008eac: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008eb0: 68db ldr r3, [r3, #12] 8008eb2: 2b00 cmp r3, #0 8008eb4: d009 beq.n 8008eca { pdev->classId = 0U; 8008eb6: 68fb ldr r3, [r7, #12] 8008eb8: 2200 movs r2, #0 8008eba: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 8008ebe: 68fb ldr r3, [r7, #12] 8008ec0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ec4: 68db ldr r3, [r3, #12] 8008ec6: 68f8 ldr r0, [r7, #12] 8008ec8: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8008eca: 2180 movs r1, #128 @ 0x80 8008ecc: 68f8 ldr r0, [r7, #12] 8008ece: f001 fc41 bl 800a754 (void)USBD_CtlReceiveStatus(pdev); 8008ed2: 68f8 ldr r0, [r7, #12] 8008ed4: f001 f8db bl 800a08e } } } if (pdev->dev_test_mode != 0U) 8008ed8: 68fb ldr r3, [r7, #12] 8008eda: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8008ede: 2b00 cmp r3, #0 8008ee0: d03a beq.n 8008f58 { (void)USBD_RunTestMode(pdev); 8008ee2: 68f8 ldr r0, [r7, #12] 8008ee4: f7ff fe30 bl 8008b48 pdev->dev_test_mode = 0U; 8008ee8: 68fb ldr r3, [r7, #12] 8008eea: 2200 movs r2, #0 8008eec: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8008ef0: e032 b.n 8008f58 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8008ef2: 7afb ldrb r3, [r7, #11] 8008ef4: f063 037f orn r3, r3, #127 @ 0x7f 8008ef8: b2db uxtb r3, r3 8008efa: 4619 mov r1, r3 8008efc: 68f8 ldr r0, [r7, #12] 8008efe: f000 f986 bl 800920e 8008f02: 4603 mov r3, r0 8008f04: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008f06: 7dfb ldrb r3, [r7, #23] 8008f08: 2bff cmp r3, #255 @ 0xff 8008f0a: d025 beq.n 8008f58 8008f0c: 7dfb ldrb r3, [r7, #23] 8008f0e: 2b00 cmp r3, #0 8008f10: d122 bne.n 8008f58 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008f12: 68fb ldr r3, [r7, #12] 8008f14: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008f18: b2db uxtb r3, r3 8008f1a: 2b03 cmp r3, #3 8008f1c: d11c bne.n 8008f58 { if (pdev->pClass[idx]->DataIn != NULL) 8008f1e: 7dfa ldrb r2, [r7, #23] 8008f20: 68fb ldr r3, [r7, #12] 8008f22: 32ae adds r2, #174 @ 0xae 8008f24: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008f28: 695b ldr r3, [r3, #20] 8008f2a: 2b00 cmp r3, #0 8008f2c: d014 beq.n 8008f58 { pdev->classId = idx; 8008f2e: 7dfa ldrb r2, [r7, #23] 8008f30: 68fb ldr r3, [r7, #12] 8008f32: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 8008f36: 7dfa ldrb r2, [r7, #23] 8008f38: 68fb ldr r3, [r7, #12] 8008f3a: 32ae adds r2, #174 @ 0xae 8008f3c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008f40: 695b ldr r3, [r3, #20] 8008f42: 7afa ldrb r2, [r7, #11] 8008f44: 4611 mov r1, r2 8008f46: 68f8 ldr r0, [r7, #12] 8008f48: 4798 blx r3 8008f4a: 4603 mov r3, r0 8008f4c: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 8008f4e: 7dbb ldrb r3, [r7, #22] 8008f50: 2b00 cmp r3, #0 8008f52: d001 beq.n 8008f58 { return ret; 8008f54: 7dbb ldrb r3, [r7, #22] 8008f56: e000 b.n 8008f5a } } } } return USBD_OK; 8008f58: 2300 movs r3, #0 } 8008f5a: 4618 mov r0, r3 8008f5c: 3718 adds r7, #24 8008f5e: 46bd mov sp, r7 8008f60: bd80 pop {r7, pc} 08008f62 : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8008f62: b580 push {r7, lr} 8008f64: b084 sub sp, #16 8008f66: af00 add r7, sp, #0 8008f68: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8008f6a: 2300 movs r3, #0 8008f6c: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8008f6e: 687b ldr r3, [r7, #4] 8008f70: 2201 movs r2, #1 8008f72: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 8008f76: 687b ldr r3, [r7, #4] 8008f78: 2200 movs r2, #0 8008f7a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 8008f7e: 687b ldr r3, [r7, #4] 8008f80: 2200 movs r2, #0 8008f82: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 8008f84: 687b ldr r3, [r7, #4] 8008f86: 2200 movs r2, #0 8008f88: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 8008f8c: 687b ldr r3, [r7, #4] 8008f8e: 2200 movs r2, #0 8008f90: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 8008f94: 687b ldr r3, [r7, #4] 8008f96: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008f9a: 2b00 cmp r3, #0 8008f9c: d014 beq.n 8008fc8 { if (pdev->pClass[0]->DeInit != NULL) 8008f9e: 687b ldr r3, [r7, #4] 8008fa0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008fa4: 685b ldr r3, [r3, #4] 8008fa6: 2b00 cmp r3, #0 8008fa8: d00e beq.n 8008fc8 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 8008faa: 687b ldr r3, [r7, #4] 8008fac: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008fb0: 685b ldr r3, [r3, #4] 8008fb2: 687a ldr r2, [r7, #4] 8008fb4: 6852 ldr r2, [r2, #4] 8008fb6: b2d2 uxtb r2, r2 8008fb8: 4611 mov r1, r2 8008fba: 6878 ldr r0, [r7, #4] 8008fbc: 4798 blx r3 8008fbe: 4603 mov r3, r0 8008fc0: 2b00 cmp r3, #0 8008fc2: d001 beq.n 8008fc8 { ret = USBD_FAIL; 8008fc4: 2303 movs r3, #3 8008fc6: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8008fc8: 2340 movs r3, #64 @ 0x40 8008fca: 2200 movs r2, #0 8008fcc: 2100 movs r1, #0 8008fce: 6878 ldr r0, [r7, #4] 8008fd0: f001 fb7b bl 800a6ca pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8008fd4: 687b ldr r3, [r7, #4] 8008fd6: 2201 movs r2, #1 8008fd8: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8008fdc: 687b ldr r3, [r7, #4] 8008fde: 2240 movs r2, #64 @ 0x40 8008fe0: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8008fe4: 2340 movs r3, #64 @ 0x40 8008fe6: 2200 movs r2, #0 8008fe8: 2180 movs r1, #128 @ 0x80 8008fea: 6878 ldr r0, [r7, #4] 8008fec: f001 fb6d bl 800a6ca pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8008ff0: 687b ldr r3, [r7, #4] 8008ff2: 2201 movs r2, #1 8008ff4: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8008ff8: 687b ldr r3, [r7, #4] 8008ffa: 2240 movs r2, #64 @ 0x40 8008ffc: 841a strh r2, [r3, #32] return ret; 8008ffe: 7bfb ldrb r3, [r7, #15] } 8009000: 4618 mov r0, r3 8009002: 3710 adds r7, #16 8009004: 46bd mov sp, r7 8009006: bd80 pop {r7, pc} 08009008 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8009008: b480 push {r7} 800900a: b083 sub sp, #12 800900c: af00 add r7, sp, #0 800900e: 6078 str r0, [r7, #4] 8009010: 460b mov r3, r1 8009012: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8009014: 687b ldr r3, [r7, #4] 8009016: 78fa ldrb r2, [r7, #3] 8009018: 741a strb r2, [r3, #16] return USBD_OK; 800901a: 2300 movs r3, #0 } 800901c: 4618 mov r0, r3 800901e: 370c adds r7, #12 8009020: 46bd mov sp, r7 8009022: f85d 7b04 ldr.w r7, [sp], #4 8009026: 4770 bx lr 08009028 : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8009028: b480 push {r7} 800902a: b083 sub sp, #12 800902c: af00 add r7, sp, #0 800902e: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8009030: 687b ldr r3, [r7, #4] 8009032: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009036: b2db uxtb r3, r3 8009038: 2b04 cmp r3, #4 800903a: d006 beq.n 800904a { pdev->dev_old_state = pdev->dev_state; 800903c: 687b ldr r3, [r7, #4] 800903e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009042: b2da uxtb r2, r3 8009044: 687b ldr r3, [r7, #4] 8009046: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 800904a: 687b ldr r3, [r7, #4] 800904c: 2204 movs r2, #4 800904e: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 8009052: 2300 movs r3, #0 } 8009054: 4618 mov r0, r3 8009056: 370c adds r7, #12 8009058: 46bd mov sp, r7 800905a: f85d 7b04 ldr.w r7, [sp], #4 800905e: 4770 bx lr 08009060 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 8009060: b480 push {r7} 8009062: b083 sub sp, #12 8009064: af00 add r7, sp, #0 8009066: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 8009068: 687b ldr r3, [r7, #4] 800906a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800906e: b2db uxtb r3, r3 8009070: 2b04 cmp r3, #4 8009072: d106 bne.n 8009082 { pdev->dev_state = pdev->dev_old_state; 8009074: 687b ldr r3, [r7, #4] 8009076: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 800907a: b2da uxtb r2, r3 800907c: 687b ldr r3, [r7, #4] 800907e: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 8009082: 2300 movs r3, #0 } 8009084: 4618 mov r0, r3 8009086: 370c adds r7, #12 8009088: 46bd mov sp, r7 800908a: f85d 7b04 ldr.w r7, [sp], #4 800908e: 4770 bx lr 08009090 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 8009090: b580 push {r7, lr} 8009092: b082 sub sp, #8 8009094: af00 add r7, sp, #0 8009096: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009098: 687b ldr r3, [r7, #4] 800909a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800909e: b2db uxtb r3, r3 80090a0: 2b03 cmp r3, #3 80090a2: d110 bne.n 80090c6 } } } } #else if (pdev->pClass[0] != NULL) 80090a4: 687b ldr r3, [r7, #4] 80090a6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80090aa: 2b00 cmp r3, #0 80090ac: d00b beq.n 80090c6 { if (pdev->pClass[0]->SOF != NULL) 80090ae: 687b ldr r3, [r7, #4] 80090b0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80090b4: 69db ldr r3, [r3, #28] 80090b6: 2b00 cmp r3, #0 80090b8: d005 beq.n 80090c6 { (void)pdev->pClass[0]->SOF(pdev); 80090ba: 687b ldr r3, [r7, #4] 80090bc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80090c0: 69db ldr r3, [r3, #28] 80090c2: 6878 ldr r0, [r7, #4] 80090c4: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 80090c6: 2300 movs r3, #0 } 80090c8: 4618 mov r0, r3 80090ca: 3708 adds r7, #8 80090cc: 46bd mov sp, r7 80090ce: bd80 pop {r7, pc} 080090d0 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 80090d0: b580 push {r7, lr} 80090d2: b082 sub sp, #8 80090d4: af00 add r7, sp, #0 80090d6: 6078 str r0, [r7, #4] 80090d8: 460b mov r3, r1 80090da: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 80090dc: 687b ldr r3, [r7, #4] 80090de: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80090e2: 687b ldr r3, [r7, #4] 80090e4: 32ae adds r2, #174 @ 0xae 80090e6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80090ea: 2b00 cmp r3, #0 80090ec: d101 bne.n 80090f2 { return USBD_FAIL; 80090ee: 2303 movs r3, #3 80090f0: e01c b.n 800912c } if (pdev->dev_state == USBD_STATE_CONFIGURED) 80090f2: 687b ldr r3, [r7, #4] 80090f4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80090f8: b2db uxtb r3, r3 80090fa: 2b03 cmp r3, #3 80090fc: d115 bne.n 800912a { if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) 80090fe: 687b ldr r3, [r7, #4] 8009100: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009104: 687b ldr r3, [r7, #4] 8009106: 32ae adds r2, #174 @ 0xae 8009108: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800910c: 6a1b ldr r3, [r3, #32] 800910e: 2b00 cmp r3, #0 8009110: d00b beq.n 800912a { (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); 8009112: 687b ldr r3, [r7, #4] 8009114: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009118: 687b ldr r3, [r7, #4] 800911a: 32ae adds r2, #174 @ 0xae 800911c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009120: 6a1b ldr r3, [r3, #32] 8009122: 78fa ldrb r2, [r7, #3] 8009124: 4611 mov r1, r2 8009126: 6878 ldr r0, [r7, #4] 8009128: 4798 blx r3 } } return USBD_OK; 800912a: 2300 movs r3, #0 } 800912c: 4618 mov r0, r3 800912e: 3708 adds r7, #8 8009130: 46bd mov sp, r7 8009132: bd80 pop {r7, pc} 08009134 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009134: b580 push {r7, lr} 8009136: b082 sub sp, #8 8009138: af00 add r7, sp, #0 800913a: 6078 str r0, [r7, #4] 800913c: 460b mov r3, r1 800913e: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009140: 687b ldr r3, [r7, #4] 8009142: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009146: 687b ldr r3, [r7, #4] 8009148: 32ae adds r2, #174 @ 0xae 800914a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800914e: 2b00 cmp r3, #0 8009150: d101 bne.n 8009156 { return USBD_FAIL; 8009152: 2303 movs r3, #3 8009154: e01c b.n 8009190 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009156: 687b ldr r3, [r7, #4] 8009158: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800915c: b2db uxtb r3, r3 800915e: 2b03 cmp r3, #3 8009160: d115 bne.n 800918e { if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) 8009162: 687b ldr r3, [r7, #4] 8009164: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009168: 687b ldr r3, [r7, #4] 800916a: 32ae adds r2, #174 @ 0xae 800916c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009170: 6a5b ldr r3, [r3, #36] @ 0x24 8009172: 2b00 cmp r3, #0 8009174: d00b beq.n 800918e { (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); 8009176: 687b ldr r3, [r7, #4] 8009178: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800917c: 687b ldr r3, [r7, #4] 800917e: 32ae adds r2, #174 @ 0xae 8009180: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009184: 6a5b ldr r3, [r3, #36] @ 0x24 8009186: 78fa ldrb r2, [r7, #3] 8009188: 4611 mov r1, r2 800918a: 6878 ldr r0, [r7, #4] 800918c: 4798 blx r3 } } return USBD_OK; 800918e: 2300 movs r3, #0 } 8009190: 4618 mov r0, r3 8009192: 3708 adds r7, #8 8009194: 46bd mov sp, r7 8009196: bd80 pop {r7, pc} 08009198 : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 8009198: b480 push {r7} 800919a: b083 sub sp, #12 800919c: af00 add r7, sp, #0 800919e: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 80091a0: 2300 movs r3, #0 } 80091a2: 4618 mov r0, r3 80091a4: 370c adds r7, #12 80091a6: 46bd mov sp, r7 80091a8: f85d 7b04 ldr.w r7, [sp], #4 80091ac: 4770 bx lr 080091ae : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 80091ae: b580 push {r7, lr} 80091b0: b084 sub sp, #16 80091b2: af00 add r7, sp, #0 80091b4: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 80091b6: 2300 movs r3, #0 80091b8: 73fb strb r3, [r7, #15] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 80091ba: 687b ldr r3, [r7, #4] 80091bc: 2201 movs r2, #1 80091be: f883 229c strb.w r2, [r3, #668] @ 0x29c } } } } #else if (pdev->pClass[0] != NULL) 80091c2: 687b ldr r3, [r7, #4] 80091c4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80091c8: 2b00 cmp r3, #0 80091ca: d00e beq.n 80091ea { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) 80091cc: 687b ldr r3, [r7, #4] 80091ce: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80091d2: 685b ldr r3, [r3, #4] 80091d4: 687a ldr r2, [r7, #4] 80091d6: 6852 ldr r2, [r2, #4] 80091d8: b2d2 uxtb r2, r2 80091da: 4611 mov r1, r2 80091dc: 6878 ldr r0, [r7, #4] 80091de: 4798 blx r3 80091e0: 4603 mov r3, r0 80091e2: 2b00 cmp r3, #0 80091e4: d001 beq.n 80091ea { ret = USBD_FAIL; 80091e6: 2303 movs r3, #3 80091e8: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ return ret; 80091ea: 7bfb ldrb r3, [r7, #15] } 80091ec: 4618 mov r0, r3 80091ee: 3710 adds r7, #16 80091f0: 46bd mov sp, r7 80091f2: bd80 pop {r7, pc} 080091f4 : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 80091f4: b480 push {r7} 80091f6: b083 sub sp, #12 80091f8: af00 add r7, sp, #0 80091fa: 6078 str r0, [r7, #4] 80091fc: 460b mov r3, r1 80091fe: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009200: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009202: 4618 mov r0, r3 8009204: 370c adds r7, #12 8009206: 46bd mov sp, r7 8009208: f85d 7b04 ldr.w r7, [sp], #4 800920c: 4770 bx lr 0800920e : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 800920e: b480 push {r7} 8009210: b083 sub sp, #12 8009212: af00 add r7, sp, #0 8009214: 6078 str r0, [r7, #4] 8009216: 460b mov r3, r1 8009218: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 800921a: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 800921c: 4618 mov r0, r3 800921e: 370c adds r7, #12 8009220: 46bd mov sp, r7 8009222: f85d 7b04 ldr.w r7, [sp], #4 8009226: 4770 bx lr 08009228 : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 8009228: b580 push {r7, lr} 800922a: b086 sub sp, #24 800922c: af00 add r7, sp, #0 800922e: 6078 str r0, [r7, #4] 8009230: 460b mov r3, r1 8009232: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 8009234: 687b ldr r3, [r7, #4] 8009236: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 8009238: 687b ldr r3, [r7, #4] 800923a: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 800923c: 2300 movs r3, #0 800923e: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8009240: 68fb ldr r3, [r7, #12] 8009242: 885b ldrh r3, [r3, #2] 8009244: b29b uxth r3, r3 8009246: 68fa ldr r2, [r7, #12] 8009248: 7812 ldrb r2, [r2, #0] 800924a: 4293 cmp r3, r2 800924c: d91f bls.n 800928e { ptr = desc->bLength; 800924e: 68fb ldr r3, [r7, #12] 8009250: 781b ldrb r3, [r3, #0] 8009252: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 8009254: e013 b.n 800927e { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 8009256: f107 030a add.w r3, r7, #10 800925a: 4619 mov r1, r3 800925c: 6978 ldr r0, [r7, #20] 800925e: f000 f81b bl 8009298 8009262: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 8009264: 697b ldr r3, [r7, #20] 8009266: 785b ldrb r3, [r3, #1] 8009268: 2b05 cmp r3, #5 800926a: d108 bne.n 800927e { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 800926c: 697b ldr r3, [r7, #20] 800926e: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 8009270: 693b ldr r3, [r7, #16] 8009272: 789b ldrb r3, [r3, #2] 8009274: 78fa ldrb r2, [r7, #3] 8009276: 429a cmp r2, r3 8009278: d008 beq.n 800928c { break; } else { pEpDesc = NULL; 800927a: 2300 movs r3, #0 800927c: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 800927e: 68fb ldr r3, [r7, #12] 8009280: 885b ldrh r3, [r3, #2] 8009282: b29a uxth r2, r3 8009284: 897b ldrh r3, [r7, #10] 8009286: 429a cmp r2, r3 8009288: d8e5 bhi.n 8009256 800928a: e000 b.n 800928e break; 800928c: bf00 nop } } } } return (void *)pEpDesc; 800928e: 693b ldr r3, [r7, #16] } 8009290: 4618 mov r0, r3 8009292: 3718 adds r7, #24 8009294: 46bd mov sp, r7 8009296: bd80 pop {r7, pc} 08009298 : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 8009298: b480 push {r7} 800929a: b085 sub sp, #20 800929c: af00 add r7, sp, #0 800929e: 6078 str r0, [r7, #4] 80092a0: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 80092a2: 687b ldr r3, [r7, #4] 80092a4: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 80092a6: 683b ldr r3, [r7, #0] 80092a8: 881b ldrh r3, [r3, #0] 80092aa: 68fa ldr r2, [r7, #12] 80092ac: 7812 ldrb r2, [r2, #0] 80092ae: 4413 add r3, r2 80092b0: b29a uxth r2, r3 80092b2: 683b ldr r3, [r7, #0] 80092b4: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 80092b6: 68fb ldr r3, [r7, #12] 80092b8: 781b ldrb r3, [r3, #0] 80092ba: 461a mov r2, r3 80092bc: 687b ldr r3, [r7, #4] 80092be: 4413 add r3, r2 80092c0: 60fb str r3, [r7, #12] return (pnext); 80092c2: 68fb ldr r3, [r7, #12] } 80092c4: 4618 mov r0, r3 80092c6: 3714 adds r7, #20 80092c8: 46bd mov sp, r7 80092ca: f85d 7b04 ldr.w r7, [sp], #4 80092ce: 4770 bx lr 080092d0 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 80092d0: b480 push {r7} 80092d2: b087 sub sp, #28 80092d4: af00 add r7, sp, #0 80092d6: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 80092d8: 687b ldr r3, [r7, #4] 80092da: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 80092dc: 697b ldr r3, [r7, #20] 80092de: 781b ldrb r3, [r3, #0] 80092e0: 827b strh r3, [r7, #18] _pbuff++; 80092e2: 697b ldr r3, [r7, #20] 80092e4: 3301 adds r3, #1 80092e6: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 80092e8: 697b ldr r3, [r7, #20] 80092ea: 781b ldrb r3, [r3, #0] 80092ec: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 80092ee: f9b7 3010 ldrsh.w r3, [r7, #16] 80092f2: 021b lsls r3, r3, #8 80092f4: b21a sxth r2, r3 80092f6: f9b7 3012 ldrsh.w r3, [r7, #18] 80092fa: 4313 orrs r3, r2 80092fc: b21b sxth r3, r3 80092fe: 81fb strh r3, [r7, #14] return _SwapVal; 8009300: 89fb ldrh r3, [r7, #14] } 8009302: 4618 mov r0, r3 8009304: 371c adds r7, #28 8009306: 46bd mov sp, r7 8009308: f85d 7b04 ldr.w r7, [sp], #4 800930c: 4770 bx lr ... 08009310 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009310: b580 push {r7, lr} 8009312: b084 sub sp, #16 8009314: af00 add r7, sp, #0 8009316: 6078 str r0, [r7, #4] 8009318: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800931a: 2300 movs r3, #0 800931c: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800931e: 683b ldr r3, [r7, #0] 8009320: 781b ldrb r3, [r3, #0] 8009322: f003 0360 and.w r3, r3, #96 @ 0x60 8009326: 2b40 cmp r3, #64 @ 0x40 8009328: d005 beq.n 8009336 800932a: 2b40 cmp r3, #64 @ 0x40 800932c: d857 bhi.n 80093de 800932e: 2b00 cmp r3, #0 8009330: d00f beq.n 8009352 8009332: 2b20 cmp r3, #32 8009334: d153 bne.n 80093de { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 8009336: 687b ldr r3, [r7, #4] 8009338: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800933c: 687b ldr r3, [r7, #4] 800933e: 32ae adds r2, #174 @ 0xae 8009340: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009344: 689b ldr r3, [r3, #8] 8009346: 6839 ldr r1, [r7, #0] 8009348: 6878 ldr r0, [r7, #4] 800934a: 4798 blx r3 800934c: 4603 mov r3, r0 800934e: 73fb strb r3, [r7, #15] break; 8009350: e04a b.n 80093e8 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8009352: 683b ldr r3, [r7, #0] 8009354: 785b ldrb r3, [r3, #1] 8009356: 2b09 cmp r3, #9 8009358: d83b bhi.n 80093d2 800935a: a201 add r2, pc, #4 @ (adr r2, 8009360 ) 800935c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009360: 080093b5 .word 0x080093b5 8009364: 080093c9 .word 0x080093c9 8009368: 080093d3 .word 0x080093d3 800936c: 080093bf .word 0x080093bf 8009370: 080093d3 .word 0x080093d3 8009374: 08009393 .word 0x08009393 8009378: 08009389 .word 0x08009389 800937c: 080093d3 .word 0x080093d3 8009380: 080093ab .word 0x080093ab 8009384: 0800939d .word 0x0800939d { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 8009388: 6839 ldr r1, [r7, #0] 800938a: 6878 ldr r0, [r7, #4] 800938c: f000 fa3e bl 800980c break; 8009390: e024 b.n 80093dc case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 8009392: 6839 ldr r1, [r7, #0] 8009394: 6878 ldr r0, [r7, #4] 8009396: f000 fbcd bl 8009b34 break; 800939a: e01f b.n 80093dc case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 800939c: 6839 ldr r1, [r7, #0] 800939e: 6878 ldr r0, [r7, #4] 80093a0: f000 fc0c bl 8009bbc 80093a4: 4603 mov r3, r0 80093a6: 73fb strb r3, [r7, #15] break; 80093a8: e018 b.n 80093dc case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 80093aa: 6839 ldr r1, [r7, #0] 80093ac: 6878 ldr r0, [r7, #4] 80093ae: f000 fcaf bl 8009d10 break; 80093b2: e013 b.n 80093dc case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 80093b4: 6839 ldr r1, [r7, #0] 80093b6: 6878 ldr r0, [r7, #4] 80093b8: f000 fce0 bl 8009d7c break; 80093bc: e00e b.n 80093dc case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 80093be: 6839 ldr r1, [r7, #0] 80093c0: 6878 ldr r0, [r7, #4] 80093c2: f000 fd0f bl 8009de4 break; 80093c6: e009 b.n 80093dc case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 80093c8: 6839 ldr r1, [r7, #0] 80093ca: 6878 ldr r0, [r7, #4] 80093cc: f000 fd33 bl 8009e36 break; 80093d0: e004 b.n 80093dc default: USBD_CtlError(pdev, req); 80093d2: 6839 ldr r1, [r7, #0] 80093d4: 6878 ldr r0, [r7, #4] 80093d6: f000 fd8a bl 8009eee break; 80093da: bf00 nop } break; 80093dc: e004 b.n 80093e8 default: USBD_CtlError(pdev, req); 80093de: 6839 ldr r1, [r7, #0] 80093e0: 6878 ldr r0, [r7, #4] 80093e2: f000 fd84 bl 8009eee break; 80093e6: bf00 nop } return ret; 80093e8: 7bfb ldrb r3, [r7, #15] } 80093ea: 4618 mov r0, r3 80093ec: 3710 adds r7, #16 80093ee: 46bd mov sp, r7 80093f0: bd80 pop {r7, pc} 80093f2: bf00 nop 080093f4 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80093f4: b580 push {r7, lr} 80093f6: b084 sub sp, #16 80093f8: af00 add r7, sp, #0 80093fa: 6078 str r0, [r7, #4] 80093fc: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 80093fe: 2300 movs r3, #0 8009400: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009402: 683b ldr r3, [r7, #0] 8009404: 781b ldrb r3, [r3, #0] 8009406: f003 0360 and.w r3, r3, #96 @ 0x60 800940a: 2b40 cmp r3, #64 @ 0x40 800940c: d005 beq.n 800941a 800940e: 2b40 cmp r3, #64 @ 0x40 8009410: d852 bhi.n 80094b8 8009412: 2b00 cmp r3, #0 8009414: d001 beq.n 800941a 8009416: 2b20 cmp r3, #32 8009418: d14e bne.n 80094b8 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 800941a: 687b ldr r3, [r7, #4] 800941c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009420: b2db uxtb r3, r3 8009422: 3b01 subs r3, #1 8009424: 2b02 cmp r3, #2 8009426: d840 bhi.n 80094aa { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 8009428: 683b ldr r3, [r7, #0] 800942a: 889b ldrh r3, [r3, #4] 800942c: b2db uxtb r3, r3 800942e: 2b01 cmp r3, #1 8009430: d836 bhi.n 80094a0 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 8009432: 683b ldr r3, [r7, #0] 8009434: 889b ldrh r3, [r3, #4] 8009436: b2db uxtb r3, r3 8009438: 4619 mov r1, r3 800943a: 6878 ldr r0, [r7, #4] 800943c: f7ff feda bl 80091f4 8009440: 4603 mov r3, r0 8009442: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009444: 7bbb ldrb r3, [r7, #14] 8009446: 2bff cmp r3, #255 @ 0xff 8009448: d01d beq.n 8009486 800944a: 7bbb ldrb r3, [r7, #14] 800944c: 2b00 cmp r3, #0 800944e: d11a bne.n 8009486 { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009450: 7bba ldrb r2, [r7, #14] 8009452: 687b ldr r3, [r7, #4] 8009454: 32ae adds r2, #174 @ 0xae 8009456: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800945a: 689b ldr r3, [r3, #8] 800945c: 2b00 cmp r3, #0 800945e: d00f beq.n 8009480 { pdev->classId = idx; 8009460: 7bba ldrb r2, [r7, #14] 8009462: 687b ldr r3, [r7, #4] 8009464: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8009468: 7bba ldrb r2, [r7, #14] 800946a: 687b ldr r3, [r7, #4] 800946c: 32ae adds r2, #174 @ 0xae 800946e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009472: 689b ldr r3, [r3, #8] 8009474: 6839 ldr r1, [r7, #0] 8009476: 6878 ldr r0, [r7, #4] 8009478: 4798 blx r3 800947a: 4603 mov r3, r0 800947c: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 800947e: e004 b.n 800948a } else { /* should never reach this condition */ ret = USBD_FAIL; 8009480: 2303 movs r3, #3 8009482: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8009484: e001 b.n 800948a } } else { /* No relative interface found */ ret = USBD_FAIL; 8009486: 2303 movs r3, #3 8009488: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 800948a: 683b ldr r3, [r7, #0] 800948c: 88db ldrh r3, [r3, #6] 800948e: 2b00 cmp r3, #0 8009490: d110 bne.n 80094b4 8009492: 7bfb ldrb r3, [r7, #15] 8009494: 2b00 cmp r3, #0 8009496: d10d bne.n 80094b4 { (void)USBD_CtlSendStatus(pdev); 8009498: 6878 ldr r0, [r7, #4] 800949a: f000 fde5 bl 800a068 } else { USBD_CtlError(pdev, req); } break; 800949e: e009 b.n 80094b4 USBD_CtlError(pdev, req); 80094a0: 6839 ldr r1, [r7, #0] 80094a2: 6878 ldr r0, [r7, #4] 80094a4: f000 fd23 bl 8009eee break; 80094a8: e004 b.n 80094b4 default: USBD_CtlError(pdev, req); 80094aa: 6839 ldr r1, [r7, #0] 80094ac: 6878 ldr r0, [r7, #4] 80094ae: f000 fd1e bl 8009eee break; 80094b2: e000 b.n 80094b6 break; 80094b4: bf00 nop } break; 80094b6: e004 b.n 80094c2 default: USBD_CtlError(pdev, req); 80094b8: 6839 ldr r1, [r7, #0] 80094ba: 6878 ldr r0, [r7, #4] 80094bc: f000 fd17 bl 8009eee break; 80094c0: bf00 nop } return ret; 80094c2: 7bfb ldrb r3, [r7, #15] } 80094c4: 4618 mov r0, r3 80094c6: 3710 adds r7, #16 80094c8: 46bd mov sp, r7 80094ca: bd80 pop {r7, pc} 080094cc : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80094cc: b580 push {r7, lr} 80094ce: b084 sub sp, #16 80094d0: af00 add r7, sp, #0 80094d2: 6078 str r0, [r7, #4] 80094d4: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 80094d6: 2300 movs r3, #0 80094d8: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 80094da: 683b ldr r3, [r7, #0] 80094dc: 889b ldrh r3, [r3, #4] 80094de: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 80094e0: 683b ldr r3, [r7, #0] 80094e2: 781b ldrb r3, [r3, #0] 80094e4: f003 0360 and.w r3, r3, #96 @ 0x60 80094e8: 2b40 cmp r3, #64 @ 0x40 80094ea: d007 beq.n 80094fc 80094ec: 2b40 cmp r3, #64 @ 0x40 80094ee: f200 8181 bhi.w 80097f4 80094f2: 2b00 cmp r3, #0 80094f4: d02a beq.n 800954c 80094f6: 2b20 cmp r3, #32 80094f8: f040 817c bne.w 80097f4 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 80094fc: 7bbb ldrb r3, [r7, #14] 80094fe: 4619 mov r1, r3 8009500: 6878 ldr r0, [r7, #4] 8009502: f7ff fe84 bl 800920e 8009506: 4603 mov r3, r0 8009508: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800950a: 7b7b ldrb r3, [r7, #13] 800950c: 2bff cmp r3, #255 @ 0xff 800950e: f000 8176 beq.w 80097fe 8009512: 7b7b ldrb r3, [r7, #13] 8009514: 2b00 cmp r3, #0 8009516: f040 8172 bne.w 80097fe { pdev->classId = idx; 800951a: 7b7a ldrb r2, [r7, #13] 800951c: 687b ldr r3, [r7, #4] 800951e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009522: 7b7a ldrb r2, [r7, #13] 8009524: 687b ldr r3, [r7, #4] 8009526: 32ae adds r2, #174 @ 0xae 8009528: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800952c: 689b ldr r3, [r3, #8] 800952e: 2b00 cmp r3, #0 8009530: f000 8165 beq.w 80097fe { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 8009534: 7b7a ldrb r2, [r7, #13] 8009536: 687b ldr r3, [r7, #4] 8009538: 32ae adds r2, #174 @ 0xae 800953a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800953e: 689b ldr r3, [r3, #8] 8009540: 6839 ldr r1, [r7, #0] 8009542: 6878 ldr r0, [r7, #4] 8009544: 4798 blx r3 8009546: 4603 mov r3, r0 8009548: 73fb strb r3, [r7, #15] } } break; 800954a: e158 b.n 80097fe case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800954c: 683b ldr r3, [r7, #0] 800954e: 785b ldrb r3, [r3, #1] 8009550: 2b03 cmp r3, #3 8009552: d008 beq.n 8009566 8009554: 2b03 cmp r3, #3 8009556: f300 8147 bgt.w 80097e8 800955a: 2b00 cmp r3, #0 800955c: f000 809b beq.w 8009696 8009560: 2b01 cmp r3, #1 8009562: d03c beq.n 80095de 8009564: e140 b.n 80097e8 { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 8009566: 687b ldr r3, [r7, #4] 8009568: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800956c: b2db uxtb r3, r3 800956e: 2b02 cmp r3, #2 8009570: d002 beq.n 8009578 8009572: 2b03 cmp r3, #3 8009574: d016 beq.n 80095a4 8009576: e02c b.n 80095d2 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009578: 7bbb ldrb r3, [r7, #14] 800957a: 2b00 cmp r3, #0 800957c: d00d beq.n 800959a 800957e: 7bbb ldrb r3, [r7, #14] 8009580: 2b80 cmp r3, #128 @ 0x80 8009582: d00a beq.n 800959a { (void)USBD_LL_StallEP(pdev, ep_addr); 8009584: 7bbb ldrb r3, [r7, #14] 8009586: 4619 mov r1, r3 8009588: 6878 ldr r0, [r7, #4] 800958a: f001 f8e3 bl 800a754 (void)USBD_LL_StallEP(pdev, 0x80U); 800958e: 2180 movs r1, #128 @ 0x80 8009590: 6878 ldr r0, [r7, #4] 8009592: f001 f8df bl 800a754 8009596: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8009598: e020 b.n 80095dc USBD_CtlError(pdev, req); 800959a: 6839 ldr r1, [r7, #0] 800959c: 6878 ldr r0, [r7, #4] 800959e: f000 fca6 bl 8009eee break; 80095a2: e01b b.n 80095dc case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 80095a4: 683b ldr r3, [r7, #0] 80095a6: 885b ldrh r3, [r3, #2] 80095a8: 2b00 cmp r3, #0 80095aa: d10e bne.n 80095ca { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 80095ac: 7bbb ldrb r3, [r7, #14] 80095ae: 2b00 cmp r3, #0 80095b0: d00b beq.n 80095ca 80095b2: 7bbb ldrb r3, [r7, #14] 80095b4: 2b80 cmp r3, #128 @ 0x80 80095b6: d008 beq.n 80095ca 80095b8: 683b ldr r3, [r7, #0] 80095ba: 88db ldrh r3, [r3, #6] 80095bc: 2b00 cmp r3, #0 80095be: d104 bne.n 80095ca { (void)USBD_LL_StallEP(pdev, ep_addr); 80095c0: 7bbb ldrb r3, [r7, #14] 80095c2: 4619 mov r1, r3 80095c4: 6878 ldr r0, [r7, #4] 80095c6: f001 f8c5 bl 800a754 } } (void)USBD_CtlSendStatus(pdev); 80095ca: 6878 ldr r0, [r7, #4] 80095cc: f000 fd4c bl 800a068 break; 80095d0: e004 b.n 80095dc default: USBD_CtlError(pdev, req); 80095d2: 6839 ldr r1, [r7, #0] 80095d4: 6878 ldr r0, [r7, #4] 80095d6: f000 fc8a bl 8009eee break; 80095da: bf00 nop } break; 80095dc: e109 b.n 80097f2 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 80095de: 687b ldr r3, [r7, #4] 80095e0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80095e4: b2db uxtb r3, r3 80095e6: 2b02 cmp r3, #2 80095e8: d002 beq.n 80095f0 80095ea: 2b03 cmp r3, #3 80095ec: d016 beq.n 800961c 80095ee: e04b b.n 8009688 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80095f0: 7bbb ldrb r3, [r7, #14] 80095f2: 2b00 cmp r3, #0 80095f4: d00d beq.n 8009612 80095f6: 7bbb ldrb r3, [r7, #14] 80095f8: 2b80 cmp r3, #128 @ 0x80 80095fa: d00a beq.n 8009612 { (void)USBD_LL_StallEP(pdev, ep_addr); 80095fc: 7bbb ldrb r3, [r7, #14] 80095fe: 4619 mov r1, r3 8009600: 6878 ldr r0, [r7, #4] 8009602: f001 f8a7 bl 800a754 (void)USBD_LL_StallEP(pdev, 0x80U); 8009606: 2180 movs r1, #128 @ 0x80 8009608: 6878 ldr r0, [r7, #4] 800960a: f001 f8a3 bl 800a754 800960e: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8009610: e040 b.n 8009694 USBD_CtlError(pdev, req); 8009612: 6839 ldr r1, [r7, #0] 8009614: 6878 ldr r0, [r7, #4] 8009616: f000 fc6a bl 8009eee break; 800961a: e03b b.n 8009694 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 800961c: 683b ldr r3, [r7, #0] 800961e: 885b ldrh r3, [r3, #2] 8009620: 2b00 cmp r3, #0 8009622: d136 bne.n 8009692 { if ((ep_addr & 0x7FU) != 0x00U) 8009624: 7bbb ldrb r3, [r7, #14] 8009626: f003 037f and.w r3, r3, #127 @ 0x7f 800962a: 2b00 cmp r3, #0 800962c: d004 beq.n 8009638 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 800962e: 7bbb ldrb r3, [r7, #14] 8009630: 4619 mov r1, r3 8009632: 6878 ldr r0, [r7, #4] 8009634: f001 f8ad bl 800a792 } (void)USBD_CtlSendStatus(pdev); 8009638: 6878 ldr r0, [r7, #4] 800963a: f000 fd15 bl 800a068 /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 800963e: 7bbb ldrb r3, [r7, #14] 8009640: 4619 mov r1, r3 8009642: 6878 ldr r0, [r7, #4] 8009644: f7ff fde3 bl 800920e 8009648: 4603 mov r3, r0 800964a: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800964c: 7b7b ldrb r3, [r7, #13] 800964e: 2bff cmp r3, #255 @ 0xff 8009650: d01f beq.n 8009692 8009652: 7b7b ldrb r3, [r7, #13] 8009654: 2b00 cmp r3, #0 8009656: d11c bne.n 8009692 { pdev->classId = idx; 8009658: 7b7a ldrb r2, [r7, #13] 800965a: 687b ldr r3, [r7, #4] 800965c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009660: 7b7a ldrb r2, [r7, #13] 8009662: 687b ldr r3, [r7, #4] 8009664: 32ae adds r2, #174 @ 0xae 8009666: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800966a: 689b ldr r3, [r3, #8] 800966c: 2b00 cmp r3, #0 800966e: d010 beq.n 8009692 { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8009670: 7b7a ldrb r2, [r7, #13] 8009672: 687b ldr r3, [r7, #4] 8009674: 32ae adds r2, #174 @ 0xae 8009676: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800967a: 689b ldr r3, [r3, #8] 800967c: 6839 ldr r1, [r7, #0] 800967e: 6878 ldr r0, [r7, #4] 8009680: 4798 blx r3 8009682: 4603 mov r3, r0 8009684: 73fb strb r3, [r7, #15] } } } break; 8009686: e004 b.n 8009692 default: USBD_CtlError(pdev, req); 8009688: 6839 ldr r1, [r7, #0] 800968a: 6878 ldr r0, [r7, #4] 800968c: f000 fc2f bl 8009eee break; 8009690: e000 b.n 8009694 break; 8009692: bf00 nop } break; 8009694: e0ad b.n 80097f2 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 8009696: 687b ldr r3, [r7, #4] 8009698: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800969c: b2db uxtb r3, r3 800969e: 2b02 cmp r3, #2 80096a0: d002 beq.n 80096a8 80096a2: 2b03 cmp r3, #3 80096a4: d033 beq.n 800970e 80096a6: e099 b.n 80097dc { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80096a8: 7bbb ldrb r3, [r7, #14] 80096aa: 2b00 cmp r3, #0 80096ac: d007 beq.n 80096be 80096ae: 7bbb ldrb r3, [r7, #14] 80096b0: 2b80 cmp r3, #128 @ 0x80 80096b2: d004 beq.n 80096be { USBD_CtlError(pdev, req); 80096b4: 6839 ldr r1, [r7, #0] 80096b6: 6878 ldr r0, [r7, #4] 80096b8: f000 fc19 bl 8009eee break; 80096bc: e093 b.n 80097e6 } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80096be: f997 300e ldrsb.w r3, [r7, #14] 80096c2: 2b00 cmp r3, #0 80096c4: da0b bge.n 80096de 80096c6: 7bbb ldrb r3, [r7, #14] 80096c8: f003 027f and.w r2, r3, #127 @ 0x7f 80096cc: 4613 mov r3, r2 80096ce: 009b lsls r3, r3, #2 80096d0: 4413 add r3, r2 80096d2: 009b lsls r3, r3, #2 80096d4: 3310 adds r3, #16 80096d6: 687a ldr r2, [r7, #4] 80096d8: 4413 add r3, r2 80096da: 3304 adds r3, #4 80096dc: e00b b.n 80096f6 &pdev->ep_out[ep_addr & 0x7FU]; 80096de: 7bbb ldrb r3, [r7, #14] 80096e0: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80096e4: 4613 mov r3, r2 80096e6: 009b lsls r3, r3, #2 80096e8: 4413 add r3, r2 80096ea: 009b lsls r3, r3, #2 80096ec: f503 73a8 add.w r3, r3, #336 @ 0x150 80096f0: 687a ldr r2, [r7, #4] 80096f2: 4413 add r3, r2 80096f4: 3304 adds r3, #4 80096f6: 60bb str r3, [r7, #8] pep->status = 0x0000U; 80096f8: 68bb ldr r3, [r7, #8] 80096fa: 2200 movs r2, #0 80096fc: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 80096fe: 68bb ldr r3, [r7, #8] 8009700: 330e adds r3, #14 8009702: 2202 movs r2, #2 8009704: 4619 mov r1, r3 8009706: 6878 ldr r0, [r7, #4] 8009708: f000 fc6e bl 8009fe8 break; 800970c: e06b b.n 80097e6 case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 800970e: f997 300e ldrsb.w r3, [r7, #14] 8009712: 2b00 cmp r3, #0 8009714: da11 bge.n 800973a { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 8009716: 7bbb ldrb r3, [r7, #14] 8009718: f003 020f and.w r2, r3, #15 800971c: 6879 ldr r1, [r7, #4] 800971e: 4613 mov r3, r2 8009720: 009b lsls r3, r3, #2 8009722: 4413 add r3, r2 8009724: 009b lsls r3, r3, #2 8009726: 440b add r3, r1 8009728: 3323 adds r3, #35 @ 0x23 800972a: 781b ldrb r3, [r3, #0] 800972c: 2b00 cmp r3, #0 800972e: d117 bne.n 8009760 { USBD_CtlError(pdev, req); 8009730: 6839 ldr r1, [r7, #0] 8009732: 6878 ldr r0, [r7, #4] 8009734: f000 fbdb bl 8009eee break; 8009738: e055 b.n 80097e6 } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 800973a: 7bbb ldrb r3, [r7, #14] 800973c: f003 020f and.w r2, r3, #15 8009740: 6879 ldr r1, [r7, #4] 8009742: 4613 mov r3, r2 8009744: 009b lsls r3, r3, #2 8009746: 4413 add r3, r2 8009748: 009b lsls r3, r3, #2 800974a: 440b add r3, r1 800974c: f203 1363 addw r3, r3, #355 @ 0x163 8009750: 781b ldrb r3, [r3, #0] 8009752: 2b00 cmp r3, #0 8009754: d104 bne.n 8009760 { USBD_CtlError(pdev, req); 8009756: 6839 ldr r1, [r7, #0] 8009758: 6878 ldr r0, [r7, #4] 800975a: f000 fbc8 bl 8009eee break; 800975e: e042 b.n 80097e6 } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009760: f997 300e ldrsb.w r3, [r7, #14] 8009764: 2b00 cmp r3, #0 8009766: da0b bge.n 8009780 8009768: 7bbb ldrb r3, [r7, #14] 800976a: f003 027f and.w r2, r3, #127 @ 0x7f 800976e: 4613 mov r3, r2 8009770: 009b lsls r3, r3, #2 8009772: 4413 add r3, r2 8009774: 009b lsls r3, r3, #2 8009776: 3310 adds r3, #16 8009778: 687a ldr r2, [r7, #4] 800977a: 4413 add r3, r2 800977c: 3304 adds r3, #4 800977e: e00b b.n 8009798 &pdev->ep_out[ep_addr & 0x7FU]; 8009780: 7bbb ldrb r3, [r7, #14] 8009782: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009786: 4613 mov r3, r2 8009788: 009b lsls r3, r3, #2 800978a: 4413 add r3, r2 800978c: 009b lsls r3, r3, #2 800978e: f503 73a8 add.w r3, r3, #336 @ 0x150 8009792: 687a ldr r2, [r7, #4] 8009794: 4413 add r3, r2 8009796: 3304 adds r3, #4 8009798: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 800979a: 7bbb ldrb r3, [r7, #14] 800979c: 2b00 cmp r3, #0 800979e: d002 beq.n 80097a6 80097a0: 7bbb ldrb r3, [r7, #14] 80097a2: 2b80 cmp r3, #128 @ 0x80 80097a4: d103 bne.n 80097ae { pep->status = 0x0000U; 80097a6: 68bb ldr r3, [r7, #8] 80097a8: 2200 movs r2, #0 80097aa: 739a strb r2, [r3, #14] 80097ac: e00e b.n 80097cc } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 80097ae: 7bbb ldrb r3, [r7, #14] 80097b0: 4619 mov r1, r3 80097b2: 6878 ldr r0, [r7, #4] 80097b4: f001 f80c bl 800a7d0 80097b8: 4603 mov r3, r0 80097ba: 2b00 cmp r3, #0 80097bc: d003 beq.n 80097c6 { pep->status = 0x0001U; 80097be: 68bb ldr r3, [r7, #8] 80097c0: 2201 movs r2, #1 80097c2: 739a strb r2, [r3, #14] 80097c4: e002 b.n 80097cc } else { pep->status = 0x0000U; 80097c6: 68bb ldr r3, [r7, #8] 80097c8: 2200 movs r2, #0 80097ca: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 80097cc: 68bb ldr r3, [r7, #8] 80097ce: 330e adds r3, #14 80097d0: 2202 movs r2, #2 80097d2: 4619 mov r1, r3 80097d4: 6878 ldr r0, [r7, #4] 80097d6: f000 fc07 bl 8009fe8 break; 80097da: e004 b.n 80097e6 default: USBD_CtlError(pdev, req); 80097dc: 6839 ldr r1, [r7, #0] 80097de: 6878 ldr r0, [r7, #4] 80097e0: f000 fb85 bl 8009eee break; 80097e4: bf00 nop } break; 80097e6: e004 b.n 80097f2 default: USBD_CtlError(pdev, req); 80097e8: 6839 ldr r1, [r7, #0] 80097ea: 6878 ldr r0, [r7, #4] 80097ec: f000 fb7f bl 8009eee break; 80097f0: bf00 nop } break; 80097f2: e005 b.n 8009800 default: USBD_CtlError(pdev, req); 80097f4: 6839 ldr r1, [r7, #0] 80097f6: 6878 ldr r0, [r7, #4] 80097f8: f000 fb79 bl 8009eee break; 80097fc: e000 b.n 8009800 break; 80097fe: bf00 nop } return ret; 8009800: 7bfb ldrb r3, [r7, #15] } 8009802: 4618 mov r0, r3 8009804: 3710 adds r7, #16 8009806: 46bd mov sp, r7 8009808: bd80 pop {r7, pc} ... 0800980c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800980c: b580 push {r7, lr} 800980e: b084 sub sp, #16 8009810: af00 add r7, sp, #0 8009812: 6078 str r0, [r7, #4] 8009814: 6039 str r1, [r7, #0] uint16_t len = 0U; 8009816: 2300 movs r3, #0 8009818: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 800981a: 2300 movs r3, #0 800981c: 60fb str r3, [r7, #12] uint8_t err = 0U; 800981e: 2300 movs r3, #0 8009820: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 8009822: 683b ldr r3, [r7, #0] 8009824: 885b ldrh r3, [r3, #2] 8009826: 0a1b lsrs r3, r3, #8 8009828: b29b uxth r3, r3 800982a: 3b01 subs r3, #1 800982c: 2b0e cmp r3, #14 800982e: f200 8152 bhi.w 8009ad6 8009832: a201 add r2, pc, #4 @ (adr r2, 8009838 ) 8009834: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009838: 080098a9 .word 0x080098a9 800983c: 080098c1 .word 0x080098c1 8009840: 08009901 .word 0x08009901 8009844: 08009ad7 .word 0x08009ad7 8009848: 08009ad7 .word 0x08009ad7 800984c: 08009a77 .word 0x08009a77 8009850: 08009aa3 .word 0x08009aa3 8009854: 08009ad7 .word 0x08009ad7 8009858: 08009ad7 .word 0x08009ad7 800985c: 08009ad7 .word 0x08009ad7 8009860: 08009ad7 .word 0x08009ad7 8009864: 08009ad7 .word 0x08009ad7 8009868: 08009ad7 .word 0x08009ad7 800986c: 08009ad7 .word 0x08009ad7 8009870: 08009875 .word 0x08009875 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 8009874: 687b ldr r3, [r7, #4] 8009876: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800987a: 69db ldr r3, [r3, #28] 800987c: 2b00 cmp r3, #0 800987e: d00b beq.n 8009898 { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 8009880: 687b ldr r3, [r7, #4] 8009882: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009886: 69db ldr r3, [r3, #28] 8009888: 687a ldr r2, [r7, #4] 800988a: 7c12 ldrb r2, [r2, #16] 800988c: f107 0108 add.w r1, r7, #8 8009890: 4610 mov r0, r2 8009892: 4798 blx r3 8009894: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009896: e126 b.n 8009ae6 USBD_CtlError(pdev, req); 8009898: 6839 ldr r1, [r7, #0] 800989a: 6878 ldr r0, [r7, #4] 800989c: f000 fb27 bl 8009eee err++; 80098a0: 7afb ldrb r3, [r7, #11] 80098a2: 3301 adds r3, #1 80098a4: 72fb strb r3, [r7, #11] break; 80098a6: e11e b.n 8009ae6 #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 80098a8: 687b ldr r3, [r7, #4] 80098aa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80098ae: 681b ldr r3, [r3, #0] 80098b0: 687a ldr r2, [r7, #4] 80098b2: 7c12 ldrb r2, [r2, #16] 80098b4: f107 0108 add.w r1, r7, #8 80098b8: 4610 mov r0, r2 80098ba: 4798 blx r3 80098bc: 60f8 str r0, [r7, #12] break; 80098be: e112 b.n 8009ae6 case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 80098c0: 687b ldr r3, [r7, #4] 80098c2: 7c1b ldrb r3, [r3, #16] 80098c4: 2b00 cmp r3, #0 80098c6: d10d bne.n 80098e4 pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 80098c8: 687b ldr r3, [r7, #4] 80098ca: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80098ce: 6a9b ldr r3, [r3, #40] @ 0x28 80098d0: f107 0208 add.w r2, r7, #8 80098d4: 4610 mov r0, r2 80098d6: 4798 blx r3 80098d8: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 80098da: 68fb ldr r3, [r7, #12] 80098dc: 3301 adds r3, #1 80098de: 2202 movs r2, #2 80098e0: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 80098e2: e100 b.n 8009ae6 pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 80098e4: 687b ldr r3, [r7, #4] 80098e6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80098ea: 6adb ldr r3, [r3, #44] @ 0x2c 80098ec: f107 0208 add.w r2, r7, #8 80098f0: 4610 mov r0, r2 80098f2: 4798 blx r3 80098f4: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 80098f6: 68fb ldr r3, [r7, #12] 80098f8: 3301 adds r3, #1 80098fa: 2202 movs r2, #2 80098fc: 701a strb r2, [r3, #0] break; 80098fe: e0f2 b.n 8009ae6 case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 8009900: 683b ldr r3, [r7, #0] 8009902: 885b ldrh r3, [r3, #2] 8009904: b2db uxtb r3, r3 8009906: 2b05 cmp r3, #5 8009908: f200 80ac bhi.w 8009a64 800990c: a201 add r2, pc, #4 @ (adr r2, 8009914 ) 800990e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009912: bf00 nop 8009914: 0800992d .word 0x0800992d 8009918: 08009961 .word 0x08009961 800991c: 08009995 .word 0x08009995 8009920: 080099c9 .word 0x080099c9 8009924: 080099fd .word 0x080099fd 8009928: 08009a31 .word 0x08009a31 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 800992c: 687b ldr r3, [r7, #4] 800992e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009932: 685b ldr r3, [r3, #4] 8009934: 2b00 cmp r3, #0 8009936: d00b beq.n 8009950 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 8009938: 687b ldr r3, [r7, #4] 800993a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800993e: 685b ldr r3, [r3, #4] 8009940: 687a ldr r2, [r7, #4] 8009942: 7c12 ldrb r2, [r2, #16] 8009944: f107 0108 add.w r1, r7, #8 8009948: 4610 mov r0, r2 800994a: 4798 blx r3 800994c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800994e: e091 b.n 8009a74 USBD_CtlError(pdev, req); 8009950: 6839 ldr r1, [r7, #0] 8009952: 6878 ldr r0, [r7, #4] 8009954: f000 facb bl 8009eee err++; 8009958: 7afb ldrb r3, [r7, #11] 800995a: 3301 adds r3, #1 800995c: 72fb strb r3, [r7, #11] break; 800995e: e089 b.n 8009a74 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 8009960: 687b ldr r3, [r7, #4] 8009962: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009966: 689b ldr r3, [r3, #8] 8009968: 2b00 cmp r3, #0 800996a: d00b beq.n 8009984 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 800996c: 687b ldr r3, [r7, #4] 800996e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009972: 689b ldr r3, [r3, #8] 8009974: 687a ldr r2, [r7, #4] 8009976: 7c12 ldrb r2, [r2, #16] 8009978: f107 0108 add.w r1, r7, #8 800997c: 4610 mov r0, r2 800997e: 4798 blx r3 8009980: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009982: e077 b.n 8009a74 USBD_CtlError(pdev, req); 8009984: 6839 ldr r1, [r7, #0] 8009986: 6878 ldr r0, [r7, #4] 8009988: f000 fab1 bl 8009eee err++; 800998c: 7afb ldrb r3, [r7, #11] 800998e: 3301 adds r3, #1 8009990: 72fb strb r3, [r7, #11] break; 8009992: e06f b.n 8009a74 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 8009994: 687b ldr r3, [r7, #4] 8009996: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800999a: 68db ldr r3, [r3, #12] 800999c: 2b00 cmp r3, #0 800999e: d00b beq.n 80099b8 { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 80099a0: 687b ldr r3, [r7, #4] 80099a2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099a6: 68db ldr r3, [r3, #12] 80099a8: 687a ldr r2, [r7, #4] 80099aa: 7c12 ldrb r2, [r2, #16] 80099ac: f107 0108 add.w r1, r7, #8 80099b0: 4610 mov r0, r2 80099b2: 4798 blx r3 80099b4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80099b6: e05d b.n 8009a74 USBD_CtlError(pdev, req); 80099b8: 6839 ldr r1, [r7, #0] 80099ba: 6878 ldr r0, [r7, #4] 80099bc: f000 fa97 bl 8009eee err++; 80099c0: 7afb ldrb r3, [r7, #11] 80099c2: 3301 adds r3, #1 80099c4: 72fb strb r3, [r7, #11] break; 80099c6: e055 b.n 8009a74 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 80099c8: 687b ldr r3, [r7, #4] 80099ca: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099ce: 691b ldr r3, [r3, #16] 80099d0: 2b00 cmp r3, #0 80099d2: d00b beq.n 80099ec { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 80099d4: 687b ldr r3, [r7, #4] 80099d6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099da: 691b ldr r3, [r3, #16] 80099dc: 687a ldr r2, [r7, #4] 80099de: 7c12 ldrb r2, [r2, #16] 80099e0: f107 0108 add.w r1, r7, #8 80099e4: 4610 mov r0, r2 80099e6: 4798 blx r3 80099e8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80099ea: e043 b.n 8009a74 USBD_CtlError(pdev, req); 80099ec: 6839 ldr r1, [r7, #0] 80099ee: 6878 ldr r0, [r7, #4] 80099f0: f000 fa7d bl 8009eee err++; 80099f4: 7afb ldrb r3, [r7, #11] 80099f6: 3301 adds r3, #1 80099f8: 72fb strb r3, [r7, #11] break; 80099fa: e03b b.n 8009a74 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 80099fc: 687b ldr r3, [r7, #4] 80099fe: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a02: 695b ldr r3, [r3, #20] 8009a04: 2b00 cmp r3, #0 8009a06: d00b beq.n 8009a20 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 8009a08: 687b ldr r3, [r7, #4] 8009a0a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a0e: 695b ldr r3, [r3, #20] 8009a10: 687a ldr r2, [r7, #4] 8009a12: 7c12 ldrb r2, [r2, #16] 8009a14: f107 0108 add.w r1, r7, #8 8009a18: 4610 mov r0, r2 8009a1a: 4798 blx r3 8009a1c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009a1e: e029 b.n 8009a74 USBD_CtlError(pdev, req); 8009a20: 6839 ldr r1, [r7, #0] 8009a22: 6878 ldr r0, [r7, #4] 8009a24: f000 fa63 bl 8009eee err++; 8009a28: 7afb ldrb r3, [r7, #11] 8009a2a: 3301 adds r3, #1 8009a2c: 72fb strb r3, [r7, #11] break; 8009a2e: e021 b.n 8009a74 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 8009a30: 687b ldr r3, [r7, #4] 8009a32: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a36: 699b ldr r3, [r3, #24] 8009a38: 2b00 cmp r3, #0 8009a3a: d00b beq.n 8009a54 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8009a3c: 687b ldr r3, [r7, #4] 8009a3e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a42: 699b ldr r3, [r3, #24] 8009a44: 687a ldr r2, [r7, #4] 8009a46: 7c12 ldrb r2, [r2, #16] 8009a48: f107 0108 add.w r1, r7, #8 8009a4c: 4610 mov r0, r2 8009a4e: 4798 blx r3 8009a50: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009a52: e00f b.n 8009a74 USBD_CtlError(pdev, req); 8009a54: 6839 ldr r1, [r7, #0] 8009a56: 6878 ldr r0, [r7, #4] 8009a58: f000 fa49 bl 8009eee err++; 8009a5c: 7afb ldrb r3, [r7, #11] 8009a5e: 3301 adds r3, #1 8009a60: 72fb strb r3, [r7, #11] break; 8009a62: e007 b.n 8009a74 err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8009a64: 6839 ldr r1, [r7, #0] 8009a66: 6878 ldr r0, [r7, #4] 8009a68: f000 fa41 bl 8009eee err++; 8009a6c: 7afb ldrb r3, [r7, #11] 8009a6e: 3301 adds r3, #1 8009a70: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 8009a72: bf00 nop } break; 8009a74: e037 b.n 8009ae6 case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009a76: 687b ldr r3, [r7, #4] 8009a78: 7c1b ldrb r3, [r3, #16] 8009a7a: 2b00 cmp r3, #0 8009a7c: d109 bne.n 8009a92 pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 8009a7e: 687b ldr r3, [r7, #4] 8009a80: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009a84: 6b5b ldr r3, [r3, #52] @ 0x34 8009a86: f107 0208 add.w r2, r7, #8 8009a8a: 4610 mov r0, r2 8009a8c: 4798 blx r3 8009a8e: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009a90: e029 b.n 8009ae6 USBD_CtlError(pdev, req); 8009a92: 6839 ldr r1, [r7, #0] 8009a94: 6878 ldr r0, [r7, #4] 8009a96: f000 fa2a bl 8009eee err++; 8009a9a: 7afb ldrb r3, [r7, #11] 8009a9c: 3301 adds r3, #1 8009a9e: 72fb strb r3, [r7, #11] break; 8009aa0: e021 b.n 8009ae6 case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009aa2: 687b ldr r3, [r7, #4] 8009aa4: 7c1b ldrb r3, [r3, #16] 8009aa6: 2b00 cmp r3, #0 8009aa8: d10d bne.n 8009ac6 pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 8009aaa: 687b ldr r3, [r7, #4] 8009aac: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009ab0: 6b1b ldr r3, [r3, #48] @ 0x30 8009ab2: f107 0208 add.w r2, r7, #8 8009ab6: 4610 mov r0, r2 8009ab8: 4798 blx r3 8009aba: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 8009abc: 68fb ldr r3, [r7, #12] 8009abe: 3301 adds r3, #1 8009ac0: 2207 movs r2, #7 8009ac2: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 8009ac4: e00f b.n 8009ae6 USBD_CtlError(pdev, req); 8009ac6: 6839 ldr r1, [r7, #0] 8009ac8: 6878 ldr r0, [r7, #4] 8009aca: f000 fa10 bl 8009eee err++; 8009ace: 7afb ldrb r3, [r7, #11] 8009ad0: 3301 adds r3, #1 8009ad2: 72fb strb r3, [r7, #11] break; 8009ad4: e007 b.n 8009ae6 default: USBD_CtlError(pdev, req); 8009ad6: 6839 ldr r1, [r7, #0] 8009ad8: 6878 ldr r0, [r7, #4] 8009ada: f000 fa08 bl 8009eee err++; 8009ade: 7afb ldrb r3, [r7, #11] 8009ae0: 3301 adds r3, #1 8009ae2: 72fb strb r3, [r7, #11] break; 8009ae4: bf00 nop } if (err != 0U) 8009ae6: 7afb ldrb r3, [r7, #11] 8009ae8: 2b00 cmp r3, #0 8009aea: d11e bne.n 8009b2a { return; } if (req->wLength != 0U) 8009aec: 683b ldr r3, [r7, #0] 8009aee: 88db ldrh r3, [r3, #6] 8009af0: 2b00 cmp r3, #0 8009af2: d016 beq.n 8009b22 { if (len != 0U) 8009af4: 893b ldrh r3, [r7, #8] 8009af6: 2b00 cmp r3, #0 8009af8: d00e beq.n 8009b18 { len = MIN(len, req->wLength); 8009afa: 683b ldr r3, [r7, #0] 8009afc: 88da ldrh r2, [r3, #6] 8009afe: 893b ldrh r3, [r7, #8] 8009b00: 4293 cmp r3, r2 8009b02: bf28 it cs 8009b04: 4613 movcs r3, r2 8009b06: b29b uxth r3, r3 8009b08: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 8009b0a: 893b ldrh r3, [r7, #8] 8009b0c: 461a mov r2, r3 8009b0e: 68f9 ldr r1, [r7, #12] 8009b10: 6878 ldr r0, [r7, #4] 8009b12: f000 fa69 bl 8009fe8 8009b16: e009 b.n 8009b2c } else { USBD_CtlError(pdev, req); 8009b18: 6839 ldr r1, [r7, #0] 8009b1a: 6878 ldr r0, [r7, #4] 8009b1c: f000 f9e7 bl 8009eee 8009b20: e004 b.n 8009b2c } } else { (void)USBD_CtlSendStatus(pdev); 8009b22: 6878 ldr r0, [r7, #4] 8009b24: f000 faa0 bl 800a068 8009b28: e000 b.n 8009b2c return; 8009b2a: bf00 nop } } 8009b2c: 3710 adds r7, #16 8009b2e: 46bd mov sp, r7 8009b30: bd80 pop {r7, pc} 8009b32: bf00 nop 08009b34 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009b34: b580 push {r7, lr} 8009b36: b084 sub sp, #16 8009b38: af00 add r7, sp, #0 8009b3a: 6078 str r0, [r7, #4] 8009b3c: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 8009b3e: 683b ldr r3, [r7, #0] 8009b40: 889b ldrh r3, [r3, #4] 8009b42: 2b00 cmp r3, #0 8009b44: d131 bne.n 8009baa 8009b46: 683b ldr r3, [r7, #0] 8009b48: 88db ldrh r3, [r3, #6] 8009b4a: 2b00 cmp r3, #0 8009b4c: d12d bne.n 8009baa 8009b4e: 683b ldr r3, [r7, #0] 8009b50: 885b ldrh r3, [r3, #2] 8009b52: 2b7f cmp r3, #127 @ 0x7f 8009b54: d829 bhi.n 8009baa { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 8009b56: 683b ldr r3, [r7, #0] 8009b58: 885b ldrh r3, [r3, #2] 8009b5a: b2db uxtb r3, r3 8009b5c: f003 037f and.w r3, r3, #127 @ 0x7f 8009b60: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009b62: 687b ldr r3, [r7, #4] 8009b64: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009b68: b2db uxtb r3, r3 8009b6a: 2b03 cmp r3, #3 8009b6c: d104 bne.n 8009b78 { USBD_CtlError(pdev, req); 8009b6e: 6839 ldr r1, [r7, #0] 8009b70: 6878 ldr r0, [r7, #4] 8009b72: f000 f9bc bl 8009eee if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009b76: e01d b.n 8009bb4 } else { pdev->dev_address = dev_addr; 8009b78: 687b ldr r3, [r7, #4] 8009b7a: 7bfa ldrb r2, [r7, #15] 8009b7c: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 8009b80: 7bfb ldrb r3, [r7, #15] 8009b82: 4619 mov r1, r3 8009b84: 6878 ldr r0, [r7, #4] 8009b86: f000 fe4f bl 800a828 (void)USBD_CtlSendStatus(pdev); 8009b8a: 6878 ldr r0, [r7, #4] 8009b8c: f000 fa6c bl 800a068 if (dev_addr != 0U) 8009b90: 7bfb ldrb r3, [r7, #15] 8009b92: 2b00 cmp r3, #0 8009b94: d004 beq.n 8009ba0 { pdev->dev_state = USBD_STATE_ADDRESSED; 8009b96: 687b ldr r3, [r7, #4] 8009b98: 2202 movs r2, #2 8009b9a: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009b9e: e009 b.n 8009bb4 } else { pdev->dev_state = USBD_STATE_DEFAULT; 8009ba0: 687b ldr r3, [r7, #4] 8009ba2: 2201 movs r2, #1 8009ba4: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009ba8: e004 b.n 8009bb4 } } } else { USBD_CtlError(pdev, req); 8009baa: 6839 ldr r1, [r7, #0] 8009bac: 6878 ldr r0, [r7, #4] 8009bae: f000 f99e bl 8009eee } } 8009bb2: bf00 nop 8009bb4: bf00 nop 8009bb6: 3710 adds r7, #16 8009bb8: 46bd mov sp, r7 8009bba: bd80 pop {r7, pc} 08009bbc : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009bbc: b580 push {r7, lr} 8009bbe: b084 sub sp, #16 8009bc0: af00 add r7, sp, #0 8009bc2: 6078 str r0, [r7, #4] 8009bc4: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009bc6: 2300 movs r3, #0 8009bc8: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 8009bca: 683b ldr r3, [r7, #0] 8009bcc: 885b ldrh r3, [r3, #2] 8009bce: b2da uxtb r2, r3 8009bd0: 4b4e ldr r3, [pc, #312] @ (8009d0c ) 8009bd2: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 8009bd4: 4b4d ldr r3, [pc, #308] @ (8009d0c ) 8009bd6: 781b ldrb r3, [r3, #0] 8009bd8: 2b01 cmp r3, #1 8009bda: d905 bls.n 8009be8 { USBD_CtlError(pdev, req); 8009bdc: 6839 ldr r1, [r7, #0] 8009bde: 6878 ldr r0, [r7, #4] 8009be0: f000 f985 bl 8009eee return USBD_FAIL; 8009be4: 2303 movs r3, #3 8009be6: e08c b.n 8009d02 } switch (pdev->dev_state) 8009be8: 687b ldr r3, [r7, #4] 8009bea: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009bee: b2db uxtb r3, r3 8009bf0: 2b02 cmp r3, #2 8009bf2: d002 beq.n 8009bfa 8009bf4: 2b03 cmp r3, #3 8009bf6: d029 beq.n 8009c4c 8009bf8: e075 b.n 8009ce6 { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 8009bfa: 4b44 ldr r3, [pc, #272] @ (8009d0c ) 8009bfc: 781b ldrb r3, [r3, #0] 8009bfe: 2b00 cmp r3, #0 8009c00: d020 beq.n 8009c44 { pdev->dev_config = cfgidx; 8009c02: 4b42 ldr r3, [pc, #264] @ (8009d0c ) 8009c04: 781b ldrb r3, [r3, #0] 8009c06: 461a mov r2, r3 8009c08: 687b ldr r3, [r7, #4] 8009c0a: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009c0c: 4b3f ldr r3, [pc, #252] @ (8009d0c ) 8009c0e: 781b ldrb r3, [r3, #0] 8009c10: 4619 mov r1, r3 8009c12: 6878 ldr r0, [r7, #4] 8009c14: f7fe ffa3 bl 8008b5e 8009c18: 4603 mov r3, r0 8009c1a: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009c1c: 7bfb ldrb r3, [r7, #15] 8009c1e: 2b00 cmp r3, #0 8009c20: d008 beq.n 8009c34 { USBD_CtlError(pdev, req); 8009c22: 6839 ldr r1, [r7, #0] 8009c24: 6878 ldr r0, [r7, #4] 8009c26: f000 f962 bl 8009eee pdev->dev_state = USBD_STATE_ADDRESSED; 8009c2a: 687b ldr r3, [r7, #4] 8009c2c: 2202 movs r2, #2 8009c2e: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 8009c32: e065 b.n 8009d00 (void)USBD_CtlSendStatus(pdev); 8009c34: 6878 ldr r0, [r7, #4] 8009c36: f000 fa17 bl 800a068 pdev->dev_state = USBD_STATE_CONFIGURED; 8009c3a: 687b ldr r3, [r7, #4] 8009c3c: 2203 movs r2, #3 8009c3e: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009c42: e05d b.n 8009d00 (void)USBD_CtlSendStatus(pdev); 8009c44: 6878 ldr r0, [r7, #4] 8009c46: f000 fa0f bl 800a068 break; 8009c4a: e059 b.n 8009d00 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8009c4c: 4b2f ldr r3, [pc, #188] @ (8009d0c ) 8009c4e: 781b ldrb r3, [r3, #0] 8009c50: 2b00 cmp r3, #0 8009c52: d112 bne.n 8009c7a { pdev->dev_state = USBD_STATE_ADDRESSED; 8009c54: 687b ldr r3, [r7, #4] 8009c56: 2202 movs r2, #2 8009c58: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 8009c5c: 4b2b ldr r3, [pc, #172] @ (8009d0c ) 8009c5e: 781b ldrb r3, [r3, #0] 8009c60: 461a mov r2, r3 8009c62: 687b ldr r3, [r7, #4] 8009c64: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 8009c66: 4b29 ldr r3, [pc, #164] @ (8009d0c ) 8009c68: 781b ldrb r3, [r3, #0] 8009c6a: 4619 mov r1, r3 8009c6c: 6878 ldr r0, [r7, #4] 8009c6e: f7fe ff92 bl 8008b96 (void)USBD_CtlSendStatus(pdev); 8009c72: 6878 ldr r0, [r7, #4] 8009c74: f000 f9f8 bl 800a068 } else { (void)USBD_CtlSendStatus(pdev); } break; 8009c78: e042 b.n 8009d00 else if (cfgidx != pdev->dev_config) 8009c7a: 4b24 ldr r3, [pc, #144] @ (8009d0c ) 8009c7c: 781b ldrb r3, [r3, #0] 8009c7e: 461a mov r2, r3 8009c80: 687b ldr r3, [r7, #4] 8009c82: 685b ldr r3, [r3, #4] 8009c84: 429a cmp r2, r3 8009c86: d02a beq.n 8009cde (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009c88: 687b ldr r3, [r7, #4] 8009c8a: 685b ldr r3, [r3, #4] 8009c8c: b2db uxtb r3, r3 8009c8e: 4619 mov r1, r3 8009c90: 6878 ldr r0, [r7, #4] 8009c92: f7fe ff80 bl 8008b96 pdev->dev_config = cfgidx; 8009c96: 4b1d ldr r3, [pc, #116] @ (8009d0c ) 8009c98: 781b ldrb r3, [r3, #0] 8009c9a: 461a mov r2, r3 8009c9c: 687b ldr r3, [r7, #4] 8009c9e: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009ca0: 4b1a ldr r3, [pc, #104] @ (8009d0c ) 8009ca2: 781b ldrb r3, [r3, #0] 8009ca4: 4619 mov r1, r3 8009ca6: 6878 ldr r0, [r7, #4] 8009ca8: f7fe ff59 bl 8008b5e 8009cac: 4603 mov r3, r0 8009cae: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009cb0: 7bfb ldrb r3, [r7, #15] 8009cb2: 2b00 cmp r3, #0 8009cb4: d00f beq.n 8009cd6 USBD_CtlError(pdev, req); 8009cb6: 6839 ldr r1, [r7, #0] 8009cb8: 6878 ldr r0, [r7, #4] 8009cba: f000 f918 bl 8009eee (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009cbe: 687b ldr r3, [r7, #4] 8009cc0: 685b ldr r3, [r3, #4] 8009cc2: b2db uxtb r3, r3 8009cc4: 4619 mov r1, r3 8009cc6: 6878 ldr r0, [r7, #4] 8009cc8: f7fe ff65 bl 8008b96 pdev->dev_state = USBD_STATE_ADDRESSED; 8009ccc: 687b ldr r3, [r7, #4] 8009cce: 2202 movs r2, #2 8009cd0: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009cd4: e014 b.n 8009d00 (void)USBD_CtlSendStatus(pdev); 8009cd6: 6878 ldr r0, [r7, #4] 8009cd8: f000 f9c6 bl 800a068 break; 8009cdc: e010 b.n 8009d00 (void)USBD_CtlSendStatus(pdev); 8009cde: 6878 ldr r0, [r7, #4] 8009ce0: f000 f9c2 bl 800a068 break; 8009ce4: e00c b.n 8009d00 default: USBD_CtlError(pdev, req); 8009ce6: 6839 ldr r1, [r7, #0] 8009ce8: 6878 ldr r0, [r7, #4] 8009cea: f000 f900 bl 8009eee (void)USBD_ClrClassConfig(pdev, cfgidx); 8009cee: 4b07 ldr r3, [pc, #28] @ (8009d0c ) 8009cf0: 781b ldrb r3, [r3, #0] 8009cf2: 4619 mov r1, r3 8009cf4: 6878 ldr r0, [r7, #4] 8009cf6: f7fe ff4e bl 8008b96 ret = USBD_FAIL; 8009cfa: 2303 movs r3, #3 8009cfc: 73fb strb r3, [r7, #15] break; 8009cfe: bf00 nop } return ret; 8009d00: 7bfb ldrb r3, [r7, #15] } 8009d02: 4618 mov r0, r3 8009d04: 3710 adds r7, #16 8009d06: 46bd mov sp, r7 8009d08: bd80 pop {r7, pc} 8009d0a: bf00 nop 8009d0c: 20000730 .word 0x20000730 08009d10 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009d10: b580 push {r7, lr} 8009d12: b082 sub sp, #8 8009d14: af00 add r7, sp, #0 8009d16: 6078 str r0, [r7, #4] 8009d18: 6039 str r1, [r7, #0] if (req->wLength != 1U) 8009d1a: 683b ldr r3, [r7, #0] 8009d1c: 88db ldrh r3, [r3, #6] 8009d1e: 2b01 cmp r3, #1 8009d20: d004 beq.n 8009d2c { USBD_CtlError(pdev, req); 8009d22: 6839 ldr r1, [r7, #0] 8009d24: 6878 ldr r0, [r7, #4] 8009d26: f000 f8e2 bl 8009eee default: USBD_CtlError(pdev, req); break; } } } 8009d2a: e023 b.n 8009d74 switch (pdev->dev_state) 8009d2c: 687b ldr r3, [r7, #4] 8009d2e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d32: b2db uxtb r3, r3 8009d34: 2b02 cmp r3, #2 8009d36: dc02 bgt.n 8009d3e 8009d38: 2b00 cmp r3, #0 8009d3a: dc03 bgt.n 8009d44 8009d3c: e015 b.n 8009d6a 8009d3e: 2b03 cmp r3, #3 8009d40: d00b beq.n 8009d5a 8009d42: e012 b.n 8009d6a pdev->dev_default_config = 0U; 8009d44: 687b ldr r3, [r7, #4] 8009d46: 2200 movs r2, #0 8009d48: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 8009d4a: 687b ldr r3, [r7, #4] 8009d4c: 3308 adds r3, #8 8009d4e: 2201 movs r2, #1 8009d50: 4619 mov r1, r3 8009d52: 6878 ldr r0, [r7, #4] 8009d54: f000 f948 bl 8009fe8 break; 8009d58: e00c b.n 8009d74 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 8009d5a: 687b ldr r3, [r7, #4] 8009d5c: 3304 adds r3, #4 8009d5e: 2201 movs r2, #1 8009d60: 4619 mov r1, r3 8009d62: 6878 ldr r0, [r7, #4] 8009d64: f000 f940 bl 8009fe8 break; 8009d68: e004 b.n 8009d74 USBD_CtlError(pdev, req); 8009d6a: 6839 ldr r1, [r7, #0] 8009d6c: 6878 ldr r0, [r7, #4] 8009d6e: f000 f8be bl 8009eee break; 8009d72: bf00 nop } 8009d74: bf00 nop 8009d76: 3708 adds r7, #8 8009d78: 46bd mov sp, r7 8009d7a: bd80 pop {r7, pc} 08009d7c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009d7c: b580 push {r7, lr} 8009d7e: b082 sub sp, #8 8009d80: af00 add r7, sp, #0 8009d82: 6078 str r0, [r7, #4] 8009d84: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009d86: 687b ldr r3, [r7, #4] 8009d88: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d8c: b2db uxtb r3, r3 8009d8e: 3b01 subs r3, #1 8009d90: 2b02 cmp r3, #2 8009d92: d81e bhi.n 8009dd2 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 8009d94: 683b ldr r3, [r7, #0] 8009d96: 88db ldrh r3, [r3, #6] 8009d98: 2b02 cmp r3, #2 8009d9a: d004 beq.n 8009da6 { USBD_CtlError(pdev, req); 8009d9c: 6839 ldr r1, [r7, #0] 8009d9e: 6878 ldr r0, [r7, #4] 8009da0: f000 f8a5 bl 8009eee break; 8009da4: e01a b.n 8009ddc } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 8009da6: 687b ldr r3, [r7, #4] 8009da8: 2201 movs r2, #1 8009daa: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 8009dac: 687b ldr r3, [r7, #4] 8009dae: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 8009db2: 2b00 cmp r3, #0 8009db4: d005 beq.n 8009dc2 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 8009db6: 687b ldr r3, [r7, #4] 8009db8: 68db ldr r3, [r3, #12] 8009dba: f043 0202 orr.w r2, r3, #2 8009dbe: 687b ldr r3, [r7, #4] 8009dc0: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 8009dc2: 687b ldr r3, [r7, #4] 8009dc4: 330c adds r3, #12 8009dc6: 2202 movs r2, #2 8009dc8: 4619 mov r1, r3 8009dca: 6878 ldr r0, [r7, #4] 8009dcc: f000 f90c bl 8009fe8 break; 8009dd0: e004 b.n 8009ddc default: USBD_CtlError(pdev, req); 8009dd2: 6839 ldr r1, [r7, #0] 8009dd4: 6878 ldr r0, [r7, #4] 8009dd6: f000 f88a bl 8009eee break; 8009dda: bf00 nop } } 8009ddc: bf00 nop 8009dde: 3708 adds r7, #8 8009de0: 46bd mov sp, r7 8009de2: bd80 pop {r7, pc} 08009de4 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009de4: b580 push {r7, lr} 8009de6: b082 sub sp, #8 8009de8: af00 add r7, sp, #0 8009dea: 6078 str r0, [r7, #4] 8009dec: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009dee: 683b ldr r3, [r7, #0] 8009df0: 885b ldrh r3, [r3, #2] 8009df2: 2b01 cmp r3, #1 8009df4: d107 bne.n 8009e06 { pdev->dev_remote_wakeup = 1U; 8009df6: 687b ldr r3, [r7, #4] 8009df8: 2201 movs r2, #1 8009dfa: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009dfe: 6878 ldr r0, [r7, #4] 8009e00: f000 f932 bl 800a068 } else { USBD_CtlError(pdev, req); } } 8009e04: e013 b.n 8009e2e else if (req->wValue == USB_FEATURE_TEST_MODE) 8009e06: 683b ldr r3, [r7, #0] 8009e08: 885b ldrh r3, [r3, #2] 8009e0a: 2b02 cmp r3, #2 8009e0c: d10b bne.n 8009e26 pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 8009e0e: 683b ldr r3, [r7, #0] 8009e10: 889b ldrh r3, [r3, #4] 8009e12: 0a1b lsrs r3, r3, #8 8009e14: b29b uxth r3, r3 8009e16: b2da uxtb r2, r3 8009e18: 687b ldr r3, [r7, #4] 8009e1a: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 8009e1e: 6878 ldr r0, [r7, #4] 8009e20: f000 f922 bl 800a068 } 8009e24: e003 b.n 8009e2e USBD_CtlError(pdev, req); 8009e26: 6839 ldr r1, [r7, #0] 8009e28: 6878 ldr r0, [r7, #4] 8009e2a: f000 f860 bl 8009eee } 8009e2e: bf00 nop 8009e30: 3708 adds r7, #8 8009e32: 46bd mov sp, r7 8009e34: bd80 pop {r7, pc} 08009e36 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009e36: b580 push {r7, lr} 8009e38: b082 sub sp, #8 8009e3a: af00 add r7, sp, #0 8009e3c: 6078 str r0, [r7, #4] 8009e3e: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009e40: 687b ldr r3, [r7, #4] 8009e42: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009e46: b2db uxtb r3, r3 8009e48: 3b01 subs r3, #1 8009e4a: 2b02 cmp r3, #2 8009e4c: d80b bhi.n 8009e66 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009e4e: 683b ldr r3, [r7, #0] 8009e50: 885b ldrh r3, [r3, #2] 8009e52: 2b01 cmp r3, #1 8009e54: d10c bne.n 8009e70 { pdev->dev_remote_wakeup = 0U; 8009e56: 687b ldr r3, [r7, #4] 8009e58: 2200 movs r2, #0 8009e5a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009e5e: 6878 ldr r0, [r7, #4] 8009e60: f000 f902 bl 800a068 } break; 8009e64: e004 b.n 8009e70 default: USBD_CtlError(pdev, req); 8009e66: 6839 ldr r1, [r7, #0] 8009e68: 6878 ldr r0, [r7, #4] 8009e6a: f000 f840 bl 8009eee break; 8009e6e: e000 b.n 8009e72 break; 8009e70: bf00 nop } } 8009e72: bf00 nop 8009e74: 3708 adds r7, #8 8009e76: 46bd mov sp, r7 8009e78: bd80 pop {r7, pc} 08009e7a : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 8009e7a: b580 push {r7, lr} 8009e7c: b084 sub sp, #16 8009e7e: af00 add r7, sp, #0 8009e80: 6078 str r0, [r7, #4] 8009e82: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 8009e84: 683b ldr r3, [r7, #0] 8009e86: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 8009e88: 68fb ldr r3, [r7, #12] 8009e8a: 781a ldrb r2, [r3, #0] 8009e8c: 687b ldr r3, [r7, #4] 8009e8e: 701a strb r2, [r3, #0] pbuff++; 8009e90: 68fb ldr r3, [r7, #12] 8009e92: 3301 adds r3, #1 8009e94: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 8009e96: 68fb ldr r3, [r7, #12] 8009e98: 781a ldrb r2, [r3, #0] 8009e9a: 687b ldr r3, [r7, #4] 8009e9c: 705a strb r2, [r3, #1] pbuff++; 8009e9e: 68fb ldr r3, [r7, #12] 8009ea0: 3301 adds r3, #1 8009ea2: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 8009ea4: 68f8 ldr r0, [r7, #12] 8009ea6: f7ff fa13 bl 80092d0 8009eaa: 4603 mov r3, r0 8009eac: 461a mov r2, r3 8009eae: 687b ldr r3, [r7, #4] 8009eb0: 805a strh r2, [r3, #2] pbuff++; 8009eb2: 68fb ldr r3, [r7, #12] 8009eb4: 3301 adds r3, #1 8009eb6: 60fb str r3, [r7, #12] pbuff++; 8009eb8: 68fb ldr r3, [r7, #12] 8009eba: 3301 adds r3, #1 8009ebc: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 8009ebe: 68f8 ldr r0, [r7, #12] 8009ec0: f7ff fa06 bl 80092d0 8009ec4: 4603 mov r3, r0 8009ec6: 461a mov r2, r3 8009ec8: 687b ldr r3, [r7, #4] 8009eca: 809a strh r2, [r3, #4] pbuff++; 8009ecc: 68fb ldr r3, [r7, #12] 8009ece: 3301 adds r3, #1 8009ed0: 60fb str r3, [r7, #12] pbuff++; 8009ed2: 68fb ldr r3, [r7, #12] 8009ed4: 3301 adds r3, #1 8009ed6: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 8009ed8: 68f8 ldr r0, [r7, #12] 8009eda: f7ff f9f9 bl 80092d0 8009ede: 4603 mov r3, r0 8009ee0: 461a mov r2, r3 8009ee2: 687b ldr r3, [r7, #4] 8009ee4: 80da strh r2, [r3, #6] } 8009ee6: bf00 nop 8009ee8: 3710 adds r7, #16 8009eea: 46bd mov sp, r7 8009eec: bd80 pop {r7, pc} 08009eee : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009eee: b580 push {r7, lr} 8009ef0: b082 sub sp, #8 8009ef2: af00 add r7, sp, #0 8009ef4: 6078 str r0, [r7, #4] 8009ef6: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 8009ef8: 2180 movs r1, #128 @ 0x80 8009efa: 6878 ldr r0, [r7, #4] 8009efc: f000 fc2a bl 800a754 (void)USBD_LL_StallEP(pdev, 0U); 8009f00: 2100 movs r1, #0 8009f02: 6878 ldr r0, [r7, #4] 8009f04: f000 fc26 bl 800a754 } 8009f08: bf00 nop 8009f0a: 3708 adds r7, #8 8009f0c: 46bd mov sp, r7 8009f0e: bd80 pop {r7, pc} 08009f10 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8009f10: b580 push {r7, lr} 8009f12: b086 sub sp, #24 8009f14: af00 add r7, sp, #0 8009f16: 60f8 str r0, [r7, #12] 8009f18: 60b9 str r1, [r7, #8] 8009f1a: 607a str r2, [r7, #4] uint8_t idx = 0U; 8009f1c: 2300 movs r3, #0 8009f1e: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8009f20: 68fb ldr r3, [r7, #12] 8009f22: 2b00 cmp r3, #0 8009f24: d042 beq.n 8009fac { return; } pdesc = desc; 8009f26: 68fb ldr r3, [r7, #12] 8009f28: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 8009f2a: 6938 ldr r0, [r7, #16] 8009f2c: f000 f842 bl 8009fb4 8009f30: 4603 mov r3, r0 8009f32: 3301 adds r3, #1 8009f34: 005b lsls r3, r3, #1 8009f36: f5b3 7f00 cmp.w r3, #512 @ 0x200 8009f3a: d808 bhi.n 8009f4e 8009f3c: 6938 ldr r0, [r7, #16] 8009f3e: f000 f839 bl 8009fb4 8009f42: 4603 mov r3, r0 8009f44: 3301 adds r3, #1 8009f46: b29b uxth r3, r3 8009f48: 005b lsls r3, r3, #1 8009f4a: b29a uxth r2, r3 8009f4c: e001 b.n 8009f52 8009f4e: f44f 7200 mov.w r2, #512 @ 0x200 8009f52: 687b ldr r3, [r7, #4] 8009f54: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 8009f56: 7dfb ldrb r3, [r7, #23] 8009f58: 68ba ldr r2, [r7, #8] 8009f5a: 4413 add r3, r2 8009f5c: 687a ldr r2, [r7, #4] 8009f5e: 7812 ldrb r2, [r2, #0] 8009f60: 701a strb r2, [r3, #0] idx++; 8009f62: 7dfb ldrb r3, [r7, #23] 8009f64: 3301 adds r3, #1 8009f66: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 8009f68: 7dfb ldrb r3, [r7, #23] 8009f6a: 68ba ldr r2, [r7, #8] 8009f6c: 4413 add r3, r2 8009f6e: 2203 movs r2, #3 8009f70: 701a strb r2, [r3, #0] idx++; 8009f72: 7dfb ldrb r3, [r7, #23] 8009f74: 3301 adds r3, #1 8009f76: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8009f78: e013 b.n 8009fa2 { unicode[idx] = *pdesc; 8009f7a: 7dfb ldrb r3, [r7, #23] 8009f7c: 68ba ldr r2, [r7, #8] 8009f7e: 4413 add r3, r2 8009f80: 693a ldr r2, [r7, #16] 8009f82: 7812 ldrb r2, [r2, #0] 8009f84: 701a strb r2, [r3, #0] pdesc++; 8009f86: 693b ldr r3, [r7, #16] 8009f88: 3301 adds r3, #1 8009f8a: 613b str r3, [r7, #16] idx++; 8009f8c: 7dfb ldrb r3, [r7, #23] 8009f8e: 3301 adds r3, #1 8009f90: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 8009f92: 7dfb ldrb r3, [r7, #23] 8009f94: 68ba ldr r2, [r7, #8] 8009f96: 4413 add r3, r2 8009f98: 2200 movs r2, #0 8009f9a: 701a strb r2, [r3, #0] idx++; 8009f9c: 7dfb ldrb r3, [r7, #23] 8009f9e: 3301 adds r3, #1 8009fa0: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8009fa2: 693b ldr r3, [r7, #16] 8009fa4: 781b ldrb r3, [r3, #0] 8009fa6: 2b00 cmp r3, #0 8009fa8: d1e7 bne.n 8009f7a 8009faa: e000 b.n 8009fae return; 8009fac: bf00 nop } } 8009fae: 3718 adds r7, #24 8009fb0: 46bd mov sp, r7 8009fb2: bd80 pop {r7, pc} 08009fb4 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 8009fb4: b480 push {r7} 8009fb6: b085 sub sp, #20 8009fb8: af00 add r7, sp, #0 8009fba: 6078 str r0, [r7, #4] uint8_t len = 0U; 8009fbc: 2300 movs r3, #0 8009fbe: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 8009fc0: 687b ldr r3, [r7, #4] 8009fc2: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8009fc4: e005 b.n 8009fd2 { len++; 8009fc6: 7bfb ldrb r3, [r7, #15] 8009fc8: 3301 adds r3, #1 8009fca: 73fb strb r3, [r7, #15] pbuff++; 8009fcc: 68bb ldr r3, [r7, #8] 8009fce: 3301 adds r3, #1 8009fd0: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8009fd2: 68bb ldr r3, [r7, #8] 8009fd4: 781b ldrb r3, [r3, #0] 8009fd6: 2b00 cmp r3, #0 8009fd8: d1f5 bne.n 8009fc6 } return len; 8009fda: 7bfb ldrb r3, [r7, #15] } 8009fdc: 4618 mov r0, r3 8009fde: 3714 adds r7, #20 8009fe0: 46bd mov sp, r7 8009fe2: f85d 7b04 ldr.w r7, [sp], #4 8009fe6: 4770 bx lr 08009fe8 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8009fe8: b580 push {r7, lr} 8009fea: b084 sub sp, #16 8009fec: af00 add r7, sp, #0 8009fee: 60f8 str r0, [r7, #12] 8009ff0: 60b9 str r1, [r7, #8] 8009ff2: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 8009ff4: 68fb ldr r3, [r7, #12] 8009ff6: 2202 movs r2, #2 8009ff8: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 8009ffc: 68fb ldr r3, [r7, #12] 8009ffe: 687a ldr r2, [r7, #4] 800a000: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 800a002: 68fb ldr r3, [r7, #12] 800a004: 68ba ldr r2, [r7, #8] 800a006: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 800a008: 68fb ldr r3, [r7, #12] 800a00a: 687a ldr r2, [r7, #4] 800a00c: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a00e: 687b ldr r3, [r7, #4] 800a010: 68ba ldr r2, [r7, #8] 800a012: 2100 movs r1, #0 800a014: 68f8 ldr r0, [r7, #12] 800a016: f000 fc26 bl 800a866 return USBD_OK; 800a01a: 2300 movs r3, #0 } 800a01c: 4618 mov r0, r3 800a01e: 3710 adds r7, #16 800a020: 46bd mov sp, r7 800a022: bd80 pop {r7, pc} 0800a024 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a024: b580 push {r7, lr} 800a026: b084 sub sp, #16 800a028: af00 add r7, sp, #0 800a02a: 60f8 str r0, [r7, #12] 800a02c: 60b9 str r1, [r7, #8] 800a02e: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a030: 687b ldr r3, [r7, #4] 800a032: 68ba ldr r2, [r7, #8] 800a034: 2100 movs r1, #0 800a036: 68f8 ldr r0, [r7, #12] 800a038: f000 fc15 bl 800a866 return USBD_OK; 800a03c: 2300 movs r3, #0 } 800a03e: 4618 mov r0, r3 800a040: 3710 adds r7, #16 800a042: 46bd mov sp, r7 800a044: bd80 pop {r7, pc} 0800a046 : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a046: b580 push {r7, lr} 800a048: b084 sub sp, #16 800a04a: af00 add r7, sp, #0 800a04c: 60f8 str r0, [r7, #12] 800a04e: 60b9 str r1, [r7, #8] 800a050: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800a052: 687b ldr r3, [r7, #4] 800a054: 68ba ldr r2, [r7, #8] 800a056: 2100 movs r1, #0 800a058: 68f8 ldr r0, [r7, #12] 800a05a: f000 fc25 bl 800a8a8 return USBD_OK; 800a05e: 2300 movs r3, #0 } 800a060: 4618 mov r0, r3 800a062: 3710 adds r7, #16 800a064: 46bd mov sp, r7 800a066: bd80 pop {r7, pc} 0800a068 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 800a068: b580 push {r7, lr} 800a06a: b082 sub sp, #8 800a06c: af00 add r7, sp, #0 800a06e: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 800a070: 687b ldr r3, [r7, #4] 800a072: 2204 movs r2, #4 800a074: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 800a078: 2300 movs r3, #0 800a07a: 2200 movs r2, #0 800a07c: 2100 movs r1, #0 800a07e: 6878 ldr r0, [r7, #4] 800a080: f000 fbf1 bl 800a866 return USBD_OK; 800a084: 2300 movs r3, #0 } 800a086: 4618 mov r0, r3 800a088: 3708 adds r7, #8 800a08a: 46bd mov sp, r7 800a08c: bd80 pop {r7, pc} 0800a08e : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 800a08e: b580 push {r7, lr} 800a090: b082 sub sp, #8 800a092: af00 add r7, sp, #0 800a094: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 800a096: 687b ldr r3, [r7, #4] 800a098: 2205 movs r2, #5 800a09a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800a09e: 2300 movs r3, #0 800a0a0: 2200 movs r2, #0 800a0a2: 2100 movs r1, #0 800a0a4: 6878 ldr r0, [r7, #4] 800a0a6: f000 fbff bl 800a8a8 return USBD_OK; 800a0aa: 2300 movs r3, #0 } 800a0ac: 4618 mov r0, r3 800a0ae: 3708 adds r7, #8 800a0b0: 46bd mov sp, r7 800a0b2: bd80 pop {r7, pc} 0800a0b4 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 800a0b4: b580 push {r7, lr} 800a0b6: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 800a0b8: 2200 movs r2, #0 800a0ba: 490e ldr r1, [pc, #56] @ (800a0f4 ) 800a0bc: 480e ldr r0, [pc, #56] @ (800a0f8 ) 800a0be: f7fe fcd1 bl 8008a64 800a0c2: 4603 mov r3, r0 800a0c4: 2b00 cmp r3, #0 800a0c6: d001 beq.n 800a0cc { Error_Handler(); 800a0c8: f7f6 feec bl 8000ea4 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) 800a0cc: 490b ldr r1, [pc, #44] @ (800a0fc ) 800a0ce: 480a ldr r0, [pc, #40] @ (800a0f8 ) 800a0d0: f7fe fcf8 bl 8008ac4 800a0d4: 4603 mov r3, r0 800a0d6: 2b00 cmp r3, #0 800a0d8: d001 beq.n 800a0de { Error_Handler(); 800a0da: f7f6 fee3 bl 8000ea4 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 800a0de: 4806 ldr r0, [pc, #24] @ (800a0f8 ) 800a0e0: f7fe fd26 bl 8008b30 800a0e4: 4603 mov r3, r0 800a0e6: 2b00 cmp r3, #0 800a0e8: d001 beq.n 800a0ee { Error_Handler(); 800a0ea: f7f6 fedb bl 8000ea4 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 800a0ee: bf00 nop 800a0f0: bd80 pop {r7, pc} 800a0f2: bf00 nop 800a0f4: 20000140 .word 0x20000140 800a0f8: 20000734 .word 0x20000734 800a0fc: 2000009c .word 0x2000009c 0800a100 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a100: b480 push {r7} 800a102: b083 sub sp, #12 800a104: af00 add r7, sp, #0 800a106: 4603 mov r3, r0 800a108: 6039 str r1, [r7, #0] 800a10a: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 800a10c: 683b ldr r3, [r7, #0] 800a10e: 2212 movs r2, #18 800a110: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 800a112: 4b03 ldr r3, [pc, #12] @ (800a120 ) } 800a114: 4618 mov r0, r3 800a116: 370c adds r7, #12 800a118: 46bd mov sp, r7 800a11a: f85d 7b04 ldr.w r7, [sp], #4 800a11e: 4770 bx lr 800a120: 20000160 .word 0x20000160 0800a124 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a124: b480 push {r7} 800a126: b083 sub sp, #12 800a128: af00 add r7, sp, #0 800a12a: 4603 mov r3, r0 800a12c: 6039 str r1, [r7, #0] 800a12e: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 800a130: 683b ldr r3, [r7, #0] 800a132: 2204 movs r2, #4 800a134: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800a136: 4b03 ldr r3, [pc, #12] @ (800a144 ) } 800a138: 4618 mov r0, r3 800a13a: 370c adds r7, #12 800a13c: 46bd mov sp, r7 800a13e: f85d 7b04 ldr.w r7, [sp], #4 800a142: 4770 bx lr 800a144: 20000180 .word 0x20000180 0800a148 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a148: b580 push {r7, lr} 800a14a: b082 sub sp, #8 800a14c: af00 add r7, sp, #0 800a14e: 4603 mov r3, r0 800a150: 6039 str r1, [r7, #0] 800a152: 71fb strb r3, [r7, #7] if(speed == 0) 800a154: 79fb ldrb r3, [r7, #7] 800a156: 2b00 cmp r3, #0 800a158: d105 bne.n 800a166 { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a15a: 683a ldr r2, [r7, #0] 800a15c: 4907 ldr r1, [pc, #28] @ (800a17c ) 800a15e: 4808 ldr r0, [pc, #32] @ (800a180 ) 800a160: f7ff fed6 bl 8009f10 800a164: e004 b.n 800a170 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a166: 683a ldr r2, [r7, #0] 800a168: 4904 ldr r1, [pc, #16] @ (800a17c ) 800a16a: 4805 ldr r0, [pc, #20] @ (800a180 ) 800a16c: f7ff fed0 bl 8009f10 } return USBD_StrDesc; 800a170: 4b02 ldr r3, [pc, #8] @ (800a17c ) } 800a172: 4618 mov r0, r3 800a174: 3708 adds r7, #8 800a176: 46bd mov sp, r7 800a178: bd80 pop {r7, pc} 800a17a: bf00 nop 800a17c: 20000a10 .word 0x20000a10 800a180: 0800aa80 .word 0x0800aa80 0800a184 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a184: b580 push {r7, lr} 800a186: b082 sub sp, #8 800a188: af00 add r7, sp, #0 800a18a: 4603 mov r3, r0 800a18c: 6039 str r1, [r7, #0] 800a18e: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800a190: 683a ldr r2, [r7, #0] 800a192: 4904 ldr r1, [pc, #16] @ (800a1a4 ) 800a194: 4804 ldr r0, [pc, #16] @ (800a1a8 ) 800a196: f7ff febb bl 8009f10 return USBD_StrDesc; 800a19a: 4b02 ldr r3, [pc, #8] @ (800a1a4 ) } 800a19c: 4618 mov r0, r3 800a19e: 3708 adds r7, #8 800a1a0: 46bd mov sp, r7 800a1a2: bd80 pop {r7, pc} 800a1a4: 20000a10 .word 0x20000a10 800a1a8: 0800aa94 .word 0x0800aa94 0800a1ac : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a1ac: b580 push {r7, lr} 800a1ae: b082 sub sp, #8 800a1b0: af00 add r7, sp, #0 800a1b2: 4603 mov r3, r0 800a1b4: 6039 str r1, [r7, #0] 800a1b6: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800a1b8: 683b ldr r3, [r7, #0] 800a1ba: 221a movs r2, #26 800a1bc: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800a1be: f000 f855 bl 800a26c /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800a1c2: 4b02 ldr r3, [pc, #8] @ (800a1cc ) } 800a1c4: 4618 mov r0, r3 800a1c6: 3708 adds r7, #8 800a1c8: 46bd mov sp, r7 800a1ca: bd80 pop {r7, pc} 800a1cc: 20000184 .word 0x20000184 0800a1d0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a1d0: b580 push {r7, lr} 800a1d2: b082 sub sp, #8 800a1d4: af00 add r7, sp, #0 800a1d6: 4603 mov r3, r0 800a1d8: 6039 str r1, [r7, #0] 800a1da: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 800a1dc: 79fb ldrb r3, [r7, #7] 800a1de: 2b00 cmp r3, #0 800a1e0: d105 bne.n 800a1ee { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a1e2: 683a ldr r2, [r7, #0] 800a1e4: 4907 ldr r1, [pc, #28] @ (800a204 ) 800a1e6: 4808 ldr r0, [pc, #32] @ (800a208 ) 800a1e8: f7ff fe92 bl 8009f10 800a1ec: e004 b.n 800a1f8 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a1ee: 683a ldr r2, [r7, #0] 800a1f0: 4904 ldr r1, [pc, #16] @ (800a204 ) 800a1f2: 4805 ldr r0, [pc, #20] @ (800a208 ) 800a1f4: f7ff fe8c bl 8009f10 } return USBD_StrDesc; 800a1f8: 4b02 ldr r3, [pc, #8] @ (800a204 ) } 800a1fa: 4618 mov r0, r3 800a1fc: 3708 adds r7, #8 800a1fe: 46bd mov sp, r7 800a200: bd80 pop {r7, pc} 800a202: bf00 nop 800a204: 20000a10 .word 0x20000a10 800a208: 0800aaa0 .word 0x0800aaa0 0800a20c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a20c: b580 push {r7, lr} 800a20e: b082 sub sp, #8 800a210: af00 add r7, sp, #0 800a212: 4603 mov r3, r0 800a214: 6039 str r1, [r7, #0] 800a216: 71fb strb r3, [r7, #7] if(speed == 0) 800a218: 79fb ldrb r3, [r7, #7] 800a21a: 2b00 cmp r3, #0 800a21c: d105 bne.n 800a22a { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a21e: 683a ldr r2, [r7, #0] 800a220: 4907 ldr r1, [pc, #28] @ (800a240 ) 800a222: 4808 ldr r0, [pc, #32] @ (800a244 ) 800a224: f7ff fe74 bl 8009f10 800a228: e004 b.n 800a234 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a22a: 683a ldr r2, [r7, #0] 800a22c: 4904 ldr r1, [pc, #16] @ (800a240 ) 800a22e: 4805 ldr r0, [pc, #20] @ (800a244 ) 800a230: f7ff fe6e bl 8009f10 } return USBD_StrDesc; 800a234: 4b02 ldr r3, [pc, #8] @ (800a240 ) } 800a236: 4618 mov r0, r3 800a238: 3708 adds r7, #8 800a23a: 46bd mov sp, r7 800a23c: bd80 pop {r7, pc} 800a23e: bf00 nop 800a240: 20000a10 .word 0x20000a10 800a244: 0800aaac .word 0x0800aaac 0800a248 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a248: b480 push {r7} 800a24a: b083 sub sp, #12 800a24c: af00 add r7, sp, #0 800a24e: 4603 mov r3, r0 800a250: 6039 str r1, [r7, #0] 800a252: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 800a254: 683b ldr r3, [r7, #0] 800a256: 220c movs r2, #12 800a258: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 800a25a: 4b03 ldr r3, [pc, #12] @ (800a268 ) } 800a25c: 4618 mov r0, r3 800a25e: 370c adds r7, #12 800a260: 46bd mov sp, r7 800a262: f85d 7b04 ldr.w r7, [sp], #4 800a266: 4770 bx lr 800a268: 20000174 .word 0x20000174 0800a26c : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800a26c: b580 push {r7, lr} 800a26e: b084 sub sp, #16 800a270: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 800a272: 4b0f ldr r3, [pc, #60] @ (800a2b0 ) 800a274: 681b ldr r3, [r3, #0] 800a276: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800a278: 4b0e ldr r3, [pc, #56] @ (800a2b4 ) 800a27a: 681b ldr r3, [r3, #0] 800a27c: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800a27e: 4b0e ldr r3, [pc, #56] @ (800a2b8 ) 800a280: 681b ldr r3, [r3, #0] 800a282: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 800a284: 68fa ldr r2, [r7, #12] 800a286: 687b ldr r3, [r7, #4] 800a288: 4413 add r3, r2 800a28a: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 800a28c: 68fb ldr r3, [r7, #12] 800a28e: 2b00 cmp r3, #0 800a290: d009 beq.n 800a2a6 { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 800a292: 2208 movs r2, #8 800a294: 4909 ldr r1, [pc, #36] @ (800a2bc ) 800a296: 68f8 ldr r0, [r7, #12] 800a298: f000 f814 bl 800a2c4 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 800a29c: 2204 movs r2, #4 800a29e: 4908 ldr r1, [pc, #32] @ (800a2c0 ) 800a2a0: 68b8 ldr r0, [r7, #8] 800a2a2: f000 f80f bl 800a2c4 } } 800a2a6: bf00 nop 800a2a8: 3710 adds r7, #16 800a2aa: 46bd mov sp, r7 800a2ac: bd80 pop {r7, pc} 800a2ae: bf00 nop 800a2b0: 1fff7a10 .word 0x1fff7a10 800a2b4: 1fff7a14 .word 0x1fff7a14 800a2b8: 1fff7a18 .word 0x1fff7a18 800a2bc: 20000186 .word 0x20000186 800a2c0: 20000196 .word 0x20000196 0800a2c4 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800a2c4: b480 push {r7} 800a2c6: b087 sub sp, #28 800a2c8: af00 add r7, sp, #0 800a2ca: 60f8 str r0, [r7, #12] 800a2cc: 60b9 str r1, [r7, #8] 800a2ce: 4613 mov r3, r2 800a2d0: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800a2d2: 2300 movs r3, #0 800a2d4: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800a2d6: 2300 movs r3, #0 800a2d8: 75fb strb r3, [r7, #23] 800a2da: e027 b.n 800a32c { if (((value >> 28)) < 0xA) 800a2dc: 68fb ldr r3, [r7, #12] 800a2de: 0f1b lsrs r3, r3, #28 800a2e0: 2b09 cmp r3, #9 800a2e2: d80b bhi.n 800a2fc { pbuf[2 * idx] = (value >> 28) + '0'; 800a2e4: 68fb ldr r3, [r7, #12] 800a2e6: 0f1b lsrs r3, r3, #28 800a2e8: b2da uxtb r2, r3 800a2ea: 7dfb ldrb r3, [r7, #23] 800a2ec: 005b lsls r3, r3, #1 800a2ee: 4619 mov r1, r3 800a2f0: 68bb ldr r3, [r7, #8] 800a2f2: 440b add r3, r1 800a2f4: 3230 adds r2, #48 @ 0x30 800a2f6: b2d2 uxtb r2, r2 800a2f8: 701a strb r2, [r3, #0] 800a2fa: e00a b.n 800a312 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800a2fc: 68fb ldr r3, [r7, #12] 800a2fe: 0f1b lsrs r3, r3, #28 800a300: b2da uxtb r2, r3 800a302: 7dfb ldrb r3, [r7, #23] 800a304: 005b lsls r3, r3, #1 800a306: 4619 mov r1, r3 800a308: 68bb ldr r3, [r7, #8] 800a30a: 440b add r3, r1 800a30c: 3237 adds r2, #55 @ 0x37 800a30e: b2d2 uxtb r2, r2 800a310: 701a strb r2, [r3, #0] } value = value << 4; 800a312: 68fb ldr r3, [r7, #12] 800a314: 011b lsls r3, r3, #4 800a316: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 800a318: 7dfb ldrb r3, [r7, #23] 800a31a: 005b lsls r3, r3, #1 800a31c: 3301 adds r3, #1 800a31e: 68ba ldr r2, [r7, #8] 800a320: 4413 add r3, r2 800a322: 2200 movs r2, #0 800a324: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800a326: 7dfb ldrb r3, [r7, #23] 800a328: 3301 adds r3, #1 800a32a: 75fb strb r3, [r7, #23] 800a32c: 7dfa ldrb r2, [r7, #23] 800a32e: 79fb ldrb r3, [r7, #7] 800a330: 429a cmp r2, r3 800a332: d3d3 bcc.n 800a2dc } } 800a334: bf00 nop 800a336: bf00 nop 800a338: 371c adds r7, #28 800a33a: 46bd mov sp, r7 800a33c: f85d 7b04 ldr.w r7, [sp], #4 800a340: 4770 bx lr ... 0800a344 : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 800a344: b580 push {r7, lr} 800a346: b0a0 sub sp, #128 @ 0x80 800a348: af00 add r7, sp, #0 800a34a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a34c: f107 036c add.w r3, r7, #108 @ 0x6c 800a350: 2200 movs r2, #0 800a352: 601a str r2, [r3, #0] 800a354: 605a str r2, [r3, #4] 800a356: 609a str r2, [r3, #8] 800a358: 60da str r2, [r3, #12] 800a35a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800a35c: f107 0310 add.w r3, r7, #16 800a360: 225c movs r2, #92 @ 0x5c 800a362: 2100 movs r1, #0 800a364: 4618 mov r0, r3 800a366: f000 fb53 bl 800aa10 if(pcdHandle->Instance==USB_OTG_FS) 800a36a: 687b ldr r3, [r7, #4] 800a36c: 681b ldr r3, [r3, #0] 800a36e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800a372: d149 bne.n 800a408 /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 800a374: f44f 7380 mov.w r3, #256 @ 0x100 800a378: 613b str r3, [r7, #16] PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; 800a37a: 2300 movs r3, #0 800a37c: 667b str r3, [r7, #100] @ 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800a37e: f107 0310 add.w r3, r7, #16 800a382: 4618 mov r0, r3 800a384: f7f9 ffb4 bl 80042f0 800a388: 4603 mov r3, r0 800a38a: 2b00 cmp r3, #0 800a38c: d001 beq.n 800a392 { Error_Handler(); 800a38e: f7f6 fd89 bl 8000ea4 } __HAL_RCC_GPIOA_CLK_ENABLE(); 800a392: 2300 movs r3, #0 800a394: 60fb str r3, [r7, #12] 800a396: 4b1e ldr r3, [pc, #120] @ (800a410 ) 800a398: 6b1b ldr r3, [r3, #48] @ 0x30 800a39a: 4a1d ldr r2, [pc, #116] @ (800a410 ) 800a39c: f043 0301 orr.w r3, r3, #1 800a3a0: 6313 str r3, [r2, #48] @ 0x30 800a3a2: 4b1b ldr r3, [pc, #108] @ (800a410 ) 800a3a4: 6b1b ldr r3, [r3, #48] @ 0x30 800a3a6: f003 0301 and.w r3, r3, #1 800a3aa: 60fb str r3, [r7, #12] 800a3ac: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 800a3ae: f44f 53c0 mov.w r3, #6144 @ 0x1800 800a3b2: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800a3b4: 2302 movs r3, #2 800a3b6: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 800a3b8: 2300 movs r3, #0 800a3ba: 677b str r3, [r7, #116] @ 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800a3bc: 2303 movs r3, #3 800a3be: 67bb str r3, [r7, #120] @ 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 800a3c0: 230a movs r3, #10 800a3c2: 67fb str r3, [r7, #124] @ 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a3c4: f107 036c add.w r3, r7, #108 @ 0x6c 800a3c8: 4619 mov r1, r3 800a3ca: 4812 ldr r0, [pc, #72] @ (800a414 ) 800a3cc: f7f8 f8e6 bl 800259c /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800a3d0: 4b0f ldr r3, [pc, #60] @ (800a410 ) 800a3d2: 6b5b ldr r3, [r3, #52] @ 0x34 800a3d4: 4a0e ldr r2, [pc, #56] @ (800a410 ) 800a3d6: f043 0380 orr.w r3, r3, #128 @ 0x80 800a3da: 6353 str r3, [r2, #52] @ 0x34 800a3dc: 2300 movs r3, #0 800a3de: 60bb str r3, [r7, #8] 800a3e0: 4b0b ldr r3, [pc, #44] @ (800a410 ) 800a3e2: 6c5b ldr r3, [r3, #68] @ 0x44 800a3e4: 4a0a ldr r2, [pc, #40] @ (800a410 ) 800a3e6: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800a3ea: 6453 str r3, [r2, #68] @ 0x44 800a3ec: 4b08 ldr r3, [pc, #32] @ (800a410 ) 800a3ee: 6c5b ldr r3, [r3, #68] @ 0x44 800a3f0: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a3f4: 60bb str r3, [r7, #8] 800a3f6: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 800a3f8: 2200 movs r2, #0 800a3fa: 2100 movs r1, #0 800a3fc: 2043 movs r0, #67 @ 0x43 800a3fe: f7f7 fc94 bl 8001d2a HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 800a402: 2043 movs r0, #67 @ 0x43 800a404: f7f7 fcad bl 8001d62 /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 800a408: bf00 nop 800a40a: 3780 adds r7, #128 @ 0x80 800a40c: 46bd mov sp, r7 800a40e: bd80 pop {r7, pc} 800a410: 40023800 .word 0x40023800 800a414: 40020000 .word 0x40020000 0800a418 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a418: b580 push {r7, lr} 800a41a: b082 sub sp, #8 800a41c: af00 add r7, sp, #0 800a41e: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 800a420: 687b ldr r3, [r7, #4] 800a422: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 800a426: 687b ldr r3, [r7, #4] 800a428: f203 439c addw r3, r3, #1180 @ 0x49c 800a42c: 4619 mov r1, r3 800a42e: 4610 mov r0, r2 800a430: f7fe fbcb bl 8008bca } 800a434: bf00 nop 800a436: 3708 adds r7, #8 800a438: 46bd mov sp, r7 800a43a: bd80 pop {r7, pc} 0800a43c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a43c: b580 push {r7, lr} 800a43e: b082 sub sp, #8 800a440: af00 add r7, sp, #0 800a442: 6078 str r0, [r7, #4] 800a444: 460b mov r3, r1 800a446: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 800a448: 687b ldr r3, [r7, #4] 800a44a: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a44e: 78fa ldrb r2, [r7, #3] 800a450: 6879 ldr r1, [r7, #4] 800a452: 4613 mov r3, r2 800a454: 00db lsls r3, r3, #3 800a456: 4413 add r3, r2 800a458: 009b lsls r3, r3, #2 800a45a: 440b add r3, r1 800a45c: f503 7318 add.w r3, r3, #608 @ 0x260 800a460: 681a ldr r2, [r3, #0] 800a462: 78fb ldrb r3, [r7, #3] 800a464: 4619 mov r1, r3 800a466: f7fe fc05 bl 8008c74 } 800a46a: bf00 nop 800a46c: 3708 adds r7, #8 800a46e: 46bd mov sp, r7 800a470: bd80 pop {r7, pc} 0800a472 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a472: b580 push {r7, lr} 800a474: b082 sub sp, #8 800a476: af00 add r7, sp, #0 800a478: 6078 str r0, [r7, #4] 800a47a: 460b mov r3, r1 800a47c: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800a47e: 687b ldr r3, [r7, #4] 800a480: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a484: 78fa ldrb r2, [r7, #3] 800a486: 6879 ldr r1, [r7, #4] 800a488: 4613 mov r3, r2 800a48a: 00db lsls r3, r3, #3 800a48c: 4413 add r3, r2 800a48e: 009b lsls r3, r3, #2 800a490: 440b add r3, r1 800a492: 3320 adds r3, #32 800a494: 681a ldr r2, [r3, #0] 800a496: 78fb ldrb r3, [r7, #3] 800a498: 4619 mov r1, r3 800a49a: f7fe fca7 bl 8008dec } 800a49e: bf00 nop 800a4a0: 3708 adds r7, #8 800a4a2: 46bd mov sp, r7 800a4a4: bd80 pop {r7, pc} 0800a4a6 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a4a6: b580 push {r7, lr} 800a4a8: b082 sub sp, #8 800a4aa: af00 add r7, sp, #0 800a4ac: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800a4ae: 687b ldr r3, [r7, #4] 800a4b0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a4b4: 4618 mov r0, r3 800a4b6: f7fe fdeb bl 8009090 } 800a4ba: bf00 nop 800a4bc: 3708 adds r7, #8 800a4be: 46bd mov sp, r7 800a4c0: bd80 pop {r7, pc} 0800a4c2 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a4c2: b580 push {r7, lr} 800a4c4: b084 sub sp, #16 800a4c6: af00 add r7, sp, #0 800a4c8: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 800a4ca: 2301 movs r3, #1 800a4cc: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 800a4ce: 687b ldr r3, [r7, #4] 800a4d0: 79db ldrb r3, [r3, #7] 800a4d2: 2b00 cmp r3, #0 800a4d4: d102 bne.n 800a4dc { speed = USBD_SPEED_HIGH; 800a4d6: 2300 movs r3, #0 800a4d8: 73fb strb r3, [r7, #15] 800a4da: e008 b.n 800a4ee } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 800a4dc: 687b ldr r3, [r7, #4] 800a4de: 79db ldrb r3, [r3, #7] 800a4e0: 2b02 cmp r3, #2 800a4e2: d102 bne.n 800a4ea { speed = USBD_SPEED_FULL; 800a4e4: 2301 movs r3, #1 800a4e6: 73fb strb r3, [r7, #15] 800a4e8: e001 b.n 800a4ee } else { Error_Handler(); 800a4ea: f7f6 fcdb bl 8000ea4 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800a4ee: 687b ldr r3, [r7, #4] 800a4f0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a4f4: 7bfa ldrb r2, [r7, #15] 800a4f6: 4611 mov r1, r2 800a4f8: 4618 mov r0, r3 800a4fa: f7fe fd85 bl 8009008 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800a4fe: 687b ldr r3, [r7, #4] 800a500: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a504: 4618 mov r0, r3 800a506: f7fe fd2c bl 8008f62 } 800a50a: bf00 nop 800a50c: 3710 adds r7, #16 800a50e: 46bd mov sp, r7 800a510: bd80 pop {r7, pc} ... 0800a514 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a514: b580 push {r7, lr} 800a516: b082 sub sp, #8 800a518: af00 add r7, sp, #0 800a51a: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800a51c: 687b ldr r3, [r7, #4] 800a51e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a522: 4618 mov r0, r3 800a524: f7fe fd80 bl 8009028 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a528: 687b ldr r3, [r7, #4] 800a52a: 681b ldr r3, [r3, #0] 800a52c: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a530: 681b ldr r3, [r3, #0] 800a532: 687a ldr r2, [r7, #4] 800a534: 6812 ldr r2, [r2, #0] 800a536: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a53a: f043 0301 orr.w r3, r3, #1 800a53e: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 800a540: 687b ldr r3, [r7, #4] 800a542: 7adb ldrb r3, [r3, #11] 800a544: 2b00 cmp r3, #0 800a546: d005 beq.n 800a554 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a548: 4b04 ldr r3, [pc, #16] @ (800a55c ) 800a54a: 691b ldr r3, [r3, #16] 800a54c: 4a03 ldr r2, [pc, #12] @ (800a55c ) 800a54e: f043 0306 orr.w r3, r3, #6 800a552: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 800a554: bf00 nop 800a556: 3708 adds r7, #8 800a558: 46bd mov sp, r7 800a55a: bd80 pop {r7, pc} 800a55c: e000ed00 .word 0xe000ed00 0800a560 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a560: b580 push {r7, lr} 800a562: b082 sub sp, #8 800a564: af00 add r7, sp, #0 800a566: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 800a568: 687b ldr r3, [r7, #4] 800a56a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a56e: 4618 mov r0, r3 800a570: f7fe fd76 bl 8009060 } 800a574: bf00 nop 800a576: 3708 adds r7, #8 800a578: 46bd mov sp, r7 800a57a: bd80 pop {r7, pc} 0800a57c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a57c: b580 push {r7, lr} 800a57e: b082 sub sp, #8 800a580: af00 add r7, sp, #0 800a582: 6078 str r0, [r7, #4] 800a584: 460b mov r3, r1 800a586: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a588: 687b ldr r3, [r7, #4] 800a58a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a58e: 78fa ldrb r2, [r7, #3] 800a590: 4611 mov r1, r2 800a592: 4618 mov r0, r3 800a594: f7fe fdce bl 8009134 } 800a598: bf00 nop 800a59a: 3708 adds r7, #8 800a59c: 46bd mov sp, r7 800a59e: bd80 pop {r7, pc} 0800a5a0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5a0: b580 push {r7, lr} 800a5a2: b082 sub sp, #8 800a5a4: af00 add r7, sp, #0 800a5a6: 6078 str r0, [r7, #4] 800a5a8: 460b mov r3, r1 800a5aa: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a5ac: 687b ldr r3, [r7, #4] 800a5ae: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a5b2: 78fa ldrb r2, [r7, #3] 800a5b4: 4611 mov r1, r2 800a5b6: 4618 mov r0, r3 800a5b8: f7fe fd8a bl 80090d0 } 800a5bc: bf00 nop 800a5be: 3708 adds r7, #8 800a5c0: 46bd mov sp, r7 800a5c2: bd80 pop {r7, pc} 0800a5c4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5c4: b580 push {r7, lr} 800a5c6: b082 sub sp, #8 800a5c8: af00 add r7, sp, #0 800a5ca: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 800a5cc: 687b ldr r3, [r7, #4] 800a5ce: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a5d2: 4618 mov r0, r3 800a5d4: f7fe fde0 bl 8009198 } 800a5d8: bf00 nop 800a5da: 3708 adds r7, #8 800a5dc: 46bd mov sp, r7 800a5de: bd80 pop {r7, pc} 0800a5e0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5e0: b580 push {r7, lr} 800a5e2: b082 sub sp, #8 800a5e4: af00 add r7, sp, #0 800a5e6: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 800a5e8: 687b ldr r3, [r7, #4] 800a5ea: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a5ee: 4618 mov r0, r3 800a5f0: f7fe fddd bl 80091ae } 800a5f4: bf00 nop 800a5f6: 3708 adds r7, #8 800a5f8: 46bd mov sp, r7 800a5fa: bd80 pop {r7, pc} 0800a5fc : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800a5fc: b580 push {r7, lr} 800a5fe: b082 sub sp, #8 800a600: af00 add r7, sp, #0 800a602: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 800a604: 687b ldr r3, [r7, #4] 800a606: 781b ldrb r3, [r3, #0] 800a608: 2b00 cmp r3, #0 800a60a: d13c bne.n 800a686 /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 800a60c: 4a20 ldr r2, [pc, #128] @ (800a690 ) 800a60e: 687b ldr r3, [r7, #4] 800a610: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 pdev->pData = &hpcd_USB_OTG_FS; 800a614: 687b ldr r3, [r7, #4] 800a616: 4a1e ldr r2, [pc, #120] @ (800a690 ) 800a618: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800a61c: 4b1c ldr r3, [pc, #112] @ (800a690 ) 800a61e: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 800a622: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 800a624: 4b1a ldr r3, [pc, #104] @ (800a690 ) 800a626: 2206 movs r2, #6 800a628: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800a62a: 4b19 ldr r3, [pc, #100] @ (800a690 ) 800a62c: 2202 movs r2, #2 800a62e: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 800a630: 4b17 ldr r3, [pc, #92] @ (800a690 ) 800a632: 2200 movs r2, #0 800a634: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 800a636: 4b16 ldr r3, [pc, #88] @ (800a690 ) 800a638: 2202 movs r2, #2 800a63a: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 800a63c: 4b14 ldr r3, [pc, #80] @ (800a690 ) 800a63e: 2200 movs r2, #0 800a640: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800a642: 4b13 ldr r3, [pc, #76] @ (800a690 ) 800a644: 2200 movs r2, #0 800a646: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 800a648: 4b11 ldr r3, [pc, #68] @ (800a690 ) 800a64a: 2200 movs r2, #0 800a64c: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 800a64e: 4b10 ldr r3, [pc, #64] @ (800a690 ) 800a650: 2200 movs r2, #0 800a652: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 800a654: 4b0e ldr r3, [pc, #56] @ (800a690 ) 800a656: 2200 movs r2, #0 800a658: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 800a65a: 480d ldr r0, [pc, #52] @ (800a690 ) 800a65c: f7f8 faa8 bl 8002bb0 800a660: 4603 mov r3, r0 800a662: 2b00 cmp r3, #0 800a664: d001 beq.n 800a66a { Error_Handler( ); 800a666: f7f6 fc1d bl 8000ea4 HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 800a66a: 2180 movs r1, #128 @ 0x80 800a66c: 4808 ldr r0, [pc, #32] @ (800a690 ) 800a66e: f7f9 fcf0 bl 8004052 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 800a672: 2240 movs r2, #64 @ 0x40 800a674: 2100 movs r1, #0 800a676: 4806 ldr r0, [pc, #24] @ (800a690 ) 800a678: f7f9 fca4 bl 8003fc4 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 800a67c: 2280 movs r2, #128 @ 0x80 800a67e: 2101 movs r1, #1 800a680: 4803 ldr r0, [pc, #12] @ (800a690 ) 800a682: f7f9 fc9f bl 8003fc4 } return USBD_OK; 800a686: 2300 movs r3, #0 } 800a688: 4618 mov r0, r3 800a68a: 3708 adds r7, #8 800a68c: 46bd mov sp, r7 800a68e: bd80 pop {r7, pc} 800a690: 20000c10 .word 0x20000c10 0800a694 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800a694: b580 push {r7, lr} 800a696: b084 sub sp, #16 800a698: af00 add r7, sp, #0 800a69a: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800a69c: 2300 movs r3, #0 800a69e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a6a0: 2300 movs r3, #0 800a6a2: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800a6a4: 687b ldr r3, [r7, #4] 800a6a6: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a6aa: 4618 mov r0, r3 800a6ac: f7f8 fb96 bl 8002ddc 800a6b0: 4603 mov r3, r0 800a6b2: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a6b4: 7bfb ldrb r3, [r7, #15] 800a6b6: 4618 mov r0, r3 800a6b8: f000 f97e bl 800a9b8 800a6bc: 4603 mov r3, r0 800a6be: 73bb strb r3, [r7, #14] return usb_status; 800a6c0: 7bbb ldrb r3, [r7, #14] } 800a6c2: 4618 mov r0, r3 800a6c4: 3710 adds r7, #16 800a6c6: 46bd mov sp, r7 800a6c8: bd80 pop {r7, pc} 0800a6ca : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800a6ca: b580 push {r7, lr} 800a6cc: b084 sub sp, #16 800a6ce: af00 add r7, sp, #0 800a6d0: 6078 str r0, [r7, #4] 800a6d2: 4608 mov r0, r1 800a6d4: 4611 mov r1, r2 800a6d6: 461a mov r2, r3 800a6d8: 4603 mov r3, r0 800a6da: 70fb strb r3, [r7, #3] 800a6dc: 460b mov r3, r1 800a6de: 70bb strb r3, [r7, #2] 800a6e0: 4613 mov r3, r2 800a6e2: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800a6e4: 2300 movs r3, #0 800a6e6: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a6e8: 2300 movs r3, #0 800a6ea: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800a6ec: 687b ldr r3, [r7, #4] 800a6ee: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a6f2: 78bb ldrb r3, [r7, #2] 800a6f4: 883a ldrh r2, [r7, #0] 800a6f6: 78f9 ldrb r1, [r7, #3] 800a6f8: f7f9 f897 bl 800382a 800a6fc: 4603 mov r3, r0 800a6fe: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a700: 7bfb ldrb r3, [r7, #15] 800a702: 4618 mov r0, r3 800a704: f000 f958 bl 800a9b8 800a708: 4603 mov r3, r0 800a70a: 73bb strb r3, [r7, #14] return usb_status; 800a70c: 7bbb ldrb r3, [r7, #14] } 800a70e: 4618 mov r0, r3 800a710: 3710 adds r7, #16 800a712: 46bd mov sp, r7 800a714: bd80 pop {r7, pc} 0800a716 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a716: b580 push {r7, lr} 800a718: b084 sub sp, #16 800a71a: af00 add r7, sp, #0 800a71c: 6078 str r0, [r7, #4] 800a71e: 460b mov r3, r1 800a720: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a722: 2300 movs r3, #0 800a724: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a726: 2300 movs r3, #0 800a728: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800a72a: 687b ldr r3, [r7, #4] 800a72c: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a730: 78fa ldrb r2, [r7, #3] 800a732: 4611 mov r1, r2 800a734: 4618 mov r0, r3 800a736: f7f9 f8e2 bl 80038fe 800a73a: 4603 mov r3, r0 800a73c: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a73e: 7bfb ldrb r3, [r7, #15] 800a740: 4618 mov r0, r3 800a742: f000 f939 bl 800a9b8 800a746: 4603 mov r3, r0 800a748: 73bb strb r3, [r7, #14] return usb_status; 800a74a: 7bbb ldrb r3, [r7, #14] } 800a74c: 4618 mov r0, r3 800a74e: 3710 adds r7, #16 800a750: 46bd mov sp, r7 800a752: bd80 pop {r7, pc} 0800a754 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a754: b580 push {r7, lr} 800a756: b084 sub sp, #16 800a758: af00 add r7, sp, #0 800a75a: 6078 str r0, [r7, #4] 800a75c: 460b mov r3, r1 800a75e: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a760: 2300 movs r3, #0 800a762: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a764: 2300 movs r3, #0 800a766: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800a768: 687b ldr r3, [r7, #4] 800a76a: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a76e: 78fa ldrb r2, [r7, #3] 800a770: 4611 mov r1, r2 800a772: 4618 mov r0, r3 800a774: f7f9 f982 bl 8003a7c 800a778: 4603 mov r3, r0 800a77a: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a77c: 7bfb ldrb r3, [r7, #15] 800a77e: 4618 mov r0, r3 800a780: f000 f91a bl 800a9b8 800a784: 4603 mov r3, r0 800a786: 73bb strb r3, [r7, #14] return usb_status; 800a788: 7bbb ldrb r3, [r7, #14] } 800a78a: 4618 mov r0, r3 800a78c: 3710 adds r7, #16 800a78e: 46bd mov sp, r7 800a790: bd80 pop {r7, pc} 0800a792 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a792: b580 push {r7, lr} 800a794: b084 sub sp, #16 800a796: af00 add r7, sp, #0 800a798: 6078 str r0, [r7, #4] 800a79a: 460b mov r3, r1 800a79c: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a79e: 2300 movs r3, #0 800a7a0: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a7a2: 2300 movs r3, #0 800a7a4: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800a7a6: 687b ldr r3, [r7, #4] 800a7a8: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a7ac: 78fa ldrb r2, [r7, #3] 800a7ae: 4611 mov r1, r2 800a7b0: 4618 mov r0, r3 800a7b2: f7f9 f9c6 bl 8003b42 800a7b6: 4603 mov r3, r0 800a7b8: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a7ba: 7bfb ldrb r3, [r7, #15] 800a7bc: 4618 mov r0, r3 800a7be: f000 f8fb bl 800a9b8 800a7c2: 4603 mov r3, r0 800a7c4: 73bb strb r3, [r7, #14] return usb_status; 800a7c6: 7bbb ldrb r3, [r7, #14] } 800a7c8: 4618 mov r0, r3 800a7ca: 3710 adds r7, #16 800a7cc: 46bd mov sp, r7 800a7ce: bd80 pop {r7, pc} 0800a7d0 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a7d0: b480 push {r7} 800a7d2: b085 sub sp, #20 800a7d4: af00 add r7, sp, #0 800a7d6: 6078 str r0, [r7, #4] 800a7d8: 460b mov r3, r1 800a7da: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800a7dc: 687b ldr r3, [r7, #4] 800a7de: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a7e2: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800a7e4: f997 3003 ldrsb.w r3, [r7, #3] 800a7e8: 2b00 cmp r3, #0 800a7ea: da0b bge.n 800a804 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800a7ec: 78fb ldrb r3, [r7, #3] 800a7ee: f003 027f and.w r2, r3, #127 @ 0x7f 800a7f2: 68f9 ldr r1, [r7, #12] 800a7f4: 4613 mov r3, r2 800a7f6: 00db lsls r3, r3, #3 800a7f8: 4413 add r3, r2 800a7fa: 009b lsls r3, r3, #2 800a7fc: 440b add r3, r1 800a7fe: 3316 adds r3, #22 800a800: 781b ldrb r3, [r3, #0] 800a802: e00b b.n 800a81c } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800a804: 78fb ldrb r3, [r7, #3] 800a806: f003 027f and.w r2, r3, #127 @ 0x7f 800a80a: 68f9 ldr r1, [r7, #12] 800a80c: 4613 mov r3, r2 800a80e: 00db lsls r3, r3, #3 800a810: 4413 add r3, r2 800a812: 009b lsls r3, r3, #2 800a814: 440b add r3, r1 800a816: f203 2356 addw r3, r3, #598 @ 0x256 800a81a: 781b ldrb r3, [r3, #0] } } 800a81c: 4618 mov r0, r3 800a81e: 3714 adds r7, #20 800a820: 46bd mov sp, r7 800a822: f85d 7b04 ldr.w r7, [sp], #4 800a826: 4770 bx lr 0800a828 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800a828: b580 push {r7, lr} 800a82a: b084 sub sp, #16 800a82c: af00 add r7, sp, #0 800a82e: 6078 str r0, [r7, #4] 800a830: 460b mov r3, r1 800a832: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a834: 2300 movs r3, #0 800a836: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a838: 2300 movs r3, #0 800a83a: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800a83c: 687b ldr r3, [r7, #4] 800a83e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a842: 78fa ldrb r2, [r7, #3] 800a844: 4611 mov r1, r2 800a846: 4618 mov r0, r3 800a848: f7f8 ffcb bl 80037e2 800a84c: 4603 mov r3, r0 800a84e: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a850: 7bfb ldrb r3, [r7, #15] 800a852: 4618 mov r0, r3 800a854: f000 f8b0 bl 800a9b8 800a858: 4603 mov r3, r0 800a85a: 73bb strb r3, [r7, #14] return usb_status; 800a85c: 7bbb ldrb r3, [r7, #14] } 800a85e: 4618 mov r0, r3 800a860: 3710 adds r7, #16 800a862: 46bd mov sp, r7 800a864: bd80 pop {r7, pc} 0800a866 : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a866: b580 push {r7, lr} 800a868: b086 sub sp, #24 800a86a: af00 add r7, sp, #0 800a86c: 60f8 str r0, [r7, #12] 800a86e: 607a str r2, [r7, #4] 800a870: 603b str r3, [r7, #0] 800a872: 460b mov r3, r1 800a874: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a876: 2300 movs r3, #0 800a878: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a87a: 2300 movs r3, #0 800a87c: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800a87e: 68fb ldr r3, [r7, #12] 800a880: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a884: 7af9 ldrb r1, [r7, #11] 800a886: 683b ldr r3, [r7, #0] 800a888: 687a ldr r2, [r7, #4] 800a88a: f7f9 f8bd bl 8003a08 800a88e: 4603 mov r3, r0 800a890: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a892: 7dfb ldrb r3, [r7, #23] 800a894: 4618 mov r0, r3 800a896: f000 f88f bl 800a9b8 800a89a: 4603 mov r3, r0 800a89c: 75bb strb r3, [r7, #22] return usb_status; 800a89e: 7dbb ldrb r3, [r7, #22] } 800a8a0: 4618 mov r0, r3 800a8a2: 3718 adds r7, #24 800a8a4: 46bd mov sp, r7 800a8a6: bd80 pop {r7, pc} 0800a8a8 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a8a8: b580 push {r7, lr} 800a8aa: b086 sub sp, #24 800a8ac: af00 add r7, sp, #0 800a8ae: 60f8 str r0, [r7, #12] 800a8b0: 607a str r2, [r7, #4] 800a8b2: 603b str r3, [r7, #0] 800a8b4: 460b mov r3, r1 800a8b6: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a8b8: 2300 movs r3, #0 800a8ba: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a8bc: 2300 movs r3, #0 800a8be: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800a8c0: 68fb ldr r3, [r7, #12] 800a8c2: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a8c6: 7af9 ldrb r1, [r7, #11] 800a8c8: 683b ldr r3, [r7, #0] 800a8ca: 687a ldr r2, [r7, #4] 800a8cc: f7f9 f861 bl 8003992 800a8d0: 4603 mov r3, r0 800a8d2: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a8d4: 7dfb ldrb r3, [r7, #23] 800a8d6: 4618 mov r0, r3 800a8d8: f000 f86e bl 800a9b8 800a8dc: 4603 mov r3, r0 800a8de: 75bb strb r3, [r7, #22] return usb_status; 800a8e0: 7dbb ldrb r3, [r7, #22] } 800a8e2: 4618 mov r0, r3 800a8e4: 3718 adds r7, #24 800a8e6: 46bd mov sp, r7 800a8e8: bd80 pop {r7, pc} ... 0800a8ec : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 800a8ec: b580 push {r7, lr} 800a8ee: b082 sub sp, #8 800a8f0: af00 add r7, sp, #0 800a8f2: 6078 str r0, [r7, #4] 800a8f4: 460b mov r3, r1 800a8f6: 70fb strb r3, [r7, #3] switch (msg) 800a8f8: 78fb ldrb r3, [r7, #3] 800a8fa: 2b00 cmp r3, #0 800a8fc: d002 beq.n 800a904 800a8fe: 2b01 cmp r3, #1 800a900: d01f beq.n 800a942 /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 800a902: e03b b.n 800a97c if (hpcd->Init.low_power_enable) 800a904: 687b ldr r3, [r7, #4] 800a906: 7adb ldrb r3, [r3, #11] 800a908: 2b00 cmp r3, #0 800a90a: d007 beq.n 800a91c SystemClock_Config(); 800a90c: f7f6 f85c bl 80009c8 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a910: 4b1c ldr r3, [pc, #112] @ (800a984 ) 800a912: 691b ldr r3, [r3, #16] 800a914: 4a1b ldr r2, [pc, #108] @ (800a984 ) 800a916: f023 0306 bic.w r3, r3, #6 800a91a: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 800a91c: 687b ldr r3, [r7, #4] 800a91e: 681b ldr r3, [r3, #0] 800a920: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a924: 681b ldr r3, [r3, #0] 800a926: 687a ldr r2, [r7, #4] 800a928: 6812 ldr r2, [r2, #0] 800a92a: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a92e: f023 0301 bic.w r3, r3, #1 800a932: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 800a934: 687b ldr r3, [r7, #4] 800a936: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a93a: 4618 mov r0, r3 800a93c: f7fe fb90 bl 8009060 break; 800a940: e01c b.n 800a97c __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a942: 687b ldr r3, [r7, #4] 800a944: 681b ldr r3, [r3, #0] 800a946: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a94a: 681b ldr r3, [r3, #0] 800a94c: 687a ldr r2, [r7, #4] 800a94e: 6812 ldr r2, [r2, #0] 800a950: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a954: f043 0301 orr.w r3, r3, #1 800a958: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 800a95a: 687b ldr r3, [r7, #4] 800a95c: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a960: 4618 mov r0, r3 800a962: f7fe fb61 bl 8009028 if (hpcd->Init.low_power_enable) 800a966: 687b ldr r3, [r7, #4] 800a968: 7adb ldrb r3, [r3, #11] 800a96a: 2b00 cmp r3, #0 800a96c: d005 beq.n 800a97a SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a96e: 4b05 ldr r3, [pc, #20] @ (800a984 ) 800a970: 691b ldr r3, [r3, #16] 800a972: 4a04 ldr r2, [pc, #16] @ (800a984 ) 800a974: f043 0306 orr.w r3, r3, #6 800a978: 6113 str r3, [r2, #16] break; 800a97a: bf00 nop } 800a97c: bf00 nop 800a97e: 3708 adds r7, #8 800a980: 46bd mov sp, r7 800a982: bd80 pop {r7, pc} 800a984: e000ed00 .word 0xe000ed00 0800a988 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800a988: b480 push {r7} 800a98a: b083 sub sp, #12 800a98c: af00 add r7, sp, #0 800a98e: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800a990: 4b03 ldr r3, [pc, #12] @ (800a9a0 ) } 800a992: 4618 mov r0, r3 800a994: 370c adds r7, #12 800a996: 46bd mov sp, r7 800a998: f85d 7b04 ldr.w r7, [sp], #4 800a99c: 4770 bx lr 800a99e: bf00 nop 800a9a0: 200010f4 .word 0x200010f4 0800a9a4 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800a9a4: b480 push {r7} 800a9a6: b083 sub sp, #12 800a9a8: af00 add r7, sp, #0 800a9aa: 6078 str r0, [r7, #4] } 800a9ac: bf00 nop 800a9ae: 370c adds r7, #12 800a9b0: 46bd mov sp, r7 800a9b2: f85d 7b04 ldr.w r7, [sp], #4 800a9b6: 4770 bx lr 0800a9b8 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800a9b8: b480 push {r7} 800a9ba: b085 sub sp, #20 800a9bc: af00 add r7, sp, #0 800a9be: 4603 mov r3, r0 800a9c0: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800a9c2: 2300 movs r3, #0 800a9c4: 73fb strb r3, [r7, #15] switch (hal_status) 800a9c6: 79fb ldrb r3, [r7, #7] 800a9c8: 2b03 cmp r3, #3 800a9ca: d817 bhi.n 800a9fc 800a9cc: a201 add r2, pc, #4 @ (adr r2, 800a9d4 ) 800a9ce: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a9d2: bf00 nop 800a9d4: 0800a9e5 .word 0x0800a9e5 800a9d8: 0800a9eb .word 0x0800a9eb 800a9dc: 0800a9f1 .word 0x0800a9f1 800a9e0: 0800a9f7 .word 0x0800a9f7 { case HAL_OK : usb_status = USBD_OK; 800a9e4: 2300 movs r3, #0 800a9e6: 73fb strb r3, [r7, #15] break; 800a9e8: e00b b.n 800aa02 case HAL_ERROR : usb_status = USBD_FAIL; 800a9ea: 2303 movs r3, #3 800a9ec: 73fb strb r3, [r7, #15] break; 800a9ee: e008 b.n 800aa02 case HAL_BUSY : usb_status = USBD_BUSY; 800a9f0: 2301 movs r3, #1 800a9f2: 73fb strb r3, [r7, #15] break; 800a9f4: e005 b.n 800aa02 case HAL_TIMEOUT : usb_status = USBD_FAIL; 800a9f6: 2303 movs r3, #3 800a9f8: 73fb strb r3, [r7, #15] break; 800a9fa: e002 b.n 800aa02 default : usb_status = USBD_FAIL; 800a9fc: 2303 movs r3, #3 800a9fe: 73fb strb r3, [r7, #15] break; 800aa00: bf00 nop } return usb_status; 800aa02: 7bfb ldrb r3, [r7, #15] } 800aa04: 4618 mov r0, r3 800aa06: 3714 adds r7, #20 800aa08: 46bd mov sp, r7 800aa0a: f85d 7b04 ldr.w r7, [sp], #4 800aa0e: 4770 bx lr 0800aa10 : 800aa10: 4402 add r2, r0 800aa12: 4603 mov r3, r0 800aa14: 4293 cmp r3, r2 800aa16: d100 bne.n 800aa1a 800aa18: 4770 bx lr 800aa1a: f803 1b01 strb.w r1, [r3], #1 800aa1e: e7f9 b.n 800aa14 0800aa20 <__libc_init_array>: 800aa20: b570 push {r4, r5, r6, lr} 800aa22: 4d0d ldr r5, [pc, #52] @ (800aa58 <__libc_init_array+0x38>) 800aa24: 4c0d ldr r4, [pc, #52] @ (800aa5c <__libc_init_array+0x3c>) 800aa26: 1b64 subs r4, r4, r5 800aa28: 10a4 asrs r4, r4, #2 800aa2a: 2600 movs r6, #0 800aa2c: 42a6 cmp r6, r4 800aa2e: d109 bne.n 800aa44 <__libc_init_array+0x24> 800aa30: 4d0b ldr r5, [pc, #44] @ (800aa60 <__libc_init_array+0x40>) 800aa32: 4c0c ldr r4, [pc, #48] @ (800aa64 <__libc_init_array+0x44>) 800aa34: f000 f818 bl 800aa68 <_init> 800aa38: 1b64 subs r4, r4, r5 800aa3a: 10a4 asrs r4, r4, #2 800aa3c: 2600 movs r6, #0 800aa3e: 42a6 cmp r6, r4 800aa40: d105 bne.n 800aa4e <__libc_init_array+0x2e> 800aa42: bd70 pop {r4, r5, r6, pc} 800aa44: f855 3b04 ldr.w r3, [r5], #4 800aa48: 4798 blx r3 800aa4a: 3601 adds r6, #1 800aa4c: e7ee b.n 800aa2c <__libc_init_array+0xc> 800aa4e: f855 3b04 ldr.w r3, [r5], #4 800aa52: 4798 blx r3 800aa54: 3601 adds r6, #1 800aa56: e7f2 b.n 800aa3e <__libc_init_array+0x1e> 800aa58: 0800aae4 .word 0x0800aae4 800aa5c: 0800aae4 .word 0x0800aae4 800aa60: 0800aae4 .word 0x0800aae4 800aa64: 0800aae8 .word 0x0800aae8 0800aa68 <_init>: 800aa68: b5f8 push {r3, r4, r5, r6, r7, lr} 800aa6a: bf00 nop 800aa6c: bcf8 pop {r3, r4, r5, r6, r7} 800aa6e: bc08 pop {r3} 800aa70: 469e mov lr, r3 800aa72: 4770 bx lr 0800aa74 <_fini>: 800aa74: b5f8 push {r3, r4, r5, r6, r7, lr} 800aa76: bf00 nop 800aa78: bcf8 pop {r3, r4, r5, r6, r7} 800aa7a: bc08 pop {r3} 800aa7c: 469e mov lr, r3 800aa7e: 4770 bx lr