numpad.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000b688 080001c4 080001c4 000011c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000005c 0800b84c 0800b84c 0000c84c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800b8a8 0800b8a8 0000d1a0 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800b8a8 0800b8a8 0000c8a8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800b8b0 0800b8b0 0000d1a0 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800b8b0 0800b8b0 0000c8b0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800b8b4 0800b8b4 0000c8b4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 000001a0 20000000 0800b8b8 0000d000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 0000173c 200001a0 0800ba58 0000d1a0 2**2 ALLOC 10 ._user_heap_stack 00000604 200018dc 0800ba58 0000d8dc 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000d1a0 2**0 CONTENTS, READONLY 12 .debug_info 0001b77c 00000000 00000000 0000d1d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000040bb 00000000 00000000 0002894c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000017d0 00000000 00000000 0002ca08 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 0000127f 00000000 00000000 0002e1d8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0002609f 00000000 00000000 0002f457 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001e97e 00000000 00000000 000554f6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d80c4 00000000 00000000 00073e74 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014bf38 2**0 CONTENTS, READONLY 20 .debug_frame 00006430 00000000 00000000 0014bf7c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 0000005e 00000000 00000000 001523ac 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 200001a0 .word 0x200001a0 80001e0: 00000000 .word 0x00000000 80001e4: 0800b834 .word 0x0800b834 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 200001a4 .word 0x200001a4 8000200: 0800b834 .word 0x0800b834 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 468e mov lr, r1 800023c: 4604 mov r4, r0 800023e: 4688 mov r8, r1 8000240: 2b00 cmp r3, #0 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> 800024a: fab2 f682 clz r6, r2 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> 8000250: f1c6 0320 rsb r3, r6, #32 8000254: fa01 f806 lsl.w r8, r1, r6 8000258: fa20 f303 lsr.w r3, r0, r3 800025c: 40b7 lsls r7, r6 800025e: ea43 0808 orr.w r8, r3, r8 8000262: 40b4 lsls r4, r6 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 8000268: fa1f fc87 uxth.w ip, r7 800026c: fbb8 f1fe udiv r1, r8, lr 8000270: 0c23 lsrs r3, r4, #16 8000272: fb0e 8811 mls r8, lr, r1, r8 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 800027a: fb01 f20c mul.w r2, r1, ip 800027e: 429a cmp r2, r3 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> 8000282: 18fb adds r3, r7, r3 8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> 800028c: 429a cmp r2, r3 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> 8000292: 3902 subs r1, #2 8000294: 443b add r3, r7 8000296: 1a9a subs r2, r3, r2 8000298: b2a3 uxth r3, r4 800029a: fbb2 f0fe udiv r0, r2, lr 800029e: fb0e 2210 mls r2, lr, r0, r2 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 80002a6: fb00 fc0c mul.w ip, r0, ip 80002aa: 459c cmp ip, r3 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> 80002ae: 18fb adds r3, r7, r3 80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> 80002b8: 459c cmp ip, r3 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> 80002be: 443b add r3, r7 80002c0: 3802 subs r0, #2 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 80002c6: eba3 030c sub.w r3, r3, ip 80002ca: 2100 movs r1, #0 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> 80002ce: 40f3 lsrs r3, r6 80002d0: 2200 movs r2, #0 80002d2: e9c5 3200 strd r3, r2, [r5] 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: 428b cmp r3, r1 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> 80002e0: e9c5 0100 strd r0, r1, [r5] 80002e4: 2100 movs r1, #0 80002e6: 4608 mov r0, r1 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> 80002ea: fab3 f183 clz r1, r3 80002ee: 2900 cmp r1, #0 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> 80002f2: 4573 cmp r3, lr 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> 80002f6: 4282 cmp r2, r0 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> 80002fc: 1a84 subs r4, r0, r2 80002fe: eb6e 0203 sbc.w r2, lr, r3 8000302: 2001 movs r0, #1 8000304: 4690 mov r8, r2 8000306: 2d00 cmp r5, #0 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> 800030a: e9c5 4800 strd r4, r8, [r5] 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> 8000310: 2a00 cmp r2, #0 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> 8000316: fab2 f682 clz r6, r2 800031a: 2e00 cmp r6, #0 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> 8000320: 1a8a subs r2, r1, r2 8000322: 0c03 lsrs r3, r0, #16 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 8000328: b280 uxth r0, r0 800032a: b2bc uxth r4, r7 800032c: 2101 movs r1, #1 800032e: fbb2 fcfe udiv ip, r2, lr 8000332: fb0e 221c mls r2, lr, ip, r2 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 800033a: fb04 f20c mul.w r2, r4, ip 800033e: 429a cmp r2, r3 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> 8000342: 18fb adds r3, r7, r3 8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> 800034a: 429a cmp r2, r3 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> 8000350: 46c4 mov ip, r8 8000352: 1a9b subs r3, r3, r2 8000354: fbb3 f2fe udiv r2, r3, lr 8000358: fb0e 3312 mls r3, lr, r2, r3 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 8000360: fb02 f404 mul.w r4, r2, r4 8000364: 429c cmp r4, r3 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> 8000368: 18fb adds r3, r7, r3 800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> 8000370: 429c cmp r4, r3 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> 8000376: 4602 mov r2, r0 8000378: 1b1b subs r3, r3, r4 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> 8000380: f1c1 0620 rsb r6, r1, #32 8000384: 408b lsls r3, r1 8000386: fa22 f706 lsr.w r7, r2, r6 800038a: 431f orrs r7, r3 800038c: fa0e f401 lsl.w r4, lr, r1 8000390: fa20 f306 lsr.w r3, r0, r6 8000394: fa2e fe06 lsr.w lr, lr, r6 8000398: ea4f 4917 mov.w r9, r7, lsr #16 800039c: 4323 orrs r3, r4 800039e: fa00 f801 lsl.w r8, r0, r1 80003a2: fa1f fc87 uxth.w ip, r7 80003a6: fbbe f0f9 udiv r0, lr, r9 80003aa: 0c1c lsrs r4, r3, #16 80003ac: fb09 ee10 mls lr, r9, r0, lr 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 80003b4: fb00 fe0c mul.w lr, r0, ip 80003b8: 45a6 cmp lr, r4 80003ba: fa02 f201 lsl.w r2, r2, r1 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> 80003c0: 193c adds r4, r7, r4 80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> 80003ca: 45a6 cmp lr, r4 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> 80003d0: 3802 subs r0, #2 80003d2: 443c add r4, r7 80003d4: eba4 040e sub.w r4, r4, lr 80003d8: fa1f fe83 uxth.w lr, r3 80003dc: fbb4 f3f9 udiv r3, r4, r9 80003e0: fb09 4413 mls r4, r9, r3, r4 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003e8: fb03 fc0c mul.w ip, r3, ip 80003ec: 45a4 cmp ip, r4 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> 80003f0: 193c adds r4, r7, r4 80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> 80003fa: 45a4 cmp ip, r4 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> 80003fe: 3b02 subs r3, #2 8000400: 443c add r4, r7 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 8000406: eba4 040c sub.w r4, r4, ip 800040a: fba0 ec02 umull lr, ip, r0, r2 800040e: 4564 cmp r4, ip 8000410: 4673 mov r3, lr 8000412: 46e1 mov r9, ip 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> 800041a: ebb8 0203 subs.w r2, r8, r3 800041e: eb64 0409 sbc.w r4, r4, r9 8000422: fa04 f606 lsl.w r6, r4, r6 8000426: fa22 f301 lsr.w r3, r2, r1 800042a: 431e orrs r6, r3 800042c: 40cc lsrs r4, r1 800042e: e9c5 6400 strd r6, r4, [r5] 8000432: 2100 movs r1, #0 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> 8000436: fbb1 fcf2 udiv ip, r1, r2 800043a: 0c01 lsrs r1, r0, #16 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 8000440: b280 uxth r0, r0 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 8000446: 463b mov r3, r7 8000448: 4638 mov r0, r7 800044a: 463c mov r4, r7 800044c: 46b8 mov r8, r7 800044e: 46be mov lr, r7 8000450: 2620 movs r6, #32 8000452: fbb1 f1f7 udiv r1, r1, r7 8000456: eba2 0208 sub.w r2, r2, r8 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> 8000460: 4601 mov r1, r0 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> 8000464: 4610 mov r0, r2 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> 8000468: f1c6 0220 rsb r2, r6, #32 800046c: fa2e f302 lsr.w r3, lr, r2 8000470: 40b7 lsls r7, r6 8000472: 40b1 lsls r1, r6 8000474: fa20 f202 lsr.w r2, r0, r2 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 800047c: 430a orrs r2, r1 800047e: fbb3 f8fe udiv r8, r3, lr 8000482: b2bc uxth r4, r7 8000484: fb0e 3318 mls r3, lr, r8, r3 8000488: 0c11 lsrs r1, r2, #16 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 800048e: fb08 f904 mul.w r9, r8, r4 8000492: 40b0 lsls r0, r6 8000494: 4589 cmp r9, r1 8000496: ea4f 4310 mov.w r3, r0, lsr #16 800049a: b280 uxth r0, r0 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> 800049e: 1879 adds r1, r7, r1 80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> 80004a6: 4589 cmp r9, r1 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> 80004aa: eba1 0109 sub.w r1, r1, r9 80004ae: fbb1 f9fe udiv r9, r1, lr 80004b2: fb09 f804 mul.w r8, r9, r4 80004b6: fb0e 1119 mls r1, lr, r9, r1 80004ba: b292 uxth r2, r2 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 80004c0: 4542 cmp r2, r8 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> 80004c4: 18ba adds r2, r7, r2 80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> 80004cc: 4542 cmp r2, r8 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> 80004d0: f1a9 0102 sub.w r1, r9, #2 80004d4: 443a add r2, r7 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> 80004d8: 45f0 cmp r8, lr 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> 80004dc: ebbe 0302 subs.w r3, lr, r2 80004e0: eb6c 0c07 sbc.w ip, ip, r7 80004e4: 3801 subs r0, #1 80004e6: 46e1 mov r9, ip 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> 80004ea: eba7 0909 sub.w r9, r7, r9 80004ee: 4449 add r1, r9 80004f0: f1a8 0c02 sub.w ip, r8, #2 80004f4: fbb1 f9fe udiv r9, r1, lr 80004f8: fb09 f804 mul.w r8, r9, r4 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> 80004fe: 4673 mov r3, lr 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> 8000502: 4650 mov r0, sl 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> 8000506: 4608 mov r0, r1 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> 800050a: 443b add r3, r7 800050c: 3a02 subs r2, #2 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> 8000510: f1ac 0c02 sub.w ip, ip, #2 8000514: 443b add r3, r7 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> 8000518: 4649 mov r1, r9 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> 800051c: eba1 0109 sub.w r1, r1, r9 8000520: 46c4 mov ip, r8 8000522: fbb1 f9fe udiv r9, r1, lr 8000526: fb09 f804 mul.w r8, r9, r4 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> 0800052c <__aeabi_idiv0>: 800052c: 4770 bx lr 800052e: bf00 nop 08000530 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000530: b580 push {r7, lr} 8000532: b082 sub sp, #8 8000534: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000536: 2300 movs r3, #0 8000538: 607b str r3, [r7, #4] 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000544: 6313 str r3, [r2, #48] @ 0x30 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 8000552: 2300 movs r3, #0 8000554: 603b str r3, [r7, #0] 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000560: 6313 str r3, [r2, #48] @ 0x30 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800056a: 603b str r3, [r7, #0] 800056c: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 800056e: 2200 movs r2, #0 8000570: 2100 movs r1, #0 8000572: 200b movs r0, #11 8000574: f001 fe0d bl 8002192 HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000578: 200b movs r0, #11 800057a: f001 fe26 bl 80021ca /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 800057e: 2200 movs r2, #0 8000580: 2100 movs r1, #0 8000582: 200d movs r0, #13 8000584: f001 fe05 bl 8002192 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000588: 200d movs r0, #13 800058a: f001 fe1e bl 80021ca /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); 800058e: 2200 movs r2, #0 8000590: 2100 movs r1, #0 8000592: 200f movs r0, #15 8000594: f001 fdfd bl 8002192 HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 8000598: 200f movs r0, #15 800059a: f001 fe16 bl 80021ca /* DMA1_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); 800059e: 2200 movs r2, #0 80005a0: 2100 movs r1, #0 80005a2: 2010 movs r0, #16 80005a4: f001 fdf5 bl 8002192 HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); 80005a8: 2010 movs r0, #16 80005aa: f001 fe0e bl 80021ca /* DMA1_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); 80005ae: 2200 movs r2, #0 80005b0: 2100 movs r1, #0 80005b2: 2011 movs r0, #17 80005b4: f001 fded bl 8002192 HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); 80005b8: 2011 movs r0, #17 80005ba: f001 fe06 bl 80021ca /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); 80005be: 2200 movs r2, #0 80005c0: 2100 movs r1, #0 80005c2: 202f movs r0, #47 @ 0x2f 80005c4: f001 fde5 bl 8002192 HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); 80005c8: 202f movs r0, #47 @ 0x2f 80005ca: f001 fdfe bl 80021ca /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); 80005ce: 2200 movs r2, #0 80005d0: 2100 movs r1, #0 80005d2: 203a movs r0, #58 @ 0x3a 80005d4: f001 fddd bl 8002192 HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); 80005d8: 203a movs r0, #58 @ 0x3a 80005da: f001 fdf6 bl 80021ca /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 80005de: 2200 movs r2, #0 80005e0: 2100 movs r1, #0 80005e2: 2046 movs r0, #70 @ 0x46 80005e4: f001 fdd5 bl 8002192 HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 80005e8: 2046 movs r0, #70 @ 0x46 80005ea: f001 fdee bl 80021ca } 80005ee: bf00 nop 80005f0: 3708 adds r7, #8 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 80005f6: bf00 nop 80005f8: 40023800 .word 0x40023800 080005fc : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000602: f107 0314 add.w r3, r7, #20 8000606: 2200 movs r2, #0 8000608: 601a str r2, [r3, #0] 800060a: 605a str r2, [r3, #4] 800060c: 609a str r2, [r3, #8] 800060e: 60da str r2, [r3, #12] 8000610: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000612: 2300 movs r3, #0 8000614: 613b str r3, [r7, #16] 8000616: 4b45 ldr r3, [pc, #276] @ (800072c ) 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 800061a: 4a44 ldr r2, [pc, #272] @ (800072c ) 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000620: 6313 str r3, [r2, #48] @ 0x30 8000622: 4b42 ldr r3, [pc, #264] @ (800072c ) 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 800062a: 613b str r3, [r7, #16] 800062c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800062e: 2300 movs r3, #0 8000630: 60fb str r3, [r7, #12] 8000632: 4b3e ldr r3, [pc, #248] @ (800072c ) 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 8000636: 4a3d ldr r2, [pc, #244] @ (800072c ) 8000638: f043 0301 orr.w r3, r3, #1 800063c: 6313 str r3, [r2, #48] @ 0x30 800063e: 4b3b ldr r3, [pc, #236] @ (800072c ) 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 8000642: f003 0301 and.w r3, r3, #1 8000646: 60fb str r3, [r7, #12] 8000648: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800064a: 2300 movs r3, #0 800064c: 60bb str r3, [r7, #8] 800064e: 4b37 ldr r3, [pc, #220] @ (800072c ) 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 8000652: 4a36 ldr r2, [pc, #216] @ (800072c ) 8000654: f043 0304 orr.w r3, r3, #4 8000658: 6313 str r3, [r2, #48] @ 0x30 800065a: 4b34 ldr r3, [pc, #208] @ (800072c ) 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 800065e: f003 0304 and.w r3, r3, #4 8000662: 60bb str r3, [r7, #8] 8000664: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000666: 2300 movs r3, #0 8000668: 607b str r3, [r7, #4] 800066a: 4b30 ldr r3, [pc, #192] @ (800072c ) 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 800066e: 4a2f ldr r2, [pc, #188] @ (800072c ) 8000670: f043 0302 orr.w r3, r3, #2 8000674: 6313 str r3, [r2, #48] @ 0x30 8000676: 4b2d ldr r3, [pc, #180] @ (800072c ) 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 800067a: f003 0302 and.w r3, r3, #2 800067e: 607b str r3, [r7, #4] 8000680: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000682: 2300 movs r3, #0 8000684: 603b str r3, [r7, #0] 8000686: 4b29 ldr r3, [pc, #164] @ (800072c ) 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 800068a: 4a28 ldr r2, [pc, #160] @ (800072c ) 800068c: f043 0308 orr.w r3, r3, #8 8000690: 6313 str r3, [r2, #48] @ 0x30 8000692: 4b26 ldr r3, [pc, #152] @ (800072c ) 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 8000696: f003 0308 and.w r3, r3, #8 800069a: 603b str r3, [r7, #0] 800069c: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); 800069e: 2200 movs r2, #0 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 80006a4: 4822 ldr r0, [pc, #136] @ (8000730 ) 80006a6: f002 fb59 bl 8002d5c /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); 80006aa: 2200 movs r2, #0 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 80006b0: 4820 ldr r0, [pc, #128] @ (8000734 ) 80006b2: f002 fb53 bl 8002d5c /*Configure GPIO pins : PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80006b6: 2330 movs r3, #48 @ 0x30 80006b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ba: 2300 movs r3, #0 80006bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006be: 2302 movs r3, #2 80006c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006c2: f107 0314 add.w r3, r7, #20 80006c6: 4619 mov r1, r3 80006c8: 4819 ldr r0, [pc, #100] @ (8000730 ) 80006ca: f002 f99b bl 8002a04 /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; 80006ce: f240 4307 movw r3, #1031 @ 0x407 80006d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 2300 movs r3, #0 80006d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006d8: 2302 movs r3, #2 80006da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006dc: f107 0314 add.w r3, r7, #20 80006e0: 4619 mov r1, r3 80006e2: 4815 ldr r0, [pc, #84] @ (8000738 ) 80006e4: f002 f98e bl 8002a04 /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 80006ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006ee: 2301 movs r3, #1 80006f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006f2: 2300 movs r3, #0 80006f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006f6: 2300 movs r3, #0 80006f8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006fa: f107 0314 add.w r3, r7, #20 80006fe: 4619 mov r1, r3 8000700: 480b ldr r0, [pc, #44] @ (8000730 ) 8000702: f002 f97f bl 8002a04 /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000706: f44f 7380 mov.w r3, #256 @ 0x100 800070a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 2301 movs r3, #1 800070e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 2300 movs r3, #0 8000712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000714: 2300 movs r3, #0 8000716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000718: f107 0314 add.w r3, r7, #20 800071c: 4619 mov r1, r3 800071e: 4805 ldr r0, [pc, #20] @ (8000734 ) 8000720: f002 f970 bl 8002a04 } 8000724: bf00 nop 8000726: 3728 adds r7, #40 @ 0x28 8000728: 46bd mov sp, r7 800072a: bd80 pop {r7, pc} 800072c: 40023800 .word 0x40023800 8000730: 40020800 .word 0x40020800 8000734: 40020000 .word 0x40020000 8000738: 40020400 .word 0x40020400 0800073c : I2C_HandleTypeDef hi2c1; /* I2C1 init function */ void MX_I2C1_Init(void) { 800073c: b580 push {r7, lr} 800073e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000740: 4b12 ldr r3, [pc, #72] @ (800078c ) 8000742: 4a13 ldr r2, [pc, #76] @ (8000790 ) 8000744: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8000746: 4b11 ldr r3, [pc, #68] @ (800078c ) 8000748: 4a12 ldr r2, [pc, #72] @ (8000794 ) 800074a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800074c: 4b0f ldr r3, [pc, #60] @ (800078c ) 800074e: 2200 movs r2, #0 8000750: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8000752: 4b0e ldr r3, [pc, #56] @ (800078c ) 8000754: 2200 movs r2, #0 8000756: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000758: 4b0c ldr r3, [pc, #48] @ (800078c ) 800075a: f44f 4280 mov.w r2, #16384 @ 0x4000 800075e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000760: 4b0a ldr r3, [pc, #40] @ (800078c ) 8000762: 2200 movs r2, #0 8000764: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8000766: 4b09 ldr r3, [pc, #36] @ (800078c ) 8000768: 2200 movs r2, #0 800076a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800076c: 4b07 ldr r3, [pc, #28] @ (800078c ) 800076e: 2200 movs r2, #0 8000770: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000772: 4b06 ldr r3, [pc, #24] @ (800078c ) 8000774: 2200 movs r2, #0 8000776: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000778: 4804 ldr r0, [pc, #16] @ (800078c ) 800077a: f002 fb09 bl 8002d90 800077e: 4603 mov r3, r0 8000780: 2b00 cmp r3, #0 8000782: d001 beq.n 8000788 { Error_Handler(); 8000784: f000 fde2 bl 800134c } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000788: bf00 nop 800078a: bd80 pop {r7, pc} 800078c: 200001bc .word 0x200001bc 8000790: 40005400 .word 0x40005400 8000794: 000186a0 .word 0x000186a0 08000798 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 8000798: b580 push {r7, lr} 800079a: b08a sub sp, #40 @ 0x28 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007a0: f107 0314 add.w r3, r7, #20 80007a4: 2200 movs r2, #0 80007a6: 601a str r2, [r3, #0] 80007a8: 605a str r2, [r3, #4] 80007aa: 609a str r2, [r3, #8] 80007ac: 60da str r2, [r3, #12] 80007ae: 611a str r2, [r3, #16] if(i2cHandle->Instance==I2C1) 80007b0: 687b ldr r3, [r7, #4] 80007b2: 681b ldr r3, [r3, #0] 80007b4: 4a19 ldr r2, [pc, #100] @ (800081c ) 80007b6: 4293 cmp r3, r2 80007b8: d12b bne.n 8000812 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007ba: 2300 movs r3, #0 80007bc: 613b str r3, [r7, #16] 80007be: 4b18 ldr r3, [pc, #96] @ (8000820 ) 80007c0: 6b1b ldr r3, [r3, #48] @ 0x30 80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 ) 80007c4: f043 0302 orr.w r3, r3, #2 80007c8: 6313 str r3, [r2, #48] @ 0x30 80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 ) 80007cc: 6b1b ldr r3, [r3, #48] @ 0x30 80007ce: f003 0302 and.w r3, r3, #2 80007d2: 613b str r3, [r7, #16] 80007d4: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80007d6: 23c0 movs r3, #192 @ 0xc0 80007d8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80007da: 2312 movs r3, #18 80007dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80007de: 2300 movs r3, #0 80007e0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80007e2: 2303 movs r3, #3 80007e4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 80007e6: 2304 movs r3, #4 80007e8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80007ea: f107 0314 add.w r3, r7, #20 80007ee: 4619 mov r1, r3 80007f0: 480c ldr r0, [pc, #48] @ (8000824 ) 80007f2: f002 f907 bl 8002a04 /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 80007f6: 2300 movs r3, #0 80007f8: 60fb str r3, [r7, #12] 80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 ) 80007fc: 6c1b ldr r3, [r3, #64] @ 0x40 80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 ) 8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000804: 6413 str r3, [r2, #64] @ 0x40 8000806: 4b06 ldr r3, [pc, #24] @ (8000820 ) 8000808: 6c1b ldr r3, [r3, #64] @ 0x40 800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800080e: 60fb str r3, [r7, #12] 8000810: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000812: bf00 nop 8000814: 3728 adds r7, #40 @ 0x28 8000816: 46bd mov sp, r7 8000818: bd80 pop {r7, pc} 800081a: bf00 nop 800081c: 40005400 .word 0x40005400 8000820: 40023800 .word 0x40023800 8000824: 40020400 .word 0x40020400 08000828 : volatile uint8_t tail; // accessed in ISR volatile uint8_t count; // optional, only if needed } PacketQueue; // Initialize void pq_init(PacketQueue *q){ 8000828: b480 push {r7} 800082a: b083 sub sp, #12 800082c: af00 add r7, sp, #0 800082e: 6078 str r0, [r7, #4] q->head = 0; 8000830: 687b ldr r3, [r7, #4] 8000832: 2200 movs r2, #0 8000834: f883 2180 strb.w r2, [r3, #384] @ 0x180 q->tail = 0; 8000838: 687b ldr r3, [r7, #4] 800083a: 2200 movs r2, #0 800083c: f883 2181 strb.w r2, [r3, #385] @ 0x181 q->count = 0; 8000840: 687b ldr r3, [r7, #4] 8000842: 2200 movs r2, #0 8000844: f883 2182 strb.w r2, [r3, #386] @ 0x182 } 8000848: bf00 nop 800084a: 370c adds r7, #12 800084c: 46bd mov sp, r7 800084e: f85d 7b04 ldr.w r7, [sp], #4 8000852: 4770 bx lr 08000854 : // Called from ISR bool pq_push(PacketQueue *q, const uint8_t packet[PACKET_SIZE]){ 8000854: b580 push {r7, lr} 8000856: b084 sub sp, #16 8000858: af00 add r7, sp, #0 800085a: 6078 str r0, [r7, #4] 800085c: 6039 str r1, [r7, #0] uint8_t nextTail = (q->tail + 1) % QUEUE_CAPACITY; 800085e: 687b ldr r3, [r7, #4] 8000860: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 8000864: b2db uxtb r3, r3 8000866: 3301 adds r3, #1 8000868: 425a negs r2, r3 800086a: f003 031f and.w r3, r3, #31 800086e: f002 021f and.w r2, r2, #31 8000872: bf58 it pl 8000874: 4253 negpl r3, r2 8000876: 73fb strb r3, [r7, #15] if(nextTail == q->head) return false; // queue full 8000878: 687b ldr r3, [r7, #4] 800087a: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 800087e: b2db uxtb r3, r3 8000880: 7bfa ldrb r2, [r7, #15] 8000882: 429a cmp r2, r3 8000884: d101 bne.n 800088a 8000886: 2300 movs r3, #0 8000888: e014 b.n 80008b4 memcpy(q->data[q->tail], packet, PACKET_SIZE); 800088a: 687b ldr r3, [r7, #4] 800088c: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 8000890: b2db uxtb r3, r3 8000892: 461a mov r2, r3 8000894: 4613 mov r3, r2 8000896: 005b lsls r3, r3, #1 8000898: 4413 add r3, r2 800089a: 009b lsls r3, r3, #2 800089c: 687a ldr r2, [r7, #4] 800089e: 4413 add r3, r2 80008a0: 220c movs r2, #12 80008a2: 6839 ldr r1, [r7, #0] 80008a4: 4618 mov r0, r3 80008a6: f00a ffb7 bl 800b818 q->tail = nextTail; 80008aa: 687b ldr r3, [r7, #4] 80008ac: 7bfa ldrb r2, [r7, #15] 80008ae: f883 2181 strb.w r2, [r3, #385] @ 0x181 return true; 80008b2: 2301 movs r3, #1 } 80008b4: 4618 mov r0, r3 80008b6: 3710 adds r7, #16 80008b8: 46bd mov sp, r7 80008ba: bd80 pop {r7, pc} 080008bc : // Called from main bool pq_pop(PacketQueue *q, uint8_t out_packet[PACKET_SIZE]){ 80008bc: b580 push {r7, lr} 80008be: b082 sub sp, #8 80008c0: af00 add r7, sp, #0 80008c2: 6078 str r0, [r7, #4] 80008c4: 6039 str r1, [r7, #0] if(q->head == q->tail) return false; // queue empty 80008c6: 687b ldr r3, [r7, #4] 80008c8: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 80008cc: b2da uxtb r2, r3 80008ce: 687b ldr r3, [r7, #4] 80008d0: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 80008d4: b2db uxtb r3, r3 80008d6: 429a cmp r2, r3 80008d8: d101 bne.n 80008de 80008da: 2300 movs r3, #0 80008dc: e020 b.n 8000920 memcpy(out_packet, q->data[q->head], PACKET_SIZE); 80008de: 687b ldr r3, [r7, #4] 80008e0: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 80008e4: b2db uxtb r3, r3 80008e6: 461a mov r2, r3 80008e8: 4613 mov r3, r2 80008ea: 005b lsls r3, r3, #1 80008ec: 4413 add r3, r2 80008ee: 009b lsls r3, r3, #2 80008f0: 687a ldr r2, [r7, #4] 80008f2: 4413 add r3, r2 80008f4: 220c movs r2, #12 80008f6: 4619 mov r1, r3 80008f8: 6838 ldr r0, [r7, #0] 80008fa: f00a ff8d bl 800b818 q->head = (q->head + 1) % QUEUE_CAPACITY; 80008fe: 687b ldr r3, [r7, #4] 8000900: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 8000904: b2db uxtb r3, r3 8000906: 3301 adds r3, #1 8000908: 425a negs r2, r3 800090a: f003 031f and.w r3, r3, #31 800090e: f002 021f and.w r2, r2, #31 8000912: bf58 it pl 8000914: 4253 negpl r3, r2 8000916: b2da uxtb r2, r3 8000918: 687b ldr r3, [r7, #4] 800091a: f883 2180 strb.w r2, [r3, #384] @ 0x180 return true; 800091e: 2301 movs r3, #1 } 8000920: 4618 mov r0, r3 8000922: 3708 adds r7, #8 8000924: 46bd mov sp, r7 8000926: bd80 pop {r7, pc} 08000928
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000928: b580 push {r7, lr} 800092a: b088 sub sp, #32 800092c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800092e: f001 fabf bl 8001eb0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000932: f000 fa03 bl 8000d3c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000936: f7ff fe61 bl 80005fc MX_DMA_Init(); 800093a: f7ff fdf9 bl 8000530 MX_TIM2_Init(); 800093e: f000 fdf7 bl 8001530 MX_TIM3_Init(); 8000942: f000 fe4d bl 80015e0 MX_UART4_Init(); 8000946: f000 ff1f bl 8001788 MX_UART5_Init(); 800094a: f000 ff47 bl 80017dc MX_USART1_UART_Init(); 800094e: f000 ff6f bl 8001830 MX_USART2_UART_Init(); 8000952: f000 ff97 bl 8001884 MX_I2C1_Init(); 8000956: f7ff fef1 bl 800073c MX_USB_DEVICE_Init(); 800095a: f00a fa83 bl 800ae64 /* USER CODE BEGIN 2 */ //Enable UART RX DMA for all ports HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 800095e: 2210 movs r2, #16 8000960: 4956 ldr r1, [pc, #344] @ (8000abc ) 8000962: 4857 ldr r0, [pc, #348] @ (8000ac0 ) 8000964: f006 f884 bl 8006a70 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000968: 2210 movs r2, #16 800096a: 4956 ldr r1, [pc, #344] @ (8000ac4 ) 800096c: 4856 ldr r0, [pc, #344] @ (8000ac8 ) 800096e: f006 f87f bl 8006a70 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000972: 2210 movs r2, #16 8000974: 4955 ldr r1, [pc, #340] @ (8000acc ) 8000976: 4856 ldr r0, [pc, #344] @ (8000ad0 ) 8000978: f006 f87a bl 8006a70 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 800097c: 2210 movs r2, #16 800097e: 4955 ldr r1, [pc, #340] @ (8000ad4 ) 8000980: 4855 ldr r0, [pc, #340] @ (8000ad8 ) 8000982: f006 f875 bl 8006a70 // Start TIM3 encoder (PA6/PA7) so we can read encoder delta HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL); 8000986: 213c movs r1, #60 @ 0x3c 8000988: 4854 ldr r0, [pc, #336] @ (8000adc ) 800098a: f005 fa77 bl 8005e7c LAST_ENCODER_COUNT = __HAL_TIM_GET_COUNTER(&htim3); 800098e: 4b53 ldr r3, [pc, #332] @ (8000adc ) 8000990: 681b ldr r3, [r3, #0] 8000992: 6a5b ldr r3, [r3, #36] @ 0x24 8000994: 461a mov r2, r3 8000996: 4b52 ldr r3, [pc, #328] @ (8000ae0 ) 8000998: 601a str r2, [r3, #0] //Prealloc Kestate matrix memset(KEYSTATE, 0, sizeof(KEYSTATE)); 800099a: 221e movs r2, #30 800099c: 2100 movs r1, #0 800099e: 4851 ldr r0, [pc, #324] @ (8000ae4 ) 80009a0: f00a ff0e bl 800b7c0 pq_init(&huart1q); 80009a4: 4850 ldr r0, [pc, #320] @ (8000ae8 ) 80009a6: f7ff ff3f bl 8000828 pq_init(&huart2q); 80009aa: 4850 ldr r0, [pc, #320] @ (8000aec ) 80009ac: f7ff ff3c bl 8000828 pq_init(&huart4q); 80009b0: 484f ldr r0, [pc, #316] @ (8000af0 ) 80009b2: f7ff ff39 bl 8000828 pq_init(&huart5q); 80009b6: 484f ldr r0, [pc, #316] @ (8000af4 ) 80009b8: f7ff ff36 bl 8000828 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { switch (MODE){ 80009bc: 4b4e ldr r3, [pc, #312] @ (8000af8 ) 80009be: 781b ldrb r3, [r3, #0] 80009c0: b2db uxtb r3, r3 80009c2: 2b02 cmp r3, #2 80009c4: d006 beq.n 80009d4 80009c6: 2b02 cmp r3, #2 80009c8: dc6e bgt.n 8000aa8 80009ca: 2b00 cmp r3, #0 80009cc: d027 beq.n 8000a1e 80009ce: 2b01 cmp r3, #1 80009d0: d05c beq.n 8000a8c encoderProcess(); USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); break; default: break; 80009d2: e069 b.n 8000aa8 KEYSTATE_CHANGED_FLAG = 1; 80009d4: 4b49 ldr r3, [pc, #292] @ (8000afc ) 80009d6: 2201 movs r2, #1 80009d8: 701a strb r2, [r3, #0] resetReport(); 80009da: f000 fcab bl 8001334 matrixScan(); 80009de: f000 fbd9 bl 8001194 mergeChild(); 80009e2: f000 f927 bl 8000c34 encoderProcess(); 80009e6: f000 fc4d bl 8001284 if(KEYSTATE_CHANGED_FLAG == 1){ 80009ea: 4b44 ldr r3, [pc, #272] @ (8000afc ) 80009ec: 781b ldrb r3, [r3, #0] 80009ee: 2b01 cmp r3, #1 80009f0: d15c bne.n 8000aac UARTREPORT.DEPTH = DEPTH; 80009f2: 4b43 ldr r3, [pc, #268] @ (8000b00 ) 80009f4: 881b ldrh r3, [r3, #0] 80009f6: 823b strh r3, [r7, #16] UARTREPORT.TYPE = 0xEE; 80009f8: 23ee movs r3, #238 @ 0xee 80009fa: 827b strh r3, [r7, #18] memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS)); 80009fc: 4a41 ldr r2, [pc, #260] @ (8000b04 ) 80009fe: f107 0314 add.w r3, r7, #20 8000a02: 3202 adds r2, #2 8000a04: 6810 ldr r0, [r2, #0] 8000a06: 6851 ldr r1, [r2, #4] 8000a08: 6892 ldr r2, [r2, #8] 8000a0a: c307 stmia r3!, {r0, r1, r2} HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT)); 8000a0c: 4b3e ldr r3, [pc, #248] @ (8000b08 ) 8000a0e: 681b ldr r3, [r3, #0] 8000a10: f107 0110 add.w r1, r7, #16 8000a14: 2210 movs r2, #16 8000a16: 4618 mov r0, r3 8000a18: f005 ffae bl 8006978 break; 8000a1c: e046 b.n 8000aac if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ 8000a1e: 4b3b ldr r3, [pc, #236] @ (8000b0c ) 8000a20: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8000a24: b2db uxtb r3, r3 8000a26: 2b03 cmp r3, #3 8000a28: d106 bne.n 8000a38 MODE = MODE_MAINBOARD; 8000a2a: 4b33 ldr r3, [pc, #204] @ (8000af8 ) 8000a2c: 2201 movs r2, #1 8000a2e: 701a strb r2, [r3, #0] DEPTH = 0; 8000a30: 4b33 ldr r3, [pc, #204] @ (8000b00 ) 8000a32: 2200 movs r2, #0 8000a34: 801a strh r2, [r3, #0] break; 8000a36: e03a b.n 8000aae REQ.DEPTH = 0; 8000a38: 2300 movs r3, #0 8000a3a: 803b strh r3, [r7, #0] REQ.TYPE = 0xFF; //Message code for request is 0xFF 8000a3c: 23ff movs r3, #255 @ 0xff 8000a3e: 807b strh r3, [r7, #2] memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); 8000a40: 463b mov r3, r7 8000a42: 3304 adds r3, #4 8000a44: 220c movs r2, #12 8000a46: 2100 movs r1, #0 8000a48: 4618 mov r0, r3 8000a4a: f00a feb9 bl 800b7c0 HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); 8000a4e: 463b mov r3, r7 8000a50: 2210 movs r2, #16 8000a52: 4619 mov r1, r3 8000a54: 481a ldr r0, [pc, #104] @ (8000ac0 ) 8000a56: f005 ff8f bl 8006978 HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); 8000a5a: 463b mov r3, r7 8000a5c: 2210 movs r2, #16 8000a5e: 4619 mov r1, r3 8000a60: 4819 ldr r0, [pc, #100] @ (8000ac8 ) 8000a62: f005 ff89 bl 8006978 HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); 8000a66: 463b mov r3, r7 8000a68: 2210 movs r2, #16 8000a6a: 4619 mov r1, r3 8000a6c: 4818 ldr r0, [pc, #96] @ (8000ad0 ) 8000a6e: f005 ff83 bl 8006978 HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); 8000a72: 463b mov r3, r7 8000a74: 2210 movs r2, #16 8000a76: 4619 mov r1, r3 8000a78: 4817 ldr r0, [pc, #92] @ (8000ad8 ) 8000a7a: f005 ff7d bl 8006978 HAL_Delay(500); 8000a7e: f44f 70fa mov.w r0, #500 @ 0x1f4 8000a82: f001 fa87 bl 8001f94 findBestParent(); //So true... 8000a86: f000 fa6d bl 8000f64 break; 8000a8a: e010 b.n 8000aae resetReport(); 8000a8c: f000 fc52 bl 8001334 matrixScan();//Something related to this making the key stick. Likely due to race conditions 8000a90: f000 fb80 bl 8001194 mergeChild(); 8000a94: f000 f8ce bl 8000c34 encoderProcess(); 8000a98: f000 fbf4 bl 8001284 USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); 8000a9c: 220e movs r2, #14 8000a9e: 4919 ldr r1, [pc, #100] @ (8000b04 ) 8000aa0: 481a ldr r0, [pc, #104] @ (8000b0c ) 8000aa2: f008 fe13 bl 80096cc break; 8000aa6: e002 b.n 8000aae break; 8000aa8: bf00 nop 8000aaa: e000 b.n 8000aae break; 8000aac: bf00 nop } RGBProcess(); 8000aae: f000 f82f bl 8000b10 HAL_Delay(1); 8000ab2: 2001 movs r0, #1 8000ab4: f001 fa6e bl 8001f94 switch (MODE){ 8000ab8: e780 b.n 80009bc 8000aba: bf00 nop 8000abc: 200003b0 .word 0x200003b0 8000ac0: 20000b70 .word 0x20000b70 8000ac4: 200003c0 .word 0x200003c0 8000ac8: 20000bb8 .word 0x20000bb8 8000acc: 200003d0 .word 0x200003d0 8000ad0: 20000ae0 .word 0x20000ae0 8000ad4: 200003a0 .word 0x200003a0 8000ad8: 20000b28 .word 0x20000b28 8000adc: 20000a98 .word 0x20000a98 8000ae0: 2000040c .word 0x2000040c 8000ae4: 200003ec .word 0x200003ec 8000ae8: 20000440 .word 0x20000440 8000aec: 200005c4 .word 0x200005c4 8000af0: 20000748 .word 0x20000748 8000af4: 200008cc .word 0x200008cc 8000af8: 2000040a .word 0x2000040a 8000afc: 200003e8 .word 0x200003e8 8000b00: 200003e0 .word 0x200003e0 8000b04: 20000390 .word 0x20000390 8000b08: 200003e4 .word 0x200003e4 8000b0c: 20000f08 .word 0x20000f08 08000b10 : /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ } void RGBProcess(){ 8000b10: b580 push {r7, lr} 8000b12: b082 sub sp, #8 8000b14: af00 add r7, sp, #0 uint8_t red = 255; 8000b16: 23ff movs r3, #255 @ 0xff 8000b18: 71fb strb r3, [r7, #7] uint8_t blue = 256/2; 8000b1a: 2380 movs r3, #128 @ 0x80 8000b1c: 71bb strb r3, [r7, #6] uint8_t green = 0; 8000b1e: 2300 movs r3, #0 8000b20: 717b strb r3, [r7, #5] for(int i = 0; i < LED_COUNT; i++){ 8000b22: 2300 movs r3, #0 8000b24: 603b str r3, [r7, #0] 8000b26: e011 b.n 8000b4c setRGBcolor(i, red, blue, green); 8000b28: 797b ldrb r3, [r7, #5] 8000b2a: 79ba ldrb r2, [r7, #6] 8000b2c: 79f9 ldrb r1, [r7, #7] 8000b2e: 6838 ldr r0, [r7, #0] 8000b30: f000 f816 bl 8000b60 red += 10; 8000b34: 79fb ldrb r3, [r7, #7] 8000b36: 330a adds r3, #10 8000b38: 71fb strb r3, [r7, #7] blue+= 10; 8000b3a: 79bb ldrb r3, [r7, #6] 8000b3c: 330a adds r3, #10 8000b3e: 71bb strb r3, [r7, #6] green += 10; 8000b40: 797b ldrb r3, [r7, #5] 8000b42: 330a adds r3, #10 8000b44: 717b strb r3, [r7, #5] for(int i = 0; i < LED_COUNT; i++){ 8000b46: 683b ldr r3, [r7, #0] 8000b48: 3301 adds r3, #1 8000b4a: 603b str r3, [r7, #0] 8000b4c: 683b ldr r3, [r7, #0] 8000b4e: 2b07 cmp r3, #7 8000b50: ddea ble.n 8000b28 } sendRGBcolor(); 8000b52: f000 f861 bl 8000c18 } 8000b56: bf00 nop 8000b58: 3708 adds r7, #8 8000b5a: 46bd mov sp, r7 8000b5c: bd80 pop {r7, pc} ... 08000b60 : //Sets each bit in the buffer that is going to get sent thru PWM DMA void setRGBcolor(int index, uint8_t r, uint8_t g, uint8_t b) { 8000b60: b480 push {r7} 8000b62: b087 sub sp, #28 8000b64: af00 add r7, sp, #0 8000b66: 6078 str r0, [r7, #4] 8000b68: 4608 mov r0, r1 8000b6a: 4611 mov r1, r2 8000b6c: 461a mov r2, r3 8000b6e: 4603 mov r3, r0 8000b70: 70fb strb r3, [r7, #3] 8000b72: 460b mov r3, r1 8000b74: 70bb strb r3, [r7, #2] 8000b76: 4613 mov r3, r2 8000b78: 707b strb r3, [r7, #1] uint8_t colors[3] = {g, r, b}; 8000b7a: 78bb ldrb r3, [r7, #2] 8000b7c: 733b strb r3, [r7, #12] 8000b7e: 78fb ldrb r3, [r7, #3] 8000b80: 737b strb r3, [r7, #13] 8000b82: 787b ldrb r3, [r7, #1] 8000b84: 73bb strb r3, [r7, #14] for (int c = 0; c < 3; c++) { 8000b86: 2300 movs r3, #0 8000b88: 617b str r3, [r7, #20] 8000b8a: e039 b.n 8000c00 for (int bit = 0; bit < 8; bit++) { 8000b8c: 2300 movs r3, #0 8000b8e: 613b str r3, [r7, #16] 8000b90: e030 b.n 8000bf4 if (colors[c] & (1 << (7 - bit))) { 8000b92: f107 020c add.w r2, r7, #12 8000b96: 697b ldr r3, [r7, #20] 8000b98: 4413 add r3, r2 8000b9a: 781b ldrb r3, [r3, #0] 8000b9c: 461a mov r2, r3 8000b9e: 693b ldr r3, [r7, #16] 8000ba0: f1c3 0307 rsb r3, r3, #7 8000ba4: fa42 f303 asr.w r3, r2, r3 8000ba8: f003 0301 and.w r3, r3, #1 8000bac: 2b00 cmp r3, #0 8000bae: d00f beq.n 8000bd0 led_buffer[index * 24 + (c * 8 + bit)] = T1H; 8000bb0: 687a ldr r2, [r7, #4] 8000bb2: 4613 mov r3, r2 8000bb4: 005b lsls r3, r3, #1 8000bb6: 4413 add r3, r2 8000bb8: 00db lsls r3, r3, #3 8000bba: 4619 mov r1, r3 8000bbc: 697b ldr r3, [r7, #20] 8000bbe: 00da lsls r2, r3, #3 8000bc0: 693b ldr r3, [r7, #16] 8000bc2: 4413 add r3, r2 8000bc4: 440b add r3, r1 8000bc6: 4a13 ldr r2, [pc, #76] @ (8000c14 ) 8000bc8: 2104 movs r1, #4 8000bca: f822 1013 strh.w r1, [r2, r3, lsl #1] 8000bce: e00e b.n 8000bee } else { led_buffer[index * 24 + (c * 8 + bit)] = T0H; 8000bd0: 687a ldr r2, [r7, #4] 8000bd2: 4613 mov r3, r2 8000bd4: 005b lsls r3, r3, #1 8000bd6: 4413 add r3, r2 8000bd8: 00db lsls r3, r3, #3 8000bda: 4619 mov r1, r3 8000bdc: 697b ldr r3, [r7, #20] 8000bde: 00da lsls r2, r3, #3 8000be0: 693b ldr r3, [r7, #16] 8000be2: 4413 add r3, r2 8000be4: 440b add r3, r1 8000be6: 4a0b ldr r2, [pc, #44] @ (8000c14 ) 8000be8: 2103 movs r1, #3 8000bea: f822 1013 strh.w r1, [r2, r3, lsl #1] for (int bit = 0; bit < 8; bit++) { 8000bee: 693b ldr r3, [r7, #16] 8000bf0: 3301 adds r3, #1 8000bf2: 613b str r3, [r7, #16] 8000bf4: 693b ldr r3, [r7, #16] 8000bf6: 2b07 cmp r3, #7 8000bf8: ddcb ble.n 8000b92 for (int c = 0; c < 3; c++) { 8000bfa: 697b ldr r3, [r7, #20] 8000bfc: 3301 adds r3, #1 8000bfe: 617b str r3, [r7, #20] 8000c00: 697b ldr r3, [r7, #20] 8000c02: 2b02 cmp r3, #2 8000c04: ddc2 ble.n 8000b8c } } } } 8000c06: bf00 nop 8000c08: bf00 nop 8000c0a: 371c adds r7, #28 8000c0c: 46bd mov sp, r7 8000c0e: f85d 7b04 ldr.w r7, [sp], #4 8000c12: 4770 bx lr 8000c14: 20000210 .word 0x20000210 08000c18 : //Sends whats on the buffer thru DMA void sendRGBcolor(){ 8000c18: b580 push {r7, lr} 8000c1a: af00 add r7, sp, #0 HAL_TIM_PWM_Start_DMA(&htim2, TIM_CHANNEL_1,(uint32_t*)led_buffer,LED_BUFFER_SIZE); 8000c1c: 23c0 movs r3, #192 @ 0xc0 8000c1e: 4a03 ldr r2, [pc, #12] @ (8000c2c ) 8000c20: 2100 movs r1, #0 8000c22: 4803 ldr r0, [pc, #12] @ (8000c30 ) 8000c24: f004 fdea bl 80057fc } 8000c28: bf00 nop 8000c2a: bd80 pop {r7, pc} 8000c2c: 20000210 .word 0x20000210 8000c30: 20000a50 .word 0x20000a50 08000c34 : void mergeChild(){ 8000c34: b590 push {r4, r7, lr} 8000c36: b087 sub sp, #28 8000c38: af00 add r7, sp, #0 uint8_t packet[12]; if (pq_pop(&huart1q, packet)) { 8000c3a: 1d3b adds r3, r7, #4 8000c3c: 4619 mov r1, r3 8000c3e: 4838 ldr r0, [pc, #224] @ (8000d20 ) 8000c40: f7ff fe3c bl 80008bc 8000c44: 4603 mov r3, r0 8000c46: 2b00 cmp r3, #0 8000c48: d008 beq.n 8000c5c memcpy(UART_KEYSTATE[1], packet, 12); 8000c4a: 4b36 ldr r3, [pc, #216] @ (8000d24 ) 8000c4c: 330c adds r3, #12 8000c4e: 1d3a adds r2, r7, #4 8000c50: ca07 ldmia r2, {r0, r1, r2} 8000c52: e883 0007 stmia.w r3, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000c56: 4b34 ldr r3, [pc, #208] @ (8000d28 ) 8000c58: 2201 movs r2, #1 8000c5a: 701a strb r2, [r3, #0] } if (pq_pop(&huart2q, packet)) { 8000c5c: 1d3b adds r3, r7, #4 8000c5e: 4619 mov r1, r3 8000c60: 4832 ldr r0, [pc, #200] @ (8000d2c ) 8000c62: f7ff fe2b bl 80008bc 8000c66: 4603 mov r3, r0 8000c68: 2b00 cmp r3, #0 8000c6a: d008 beq.n 8000c7e memcpy(UART_KEYSTATE[2], packet, 12); 8000c6c: 4b2d ldr r3, [pc, #180] @ (8000d24 ) 8000c6e: 3318 adds r3, #24 8000c70: 1d3a adds r2, r7, #4 8000c72: ca07 ldmia r2, {r0, r1, r2} 8000c74: e883 0007 stmia.w r3, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000c78: 4b2b ldr r3, [pc, #172] @ (8000d28 ) 8000c7a: 2201 movs r2, #1 8000c7c: 701a strb r2, [r3, #0] } if (pq_pop(&huart4q, packet)) { 8000c7e: 1d3b adds r3, r7, #4 8000c80: 4619 mov r1, r3 8000c82: 482b ldr r0, [pc, #172] @ (8000d30 ) 8000c84: f7ff fe1a bl 80008bc 8000c88: 4603 mov r3, r0 8000c8a: 2b00 cmp r3, #0 8000c8c: d008 beq.n 8000ca0 memcpy(UART_KEYSTATE[3], packet, 12); 8000c8e: 4b25 ldr r3, [pc, #148] @ (8000d24 ) 8000c90: 3324 adds r3, #36 @ 0x24 8000c92: 1d3a adds r2, r7, #4 8000c94: ca07 ldmia r2, {r0, r1, r2} 8000c96: e883 0007 stmia.w r3, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000c9a: 4b23 ldr r3, [pc, #140] @ (8000d28 ) 8000c9c: 2201 movs r2, #1 8000c9e: 701a strb r2, [r3, #0] } if (pq_pop(&huart5q, packet)) { 8000ca0: 1d3b adds r3, r7, #4 8000ca2: 4619 mov r1, r3 8000ca4: 4823 ldr r0, [pc, #140] @ (8000d34 ) 8000ca6: f7ff fe09 bl 80008bc 8000caa: 4603 mov r3, r0 8000cac: 2b00 cmp r3, #0 8000cae: d009 beq.n 8000cc4 memcpy(UART_KEYSTATE[0], packet, 12); 8000cb0: 4b1c ldr r3, [pc, #112] @ (8000d24 ) 8000cb2: 461c mov r4, r3 8000cb4: 1d3b adds r3, r7, #4 8000cb6: e893 0007 ldmia.w r3, {r0, r1, r2} 8000cba: e884 0007 stmia.w r4, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000cbe: 4b1a ldr r3, [pc, #104] @ (8000d28 ) 8000cc0: 2201 movs r2, #1 8000cc2: 701a strb r2, [r3, #0] } for(int i = 0; i < 4; i++){ 8000cc4: 2300 movs r3, #0 8000cc6: 617b str r3, [r7, #20] 8000cc8: e022 b.n 8000d10 for(int j = 0; j < 12; j++){ 8000cca: 2300 movs r3, #0 8000ccc: 613b str r3, [r7, #16] 8000cce: e019 b.n 8000d04 REPORT.KEYPRESS[j] |= UART_KEYSTATE[i][j]; 8000cd0: 4a19 ldr r2, [pc, #100] @ (8000d38 ) 8000cd2: 693b ldr r3, [r7, #16] 8000cd4: 4413 add r3, r2 8000cd6: 3302 adds r3, #2 8000cd8: 7819 ldrb r1, [r3, #0] 8000cda: 4812 ldr r0, [pc, #72] @ (8000d24 ) 8000cdc: 697a ldr r2, [r7, #20] 8000cde: 4613 mov r3, r2 8000ce0: 005b lsls r3, r3, #1 8000ce2: 4413 add r3, r2 8000ce4: 009b lsls r3, r3, #2 8000ce6: 18c2 adds r2, r0, r3 8000ce8: 693b ldr r3, [r7, #16] 8000cea: 4413 add r3, r2 8000cec: 781b ldrb r3, [r3, #0] 8000cee: 430b orrs r3, r1 8000cf0: b2d9 uxtb r1, r3 8000cf2: 4a11 ldr r2, [pc, #68] @ (8000d38 ) 8000cf4: 693b ldr r3, [r7, #16] 8000cf6: 4413 add r3, r2 8000cf8: 3302 adds r3, #2 8000cfa: 460a mov r2, r1 8000cfc: 701a strb r2, [r3, #0] for(int j = 0; j < 12; j++){ 8000cfe: 693b ldr r3, [r7, #16] 8000d00: 3301 adds r3, #1 8000d02: 613b str r3, [r7, #16] 8000d04: 693b ldr r3, [r7, #16] 8000d06: 2b0b cmp r3, #11 8000d08: dde2 ble.n 8000cd0 for(int i = 0; i < 4; i++){ 8000d0a: 697b ldr r3, [r7, #20] 8000d0c: 3301 adds r3, #1 8000d0e: 617b str r3, [r7, #20] 8000d10: 697b ldr r3, [r7, #20] 8000d12: 2b03 cmp r3, #3 8000d14: ddd9 ble.n 8000cca } } } 8000d16: bf00 nop 8000d18: bf00 nop 8000d1a: 371c adds r7, #28 8000d1c: 46bd mov sp, r7 8000d1e: bd90 pop {r4, r7, pc} 8000d20: 20000440 .word 0x20000440 8000d24: 20000410 .word 0x20000410 8000d28: 200003e8 .word 0x200003e8 8000d2c: 200005c4 .word 0x200005c4 8000d30: 20000748 .word 0x20000748 8000d34: 200008cc .word 0x200008cc 8000d38: 20000390 .word 0x20000390 08000d3c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000d3c: b580 push {r7, lr} 8000d3e: b094 sub sp, #80 @ 0x50 8000d40: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000d42: f107 031c add.w r3, r7, #28 8000d46: 2234 movs r2, #52 @ 0x34 8000d48: 2100 movs r1, #0 8000d4a: 4618 mov r0, r3 8000d4c: f00a fd38 bl 800b7c0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000d50: f107 0308 add.w r3, r7, #8 8000d54: 2200 movs r2, #0 8000d56: 601a str r2, [r3, #0] 8000d58: 605a str r2, [r3, #4] 8000d5a: 609a str r2, [r3, #8] 8000d5c: 60da str r2, [r3, #12] 8000d5e: 611a str r2, [r3, #16] /** Configure the main internal regulator out put voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000d60: 2300 movs r3, #0 8000d62: 607b str r3, [r7, #4] 8000d64: 4b29 ldr r3, [pc, #164] @ (8000e0c ) 8000d66: 6c1b ldr r3, [r3, #64] @ 0x40 8000d68: 4a28 ldr r2, [pc, #160] @ (8000e0c ) 8000d6a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000d6e: 6413 str r3, [r2, #64] @ 0x40 8000d70: 4b26 ldr r3, [pc, #152] @ (8000e0c ) 8000d72: 6c1b ldr r3, [r3, #64] @ 0x40 8000d74: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000d78: 607b str r3, [r7, #4] 8000d7a: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 8000d7c: 2300 movs r3, #0 8000d7e: 603b str r3, [r7, #0] 8000d80: 4b23 ldr r3, [pc, #140] @ (8000e10 ) 8000d82: 681b ldr r3, [r3, #0] 8000d84: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8000d88: 4a21 ldr r2, [pc, #132] @ (8000e10 ) 8000d8a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000d8e: 6013 str r3, [r2, #0] 8000d90: 4b1f ldr r3, [pc, #124] @ (8000e10 ) 8000d92: 681b ldr r3, [r3, #0] 8000d94: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000d98: 603b str r3, [r7, #0] 8000d9a: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000d9c: 2301 movs r3, #1 8000d9e: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000da0: f44f 3380 mov.w r3, #65536 @ 0x10000 8000da4: 623b str r3, [r7, #32] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000da6: 2302 movs r3, #2 8000da8: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000daa: f44f 0380 mov.w r3, #4194304 @ 0x400000 8000dae: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 8000db0: 2304 movs r3, #4 8000db2: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 96; 8000db4: 2360 movs r3, #96 @ 0x60 8000db6: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000db8: 2302 movs r3, #2 8000dba: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 8000dbc: 2304 movs r3, #4 8000dbe: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 8000dc0: 2302 movs r3, #2 8000dc2: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000dc4: f107 031c add.w r3, r7, #28 8000dc8: 4618 mov r0, r3 8000dca: f004 fa1f bl 800520c 8000dce: 4603 mov r3, r0 8000dd0: 2b00 cmp r3, #0 8000dd2: d001 beq.n 8000dd8 { Error_Handler(); 8000dd4: f000 faba bl 800134c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000dd8: 230f movs r3, #15 8000dda: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000ddc: 2302 movs r3, #2 8000dde: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; 8000de0: 2380 movs r3, #128 @ 0x80 8000de2: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000de4: f44f 5380 mov.w r3, #4096 @ 0x1000 8000de8: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000dea: 2300 movs r3, #0 8000dec: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000dee: f107 0308 add.w r3, r7, #8 8000df2: 2101 movs r1, #1 8000df4: 4618 mov r0, r3 8000df6: f003 fb95 bl 8004524 8000dfa: 4603 mov r3, r0 8000dfc: 2b00 cmp r3, #0 8000dfe: d001 beq.n 8000e04 { Error_Handler(); 8000e00: f000 faa4 bl 800134c } } 8000e04: bf00 nop 8000e06: 3750 adds r7, #80 @ 0x50 8000e08: 46bd mov sp, r7 8000e0a: bd80 pop {r7, pc} 8000e0c: 40023800 .word 0x40023800 8000e10: 40007000 .word 0x40007000 08000e14 : /* USER CODE BEGIN 4 */ // UART Message Requests Goes Here void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000e14: b580 push {r7, lr} 8000e16: b082 sub sp, #8 8000e18: af00 add r7, sp, #0 8000e1a: 6078 str r0, [r7, #4] if (huart->Instance == USART1) { 8000e1c: 687b ldr r3, [r7, #4] 8000e1e: 681b ldr r3, [r3, #0] 8000e20: 4a1e ldr r2, [pc, #120] @ (8000e9c ) 8000e22: 4293 cmp r3, r2 8000e24: d109 bne.n 8000e3a handleUARTMessages((uint8_t*)&RX1Msg, &huart1); 8000e26: 491e ldr r1, [pc, #120] @ (8000ea0 ) 8000e28: 481e ldr r0, [pc, #120] @ (8000ea4 ) 8000e2a: f000 f8dd bl 8000fe8 HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000e2e: 2210 movs r2, #16 8000e30: 491c ldr r1, [pc, #112] @ (8000ea4 ) 8000e32: 481b ldr r0, [pc, #108] @ (8000ea0 ) 8000e34: f005 fe1c bl 8006a70 } else if (huart->Instance == UART5) { handleUARTMessages((uint8_t*)&RX5Msg, &huart5); HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000e38: e02b b.n 8000e92 else if (huart->Instance == USART2) { 8000e3a: 687b ldr r3, [r7, #4] 8000e3c: 681b ldr r3, [r3, #0] 8000e3e: 4a1a ldr r2, [pc, #104] @ (8000ea8 ) 8000e40: 4293 cmp r3, r2 8000e42: d109 bne.n 8000e58 handleUARTMessages((uint8_t*)&RX2Msg, &huart2); 8000e44: 4919 ldr r1, [pc, #100] @ (8000eac ) 8000e46: 481a ldr r0, [pc, #104] @ (8000eb0 ) 8000e48: f000 f8ce bl 8000fe8 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000e4c: 2210 movs r2, #16 8000e4e: 4918 ldr r1, [pc, #96] @ (8000eb0 ) 8000e50: 4816 ldr r0, [pc, #88] @ (8000eac ) 8000e52: f005 fe0d bl 8006a70 } 8000e56: e01c b.n 8000e92 else if (huart->Instance == UART4) { 8000e58: 687b ldr r3, [r7, #4] 8000e5a: 681b ldr r3, [r3, #0] 8000e5c: 4a15 ldr r2, [pc, #84] @ (8000eb4 ) 8000e5e: 4293 cmp r3, r2 8000e60: d109 bne.n 8000e76 handleUARTMessages((uint8_t*)&RX4Msg, &huart4); 8000e62: 4915 ldr r1, [pc, #84] @ (8000eb8 ) 8000e64: 4815 ldr r0, [pc, #84] @ (8000ebc ) 8000e66: f000 f8bf bl 8000fe8 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000e6a: 2210 movs r2, #16 8000e6c: 4913 ldr r1, [pc, #76] @ (8000ebc ) 8000e6e: 4812 ldr r0, [pc, #72] @ (8000eb8 ) 8000e70: f005 fdfe bl 8006a70 } 8000e74: e00d b.n 8000e92 else if (huart->Instance == UART5) { 8000e76: 687b ldr r3, [r7, #4] 8000e78: 681b ldr r3, [r3, #0] 8000e7a: 4a11 ldr r2, [pc, #68] @ (8000ec0 ) 8000e7c: 4293 cmp r3, r2 8000e7e: d108 bne.n 8000e92 handleUARTMessages((uint8_t*)&RX5Msg, &huart5); 8000e80: 4910 ldr r1, [pc, #64] @ (8000ec4 ) 8000e82: 4811 ldr r0, [pc, #68] @ (8000ec8 ) 8000e84: f000 f8b0 bl 8000fe8 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000e88: 2210 movs r2, #16 8000e8a: 490f ldr r1, [pc, #60] @ (8000ec8 ) 8000e8c: 480d ldr r0, [pc, #52] @ (8000ec4 ) 8000e8e: f005 fdef bl 8006a70 } 8000e92: bf00 nop 8000e94: 3708 adds r7, #8 8000e96: 46bd mov sp, r7 8000e98: bd80 pop {r7, pc} 8000e9a: bf00 nop 8000e9c: 40011000 .word 0x40011000 8000ea0: 20000b70 .word 0x20000b70 8000ea4: 200003b0 .word 0x200003b0 8000ea8: 40004400 .word 0x40004400 8000eac: 20000bb8 .word 0x20000bb8 8000eb0: 200003c0 .word 0x200003c0 8000eb4: 40004c00 .word 0x40004c00 8000eb8: 20000ae0 .word 0x20000ae0 8000ebc: 200003d0 .word 0x200003d0 8000ec0: 40005000 .word 0x40005000 8000ec4: 20000b28 .word 0x20000b28 8000ec8: 200003a0 .word 0x200003a0 08000ecc : void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8000ecc: b580 push {r7, lr} 8000ece: b082 sub sp, #8 8000ed0: af00 add r7, sp, #0 8000ed2: 6078 str r0, [r7, #4] // Restart DMA on error if (huart->Instance == USART1) { 8000ed4: 687b ldr r3, [r7, #4] 8000ed6: 681b ldr r3, [r3, #0] 8000ed8: 4a16 ldr r2, [pc, #88] @ (8000f34 ) 8000eda: 4293 cmp r3, r2 8000edc: d105 bne.n 8000eea HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000ede: 2210 movs r2, #16 8000ee0: 4915 ldr r1, [pc, #84] @ (8000f38 ) 8000ee2: 4816 ldr r0, [pc, #88] @ (8000f3c ) 8000ee4: f005 fdc4 bl 8006a70 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); } else if (huart->Instance == UART5) { HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000ee8: e01f b.n 8000f2a else if (huart->Instance == USART2) { 8000eea: 687b ldr r3, [r7, #4] 8000eec: 681b ldr r3, [r3, #0] 8000eee: 4a14 ldr r2, [pc, #80] @ (8000f40 ) 8000ef0: 4293 cmp r3, r2 8000ef2: d105 bne.n 8000f00 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000ef4: 2210 movs r2, #16 8000ef6: 4913 ldr r1, [pc, #76] @ (8000f44 ) 8000ef8: 4813 ldr r0, [pc, #76] @ (8000f48 ) 8000efa: f005 fdb9 bl 8006a70 } 8000efe: e014 b.n 8000f2a else if (huart->Instance == UART4) { 8000f00: 687b ldr r3, [r7, #4] 8000f02: 681b ldr r3, [r3, #0] 8000f04: 4a11 ldr r2, [pc, #68] @ (8000f4c ) 8000f06: 4293 cmp r3, r2 8000f08: d105 bne.n 8000f16 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000f0a: 2210 movs r2, #16 8000f0c: 4910 ldr r1, [pc, #64] @ (8000f50 ) 8000f0e: 4811 ldr r0, [pc, #68] @ (8000f54 ) 8000f10: f005 fdae bl 8006a70 } 8000f14: e009 b.n 8000f2a else if (huart->Instance == UART5) { 8000f16: 687b ldr r3, [r7, #4] 8000f18: 681b ldr r3, [r3, #0] 8000f1a: 4a0f ldr r2, [pc, #60] @ (8000f58 ) 8000f1c: 4293 cmp r3, r2 8000f1e: d104 bne.n 8000f2a HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000f20: 2210 movs r2, #16 8000f22: 490e ldr r1, [pc, #56] @ (8000f5c ) 8000f24: 480e ldr r0, [pc, #56] @ (8000f60 ) 8000f26: f005 fda3 bl 8006a70 } 8000f2a: bf00 nop 8000f2c: 3708 adds r7, #8 8000f2e: 46bd mov sp, r7 8000f30: bd80 pop {r7, pc} 8000f32: bf00 nop 8000f34: 40011000 .word 0x40011000 8000f38: 200003b0 .word 0x200003b0 8000f3c: 20000b70 .word 0x20000b70 8000f40: 40004400 .word 0x40004400 8000f44: 200003c0 .word 0x200003c0 8000f48: 20000bb8 .word 0x20000bb8 8000f4c: 40004c00 .word 0x40004c00 8000f50: 200003d0 .word 0x200003d0 8000f54: 20000ae0 .word 0x20000ae0 8000f58: 40005000 .word 0x40005000 8000f5c: 200003a0 .word 0x200003a0 8000f60: 20000b28 .word 0x20000b28 08000f64 : void findBestParent(){ 8000f64: b580 push {r7, lr} 8000f66: b084 sub sp, #16 8000f68: af00 add r7, sp, #0 //Find least depth parent uint16_t least_val = 0xFF; 8000f6a: 23ff movs r3, #255 @ 0xff 8000f6c: 81fb strh r3, [r7, #14] UART_HandleTypeDef* least_port = NULL; 8000f6e: 2300 movs r3, #0 8000f70: 60bb str r3, [r7, #8] for(uint8_t i = 0; i < 4; i++){ 8000f72: 2300 movs r3, #0 8000f74: 71fb strb r3, [r7, #7] 8000f76: e013 b.n 8000fa0 if(PORT_DEPTH[i]) 8000f7c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000f80: 89fa ldrh r2, [r7, #14] 8000f82: 429a cmp r2, r3 8000f84: d909 bls.n 8000f9a least_port = PORTS[i]; 8000f86: 79fb ldrb r3, [r7, #7] 8000f88: 4a13 ldr r2, [pc, #76] @ (8000fd8 ) 8000f8a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000f8e: 60bb str r3, [r7, #8] least_val = PORT_DEPTH[i]; 8000f90: 79fb ldrb r3, [r7, #7] 8000f92: 4a10 ldr r2, [pc, #64] @ (8000fd4 ) 8000f94: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000f98: 81fb strh r3, [r7, #14] for(uint8_t i = 0; i < 4; i++){ 8000f9a: 79fb ldrb r3, [r7, #7] 8000f9c: 3301 adds r3, #1 8000f9e: 71fb strb r3, [r7, #7] 8000fa0: 79fb ldrb r3, [r7, #7] 8000fa2: 2b03 cmp r3, #3 8000fa4: d9e8 bls.n 8000f78 } } //Assign if valid if(least_val < 0xFF){ 8000fa6: 89fb ldrh r3, [r7, #14] 8000fa8: 2bfe cmp r3, #254 @ 0xfe 8000faa: d80e bhi.n 8000fca PARENT = least_port; 8000fac: 4a0b ldr r2, [pc, #44] @ (8000fdc ) 8000fae: 68bb ldr r3, [r7, #8] 8000fb0: 6013 str r3, [r2, #0] DEPTH = least_val + 1; 8000fb2: 89fb ldrh r3, [r7, #14] 8000fb4: 3301 adds r3, #1 8000fb6: b29a uxth r2, r3 8000fb8: 4b09 ldr r3, [pc, #36] @ (8000fe0 ) 8000fba: 801a strh r2, [r3, #0] MODE = MODE_ACTIVE; 8000fbc: 4b09 ldr r3, [pc, #36] @ (8000fe4 ) 8000fbe: 2202 movs r2, #2 8000fc0: 701a strb r2, [r3, #0] HAL_Delay(500); 8000fc2: f44f 70fa mov.w r0, #500 @ 0x1f4 8000fc6: f000 ffe5 bl 8001f94 } } 8000fca: bf00 nop 8000fcc: 3710 adds r7, #16 8000fce: 46bd mov sp, r7 8000fd0: bd80 pop {r7, pc} 8000fd2: bf00 nop 8000fd4: 20000078 .word 0x20000078 8000fd8: 20000080 .word 0x20000080 8000fdc: 200003e4 .word 0x200003e4 8000fe0: 200003e0 .word 0x200003e0 8000fe4: 2000040a .word 0x2000040a 08000fe8 : // Called when UART RX interrupt completes void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) { 8000fe8: b590 push {r4, r7, lr} 8000fea: b08b sub sp, #44 @ 0x2c 8000fec: af00 add r7, sp, #0 8000fee: 6078 str r0, [r7, #4] 8000ff0: 6039 str r1, [r7, #0] UARTMessage msg; UARTMessage reply; // Parse incoming message into struct memcpy(&msg, data, sizeof(UARTMessage)); 8000ff2: 687b ldr r3, [r7, #4] 8000ff4: f107 0418 add.w r4, r7, #24 8000ff8: 6818 ldr r0, [r3, #0] 8000ffa: 6859 ldr r1, [r3, #4] 8000ffc: 689a ldr r2, [r3, #8] 8000ffe: 68db ldr r3, [r3, #12] 8001000: c40f stmia r4!, {r0, r1, r2, r3} switch(msg.TYPE) { 8001002: 8b7b ldrh r3, [r7, #26] 8001004: 2bff cmp r3, #255 @ 0xff 8001006: d026 beq.n 8001056 8001008: 2bff cmp r3, #255 @ 0xff 800100a: dc6e bgt.n 80010ea 800100c: 2baa cmp r3, #170 @ 0xaa 800100e: d002 beq.n 8001016 8001010: 2bee cmp r3, #238 @ 0xee 8001012: d03a beq.n 800108a } break; default: break; 8001014: e069 b.n 80010ea if(sender == &huart5) { 8001016: 683b ldr r3, [r7, #0] 8001018: 4a39 ldr r2, [pc, #228] @ (8001100 ) 800101a: 4293 cmp r3, r2 800101c: d103 bne.n 8001026 PORT_DEPTH[0] = msg.DEPTH; 800101e: 8b3a ldrh r2, [r7, #24] 8001020: 4b38 ldr r3, [pc, #224] @ (8001104 ) 8001022: 801a strh r2, [r3, #0] break; 8001024: e063 b.n 80010ee } else if(sender == &huart1) { 8001026: 683b ldr r3, [r7, #0] 8001028: 4a37 ldr r2, [pc, #220] @ (8001108 ) 800102a: 4293 cmp r3, r2 800102c: d103 bne.n 8001036 PORT_DEPTH[1] = msg.DEPTH; 800102e: 8b3a ldrh r2, [r7, #24] 8001030: 4b34 ldr r3, [pc, #208] @ (8001104 ) 8001032: 805a strh r2, [r3, #2] break; 8001034: e05b b.n 80010ee } else if(sender == &huart2) { 8001036: 683b ldr r3, [r7, #0] 8001038: 4a34 ldr r2, [pc, #208] @ (800110c ) 800103a: 4293 cmp r3, r2 800103c: d103 bne.n 8001046 PORT_DEPTH[2] = msg.DEPTH; 800103e: 8b3a ldrh r2, [r7, #24] 8001040: 4b30 ldr r3, [pc, #192] @ (8001104 ) 8001042: 809a strh r2, [r3, #4] break; 8001044: e053 b.n 80010ee } else if(sender == &huart4) { 8001046: 683b ldr r3, [r7, #0] 8001048: 4a31 ldr r2, [pc, #196] @ (8001110 ) 800104a: 4293 cmp r3, r2 800104c: d14f bne.n 80010ee PORT_DEPTH[3] = msg.DEPTH; 800104e: 8b3a ldrh r2, [r7, #24] 8001050: 4b2c ldr r3, [pc, #176] @ (8001104 ) 8001052: 80da strh r2, [r3, #6] break; 8001054: e04b b.n 80010ee if(MODE!=MODE_INACTIVE){ 8001056: 4b2f ldr r3, [pc, #188] @ (8001114 ) 8001058: 781b ldrb r3, [r3, #0] 800105a: b2db uxtb r3, r3 800105c: 2b00 cmp r3, #0 800105e: d048 beq.n 80010f2 reply.TYPE = 0xAA; 8001060: 23aa movs r3, #170 @ 0xaa 8001062: 817b strh r3, [r7, #10] reply.DEPTH = DEPTH; // use your local DEPTH 8001064: 4b2c ldr r3, [pc, #176] @ (8001118 ) 8001066: 881b ldrh r3, [r3, #0] 8001068: 813b strh r3, [r7, #8] memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS)); 800106a: f107 0308 add.w r3, r7, #8 800106e: 3304 adds r3, #4 8001070: 220c movs r2, #12 8001072: 2100 movs r1, #0 8001074: 4618 mov r0, r3 8001076: f00a fba3 bl 800b7c0 HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply)); 800107a: f107 0308 add.w r3, r7, #8 800107e: 2210 movs r2, #16 8001080: 4619 mov r1, r3 8001082: 6838 ldr r0, [r7, #0] 8001084: f005 fc78 bl 8006978 break; 8001088: e033 b.n 80010f2 if(sender == &huart5) { 800108a: 683b ldr r3, [r7, #0] 800108c: 4a1c ldr r2, [pc, #112] @ (8001100 ) 800108e: 4293 cmp r3, r2 8001090: d107 bne.n 80010a2 pq_push(&huart5q, msg.KEYPRESS); 8001092: f107 0318 add.w r3, r7, #24 8001096: 3304 adds r3, #4 8001098: 4619 mov r1, r3 800109a: 4820 ldr r0, [pc, #128] @ (800111c ) 800109c: f7ff fbda bl 8000854 break; 80010a0: e029 b.n 80010f6 } else if(sender == &huart1) { 80010a2: 683b ldr r3, [r7, #0] 80010a4: 4a18 ldr r2, [pc, #96] @ (8001108 ) 80010a6: 4293 cmp r3, r2 80010a8: d107 bne.n 80010ba pq_push(&huart1q, msg.KEYPRESS); 80010aa: f107 0318 add.w r3, r7, #24 80010ae: 3304 adds r3, #4 80010b0: 4619 mov r1, r3 80010b2: 481b ldr r0, [pc, #108] @ (8001120 ) 80010b4: f7ff fbce bl 8000854 break; 80010b8: e01d b.n 80010f6 } else if(sender == &huart2) { 80010ba: 683b ldr r3, [r7, #0] 80010bc: 4a13 ldr r2, [pc, #76] @ (800110c ) 80010be: 4293 cmp r3, r2 80010c0: d107 bne.n 80010d2 pq_push(&huart2q, msg.KEYPRESS); 80010c2: f107 0318 add.w r3, r7, #24 80010c6: 3304 adds r3, #4 80010c8: 4619 mov r1, r3 80010ca: 4816 ldr r0, [pc, #88] @ (8001124 ) 80010cc: f7ff fbc2 bl 8000854 break; 80010d0: e011 b.n 80010f6 } else if(sender == &huart4) { 80010d2: 683b ldr r3, [r7, #0] 80010d4: 4a0e ldr r2, [pc, #56] @ (8001110 ) 80010d6: 4293 cmp r3, r2 80010d8: d10d bne.n 80010f6 pq_push(&huart4q, msg.KEYPRESS); 80010da: f107 0318 add.w r3, r7, #24 80010de: 3304 adds r3, #4 80010e0: 4619 mov r1, r3 80010e2: 4811 ldr r0, [pc, #68] @ (8001128 ) 80010e4: f7ff fbb6 bl 8000854 break; 80010e8: e005 b.n 80010f6 break; 80010ea: bf00 nop 80010ec: e004 b.n 80010f8 break; 80010ee: bf00 nop 80010f0: e002 b.n 80010f8 break; 80010f2: bf00 nop 80010f4: e000 b.n 80010f8 break; 80010f6: bf00 nop } } 80010f8: bf00 nop 80010fa: 372c adds r7, #44 @ 0x2c 80010fc: 46bd mov sp, r7 80010fe: bd90 pop {r4, r7, pc} 8001100: 20000b28 .word 0x20000b28 8001104: 20000078 .word 0x20000078 8001108: 20000b70 .word 0x20000b70 800110c: 20000bb8 .word 0x20000bb8 8001110: 20000ae0 .word 0x20000ae0 8001114: 2000040a .word 0x2000040a 8001118: 200003e0 .word 0x200003e0 800111c: 200008cc .word 0x200008cc 8001120: 20000440 .word 0x20000440 8001124: 200005c4 .word 0x200005c4 8001128: 20000748 .word 0x20000748 0800112c : void addUSBReport(uint8_t usageID){ 800112c: b480 push {r7} 800112e: b085 sub sp, #20 8001130: af00 add r7, sp, #0 8001132: 4603 mov r3, r0 8001134: 71fb strb r3, [r7, #7] if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8001136: 79fb ldrb r3, [r7, #7] 8001138: 2b03 cmp r3, #3 800113a: d922 bls.n 8001182 800113c: 79fb ldrb r3, [r7, #7] 800113e: 2b73 cmp r3, #115 @ 0x73 8001140: d81f bhi.n 8001182 uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit 8001142: 79fb ldrb r3, [r7, #7] 8001144: b29b uxth r3, r3 8001146: 3b04 subs r3, #4 8001148: 81fb strh r3, [r7, #14] uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array 800114a: 89fb ldrh r3, [r7, #14] 800114c: 08db lsrs r3, r3, #3 800114e: b29b uxth r3, r3 8001150: 737b strb r3, [r7, #13] uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset 8001152: 89fb ldrh r3, [r7, #14] 8001154: b2db uxtb r3, r3 8001156: f003 0307 and.w r3, r3, #7 800115a: 733b strb r3, [r7, #12] REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); 800115c: 7b7b ldrb r3, [r7, #13] 800115e: 4a0c ldr r2, [pc, #48] @ (8001190 ) 8001160: 4413 add r3, r2 8001162: 789b ldrb r3, [r3, #2] 8001164: b25a sxtb r2, r3 8001166: 7b3b ldrb r3, [r7, #12] 8001168: 2101 movs r1, #1 800116a: fa01 f303 lsl.w r3, r1, r3 800116e: b25b sxtb r3, r3 8001170: 4313 orrs r3, r2 8001172: b25a sxtb r2, r3 8001174: 7b7b ldrb r3, [r7, #13] 8001176: b2d1 uxtb r1, r2 8001178: 4a05 ldr r2, [pc, #20] @ (8001190 ) 800117a: 4413 add r3, r2 800117c: 460a mov r2, r1 800117e: 709a strb r2, [r3, #2] 8001180: e000 b.n 8001184 if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8001182: bf00 nop } 8001184: 3714 adds r7, #20 8001186: 46bd mov sp, r7 8001188: f85d 7b04 ldr.w r7, [sp], #4 800118c: 4770 bx lr 800118e: bf00 nop 8001190: 20000390 .word 0x20000390 08001194 : void matrixScan(void){ 8001194: b580 push {r7, lr} 8001196: b082 sub sp, #8 8001198: af00 add r7, sp, #0 for (uint8_t col = 0; col < COL; col++){ 800119a: 2300 movs r3, #0 800119c: 71fb strb r3, [r7, #7] 800119e: e05f b.n 8001260 HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); 80011a0: 79fb ldrb r3, [r7, #7] 80011a2: 4a33 ldr r2, [pc, #204] @ (8001270 ) 80011a4: f852 0033 ldr.w r0, [r2, r3, lsl #3] 80011a8: 79fb ldrb r3, [r7, #7] 80011aa: 4a31 ldr r2, [pc, #196] @ (8001270 ) 80011ac: 00db lsls r3, r3, #3 80011ae: 4413 add r3, r2 80011b0: 889b ldrh r3, [r3, #4] 80011b2: 2201 movs r2, #1 80011b4: 4619 mov r1, r3 80011b6: f001 fdd1 bl 8002d5c HAL_Delay(1); 80011ba: 2001 movs r0, #1 80011bc: f000 feea bl 8001f94 for(uint8_t row = 0; row < ROW; row++){ 80011c0: 2300 movs r3, #0 80011c2: 71bb strb r3, [r7, #6] 80011c4: e039 b.n 800123a uint8_t new_key = HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN); 80011c6: 79bb ldrb r3, [r7, #6] 80011c8: 4a2a ldr r2, [pc, #168] @ (8001274 ) 80011ca: f852 2033 ldr.w r2, [r2, r3, lsl #3] 80011ce: 79bb ldrb r3, [r7, #6] 80011d0: 4928 ldr r1, [pc, #160] @ (8001274 ) 80011d2: 00db lsls r3, r3, #3 80011d4: 440b add r3, r1 80011d6: 889b ldrh r3, [r3, #4] 80011d8: 4619 mov r1, r3 80011da: 4610 mov r0, r2 80011dc: f001 fda6 bl 8002d2c 80011e0: 4603 mov r3, r0 80011e2: 717b strb r3, [r7, #5] if(new_key != KEYSTATE[row][col]){ 80011e4: 79ba ldrb r2, [r7, #6] 80011e6: 79f9 ldrb r1, [r7, #7] 80011e8: 4823 ldr r0, [pc, #140] @ (8001278 ) 80011ea: 4613 mov r3, r2 80011ec: 009b lsls r3, r3, #2 80011ee: 4413 add r3, r2 80011f0: 4403 add r3, r0 80011f2: 440b add r3, r1 80011f4: 781b ldrb r3, [r3, #0] 80011f6: 797a ldrb r2, [r7, #5] 80011f8: 429a cmp r2, r3 80011fa: d00c beq.n 8001216 KEYSTATE_CHANGED_FLAG = 1; 80011fc: 4b1f ldr r3, [pc, #124] @ (800127c ) 80011fe: 2201 movs r2, #1 8001200: 701a strb r2, [r3, #0] KEYSTATE[row][col] = new_key; 8001202: 79ba ldrb r2, [r7, #6] 8001204: 79f9 ldrb r1, [r7, #7] 8001206: 481c ldr r0, [pc, #112] @ (8001278 ) 8001208: 4613 mov r3, r2 800120a: 009b lsls r3, r3, #2 800120c: 4413 add r3, r2 800120e: 4403 add r3, r0 8001210: 440b add r3, r1 8001212: 797a ldrb r2, [r7, #5] 8001214: 701a strb r2, [r3, #0] } if(new_key){ 8001216: 797b ldrb r3, [r7, #5] 8001218: 2b00 cmp r3, #0 800121a: d00b beq.n 8001234 addUSBReport(KEYCODES[row][col]); 800121c: 79ba ldrb r2, [r7, #6] 800121e: 79f9 ldrb r1, [r7, #7] 8001220: 4817 ldr r0, [pc, #92] @ (8001280 ) 8001222: 4613 mov r3, r2 8001224: 009b lsls r3, r3, #2 8001226: 4413 add r3, r2 8001228: 4403 add r3, r0 800122a: 440b add r3, r1 800122c: 781b ldrb r3, [r3, #0] 800122e: 4618 mov r0, r3 8001230: f7ff ff7c bl 800112c for(uint8_t row = 0; row < ROW; row++){ 8001234: 79bb ldrb r3, [r7, #6] 8001236: 3301 adds r3, #1 8001238: 71bb strb r3, [r7, #6] 800123a: 79bb ldrb r3, [r7, #6] 800123c: 2b05 cmp r3, #5 800123e: d9c2 bls.n 80011c6 } } HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); 8001240: 79fb ldrb r3, [r7, #7] 8001242: 4a0b ldr r2, [pc, #44] @ (8001270 ) 8001244: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8001248: 79fb ldrb r3, [r7, #7] 800124a: 4a09 ldr r2, [pc, #36] @ (8001270 ) 800124c: 00db lsls r3, r3, #3 800124e: 4413 add r3, r2 8001250: 889b ldrh r3, [r3, #4] 8001252: 2200 movs r2, #0 8001254: 4619 mov r1, r3 8001256: f001 fd81 bl 8002d5c for (uint8_t col = 0; col < COL; col++){ 800125a: 79fb ldrb r3, [r7, #7] 800125c: 3301 adds r3, #1 800125e: 71fb strb r3, [r7, #7] 8001260: 79fb ldrb r3, [r7, #7] 8001262: 2b04 cmp r3, #4 8001264: d99c bls.n 80011a0 } } 8001266: bf00 nop 8001268: bf00 nop 800126a: 3708 adds r7, #8 800126c: 46bd mov sp, r7 800126e: bd80 pop {r7, pc} 8001270: 20000030 .word 0x20000030 8001274: 20000000 .word 0x20000000 8001278: 200003ec .word 0x200003ec 800127c: 200003e8 .word 0x200003e8 8001280: 20000058 .word 0x20000058 08001284 : // Read TIM3 encoder counter, calculate delta and add corresponding keycodes void encoderProcess(void){ 8001284: b580 push {r7, lr} 8001286: b086 sub sp, #24 8001288: af00 add r7, sp, #0 int32_t cnt = (int32_t)__HAL_TIM_GET_COUNTER(&htim3); 800128a: 4b28 ldr r3, [pc, #160] @ (800132c ) 800128c: 681b ldr r3, [r3, #0] 800128e: 6a5b ldr r3, [r3, #36] @ 0x24 8001290: 603b str r3, [r7, #0] int32_t diff = cnt - LAST_ENCODER_COUNT; 8001292: 4b27 ldr r3, [pc, #156] @ (8001330 ) 8001294: 681b ldr r3, [r3, #0] 8001296: 683a ldr r2, [r7, #0] 8001298: 1ad3 subs r3, r2, r3 800129a: 617b str r3, [r7, #20] // TIM3 configured as 16-bit counter (period 65535). Fix wrap-around. if(diff > 32767) diff -= 65536; 800129c: 697b ldr r3, [r7, #20] 800129e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80012a2: db03 blt.n 80012ac 80012a4: 697b ldr r3, [r7, #20] 80012a6: f5a3 3380 sub.w r3, r3, #65536 @ 0x10000 80012aa: 617b str r3, [r7, #20] if(diff < -32768) diff += 65536; 80012ac: 697b ldr r3, [r7, #20] 80012ae: f513 4f00 cmn.w r3, #32768 @ 0x8000 80012b2: da03 bge.n 80012bc 80012b4: 697b ldr r3, [r7, #20] 80012b6: f503 3380 add.w r3, r3, #65536 @ 0x10000 80012ba: 617b str r3, [r7, #20] if(diff > 0){ 80012bc: 697b ldr r3, [r7, #20] 80012be: 2b00 cmp r3, #0 80012c0: dd14 ble.n 80012ec int steps = diff; 80012c2: 697b ldr r3, [r7, #20] 80012c4: 613b str r3, [r7, #16] if(steps > 10) steps = 10; // cap bursts 80012c6: 693b ldr r3, [r7, #16] 80012c8: 2b0a cmp r3, #10 80012ca: dd01 ble.n 80012d0 80012cc: 230a movs r3, #10 80012ce: 613b str r3, [r7, #16] for(int i = 0; i < steps; i++){ 80012d0: 2300 movs r3, #0 80012d2: 60fb str r3, [r7, #12] 80012d4: e005 b.n 80012e2 // CW -> KEYCODES[0][0] addUSBReport(KEY_RIGHT_ARROW); 80012d6: 204f movs r0, #79 @ 0x4f 80012d8: f7ff ff28 bl 800112c for(int i = 0; i < steps; i++){ 80012dc: 68fb ldr r3, [r7, #12] 80012de: 3301 adds r3, #1 80012e0: 60fb str r3, [r7, #12] 80012e2: 68fa ldr r2, [r7, #12] 80012e4: 693b ldr r3, [r7, #16] 80012e6: 429a cmp r2, r3 80012e8: dbf5 blt.n 80012d6 80012ea: e017 b.n 800131c } }else if(diff < 0){ 80012ec: 697b ldr r3, [r7, #20] 80012ee: 2b00 cmp r3, #0 80012f0: da14 bge.n 800131c int steps = -diff; 80012f2: 697b ldr r3, [r7, #20] 80012f4: 425b negs r3, r3 80012f6: 60bb str r3, [r7, #8] if(steps > 10) steps = 10; 80012f8: 68bb ldr r3, [r7, #8] 80012fa: 2b0a cmp r3, #10 80012fc: dd01 ble.n 8001302 80012fe: 230a movs r3, #10 8001300: 60bb str r3, [r7, #8] for(int i = 0; i < steps; i++){ 8001302: 2300 movs r3, #0 8001304: 607b str r3, [r7, #4] 8001306: e005 b.n 8001314 // CCW -> KEYCODES[0][1] addUSBReport(KEY_LEFT_ARROW); 8001308: 2050 movs r0, #80 @ 0x50 800130a: f7ff ff0f bl 800112c for(int i = 0; i < steps; i++){ 800130e: 687b ldr r3, [r7, #4] 8001310: 3301 adds r3, #1 8001312: 607b str r3, [r7, #4] 8001314: 687a ldr r2, [r7, #4] 8001316: 68bb ldr r3, [r7, #8] 8001318: 429a cmp r2, r3 800131a: dbf5 blt.n 8001308 } } LAST_ENCODER_COUNT = cnt; 800131c: 4a04 ldr r2, [pc, #16] @ (8001330 ) 800131e: 683b ldr r3, [r7, #0] 8001320: 6013 str r3, [r2, #0] } 8001322: bf00 nop 8001324: 3718 adds r7, #24 8001326: 46bd mov sp, r7 8001328: bd80 pop {r7, pc} 800132a: bf00 nop 800132c: 20000a98 .word 0x20000a98 8001330: 2000040c .word 0x2000040c 08001334 : void resetReport(void){ 8001334: b580 push {r7, lr} 8001336: af00 add r7, sp, #0 memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); 8001338: 220c movs r2, #12 800133a: 2100 movs r1, #0 800133c: 4802 ldr r0, [pc, #8] @ (8001348 ) 800133e: f00a fa3f bl 800b7c0 } 8001342: bf00 nop 8001344: bd80 pop {r7, pc} 8001346: bf00 nop 8001348: 20000392 .word 0x20000392 0800134c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800134c: b480 push {r7} 800134e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001350: b672 cpsid i } 8001352: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001354: bf00 nop 8001356: e7fd b.n 8001354 08001358 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001358: b480 push {r7} 800135a: b083 sub sp, #12 800135c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800135e: 2300 movs r3, #0 8001360: 607b str r3, [r7, #4] 8001362: 4b10 ldr r3, [pc, #64] @ (80013a4 ) 8001364: 6c5b ldr r3, [r3, #68] @ 0x44 8001366: 4a0f ldr r2, [pc, #60] @ (80013a4 ) 8001368: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800136c: 6453 str r3, [r2, #68] @ 0x44 800136e: 4b0d ldr r3, [pc, #52] @ (80013a4 ) 8001370: 6c5b ldr r3, [r3, #68] @ 0x44 8001372: f403 4380 and.w r3, r3, #16384 @ 0x4000 8001376: 607b str r3, [r7, #4] 8001378: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 800137a: 2300 movs r3, #0 800137c: 603b str r3, [r7, #0] 800137e: 4b09 ldr r3, [pc, #36] @ (80013a4 ) 8001380: 6c1b ldr r3, [r3, #64] @ 0x40 8001382: 4a08 ldr r2, [pc, #32] @ (80013a4 ) 8001384: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8001388: 6413 str r3, [r2, #64] @ 0x40 800138a: 4b06 ldr r3, [pc, #24] @ (80013a4 ) 800138c: 6c1b ldr r3, [r3, #64] @ 0x40 800138e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8001392: 603b str r3, [r7, #0] 8001394: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001396: bf00 nop 8001398: 370c adds r7, #12 800139a: 46bd mov sp, r7 800139c: f85d 7b04 ldr.w r7, [sp], #4 80013a0: 4770 bx lr 80013a2: bf00 nop 80013a4: 40023800 .word 0x40023800 080013a8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80013a8: b480 push {r7} 80013aa: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80013ac: bf00 nop 80013ae: e7fd b.n 80013ac 080013b0 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80013b0: b480 push {r7} 80013b2: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80013b4: bf00 nop 80013b6: e7fd b.n 80013b4 080013b8 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80013b8: b480 push {r7} 80013ba: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80013bc: bf00 nop 80013be: e7fd b.n 80013bc 080013c0 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 80013c0: b480 push {r7} 80013c2: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80013c4: bf00 nop 80013c6: e7fd b.n 80013c4 080013c8 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80013c8: b480 push {r7} 80013ca: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80013cc: bf00 nop 80013ce: e7fd b.n 80013cc 080013d0 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80013d0: b480 push {r7} 80013d2: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80013d4: bf00 nop 80013d6: 46bd mov sp, r7 80013d8: f85d 7b04 ldr.w r7, [sp], #4 80013dc: 4770 bx lr 080013de : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80013de: b480 push {r7} 80013e0: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80013e2: bf00 nop 80013e4: 46bd mov sp, r7 80013e6: f85d 7b04 ldr.w r7, [sp], #4 80013ea: 4770 bx lr 080013ec : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80013ec: b480 push {r7} 80013ee: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80013f0: bf00 nop 80013f2: 46bd mov sp, r7 80013f4: f85d 7b04 ldr.w r7, [sp], #4 80013f8: 4770 bx lr 080013fa : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80013fa: b580 push {r7, lr} 80013fc: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80013fe: f000 fda9 bl 8001f54 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8001402: bf00 nop 8001404: bd80 pop {r7, pc} ... 08001408 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8001408: b580 push {r7, lr} 800140a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_rx); 800140c: 4802 ldr r0, [pc, #8] @ (8001418 ) 800140e: f001 f88f bl 8002530 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8001412: bf00 nop 8001414: bd80 pop {r7, pc} 8001416: bf00 nop 8001418: 20000cc0 .word 0x20000cc0 0800141c : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 800141c: b580 push {r7, lr} 800141e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_rx); 8001420: 4802 ldr r0, [pc, #8] @ (800142c ) 8001422: f001 f885 bl 8002530 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8001426: bf00 nop 8001428: bd80 pop {r7, pc} 800142a: bf00 nop 800142c: 20000c00 .word 0x20000c00 08001430 : /** * @brief This function handles DMA1 stream4 global interrupt. */ void DMA1_Stream4_IRQHandler(void) { 8001430: b580 push {r7, lr} 8001432: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ /* USER CODE END DMA1_Stream4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_tx); 8001434: 4802 ldr r0, [pc, #8] @ (8001440 ) 8001436: f001 f87b bl 8002530 /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ /* USER CODE END DMA1_Stream4_IRQn 1 */ } 800143a: bf00 nop 800143c: bd80 pop {r7, pc} 800143e: bf00 nop 8001440: 20000c60 .word 0x20000c60 08001444 : /** * @brief This function handles DMA1 stream5 global interrupt. */ void DMA1_Stream5_IRQHandler(void) { 8001444: b580 push {r7, lr} 8001446: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ /* USER CODE END DMA1_Stream5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8001448: 4802 ldr r0, [pc, #8] @ (8001454 ) 800144a: f001 f871 bl 8002530 /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ /* USER CODE END DMA1_Stream5_IRQn 1 */ } 800144e: bf00 nop 8001450: bd80 pop {r7, pc} 8001452: bf00 nop 8001454: 20000e40 .word 0x20000e40 08001458 : /** * @brief This function handles DMA1 stream6 global interrupt. */ void DMA1_Stream6_IRQHandler(void) { 8001458: b580 push {r7, lr} 800145a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ /* USER CODE END DMA1_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 800145c: 4802 ldr r0, [pc, #8] @ (8001468 ) 800145e: f001 f867 bl 8002530 /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ /* USER CODE END DMA1_Stream6_IRQn 1 */ } 8001462: bf00 nop 8001464: bd80 pop {r7, pc} 8001466: bf00 nop 8001468: 20000ea0 .word 0x20000ea0 0800146c : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 800146c: b580 push {r7, lr} 800146e: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8001470: 4802 ldr r0, [pc, #8] @ (800147c ) 8001472: f005 fb23 bl 8006abc /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8001476: bf00 nop 8001478: bd80 pop {r7, pc} 800147a: bf00 nop 800147c: 20000b70 .word 0x20000b70 08001480 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 8001480: b580 push {r7, lr} 8001482: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8001484: 4802 ldr r0, [pc, #8] @ (8001490 ) 8001486: f005 fb19 bl 8006abc /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 800148a: bf00 nop 800148c: bd80 pop {r7, pc} 800148e: bf00 nop 8001490: 20000bb8 .word 0x20000bb8 08001494 : /** * @brief This function handles DMA1 stream7 global interrupt. */ void DMA1_Stream7_IRQHandler(void) { 8001494: b580 push {r7, lr} 8001496: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ /* USER CODE END DMA1_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_tx); 8001498: 4802 ldr r0, [pc, #8] @ (80014a4 ) 800149a: f001 f849 bl 8002530 /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ /* USER CODE END DMA1_Stream7_IRQn 1 */ } 800149e: bf00 nop 80014a0: bd80 pop {r7, pc} 80014a2: bf00 nop 80014a4: 20000d20 .word 0x20000d20 080014a8 : /** * @brief This function handles UART4 global interrupt. */ void UART4_IRQHandler(void) { 80014a8: b580 push {r7, lr} 80014aa: af00 add r7, sp, #0 /* USER CODE BEGIN UART4_IRQn 0 */ /* USER CODE END UART4_IRQn 0 */ HAL_UART_IRQHandler(&huart4); 80014ac: 4802 ldr r0, [pc, #8] @ (80014b8 ) 80014ae: f005 fb05 bl 8006abc /* USER CODE BEGIN UART4_IRQn 1 */ /* USER CODE END UART4_IRQn 1 */ } 80014b2: bf00 nop 80014b4: bd80 pop {r7, pc} 80014b6: bf00 nop 80014b8: 20000ae0 .word 0x20000ae0 080014bc : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 80014bc: b580 push {r7, lr} 80014be: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 80014c0: 4802 ldr r0, [pc, #8] @ (80014cc ) 80014c2: f005 fafb bl 8006abc /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 80014c6: bf00 nop 80014c8: bd80 pop {r7, pc} 80014ca: bf00 nop 80014cc: 20000b28 .word 0x20000b28 080014d0 : /** * @brief This function handles DMA2 stream2 global interrupt. */ void DMA2_Stream2_IRQHandler(void) { 80014d0: b580 push {r7, lr} 80014d2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 80014d4: 4802 ldr r0, [pc, #8] @ (80014e0 ) 80014d6: f001 f82b bl 8002530 /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } 80014da: bf00 nop 80014dc: bd80 pop {r7, pc} 80014de: bf00 nop 80014e0: 20000d80 .word 0x20000d80 080014e4 : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 80014e4: b580 push {r7, lr} 80014e6: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 80014e8: 4802 ldr r0, [pc, #8] @ (80014f4 ) 80014ea: f001 fee0 bl 80032ae /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 80014ee: bf00 nop 80014f0: bd80 pop {r7, pc} 80014f2: bf00 nop 80014f4: 200013e4 .word 0x200013e4 080014f8 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 80014f8: b580 push {r7, lr} 80014fa: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 80014fc: 4802 ldr r0, [pc, #8] @ (8001508 ) 80014fe: f001 f817 bl 8002530 /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 8001502: bf00 nop 8001504: bd80 pop {r7, pc} 8001506: bf00 nop 8001508: 20000de0 .word 0x20000de0 0800150c : * configuration. * @param None * @retval None */ void SystemInit(void) { 800150c: b480 push {r7} 800150e: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8001510: 4b06 ldr r3, [pc, #24] @ (800152c ) 8001512: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8001516: 4a05 ldr r2, [pc, #20] @ (800152c ) 8001518: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800151c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001520: bf00 nop 8001522: 46bd mov sp, r7 8001524: f85d 7b04 ldr.w r7, [sp], #4 8001528: 4770 bx lr 800152a: bf00 nop 800152c: e000ed00 .word 0xe000ed00 08001530 : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; void MX_TIM2_Init(void) { 8001530: b580 push {r7, lr} 8001532: b088 sub sp, #32 8001534: af00 add r7, sp, #0 TIM_OC_InitTypeDef sConfigOC = {0}; 8001536: 1d3b adds r3, r7, #4 8001538: 2200 movs r2, #0 800153a: 601a str r2, [r3, #0] 800153c: 605a str r2, [r3, #4] 800153e: 609a str r2, [r3, #8] 8001540: 60da str r2, [r3, #12] 8001542: 611a str r2, [r3, #16] 8001544: 615a str r2, [r3, #20] 8001546: 619a str r2, [r3, #24] htim2.Instance = TIM2; 8001548: 4b1a ldr r3, [pc, #104] @ (80015b4 ) 800154a: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 800154e: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 8001550: 4b18 ldr r3, [pc, #96] @ (80015b4 ) 8001552: 2200 movs r2, #0 8001554: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8001556: 4b17 ldr r3, [pc, #92] @ (80015b4 ) 8001558: 2200 movs r2, #0 800155a: 609a str r2, [r3, #8] htim2.Init.Period = 9; 800155c: 4b15 ldr r3, [pc, #84] @ (80015b4 ) 800155e: 2209 movs r2, #9 8001560: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001562: 4b14 ldr r3, [pc, #80] @ (80015b4 ) 8001564: 2200 movs r2, #0 8001566: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001568: 4b12 ldr r3, [pc, #72] @ (80015b4 ) 800156a: 2200 movs r2, #0 800156c: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) Error_Handler(); 800156e: 4811 ldr r0, [pc, #68] @ (80015b4 ) 8001570: f004 f8ea bl 8005748 8001574: 4603 mov r3, r0 8001576: 2b00 cmp r3, #0 8001578: d001 beq.n 800157e 800157a: f7ff fee7 bl 800134c sConfigOC.OCMode = TIM_OCMODE_PWM1; 800157e: 2360 movs r3, #96 @ 0x60 8001580: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 8001582: 2300 movs r3, #0 8001584: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001586: 2300 movs r3, #0 8001588: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800158a: 2300 movs r3, #0 800158c: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) Error_Handler(); 800158e: 1d3b adds r3, r7, #4 8001590: 2200 movs r2, #0 8001592: 4619 mov r1, r3 8001594: 4807 ldr r0, [pc, #28] @ (80015b4 ) 8001596: f004 fcff bl 8005f98 800159a: 4603 mov r3, r0 800159c: 2b00 cmp r3, #0 800159e: d001 beq.n 80015a4 80015a0: f7ff fed4 bl 800134c HAL_TIM_MspPostInit(&htim2); 80015a4: 4803 ldr r0, [pc, #12] @ (80015b4 ) 80015a6: f000 f8b7 bl 8001718 } 80015aa: bf00 nop 80015ac: 3720 adds r7, #32 80015ae: 46bd mov sp, r7 80015b0: bd80 pop {r7, pc} 80015b2: bf00 nop 80015b4: 20000a50 .word 0x20000a50 080015b8 : void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80015b8: b580 push {r7, lr} 80015ba: b082 sub sp, #8 80015bc: af00 add r7, sp, #0 80015be: 6078 str r0, [r7, #4] if (htim->Instance == TIM2) { 80015c0: 687b ldr r3, [r7, #4] 80015c2: 681b ldr r3, [r3, #0] 80015c4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80015c8: d103 bne.n 80015d2 HAL_TIM_PWM_Stop_DMA(&htim2, TIM_CHANNEL_1); 80015ca: 2100 movs r1, #0 80015cc: 4803 ldr r0, [pc, #12] @ (80015dc ) 80015ce: f004 fadd bl 8005b8c } } 80015d2: bf00 nop 80015d4: 3708 adds r7, #8 80015d6: 46bd mov sp, r7 80015d8: bd80 pop {r7, pc} 80015da: bf00 nop 80015dc: 20000a50 .word 0x20000a50 080015e0 : /* TIM3 init function */ void MX_TIM3_Init(void) { 80015e0: b580 push {r7, lr} 80015e2: b08c sub sp, #48 @ 0x30 80015e4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 80015e6: f107 030c add.w r3, r7, #12 80015ea: 2224 movs r2, #36 @ 0x24 80015ec: 2100 movs r1, #0 80015ee: 4618 mov r0, r3 80015f0: f00a f8e6 bl 800b7c0 TIM_MasterConfigTypeDef sMasterConfig = {0}; 80015f4: 1d3b adds r3, r7, #4 80015f6: 2200 movs r2, #0 80015f8: 601a str r2, [r3, #0] 80015fa: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80015fc: 4b20 ldr r3, [pc, #128] @ (8001680 ) 80015fe: 4a21 ldr r2, [pc, #132] @ (8001684 ) 8001600: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 8001602: 4b1f ldr r3, [pc, #124] @ (8001680 ) 8001604: 2200 movs r2, #0 8001606: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001608: 4b1d ldr r3, [pc, #116] @ (8001680 ) 800160a: 2200 movs r2, #0 800160c: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800160e: 4b1c ldr r3, [pc, #112] @ (8001680 ) 8001610: f64f 72ff movw r2, #65535 @ 0xffff 8001614: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001616: 4b1a ldr r3, [pc, #104] @ (8001680 ) 8001618: 2200 movs r2, #0 800161a: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800161c: 4b18 ldr r3, [pc, #96] @ (8001680 ) 800161e: 2200 movs r2, #0 8001620: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI1; 8001622: 2301 movs r3, #1 8001624: 60fb str r3, [r7, #12] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 8001626: 2300 movs r3, #0 8001628: 613b str r3, [r7, #16] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 800162a: 2301 movs r3, #1 800162c: 617b str r3, [r7, #20] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 800162e: 2300 movs r3, #0 8001630: 61bb str r3, [r7, #24] sConfig.IC1Filter = 0; 8001632: 2300 movs r3, #0 8001634: 61fb str r3, [r7, #28] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 8001636: 2300 movs r3, #0 8001638: 623b str r3, [r7, #32] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 800163a: 2301 movs r3, #1 800163c: 627b str r3, [r7, #36] @ 0x24 sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 800163e: 2300 movs r3, #0 8001640: 62bb str r3, [r7, #40] @ 0x28 sConfig.IC2Filter = 0; 8001642: 2300 movs r3, #0 8001644: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 8001646: f107 030c add.w r3, r7, #12 800164a: 4619 mov r1, r3 800164c: 480c ldr r0, [pc, #48] @ (8001680 ) 800164e: f004 fb6f bl 8005d30 8001652: 4603 mov r3, r0 8001654: 2b00 cmp r3, #0 8001656: d001 beq.n 800165c { Error_Handler(); 8001658: f7ff fe78 bl 800134c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800165c: 2300 movs r3, #0 800165e: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001660: 2300 movs r3, #0 8001662: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8001664: 1d3b adds r3, r7, #4 8001666: 4619 mov r1, r3 8001668: 4805 ldr r0, [pc, #20] @ (8001680 ) 800166a: f005 f8b9 bl 80067e0 800166e: 4603 mov r3, r0 8001670: 2b00 cmp r3, #0 8001672: d001 beq.n 8001678 { Error_Handler(); 8001674: f7ff fe6a bl 800134c } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8001678: bf00 nop 800167a: 3730 adds r7, #48 @ 0x30 800167c: 46bd mov sp, r7 800167e: bd80 pop {r7, pc} 8001680: 20000a98 .word 0x20000a98 8001684: 40000400 .word 0x40000400 08001688 : /* USER CODE END TIM2_MspInit 1 */ } } void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) { 8001688: b580 push {r7, lr} 800168a: b08a sub sp, #40 @ 0x28 800168c: af00 add r7, sp, #0 800168e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001690: f107 0314 add.w r3, r7, #20 8001694: 2200 movs r2, #0 8001696: 601a str r2, [r3, #0] 8001698: 605a str r2, [r3, #4] 800169a: 609a str r2, [r3, #8] 800169c: 60da str r2, [r3, #12] 800169e: 611a str r2, [r3, #16] if(tim_encoderHandle->Instance==TIM3) 80016a0: 687b ldr r3, [r7, #4] 80016a2: 681b ldr r3, [r3, #0] 80016a4: 4a19 ldr r2, [pc, #100] @ (800170c ) 80016a6: 4293 cmp r3, r2 80016a8: d12b bne.n 8001702 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 80016aa: 2300 movs r3, #0 80016ac: 613b str r3, [r7, #16] 80016ae: 4b18 ldr r3, [pc, #96] @ (8001710 ) 80016b0: 6c1b ldr r3, [r3, #64] @ 0x40 80016b2: 4a17 ldr r2, [pc, #92] @ (8001710 ) 80016b4: f043 0302 orr.w r3, r3, #2 80016b8: 6413 str r3, [r2, #64] @ 0x40 80016ba: 4b15 ldr r3, [pc, #84] @ (8001710 ) 80016bc: 6c1b ldr r3, [r3, #64] @ 0x40 80016be: f003 0302 and.w r3, r3, #2 80016c2: 613b str r3, [r7, #16] 80016c4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80016c6: 2300 movs r3, #0 80016c8: 60fb str r3, [r7, #12] 80016ca: 4b11 ldr r3, [pc, #68] @ (8001710 ) 80016cc: 6b1b ldr r3, [r3, #48] @ 0x30 80016ce: 4a10 ldr r2, [pc, #64] @ (8001710 ) 80016d0: f043 0301 orr.w r3, r3, #1 80016d4: 6313 str r3, [r2, #48] @ 0x30 80016d6: 4b0e ldr r3, [pc, #56] @ (8001710 ) 80016d8: 6b1b ldr r3, [r3, #48] @ 0x30 80016da: f003 0301 and.w r3, r3, #1 80016de: 60fb str r3, [r7, #12] 80016e0: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80016e2: 23c0 movs r3, #192 @ 0xc0 80016e4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80016e6: 2302 movs r3, #2 80016e8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016ea: 2300 movs r3, #0 80016ec: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80016ee: 2300 movs r3, #0 80016f0: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 80016f2: 2302 movs r3, #2 80016f4: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80016f6: f107 0314 add.w r3, r7, #20 80016fa: 4619 mov r1, r3 80016fc: 4805 ldr r0, [pc, #20] @ (8001714 ) 80016fe: f001 f981 bl 8002a04 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8001702: bf00 nop 8001704: 3728 adds r7, #40 @ 0x28 8001706: 46bd mov sp, r7 8001708: bd80 pop {r7, pc} 800170a: bf00 nop 800170c: 40000400 .word 0x40000400 8001710: 40023800 .word 0x40023800 8001714: 40020000 .word 0x40020000 08001718 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 8001718: b580 push {r7, lr} 800171a: b088 sub sp, #32 800171c: af00 add r7, sp, #0 800171e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001720: f107 030c add.w r3, r7, #12 8001724: 2200 movs r2, #0 8001726: 601a str r2, [r3, #0] 8001728: 605a str r2, [r3, #4] 800172a: 609a str r2, [r3, #8] 800172c: 60da str r2, [r3, #12] 800172e: 611a str r2, [r3, #16] if(timHandle->Instance==TIM2) 8001730: 687b ldr r3, [r7, #4] 8001732: 681b ldr r3, [r3, #0] 8001734: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001738: d11d bne.n 8001776 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800173a: 2300 movs r3, #0 800173c: 60bb str r3, [r7, #8] 800173e: 4b10 ldr r3, [pc, #64] @ (8001780 ) 8001740: 6b1b ldr r3, [r3, #48] @ 0x30 8001742: 4a0f ldr r2, [pc, #60] @ (8001780 ) 8001744: f043 0301 orr.w r3, r3, #1 8001748: 6313 str r3, [r2, #48] @ 0x30 800174a: 4b0d ldr r3, [pc, #52] @ (8001780 ) 800174c: 6b1b ldr r3, [r3, #48] @ 0x30 800174e: f003 0301 and.w r3, r3, #1 8001752: 60bb str r3, [r7, #8] 8001754: 68bb ldr r3, [r7, #8] /**TIM2 GPIO Configuration PA5 ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8001756: 2320 movs r3, #32 8001758: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800175a: 2302 movs r3, #2 800175c: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800175e: 2300 movs r3, #0 8001760: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001762: 2300 movs r3, #0 8001764: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8001766: 2301 movs r3, #1 8001768: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800176a: f107 030c add.w r3, r7, #12 800176e: 4619 mov r1, r3 8001770: 4804 ldr r0, [pc, #16] @ (8001784 ) 8001772: f001 f947 bl 8002a04 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8001776: bf00 nop 8001778: 3720 adds r7, #32 800177a: 46bd mov sp, r7 800177c: bd80 pop {r7, pc} 800177e: bf00 nop 8001780: 40023800 .word 0x40023800 8001784: 40020000 .word 0x40020000 08001788 : DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart2_tx; /* UART4 init function */ void MX_UART4_Init(void) { 8001788: b580 push {r7, lr} 800178a: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 800178c: 4b11 ldr r3, [pc, #68] @ (80017d4 ) 800178e: 4a12 ldr r2, [pc, #72] @ (80017d8 ) 8001790: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 8001792: 4b10 ldr r3, [pc, #64] @ (80017d4 ) 8001794: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001798: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 800179a: 4b0e ldr r3, [pc, #56] @ (80017d4 ) 800179c: 2200 movs r2, #0 800179e: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 80017a0: 4b0c ldr r3, [pc, #48] @ (80017d4 ) 80017a2: 2200 movs r2, #0 80017a4: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 80017a6: 4b0b ldr r3, [pc, #44] @ (80017d4 ) 80017a8: 2200 movs r2, #0 80017aa: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 80017ac: 4b09 ldr r3, [pc, #36] @ (80017d4 ) 80017ae: 220c movs r2, #12 80017b0: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80017b2: 4b08 ldr r3, [pc, #32] @ (80017d4 ) 80017b4: 2200 movs r2, #0 80017b6: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 80017b8: 4b06 ldr r3, [pc, #24] @ (80017d4 ) 80017ba: 2200 movs r2, #0 80017bc: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart4) != HAL_OK) 80017be: 4805 ldr r0, [pc, #20] @ (80017d4 ) 80017c0: f005 f88a bl 80068d8 80017c4: 4603 mov r3, r0 80017c6: 2b00 cmp r3, #0 80017c8: d001 beq.n 80017ce { Error_Handler(); 80017ca: f7ff fdbf bl 800134c } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 80017ce: bf00 nop 80017d0: bd80 pop {r7, pc} 80017d2: bf00 nop 80017d4: 20000ae0 .word 0x20000ae0 80017d8: 40004c00 .word 0x40004c00 080017dc : /* UART5 init function */ void MX_UART5_Init(void) { 80017dc: b580 push {r7, lr} 80017de: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 80017e0: 4b11 ldr r3, [pc, #68] @ (8001828 ) 80017e2: 4a12 ldr r2, [pc, #72] @ (800182c ) 80017e4: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 80017e6: 4b10 ldr r3, [pc, #64] @ (8001828 ) 80017e8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80017ec: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 80017ee: 4b0e ldr r3, [pc, #56] @ (8001828 ) 80017f0: 2200 movs r2, #0 80017f2: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 80017f4: 4b0c ldr r3, [pc, #48] @ (8001828 ) 80017f6: 2200 movs r2, #0 80017f8: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 80017fa: 4b0b ldr r3, [pc, #44] @ (8001828 ) 80017fc: 2200 movs r2, #0 80017fe: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 8001800: 4b09 ldr r3, [pc, #36] @ (8001828 ) 8001802: 220c movs r2, #12 8001804: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001806: 4b08 ldr r3, [pc, #32] @ (8001828 ) 8001808: 2200 movs r2, #0 800180a: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800180c: 4b06 ldr r3, [pc, #24] @ (8001828 ) 800180e: 2200 movs r2, #0 8001810: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 8001812: 4805 ldr r0, [pc, #20] @ (8001828 ) 8001814: f005 f860 bl 80068d8 8001818: 4603 mov r3, r0 800181a: 2b00 cmp r3, #0 800181c: d001 beq.n 8001822 { Error_Handler(); 800181e: f7ff fd95 bl 800134c } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 8001822: bf00 nop 8001824: bd80 pop {r7, pc} 8001826: bf00 nop 8001828: 20000b28 .word 0x20000b28 800182c: 40005000 .word 0x40005000 08001830 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 8001830: b580 push {r7, lr} 8001832: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001834: 4b11 ldr r3, [pc, #68] @ (800187c ) 8001836: 4a12 ldr r2, [pc, #72] @ (8001880 ) 8001838: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800183a: 4b10 ldr r3, [pc, #64] @ (800187c ) 800183c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001840: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8001842: 4b0e ldr r3, [pc, #56] @ (800187c ) 8001844: 2200 movs r2, #0 8001846: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001848: 4b0c ldr r3, [pc, #48] @ (800187c ) 800184a: 2200 movs r2, #0 800184c: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800184e: 4b0b ldr r3, [pc, #44] @ (800187c ) 8001850: 2200 movs r2, #0 8001852: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001854: 4b09 ldr r3, [pc, #36] @ (800187c ) 8001856: 220c movs r2, #12 8001858: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800185a: 4b08 ldr r3, [pc, #32] @ (800187c ) 800185c: 2200 movs r2, #0 800185e: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001860: 4b06 ldr r3, [pc, #24] @ (800187c ) 8001862: 2200 movs r2, #0 8001864: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8001866: 4805 ldr r0, [pc, #20] @ (800187c ) 8001868: f005 f836 bl 80068d8 800186c: 4603 mov r3, r0 800186e: 2b00 cmp r3, #0 8001870: d001 beq.n 8001876 { Error_Handler(); 8001872: f7ff fd6b bl 800134c } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001876: bf00 nop 8001878: bd80 pop {r7, pc} 800187a: bf00 nop 800187c: 20000b70 .word 0x20000b70 8001880: 40011000 .word 0x40011000 08001884 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 8001884: b580 push {r7, lr} 8001886: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8001888: 4b11 ldr r3, [pc, #68] @ (80018d0 ) 800188a: 4a12 ldr r2, [pc, #72] @ (80018d4 ) 800188c: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800188e: 4b10 ldr r3, [pc, #64] @ (80018d0 ) 8001890: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001894: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8001896: 4b0e ldr r3, [pc, #56] @ (80018d0 ) 8001898: 2200 movs r2, #0 800189a: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800189c: 4b0c ldr r3, [pc, #48] @ (80018d0 ) 800189e: 2200 movs r2, #0 80018a0: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80018a2: 4b0b ldr r3, [pc, #44] @ (80018d0 ) 80018a4: 2200 movs r2, #0 80018a6: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80018a8: 4b09 ldr r3, [pc, #36] @ (80018d0 ) 80018aa: 220c movs r2, #12 80018ac: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80018ae: 4b08 ldr r3, [pc, #32] @ (80018d0 ) 80018b0: 2200 movs r2, #0 80018b2: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 80018b4: 4b06 ldr r3, [pc, #24] @ (80018d0 ) 80018b6: 2200 movs r2, #0 80018b8: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 80018ba: 4805 ldr r0, [pc, #20] @ (80018d0 ) 80018bc: f005 f80c bl 80068d8 80018c0: 4603 mov r3, r0 80018c2: 2b00 cmp r3, #0 80018c4: d001 beq.n 80018ca { Error_Handler(); 80018c6: f7ff fd41 bl 800134c } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80018ca: bf00 nop 80018cc: bd80 pop {r7, pc} 80018ce: bf00 nop 80018d0: 20000bb8 .word 0x20000bb8 80018d4: 40004400 .word 0x40004400 080018d8 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 80018d8: b580 push {r7, lr} 80018da: b090 sub sp, #64 @ 0x40 80018dc: af00 add r7, sp, #0 80018de: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80018e0: f107 032c add.w r3, r7, #44 @ 0x2c 80018e4: 2200 movs r2, #0 80018e6: 601a str r2, [r3, #0] 80018e8: 605a str r2, [r3, #4] 80018ea: 609a str r2, [r3, #8] 80018ec: 60da str r2, [r3, #12] 80018ee: 611a str r2, [r3, #16] if(uartHandle->Instance==UART4) 80018f0: 687b ldr r3, [r7, #4] 80018f2: 681b ldr r3, [r3, #0] 80018f4: 4a4a ldr r2, [pc, #296] @ (8001a20 ) 80018f6: 4293 cmp r3, r2 80018f8: f040 80a0 bne.w 8001a3c { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* UART4 clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 80018fc: 2300 movs r3, #0 80018fe: 62bb str r3, [r7, #40] @ 0x28 8001900: 4b48 ldr r3, [pc, #288] @ (8001a24 ) 8001902: 6c1b ldr r3, [r3, #64] @ 0x40 8001904: 4a47 ldr r2, [pc, #284] @ (8001a24 ) 8001906: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800190a: 6413 str r3, [r2, #64] @ 0x40 800190c: 4b45 ldr r3, [pc, #276] @ (8001a24 ) 800190e: 6c1b ldr r3, [r3, #64] @ 0x40 8001910: f403 2300 and.w r3, r3, #524288 @ 0x80000 8001914: 62bb str r3, [r7, #40] @ 0x28 8001916: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001918: 2300 movs r3, #0 800191a: 627b str r3, [r7, #36] @ 0x24 800191c: 4b41 ldr r3, [pc, #260] @ (8001a24 ) 800191e: 6b1b ldr r3, [r3, #48] @ 0x30 8001920: 4a40 ldr r2, [pc, #256] @ (8001a24 ) 8001922: f043 0301 orr.w r3, r3, #1 8001926: 6313 str r3, [r2, #48] @ 0x30 8001928: 4b3e ldr r3, [pc, #248] @ (8001a24 ) 800192a: 6b1b ldr r3, [r3, #48] @ 0x30 800192c: f003 0301 and.w r3, r3, #1 8001930: 627b str r3, [r7, #36] @ 0x24 8001932: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART4 GPIO Configuration PA0-WKUP ------> UART4_TX PA1 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8001934: 2303 movs r3, #3 8001936: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001938: 2302 movs r3, #2 800193a: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 800193c: 2300 movs r3, #0 800193e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001940: 2303 movs r3, #3 8001942: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 8001944: 2308 movs r3, #8 8001946: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001948: f107 032c add.w r3, r7, #44 @ 0x2c 800194c: 4619 mov r1, r3 800194e: 4836 ldr r0, [pc, #216] @ (8001a28 ) 8001950: f001 f858 bl 8002a04 /* UART4 DMA Init */ /* UART4_RX Init */ hdma_uart4_rx.Instance = DMA1_Stream2; 8001954: 4b35 ldr r3, [pc, #212] @ (8001a2c ) 8001956: 4a36 ldr r2, [pc, #216] @ (8001a30 ) 8001958: 601a str r2, [r3, #0] hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; 800195a: 4b34 ldr r3, [pc, #208] @ (8001a2c ) 800195c: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001960: 605a str r2, [r3, #4] hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001962: 4b32 ldr r3, [pc, #200] @ (8001a2c ) 8001964: 2200 movs r2, #0 8001966: 609a str r2, [r3, #8] hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001968: 4b30 ldr r3, [pc, #192] @ (8001a2c ) 800196a: 2200 movs r2, #0 800196c: 60da str r2, [r3, #12] hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; 800196e: 4b2f ldr r3, [pc, #188] @ (8001a2c ) 8001970: f44f 6280 mov.w r2, #1024 @ 0x400 8001974: 611a str r2, [r3, #16] hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001976: 4b2d ldr r3, [pc, #180] @ (8001a2c ) 8001978: 2200 movs r2, #0 800197a: 615a str r2, [r3, #20] hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800197c: 4b2b ldr r3, [pc, #172] @ (8001a2c ) 800197e: 2200 movs r2, #0 8001980: 619a str r2, [r3, #24] hdma_uart4_rx.Init.Mode = DMA_NORMAL; 8001982: 4b2a ldr r3, [pc, #168] @ (8001a2c ) 8001984: 2200 movs r2, #0 8001986: 61da str r2, [r3, #28] hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; 8001988: 4b28 ldr r3, [pc, #160] @ (8001a2c ) 800198a: 2200 movs r2, #0 800198c: 621a str r2, [r3, #32] hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800198e: 4b27 ldr r3, [pc, #156] @ (8001a2c ) 8001990: 2200 movs r2, #0 8001992: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) 8001994: 4825 ldr r0, [pc, #148] @ (8001a2c ) 8001996: f000 fc33 bl 8002200 800199a: 4603 mov r3, r0 800199c: 2b00 cmp r3, #0 800199e: d001 beq.n 80019a4 { Error_Handler(); 80019a0: f7ff fcd4 bl 800134c } __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); 80019a4: 687b ldr r3, [r7, #4] 80019a6: 4a21 ldr r2, [pc, #132] @ (8001a2c ) 80019a8: 63da str r2, [r3, #60] @ 0x3c 80019aa: 4a20 ldr r2, [pc, #128] @ (8001a2c ) 80019ac: 687b ldr r3, [r7, #4] 80019ae: 6393 str r3, [r2, #56] @ 0x38 /* UART4_TX Init */ hdma_uart4_tx.Instance = DMA1_Stream4; 80019b0: 4b20 ldr r3, [pc, #128] @ (8001a34 ) 80019b2: 4a21 ldr r2, [pc, #132] @ (8001a38 ) 80019b4: 601a str r2, [r3, #0] hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; 80019b6: 4b1f ldr r3, [pc, #124] @ (8001a34 ) 80019b8: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80019bc: 605a str r2, [r3, #4] hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80019be: 4b1d ldr r3, [pc, #116] @ (8001a34 ) 80019c0: 2240 movs r2, #64 @ 0x40 80019c2: 609a str r2, [r3, #8] hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80019c4: 4b1b ldr r3, [pc, #108] @ (8001a34 ) 80019c6: 2200 movs r2, #0 80019c8: 60da str r2, [r3, #12] hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; 80019ca: 4b1a ldr r3, [pc, #104] @ (8001a34 ) 80019cc: f44f 6280 mov.w r2, #1024 @ 0x400 80019d0: 611a str r2, [r3, #16] hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80019d2: 4b18 ldr r3, [pc, #96] @ (8001a34 ) 80019d4: 2200 movs r2, #0 80019d6: 615a str r2, [r3, #20] hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80019d8: 4b16 ldr r3, [pc, #88] @ (8001a34 ) 80019da: 2200 movs r2, #0 80019dc: 619a str r2, [r3, #24] hdma_uart4_tx.Init.Mode = DMA_NORMAL; 80019de: 4b15 ldr r3, [pc, #84] @ (8001a34 ) 80019e0: 2200 movs r2, #0 80019e2: 61da str r2, [r3, #28] hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; 80019e4: 4b13 ldr r3, [pc, #76] @ (8001a34 ) 80019e6: 2200 movs r2, #0 80019e8: 621a str r2, [r3, #32] hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80019ea: 4b12 ldr r3, [pc, #72] @ (8001a34 ) 80019ec: 2200 movs r2, #0 80019ee: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) 80019f0: 4810 ldr r0, [pc, #64] @ (8001a34 ) 80019f2: f000 fc05 bl 8002200 80019f6: 4603 mov r3, r0 80019f8: 2b00 cmp r3, #0 80019fa: d001 beq.n 8001a00 { Error_Handler(); 80019fc: f7ff fca6 bl 800134c } __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); 8001a00: 687b ldr r3, [r7, #4] 8001a02: 4a0c ldr r2, [pc, #48] @ (8001a34 ) 8001a04: 639a str r2, [r3, #56] @ 0x38 8001a06: 4a0b ldr r2, [pc, #44] @ (8001a34 ) 8001a08: 687b ldr r3, [r7, #4] 8001a0a: 6393 str r3, [r2, #56] @ 0x38 /* UART4 interrupt Init */ HAL_NVIC_SetPriority(UART4_IRQn, 5, 0); 8001a0c: 2200 movs r2, #0 8001a0e: 2105 movs r1, #5 8001a10: 2034 movs r0, #52 @ 0x34 8001a12: f000 fbbe bl 8002192 HAL_NVIC_EnableIRQ(UART4_IRQn); 8001a16: 2034 movs r0, #52 @ 0x34 8001a18: f000 fbd7 bl 80021ca HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8001a1c: e202 b.n 8001e24 8001a1e: bf00 nop 8001a20: 40004c00 .word 0x40004c00 8001a24: 40023800 .word 0x40023800 8001a28: 40020000 .word 0x40020000 8001a2c: 20000c00 .word 0x20000c00 8001a30: 40026040 .word 0x40026040 8001a34: 20000c60 .word 0x20000c60 8001a38: 40026070 .word 0x40026070 else if(uartHandle->Instance==UART5) 8001a3c: 687b ldr r3, [r7, #4] 8001a3e: 681b ldr r3, [r3, #0] 8001a40: 4a59 ldr r2, [pc, #356] @ (8001ba8 ) 8001a42: 4293 cmp r3, r2 8001a44: f040 80c0 bne.w 8001bc8 __HAL_RCC_UART5_CLK_ENABLE(); 8001a48: 2300 movs r3, #0 8001a4a: 623b str r3, [r7, #32] 8001a4c: 4b57 ldr r3, [pc, #348] @ (8001bac ) 8001a4e: 6c1b ldr r3, [r3, #64] @ 0x40 8001a50: 4a56 ldr r2, [pc, #344] @ (8001bac ) 8001a52: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8001a56: 6413 str r3, [r2, #64] @ 0x40 8001a58: 4b54 ldr r3, [pc, #336] @ (8001bac ) 8001a5a: 6c1b ldr r3, [r3, #64] @ 0x40 8001a5c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8001a60: 623b str r3, [r7, #32] 8001a62: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001a64: 2300 movs r3, #0 8001a66: 61fb str r3, [r7, #28] 8001a68: 4b50 ldr r3, [pc, #320] @ (8001bac ) 8001a6a: 6b1b ldr r3, [r3, #48] @ 0x30 8001a6c: 4a4f ldr r2, [pc, #316] @ (8001bac ) 8001a6e: f043 0304 orr.w r3, r3, #4 8001a72: 6313 str r3, [r2, #48] @ 0x30 8001a74: 4b4d ldr r3, [pc, #308] @ (8001bac ) 8001a76: 6b1b ldr r3, [r3, #48] @ 0x30 8001a78: f003 0304 and.w r3, r3, #4 8001a7c: 61fb str r3, [r7, #28] 8001a7e: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001a80: 2300 movs r3, #0 8001a82: 61bb str r3, [r7, #24] 8001a84: 4b49 ldr r3, [pc, #292] @ (8001bac ) 8001a86: 6b1b ldr r3, [r3, #48] @ 0x30 8001a88: 4a48 ldr r2, [pc, #288] @ (8001bac ) 8001a8a: f043 0308 orr.w r3, r3, #8 8001a8e: 6313 str r3, [r2, #48] @ 0x30 8001a90: 4b46 ldr r3, [pc, #280] @ (8001bac ) 8001a92: 6b1b ldr r3, [r3, #48] @ 0x30 8001a94: f003 0308 and.w r3, r3, #8 8001a98: 61bb str r3, [r7, #24] 8001a9a: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_12; 8001a9c: f44f 5380 mov.w r3, #4096 @ 0x1000 8001aa0: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001aa2: 2302 movs r3, #2 8001aa4: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001aa6: 2300 movs r3, #0 8001aa8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001aaa: 2303 movs r3, #3 8001aac: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 8001aae: 2308 movs r3, #8 8001ab0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8001ab2: f107 032c add.w r3, r7, #44 @ 0x2c 8001ab6: 4619 mov r1, r3 8001ab8: 483d ldr r0, [pc, #244] @ (8001bb0 ) 8001aba: f000 ffa3 bl 8002a04 GPIO_InitStruct.Pin = GPIO_PIN_2; 8001abe: 2304 movs r3, #4 8001ac0: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001ac2: 2302 movs r3, #2 8001ac4: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001ac6: 2300 movs r3, #0 8001ac8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001aca: 2303 movs r3, #3 8001acc: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 8001ace: 2308 movs r3, #8 8001ad0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001ad2: f107 032c add.w r3, r7, #44 @ 0x2c 8001ad6: 4619 mov r1, r3 8001ad8: 4836 ldr r0, [pc, #216] @ (8001bb4 ) 8001ada: f000 ff93 bl 8002a04 hdma_uart5_rx.Instance = DMA1_Stream0; 8001ade: 4b36 ldr r3, [pc, #216] @ (8001bb8 ) 8001ae0: 4a36 ldr r2, [pc, #216] @ (8001bbc ) 8001ae2: 601a str r2, [r3, #0] hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; 8001ae4: 4b34 ldr r3, [pc, #208] @ (8001bb8 ) 8001ae6: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001aea: 605a str r2, [r3, #4] hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001aec: 4b32 ldr r3, [pc, #200] @ (8001bb8 ) 8001aee: 2200 movs r2, #0 8001af0: 609a str r2, [r3, #8] hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001af2: 4b31 ldr r3, [pc, #196] @ (8001bb8 ) 8001af4: 2200 movs r2, #0 8001af6: 60da str r2, [r3, #12] hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; 8001af8: 4b2f ldr r3, [pc, #188] @ (8001bb8 ) 8001afa: f44f 6280 mov.w r2, #1024 @ 0x400 8001afe: 611a str r2, [r3, #16] hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001b00: 4b2d ldr r3, [pc, #180] @ (8001bb8 ) 8001b02: 2200 movs r2, #0 8001b04: 615a str r2, [r3, #20] hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001b06: 4b2c ldr r3, [pc, #176] @ (8001bb8 ) 8001b08: 2200 movs r2, #0 8001b0a: 619a str r2, [r3, #24] hdma_uart5_rx.Init.Mode = DMA_NORMAL; 8001b0c: 4b2a ldr r3, [pc, #168] @ (8001bb8 ) 8001b0e: 2200 movs r2, #0 8001b10: 61da str r2, [r3, #28] hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; 8001b12: 4b29 ldr r3, [pc, #164] @ (8001bb8 ) 8001b14: 2200 movs r2, #0 8001b16: 621a str r2, [r3, #32] hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001b18: 4b27 ldr r3, [pc, #156] @ (8001bb8 ) 8001b1a: 2200 movs r2, #0 8001b1c: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) 8001b1e: 4826 ldr r0, [pc, #152] @ (8001bb8 ) 8001b20: f000 fb6e bl 8002200 8001b24: 4603 mov r3, r0 8001b26: 2b00 cmp r3, #0 8001b28: d001 beq.n 8001b2e Error_Handler(); 8001b2a: f7ff fc0f bl 800134c __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); 8001b2e: 687b ldr r3, [r7, #4] 8001b30: 4a21 ldr r2, [pc, #132] @ (8001bb8 ) 8001b32: 63da str r2, [r3, #60] @ 0x3c 8001b34: 4a20 ldr r2, [pc, #128] @ (8001bb8 ) 8001b36: 687b ldr r3, [r7, #4] 8001b38: 6393 str r3, [r2, #56] @ 0x38 hdma_uart5_tx.Instance = DMA1_Stream7; 8001b3a: 4b21 ldr r3, [pc, #132] @ (8001bc0 ) 8001b3c: 4a21 ldr r2, [pc, #132] @ (8001bc4 ) 8001b3e: 601a str r2, [r3, #0] hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; 8001b40: 4b1f ldr r3, [pc, #124] @ (8001bc0 ) 8001b42: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001b46: 605a str r2, [r3, #4] hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001b48: 4b1d ldr r3, [pc, #116] @ (8001bc0 ) 8001b4a: 2240 movs r2, #64 @ 0x40 8001b4c: 609a str r2, [r3, #8] hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001b4e: 4b1c ldr r3, [pc, #112] @ (8001bc0 ) 8001b50: 2200 movs r2, #0 8001b52: 60da str r2, [r3, #12] hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; 8001b54: 4b1a ldr r3, [pc, #104] @ (8001bc0 ) 8001b56: f44f 6280 mov.w r2, #1024 @ 0x400 8001b5a: 611a str r2, [r3, #16] hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001b5c: 4b18 ldr r3, [pc, #96] @ (8001bc0 ) 8001b5e: 2200 movs r2, #0 8001b60: 615a str r2, [r3, #20] hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001b62: 4b17 ldr r3, [pc, #92] @ (8001bc0 ) 8001b64: 2200 movs r2, #0 8001b66: 619a str r2, [r3, #24] hdma_uart5_tx.Init.Mode = DMA_NORMAL; 8001b68: 4b15 ldr r3, [pc, #84] @ (8001bc0 ) 8001b6a: 2200 movs r2, #0 8001b6c: 61da str r2, [r3, #28] hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; 8001b6e: 4b14 ldr r3, [pc, #80] @ (8001bc0 ) 8001b70: 2200 movs r2, #0 8001b72: 621a str r2, [r3, #32] hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001b74: 4b12 ldr r3, [pc, #72] @ (8001bc0 ) 8001b76: 2200 movs r2, #0 8001b78: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) 8001b7a: 4811 ldr r0, [pc, #68] @ (8001bc0 ) 8001b7c: f000 fb40 bl 8002200 8001b80: 4603 mov r3, r0 8001b82: 2b00 cmp r3, #0 8001b84: d001 beq.n 8001b8a Error_Handler(); 8001b86: f7ff fbe1 bl 800134c __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); 8001b8a: 687b ldr r3, [r7, #4] 8001b8c: 4a0c ldr r2, [pc, #48] @ (8001bc0 ) 8001b8e: 639a str r2, [r3, #56] @ 0x38 8001b90: 4a0b ldr r2, [pc, #44] @ (8001bc0 ) 8001b92: 687b ldr r3, [r7, #4] 8001b94: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); 8001b96: 2200 movs r2, #0 8001b98: 2105 movs r1, #5 8001b9a: 2035 movs r0, #53 @ 0x35 8001b9c: f000 faf9 bl 8002192 HAL_NVIC_EnableIRQ(UART5_IRQn); 8001ba0: 2035 movs r0, #53 @ 0x35 8001ba2: f000 fb12 bl 80021ca } 8001ba6: e13d b.n 8001e24 8001ba8: 40005000 .word 0x40005000 8001bac: 40023800 .word 0x40023800 8001bb0: 40020800 .word 0x40020800 8001bb4: 40020c00 .word 0x40020c00 8001bb8: 20000cc0 .word 0x20000cc0 8001bbc: 40026010 .word 0x40026010 8001bc0: 20000d20 .word 0x20000d20 8001bc4: 400260b8 .word 0x400260b8 else if(uartHandle->Instance==USART1) 8001bc8: 687b ldr r3, [r7, #4] 8001bca: 681b ldr r3, [r3, #0] 8001bcc: 4a97 ldr r2, [pc, #604] @ (8001e2c ) 8001bce: 4293 cmp r3, r2 8001bd0: f040 8092 bne.w 8001cf8 __HAL_RCC_USART1_CLK_ENABLE(); 8001bd4: 2300 movs r3, #0 8001bd6: 617b str r3, [r7, #20] 8001bd8: 4b95 ldr r3, [pc, #596] @ (8001e30 ) 8001bda: 6c5b ldr r3, [r3, #68] @ 0x44 8001bdc: 4a94 ldr r2, [pc, #592] @ (8001e30 ) 8001bde: f043 0310 orr.w r3, r3, #16 8001be2: 6453 str r3, [r2, #68] @ 0x44 8001be4: 4b92 ldr r3, [pc, #584] @ (8001e30 ) 8001be6: 6c5b ldr r3, [r3, #68] @ 0x44 8001be8: f003 0310 and.w r3, r3, #16 8001bec: 617b str r3, [r7, #20] 8001bee: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001bf0: 2300 movs r3, #0 8001bf2: 613b str r3, [r7, #16] 8001bf4: 4b8e ldr r3, [pc, #568] @ (8001e30 ) 8001bf6: 6b1b ldr r3, [r3, #48] @ 0x30 8001bf8: 4a8d ldr r2, [pc, #564] @ (8001e30 ) 8001bfa: f043 0301 orr.w r3, r3, #1 8001bfe: 6313 str r3, [r2, #48] @ 0x30 8001c00: 4b8b ldr r3, [pc, #556] @ (8001e30 ) 8001c02: 6b1b ldr r3, [r3, #48] @ 0x30 8001c04: f003 0301 and.w r3, r3, #1 8001c08: 613b str r3, [r7, #16] 8001c0a: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 8001c0c: f44f 63c0 mov.w r3, #1536 @ 0x600 8001c10: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001c12: 2302 movs r3, #2 8001c14: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001c16: 2300 movs r3, #0 8001c18: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001c1a: 2303 movs r3, #3 8001c1c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 8001c1e: 2307 movs r3, #7 8001c20: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001c22: f107 032c add.w r3, r7, #44 @ 0x2c 8001c26: 4619 mov r1, r3 8001c28: 4882 ldr r0, [pc, #520] @ (8001e34 ) 8001c2a: f000 feeb bl 8002a04 hdma_usart1_rx.Instance = DMA2_Stream2; 8001c2e: 4b82 ldr r3, [pc, #520] @ (8001e38 ) 8001c30: 4a82 ldr r2, [pc, #520] @ (8001e3c ) 8001c32: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; 8001c34: 4b80 ldr r3, [pc, #512] @ (8001e38 ) 8001c36: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001c3a: 605a str r2, [r3, #4] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001c3c: 4b7e ldr r3, [pc, #504] @ (8001e38 ) 8001c3e: 2200 movs r2, #0 8001c40: 609a str r2, [r3, #8] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001c42: 4b7d ldr r3, [pc, #500] @ (8001e38 ) 8001c44: 2200 movs r2, #0 8001c46: 60da str r2, [r3, #12] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8001c48: 4b7b ldr r3, [pc, #492] @ (8001e38 ) 8001c4a: f44f 6280 mov.w r2, #1024 @ 0x400 8001c4e: 611a str r2, [r3, #16] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001c50: 4b79 ldr r3, [pc, #484] @ (8001e38 ) 8001c52: 2200 movs r2, #0 8001c54: 615a str r2, [r3, #20] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001c56: 4b78 ldr r3, [pc, #480] @ (8001e38 ) 8001c58: 2200 movs r2, #0 8001c5a: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 8001c5c: 4b76 ldr r3, [pc, #472] @ (8001e38 ) 8001c5e: 2200 movs r2, #0 8001c60: 61da str r2, [r3, #28] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 8001c62: 4b75 ldr r3, [pc, #468] @ (8001e38 ) 8001c64: 2200 movs r2, #0 8001c66: 621a str r2, [r3, #32] hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001c68: 4b73 ldr r3, [pc, #460] @ (8001e38 ) 8001c6a: 2200 movs r2, #0 8001c6c: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 8001c6e: 4872 ldr r0, [pc, #456] @ (8001e38 ) 8001c70: f000 fac6 bl 8002200 8001c74: 4603 mov r3, r0 8001c76: 2b00 cmp r3, #0 8001c78: d001 beq.n 8001c7e Error_Handler(); 8001c7a: f7ff fb67 bl 800134c __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); 8001c7e: 687b ldr r3, [r7, #4] 8001c80: 4a6d ldr r2, [pc, #436] @ (8001e38 ) 8001c82: 63da str r2, [r3, #60] @ 0x3c 8001c84: 4a6c ldr r2, [pc, #432] @ (8001e38 ) 8001c86: 687b ldr r3, [r7, #4] 8001c88: 6393 str r3, [r2, #56] @ 0x38 hdma_usart1_tx.Instance = DMA2_Stream7; 8001c8a: 4b6d ldr r3, [pc, #436] @ (8001e40 ) 8001c8c: 4a6d ldr r2, [pc, #436] @ (8001e44 ) 8001c8e: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; 8001c90: 4b6b ldr r3, [pc, #428] @ (8001e40 ) 8001c92: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001c96: 605a str r2, [r3, #4] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001c98: 4b69 ldr r3, [pc, #420] @ (8001e40 ) 8001c9a: 2240 movs r2, #64 @ 0x40 8001c9c: 609a str r2, [r3, #8] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001c9e: 4b68 ldr r3, [pc, #416] @ (8001e40 ) 8001ca0: 2200 movs r2, #0 8001ca2: 60da str r2, [r3, #12] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 8001ca4: 4b66 ldr r3, [pc, #408] @ (8001e40 ) 8001ca6: f44f 6280 mov.w r2, #1024 @ 0x400 8001caa: 611a str r2, [r3, #16] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001cac: 4b64 ldr r3, [pc, #400] @ (8001e40 ) 8001cae: 2200 movs r2, #0 8001cb0: 615a str r2, [r3, #20] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001cb2: 4b63 ldr r3, [pc, #396] @ (8001e40 ) 8001cb4: 2200 movs r2, #0 8001cb6: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 8001cb8: 4b61 ldr r3, [pc, #388] @ (8001e40 ) 8001cba: 2200 movs r2, #0 8001cbc: 61da str r2, [r3, #28] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 8001cbe: 4b60 ldr r3, [pc, #384] @ (8001e40 ) 8001cc0: 2200 movs r2, #0 8001cc2: 621a str r2, [r3, #32] hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001cc4: 4b5e ldr r3, [pc, #376] @ (8001e40 ) 8001cc6: 2200 movs r2, #0 8001cc8: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 8001cca: 485d ldr r0, [pc, #372] @ (8001e40 ) 8001ccc: f000 fa98 bl 8002200 8001cd0: 4603 mov r3, r0 8001cd2: 2b00 cmp r3, #0 8001cd4: d001 beq.n 8001cda Error_Handler(); 8001cd6: f7ff fb39 bl 800134c __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); 8001cda: 687b ldr r3, [r7, #4] 8001cdc: 4a58 ldr r2, [pc, #352] @ (8001e40 ) 8001cde: 639a str r2, [r3, #56] @ 0x38 8001ce0: 4a57 ldr r2, [pc, #348] @ (8001e40 ) 8001ce2: 687b ldr r3, [r7, #4] 8001ce4: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 8001ce6: 2200 movs r2, #0 8001ce8: 2105 movs r1, #5 8001cea: 2025 movs r0, #37 @ 0x25 8001cec: f000 fa51 bl 8002192 HAL_NVIC_EnableIRQ(USART1_IRQn); 8001cf0: 2025 movs r0, #37 @ 0x25 8001cf2: f000 fa6a bl 80021ca } 8001cf6: e095 b.n 8001e24 else if(uartHandle->Instance==USART2) 8001cf8: 687b ldr r3, [r7, #4] 8001cfa: 681b ldr r3, [r3, #0] 8001cfc: 4a52 ldr r2, [pc, #328] @ (8001e48 ) 8001cfe: 4293 cmp r3, r2 8001d00: f040 8090 bne.w 8001e24 __HAL_RCC_USART2_CLK_ENABLE(); 8001d04: 2300 movs r3, #0 8001d06: 60fb str r3, [r7, #12] 8001d08: 4b49 ldr r3, [pc, #292] @ (8001e30 ) 8001d0a: 6c1b ldr r3, [r3, #64] @ 0x40 8001d0c: 4a48 ldr r2, [pc, #288] @ (8001e30 ) 8001d0e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001d12: 6413 str r3, [r2, #64] @ 0x40 8001d14: 4b46 ldr r3, [pc, #280] @ (8001e30 ) 8001d16: 6c1b ldr r3, [r3, #64] @ 0x40 8001d18: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001d1c: 60fb str r3, [r7, #12] 8001d1e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001d20: 2300 movs r3, #0 8001d22: 60bb str r3, [r7, #8] 8001d24: 4b42 ldr r3, [pc, #264] @ (8001e30 ) 8001d26: 6b1b ldr r3, [r3, #48] @ 0x30 8001d28: 4a41 ldr r2, [pc, #260] @ (8001e30 ) 8001d2a: f043 0301 orr.w r3, r3, #1 8001d2e: 6313 str r3, [r2, #48] @ 0x30 8001d30: 4b3f ldr r3, [pc, #252] @ (8001e30 ) 8001d32: 6b1b ldr r3, [r3, #48] @ 0x30 8001d34: f003 0301 and.w r3, r3, #1 8001d38: 60bb str r3, [r7, #8] 8001d3a: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 8001d3c: 230c movs r3, #12 8001d3e: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001d40: 2302 movs r3, #2 8001d42: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001d44: 2300 movs r3, #0 8001d46: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001d48: 2303 movs r3, #3 8001d4a: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8001d4c: 2307 movs r3, #7 8001d4e: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001d50: f107 032c add.w r3, r7, #44 @ 0x2c 8001d54: 4619 mov r1, r3 8001d56: 4837 ldr r0, [pc, #220] @ (8001e34 ) 8001d58: f000 fe54 bl 8002a04 hdma_usart2_rx.Instance = DMA1_Stream5; 8001d5c: 4b3b ldr r3, [pc, #236] @ (8001e4c ) 8001d5e: 4a3c ldr r2, [pc, #240] @ (8001e50 ) 8001d60: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; 8001d62: 4b3a ldr r3, [pc, #232] @ (8001e4c ) 8001d64: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001d68: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001d6a: 4b38 ldr r3, [pc, #224] @ (8001e4c ) 8001d6c: 2200 movs r2, #0 8001d6e: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001d70: 4b36 ldr r3, [pc, #216] @ (8001e4c ) 8001d72: 2200 movs r2, #0 8001d74: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 8001d76: 4b35 ldr r3, [pc, #212] @ (8001e4c ) 8001d78: f44f 6280 mov.w r2, #1024 @ 0x400 8001d7c: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001d7e: 4b33 ldr r3, [pc, #204] @ (8001e4c ) 8001d80: 2200 movs r2, #0 8001d82: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001d84: 4b31 ldr r3, [pc, #196] @ (8001e4c ) 8001d86: 2200 movs r2, #0 8001d88: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 8001d8a: 4b30 ldr r3, [pc, #192] @ (8001e4c ) 8001d8c: 2200 movs r2, #0 8001d8e: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 8001d90: 4b2e ldr r3, [pc, #184] @ (8001e4c ) 8001d92: 2200 movs r2, #0 8001d94: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001d96: 4b2d ldr r3, [pc, #180] @ (8001e4c ) 8001d98: 2200 movs r2, #0 8001d9a: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8001d9c: 482b ldr r0, [pc, #172] @ (8001e4c ) 8001d9e: f000 fa2f bl 8002200 8001da2: 4603 mov r3, r0 8001da4: 2b00 cmp r3, #0 8001da6: d001 beq.n 8001dac Error_Handler(); 8001da8: f7ff fad0 bl 800134c __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 8001dac: 687b ldr r3, [r7, #4] 8001dae: 4a27 ldr r2, [pc, #156] @ (8001e4c ) 8001db0: 63da str r2, [r3, #60] @ 0x3c 8001db2: 4a26 ldr r2, [pc, #152] @ (8001e4c ) 8001db4: 687b ldr r3, [r7, #4] 8001db6: 6393 str r3, [r2, #56] @ 0x38 hdma_usart2_tx.Instance = DMA1_Stream6; 8001db8: 4b26 ldr r3, [pc, #152] @ (8001e54 ) 8001dba: 4a27 ldr r2, [pc, #156] @ (8001e58 ) 8001dbc: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; 8001dbe: 4b25 ldr r3, [pc, #148] @ (8001e54 ) 8001dc0: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001dc4: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001dc6: 4b23 ldr r3, [pc, #140] @ (8001e54 ) 8001dc8: 2240 movs r2, #64 @ 0x40 8001dca: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001dcc: 4b21 ldr r3, [pc, #132] @ (8001e54 ) 8001dce: 2200 movs r2, #0 8001dd0: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 8001dd2: 4b20 ldr r3, [pc, #128] @ (8001e54 ) 8001dd4: f44f 6280 mov.w r2, #1024 @ 0x400 8001dd8: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001dda: 4b1e ldr r3, [pc, #120] @ (8001e54 ) 8001ddc: 2200 movs r2, #0 8001dde: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001de0: 4b1c ldr r3, [pc, #112] @ (8001e54 ) 8001de2: 2200 movs r2, #0 8001de4: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 8001de6: 4b1b ldr r3, [pc, #108] @ (8001e54 ) 8001de8: 2200 movs r2, #0 8001dea: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 8001dec: 4b19 ldr r3, [pc, #100] @ (8001e54 ) 8001dee: 2200 movs r2, #0 8001df0: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001df2: 4b18 ldr r3, [pc, #96] @ (8001e54 ) 8001df4: 2200 movs r2, #0 8001df6: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 8001df8: 4816 ldr r0, [pc, #88] @ (8001e54 ) 8001dfa: f000 fa01 bl 8002200 8001dfe: 4603 mov r3, r0 8001e00: 2b00 cmp r3, #0 8001e02: d001 beq.n 8001e08 Error_Handler(); 8001e04: f7ff faa2 bl 800134c __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 8001e08: 687b ldr r3, [r7, #4] 8001e0a: 4a12 ldr r2, [pc, #72] @ (8001e54 ) 8001e0c: 639a str r2, [r3, #56] @ 0x38 8001e0e: 4a11 ldr r2, [pc, #68] @ (8001e54 ) 8001e10: 687b ldr r3, [r7, #4] 8001e12: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); 8001e14: 2200 movs r2, #0 8001e16: 2105 movs r1, #5 8001e18: 2026 movs r0, #38 @ 0x26 8001e1a: f000 f9ba bl 8002192 HAL_NVIC_EnableIRQ(USART2_IRQn); 8001e1e: 2026 movs r0, #38 @ 0x26 8001e20: f000 f9d3 bl 80021ca } 8001e24: bf00 nop 8001e26: 3740 adds r7, #64 @ 0x40 8001e28: 46bd mov sp, r7 8001e2a: bd80 pop {r7, pc} 8001e2c: 40011000 .word 0x40011000 8001e30: 40023800 .word 0x40023800 8001e34: 40020000 .word 0x40020000 8001e38: 20000d80 .word 0x20000d80 8001e3c: 40026440 .word 0x40026440 8001e40: 20000de0 .word 0x20000de0 8001e44: 400264b8 .word 0x400264b8 8001e48: 40004400 .word 0x40004400 8001e4c: 20000e40 .word 0x20000e40 8001e50: 40026088 .word 0x40026088 8001e54: 20000ea0 .word 0x20000ea0 8001e58: 400260a0 .word 0x400260a0 08001e5c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001e5c: f8df d034 ldr.w sp, [pc, #52] @ 8001e94 /* Call the clock system initialization function.*/ bl SystemInit 8001e60: f7ff fb54 bl 800150c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001e64: 480c ldr r0, [pc, #48] @ (8001e98 ) ldr r1, =_edata 8001e66: 490d ldr r1, [pc, #52] @ (8001e9c ) ldr r2, =_sidata 8001e68: 4a0d ldr r2, [pc, #52] @ (8001ea0 ) movs r3, #0 8001e6a: 2300 movs r3, #0 b LoopCopyDataInit 8001e6c: e002 b.n 8001e74 08001e6e : CopyDataInit: ldr r4, [r2, r3] 8001e6e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001e70: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001e72: 3304 adds r3, #4 08001e74 : LoopCopyDataInit: adds r4, r0, r3 8001e74: 18c4 adds r4, r0, r3 cmp r4, r1 8001e76: 428c cmp r4, r1 bcc CopyDataInit 8001e78: d3f9 bcc.n 8001e6e /* Zero fill the bss segment. */ ldr r2, =_sbss 8001e7a: 4a0a ldr r2, [pc, #40] @ (8001ea4 ) ldr r4, =_ebss 8001e7c: 4c0a ldr r4, [pc, #40] @ (8001ea8 ) movs r3, #0 8001e7e: 2300 movs r3, #0 b LoopFillZerobss 8001e80: e001 b.n 8001e86 08001e82 : FillZerobss: str r3, [r2] 8001e82: 6013 str r3, [r2, #0] adds r2, r2, #4 8001e84: 3204 adds r2, #4 08001e86 : LoopFillZerobss: cmp r2, r4 8001e86: 42a2 cmp r2, r4 bcc FillZerobss 8001e88: d3fb bcc.n 8001e82 /* Call static constructors */ bl __libc_init_array 8001e8a: f009 fca1 bl 800b7d0 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001e8e: f7fe fd4b bl 8000928
bx lr 8001e92: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001e94: 20020000 .word 0x20020000 ldr r0, =_sdata 8001e98: 20000000 .word 0x20000000 ldr r1, =_edata 8001e9c: 200001a0 .word 0x200001a0 ldr r2, =_sidata 8001ea0: 0800b8b8 .word 0x0800b8b8 ldr r2, =_sbss 8001ea4: 200001a0 .word 0x200001a0 ldr r4, =_ebss 8001ea8: 200018dc .word 0x200018dc 08001eac : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001eac: e7fe b.n 8001eac ... 08001eb0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001eb0: b580 push {r7, lr} 8001eb2: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8001eb4: 4b0e ldr r3, [pc, #56] @ (8001ef0 ) 8001eb6: 681b ldr r3, [r3, #0] 8001eb8: 4a0d ldr r2, [pc, #52] @ (8001ef0 ) 8001eba: f443 7300 orr.w r3, r3, #512 @ 0x200 8001ebe: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8001ec0: 4b0b ldr r3, [pc, #44] @ (8001ef0 ) 8001ec2: 681b ldr r3, [r3, #0] 8001ec4: 4a0a ldr r2, [pc, #40] @ (8001ef0 ) 8001ec6: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001eca: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001ecc: 4b08 ldr r3, [pc, #32] @ (8001ef0 ) 8001ece: 681b ldr r3, [r3, #0] 8001ed0: 4a07 ldr r2, [pc, #28] @ (8001ef0 ) 8001ed2: f443 7380 orr.w r3, r3, #256 @ 0x100 8001ed6: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001ed8: 2003 movs r0, #3 8001eda: f000 f94f bl 800217c /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001ede: 200f movs r0, #15 8001ee0: f000 f808 bl 8001ef4 /* Init the low level hardware */ HAL_MspInit(); 8001ee4: f7ff fa38 bl 8001358 /* Return function status */ return HAL_OK; 8001ee8: 2300 movs r3, #0 } 8001eea: 4618 mov r0, r3 8001eec: bd80 pop {r7, pc} 8001eee: bf00 nop 8001ef0: 40023c00 .word 0x40023c00 08001ef4 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001ef4: b580 push {r7, lr} 8001ef6: b082 sub sp, #8 8001ef8: af00 add r7, sp, #0 8001efa: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001efc: 4b12 ldr r3, [pc, #72] @ (8001f48 ) 8001efe: 681a ldr r2, [r3, #0] 8001f00: 4b12 ldr r3, [pc, #72] @ (8001f4c ) 8001f02: 781b ldrb r3, [r3, #0] 8001f04: 4619 mov r1, r3 8001f06: f44f 737a mov.w r3, #1000 @ 0x3e8 8001f0a: fbb3 f3f1 udiv r3, r3, r1 8001f0e: fbb2 f3f3 udiv r3, r2, r3 8001f12: 4618 mov r0, r3 8001f14: f000 f967 bl 80021e6 8001f18: 4603 mov r3, r0 8001f1a: 2b00 cmp r3, #0 8001f1c: d001 beq.n 8001f22 { return HAL_ERROR; 8001f1e: 2301 movs r3, #1 8001f20: e00e b.n 8001f40 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001f22: 687b ldr r3, [r7, #4] 8001f24: 2b0f cmp r3, #15 8001f26: d80a bhi.n 8001f3e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001f28: 2200 movs r2, #0 8001f2a: 6879 ldr r1, [r7, #4] 8001f2c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001f30: f000 f92f bl 8002192 uwTickPrio = TickPriority; 8001f34: 4a06 ldr r2, [pc, #24] @ (8001f50 ) 8001f36: 687b ldr r3, [r7, #4] 8001f38: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8001f3a: 2300 movs r3, #0 8001f3c: e000 b.n 8001f40 return HAL_ERROR; 8001f3e: 2301 movs r3, #1 } 8001f40: 4618 mov r0, r3 8001f42: 3708 adds r7, #8 8001f44: 46bd mov sp, r7 8001f46: bd80 pop {r7, pc} 8001f48: 20000090 .word 0x20000090 8001f4c: 20000098 .word 0x20000098 8001f50: 20000094 .word 0x20000094 08001f54 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001f54: b480 push {r7} 8001f56: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001f58: 4b06 ldr r3, [pc, #24] @ (8001f74 ) 8001f5a: 781b ldrb r3, [r3, #0] 8001f5c: 461a mov r2, r3 8001f5e: 4b06 ldr r3, [pc, #24] @ (8001f78 ) 8001f60: 681b ldr r3, [r3, #0] 8001f62: 4413 add r3, r2 8001f64: 4a04 ldr r2, [pc, #16] @ (8001f78 ) 8001f66: 6013 str r3, [r2, #0] } 8001f68: bf00 nop 8001f6a: 46bd mov sp, r7 8001f6c: f85d 7b04 ldr.w r7, [sp], #4 8001f70: 4770 bx lr 8001f72: bf00 nop 8001f74: 20000098 .word 0x20000098 8001f78: 20000f00 .word 0x20000f00 08001f7c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001f7c: b480 push {r7} 8001f7e: af00 add r7, sp, #0 return uwTick; 8001f80: 4b03 ldr r3, [pc, #12] @ (8001f90 ) 8001f82: 681b ldr r3, [r3, #0] } 8001f84: 4618 mov r0, r3 8001f86: 46bd mov sp, r7 8001f88: f85d 7b04 ldr.w r7, [sp], #4 8001f8c: 4770 bx lr 8001f8e: bf00 nop 8001f90: 20000f00 .word 0x20000f00 08001f94 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001f94: b580 push {r7, lr} 8001f96: b084 sub sp, #16 8001f98: af00 add r7, sp, #0 8001f9a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001f9c: f7ff ffee bl 8001f7c 8001fa0: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001fa2: 687b ldr r3, [r7, #4] 8001fa4: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001fa6: 68fb ldr r3, [r7, #12] 8001fa8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001fac: d005 beq.n 8001fba { wait += (uint32_t)(uwTickFreq); 8001fae: 4b0a ldr r3, [pc, #40] @ (8001fd8 ) 8001fb0: 781b ldrb r3, [r3, #0] 8001fb2: 461a mov r2, r3 8001fb4: 68fb ldr r3, [r7, #12] 8001fb6: 4413 add r3, r2 8001fb8: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001fba: bf00 nop 8001fbc: f7ff ffde bl 8001f7c 8001fc0: 4602 mov r2, r0 8001fc2: 68bb ldr r3, [r7, #8] 8001fc4: 1ad3 subs r3, r2, r3 8001fc6: 68fa ldr r2, [r7, #12] 8001fc8: 429a cmp r2, r3 8001fca: d8f7 bhi.n 8001fbc { } } 8001fcc: bf00 nop 8001fce: bf00 nop 8001fd0: 3710 adds r7, #16 8001fd2: 46bd mov sp, r7 8001fd4: bd80 pop {r7, pc} 8001fd6: bf00 nop 8001fd8: 20000098 .word 0x20000098 08001fdc <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001fdc: b480 push {r7} 8001fde: b085 sub sp, #20 8001fe0: af00 add r7, sp, #0 8001fe2: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001fe4: 687b ldr r3, [r7, #4] 8001fe6: f003 0307 and.w r3, r3, #7 8001fea: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001fec: 4b0c ldr r3, [pc, #48] @ (8002020 <__NVIC_SetPriorityGrouping+0x44>) 8001fee: 68db ldr r3, [r3, #12] 8001ff0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001ff2: 68ba ldr r2, [r7, #8] 8001ff4: f64f 03ff movw r3, #63743 @ 0xf8ff 8001ff8: 4013 ands r3, r2 8001ffa: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001ffc: 68fb ldr r3, [r7, #12] 8001ffe: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002000: 68bb ldr r3, [r7, #8] 8002002: 4313 orrs r3, r2 reg_value = (reg_value | 8002004: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8002008: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800200c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800200e: 4a04 ldr r2, [pc, #16] @ (8002020 <__NVIC_SetPriorityGrouping+0x44>) 8002010: 68bb ldr r3, [r7, #8] 8002012: 60d3 str r3, [r2, #12] } 8002014: bf00 nop 8002016: 3714 adds r7, #20 8002018: 46bd mov sp, r7 800201a: f85d 7b04 ldr.w r7, [sp], #4 800201e: 4770 bx lr 8002020: e000ed00 .word 0xe000ed00 08002024 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8002024: b480 push {r7} 8002026: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8002028: 4b04 ldr r3, [pc, #16] @ (800203c <__NVIC_GetPriorityGrouping+0x18>) 800202a: 68db ldr r3, [r3, #12] 800202c: 0a1b lsrs r3, r3, #8 800202e: f003 0307 and.w r3, r3, #7 } 8002032: 4618 mov r0, r3 8002034: 46bd mov sp, r7 8002036: f85d 7b04 ldr.w r7, [sp], #4 800203a: 4770 bx lr 800203c: e000ed00 .word 0xe000ed00 08002040 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8002040: b480 push {r7} 8002042: b083 sub sp, #12 8002044: af00 add r7, sp, #0 8002046: 4603 mov r3, r0 8002048: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800204a: f997 3007 ldrsb.w r3, [r7, #7] 800204e: 2b00 cmp r3, #0 8002050: db0b blt.n 800206a <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8002052: 79fb ldrb r3, [r7, #7] 8002054: f003 021f and.w r2, r3, #31 8002058: 4907 ldr r1, [pc, #28] @ (8002078 <__NVIC_EnableIRQ+0x38>) 800205a: f997 3007 ldrsb.w r3, [r7, #7] 800205e: 095b lsrs r3, r3, #5 8002060: 2001 movs r0, #1 8002062: fa00 f202 lsl.w r2, r0, r2 8002066: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 800206a: bf00 nop 800206c: 370c adds r7, #12 800206e: 46bd mov sp, r7 8002070: f85d 7b04 ldr.w r7, [sp], #4 8002074: 4770 bx lr 8002076: bf00 nop 8002078: e000e100 .word 0xe000e100 0800207c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800207c: b480 push {r7} 800207e: b083 sub sp, #12 8002080: af00 add r7, sp, #0 8002082: 4603 mov r3, r0 8002084: 6039 str r1, [r7, #0] 8002086: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002088: f997 3007 ldrsb.w r3, [r7, #7] 800208c: 2b00 cmp r3, #0 800208e: db0a blt.n 80020a6 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002090: 683b ldr r3, [r7, #0] 8002092: b2da uxtb r2, r3 8002094: 490c ldr r1, [pc, #48] @ (80020c8 <__NVIC_SetPriority+0x4c>) 8002096: f997 3007 ldrsb.w r3, [r7, #7] 800209a: 0112 lsls r2, r2, #4 800209c: b2d2 uxtb r2, r2 800209e: 440b add r3, r1 80020a0: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80020a4: e00a b.n 80020bc <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80020a6: 683b ldr r3, [r7, #0] 80020a8: b2da uxtb r2, r3 80020aa: 4908 ldr r1, [pc, #32] @ (80020cc <__NVIC_SetPriority+0x50>) 80020ac: 79fb ldrb r3, [r7, #7] 80020ae: f003 030f and.w r3, r3, #15 80020b2: 3b04 subs r3, #4 80020b4: 0112 lsls r2, r2, #4 80020b6: b2d2 uxtb r2, r2 80020b8: 440b add r3, r1 80020ba: 761a strb r2, [r3, #24] } 80020bc: bf00 nop 80020be: 370c adds r7, #12 80020c0: 46bd mov sp, r7 80020c2: f85d 7b04 ldr.w r7, [sp], #4 80020c6: 4770 bx lr 80020c8: e000e100 .word 0xe000e100 80020cc: e000ed00 .word 0xe000ed00 080020d0 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80020d0: b480 push {r7} 80020d2: b089 sub sp, #36 @ 0x24 80020d4: af00 add r7, sp, #0 80020d6: 60f8 str r0, [r7, #12] 80020d8: 60b9 str r1, [r7, #8] 80020da: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80020dc: 68fb ldr r3, [r7, #12] 80020de: f003 0307 and.w r3, r3, #7 80020e2: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80020e4: 69fb ldr r3, [r7, #28] 80020e6: f1c3 0307 rsb r3, r3, #7 80020ea: 2b04 cmp r3, #4 80020ec: bf28 it cs 80020ee: 2304 movcs r3, #4 80020f0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80020f2: 69fb ldr r3, [r7, #28] 80020f4: 3304 adds r3, #4 80020f6: 2b06 cmp r3, #6 80020f8: d902 bls.n 8002100 80020fa: 69fb ldr r3, [r7, #28] 80020fc: 3b03 subs r3, #3 80020fe: e000 b.n 8002102 8002100: 2300 movs r3, #0 8002102: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002104: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8002108: 69bb ldr r3, [r7, #24] 800210a: fa02 f303 lsl.w r3, r2, r3 800210e: 43da mvns r2, r3 8002110: 68bb ldr r3, [r7, #8] 8002112: 401a ands r2, r3 8002114: 697b ldr r3, [r7, #20] 8002116: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8002118: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800211c: 697b ldr r3, [r7, #20] 800211e: fa01 f303 lsl.w r3, r1, r3 8002122: 43d9 mvns r1, r3 8002124: 687b ldr r3, [r7, #4] 8002126: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002128: 4313 orrs r3, r2 ); } 800212a: 4618 mov r0, r3 800212c: 3724 adds r7, #36 @ 0x24 800212e: 46bd mov sp, r7 8002130: f85d 7b04 ldr.w r7, [sp], #4 8002134: 4770 bx lr ... 08002138 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8002138: b580 push {r7, lr} 800213a: b082 sub sp, #8 800213c: af00 add r7, sp, #0 800213e: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8002140: 687b ldr r3, [r7, #4] 8002142: 3b01 subs r3, #1 8002144: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002148: d301 bcc.n 800214e { return (1UL); /* Reload value impossible */ 800214a: 2301 movs r3, #1 800214c: e00f b.n 800216e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800214e: 4a0a ldr r2, [pc, #40] @ (8002178 ) 8002150: 687b ldr r3, [r7, #4] 8002152: 3b01 subs r3, #1 8002154: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8002156: 210f movs r1, #15 8002158: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800215c: f7ff ff8e bl 800207c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8002160: 4b05 ldr r3, [pc, #20] @ (8002178 ) 8002162: 2200 movs r2, #0 8002164: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002166: 4b04 ldr r3, [pc, #16] @ (8002178 ) 8002168: 2207 movs r2, #7 800216a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800216c: 2300 movs r3, #0 } 800216e: 4618 mov r0, r3 8002170: 3708 adds r7, #8 8002172: 46bd mov sp, r7 8002174: bd80 pop {r7, pc} 8002176: bf00 nop 8002178: e000e010 .word 0xe000e010 0800217c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800217c: b580 push {r7, lr} 800217e: b082 sub sp, #8 8002180: af00 add r7, sp, #0 8002182: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8002184: 6878 ldr r0, [r7, #4] 8002186: f7ff ff29 bl 8001fdc <__NVIC_SetPriorityGrouping> } 800218a: bf00 nop 800218c: 3708 adds r7, #8 800218e: 46bd mov sp, r7 8002190: bd80 pop {r7, pc} 08002192 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8002192: b580 push {r7, lr} 8002194: b086 sub sp, #24 8002196: af00 add r7, sp, #0 8002198: 4603 mov r3, r0 800219a: 60b9 str r1, [r7, #8] 800219c: 607a str r2, [r7, #4] 800219e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 80021a0: 2300 movs r3, #0 80021a2: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80021a4: f7ff ff3e bl 8002024 <__NVIC_GetPriorityGrouping> 80021a8: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80021aa: 687a ldr r2, [r7, #4] 80021ac: 68b9 ldr r1, [r7, #8] 80021ae: 6978 ldr r0, [r7, #20] 80021b0: f7ff ff8e bl 80020d0 80021b4: 4602 mov r2, r0 80021b6: f997 300f ldrsb.w r3, [r7, #15] 80021ba: 4611 mov r1, r2 80021bc: 4618 mov r0, r3 80021be: f7ff ff5d bl 800207c <__NVIC_SetPriority> } 80021c2: bf00 nop 80021c4: 3718 adds r7, #24 80021c6: 46bd mov sp, r7 80021c8: bd80 pop {r7, pc} 080021ca : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80021ca: b580 push {r7, lr} 80021cc: b082 sub sp, #8 80021ce: af00 add r7, sp, #0 80021d0: 4603 mov r3, r0 80021d2: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80021d4: f997 3007 ldrsb.w r3, [r7, #7] 80021d8: 4618 mov r0, r3 80021da: f7ff ff31 bl 8002040 <__NVIC_EnableIRQ> } 80021de: bf00 nop 80021e0: 3708 adds r7, #8 80021e2: 46bd mov sp, r7 80021e4: bd80 pop {r7, pc} 080021e6 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80021e6: b580 push {r7, lr} 80021e8: b082 sub sp, #8 80021ea: af00 add r7, sp, #0 80021ec: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80021ee: 6878 ldr r0, [r7, #4] 80021f0: f7ff ffa2 bl 8002138 80021f4: 4603 mov r3, r0 } 80021f6: 4618 mov r0, r3 80021f8: 3708 adds r7, #8 80021fa: 46bd mov sp, r7 80021fc: bd80 pop {r7, pc} ... 08002200 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8002200: b580 push {r7, lr} 8002202: b086 sub sp, #24 8002204: af00 add r7, sp, #0 8002206: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8002208: 2300 movs r3, #0 800220a: 617b str r3, [r7, #20] uint32_t tickstart = HAL_GetTick(); 800220c: f7ff feb6 bl 8001f7c 8002210: 6138 str r0, [r7, #16] DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) 8002212: 687b ldr r3, [r7, #4] 8002214: 2b00 cmp r3, #0 8002216: d101 bne.n 800221c { return HAL_ERROR; 8002218: 2301 movs r3, #1 800221a: e099 b.n 8002350 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800221c: 687b ldr r3, [r7, #4] 800221e: 2202 movs r2, #2 8002220: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8002224: 687b ldr r3, [r7, #4] 8002226: 2200 movs r2, #0 8002228: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800222c: 687b ldr r3, [r7, #4] 800222e: 681b ldr r3, [r3, #0] 8002230: 681a ldr r2, [r3, #0] 8002232: 687b ldr r3, [r7, #4] 8002234: 681b ldr r3, [r3, #0] 8002236: f022 0201 bic.w r2, r2, #1 800223a: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 800223c: e00f b.n 800225e { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 800223e: f7ff fe9d bl 8001f7c 8002242: 4602 mov r2, r0 8002244: 693b ldr r3, [r7, #16] 8002246: 1ad3 subs r3, r2, r3 8002248: 2b05 cmp r3, #5 800224a: d908 bls.n 800225e { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800224c: 687b ldr r3, [r7, #4] 800224e: 2220 movs r2, #32 8002250: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8002252: 687b ldr r3, [r7, #4] 8002254: 2203 movs r2, #3 8002256: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_TIMEOUT; 800225a: 2303 movs r3, #3 800225c: e078 b.n 8002350 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 800225e: 687b ldr r3, [r7, #4] 8002260: 681b ldr r3, [r3, #0] 8002262: 681b ldr r3, [r3, #0] 8002264: f003 0301 and.w r3, r3, #1 8002268: 2b00 cmp r3, #0 800226a: d1e8 bne.n 800223e } } /* Get the CR register value */ tmp = hdma->Instance->CR; 800226c: 687b ldr r3, [r7, #4] 800226e: 681b ldr r3, [r3, #0] 8002270: 681b ldr r3, [r3, #0] 8002272: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8002274: 697a ldr r2, [r7, #20] 8002276: 4b38 ldr r3, [pc, #224] @ (8002358 ) 8002278: 4013 ands r3, r2 800227a: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | 800227c: 687b ldr r3, [r7, #4] 800227e: 685a ldr r2, [r3, #4] 8002280: 687b ldr r3, [r7, #4] 8002282: 689b ldr r3, [r3, #8] 8002284: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8002286: 687b ldr r3, [r7, #4] 8002288: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Channel | hdma->Init.Direction | 800228a: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 800228c: 687b ldr r3, [r7, #4] 800228e: 691b ldr r3, [r3, #16] 8002290: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002292: 687b ldr r3, [r7, #4] 8002294: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8002296: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002298: 687b ldr r3, [r7, #4] 800229a: 699b ldr r3, [r3, #24] 800229c: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800229e: 687b ldr r3, [r7, #4] 80022a0: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80022a2: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80022a4: 687b ldr r3, [r7, #4] 80022a6: 6a1b ldr r3, [r3, #32] 80022a8: 4313 orrs r3, r2 tmp |= hdma->Init.Channel | hdma->Init.Direction | 80022aa: 697a ldr r2, [r7, #20] 80022ac: 4313 orrs r3, r2 80022ae: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80022b0: 687b ldr r3, [r7, #4] 80022b2: 6a5b ldr r3, [r3, #36] @ 0x24 80022b4: 2b04 cmp r3, #4 80022b6: d107 bne.n 80022c8 { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 80022b8: 687b ldr r3, [r7, #4] 80022ba: 6ada ldr r2, [r3, #44] @ 0x2c 80022bc: 687b ldr r3, [r7, #4] 80022be: 6b1b ldr r3, [r3, #48] @ 0x30 80022c0: 4313 orrs r3, r2 80022c2: 697a ldr r2, [r7, #20] 80022c4: 4313 orrs r3, r2 80022c6: 617b str r3, [r7, #20] } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; 80022c8: 687b ldr r3, [r7, #4] 80022ca: 681b ldr r3, [r3, #0] 80022cc: 697a ldr r2, [r7, #20] 80022ce: 601a str r2, [r3, #0] /* Get the FCR register value */ tmp = hdma->Instance->FCR; 80022d0: 687b ldr r3, [r7, #4] 80022d2: 681b ldr r3, [r3, #0] 80022d4: 695b ldr r3, [r3, #20] 80022d6: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 80022d8: 697b ldr r3, [r7, #20] 80022da: f023 0307 bic.w r3, r3, #7 80022de: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; 80022e0: 687b ldr r3, [r7, #4] 80022e2: 6a5b ldr r3, [r3, #36] @ 0x24 80022e4: 697a ldr r2, [r7, #20] 80022e6: 4313 orrs r3, r2 80022e8: 617b str r3, [r7, #20] /* The FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80022ea: 687b ldr r3, [r7, #4] 80022ec: 6a5b ldr r3, [r3, #36] @ 0x24 80022ee: 2b04 cmp r3, #4 80022f0: d117 bne.n 8002322 { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; 80022f2: 687b ldr r3, [r7, #4] 80022f4: 6a9b ldr r3, [r3, #40] @ 0x28 80022f6: 697a ldr r2, [r7, #20] 80022f8: 4313 orrs r3, r2 80022fa: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) 80022fc: 687b ldr r3, [r7, #4] 80022fe: 6adb ldr r3, [r3, #44] @ 0x2c 8002300: 2b00 cmp r3, #0 8002302: d00e beq.n 8002322 { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8002304: 6878 ldr r0, [r7, #4] 8002306: f000 fb01 bl 800290c 800230a: 4603 mov r3, r0 800230c: 2b00 cmp r3, #0 800230e: d008 beq.n 8002322 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8002310: 687b ldr r3, [r7, #4] 8002312: 2240 movs r2, #64 @ 0x40 8002314: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002316: 687b ldr r3, [r7, #4] 8002318: 2201 movs r2, #1 800231a: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800231e: 2301 movs r3, #1 8002320: e016 b.n 8002350 } } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; 8002322: 687b ldr r3, [r7, #4] 8002324: 681b ldr r3, [r3, #0] 8002326: 697a ldr r2, [r7, #20] 8002328: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 800232a: 6878 ldr r0, [r7, #4] 800232c: f000 fab8 bl 80028a0 8002330: 4603 mov r3, r0 8002332: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8002334: 687b ldr r3, [r7, #4] 8002336: 6ddb ldr r3, [r3, #92] @ 0x5c 8002338: 223f movs r2, #63 @ 0x3f 800233a: 409a lsls r2, r3 800233c: 68fb ldr r3, [r7, #12] 800233e: 609a str r2, [r3, #8] /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002340: 687b ldr r3, [r7, #4] 8002342: 2200 movs r2, #0 8002344: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002346: 687b ldr r3, [r7, #4] 8002348: 2201 movs r2, #1 800234a: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 800234e: 2300 movs r3, #0 } 8002350: 4618 mov r0, r3 8002352: 3718 adds r7, #24 8002354: 46bd mov sp, r7 8002356: bd80 pop {r7, pc} 8002358: f010803f .word 0xf010803f 0800235c : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800235c: b580 push {r7, lr} 800235e: b086 sub sp, #24 8002360: af00 add r7, sp, #0 8002362: 60f8 str r0, [r7, #12] 8002364: 60b9 str r1, [r7, #8] 8002366: 607a str r2, [r7, #4] 8002368: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800236a: 2300 movs r3, #0 800236c: 75fb strb r3, [r7, #23] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800236e: 68fb ldr r3, [r7, #12] 8002370: 6d9b ldr r3, [r3, #88] @ 0x58 8002372: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8002374: 68fb ldr r3, [r7, #12] 8002376: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 800237a: 2b01 cmp r3, #1 800237c: d101 bne.n 8002382 800237e: 2302 movs r3, #2 8002380: e040 b.n 8002404 8002382: 68fb ldr r3, [r7, #12] 8002384: 2201 movs r2, #1 8002386: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 800238a: 68fb ldr r3, [r7, #12] 800238c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8002390: b2db uxtb r3, r3 8002392: 2b01 cmp r3, #1 8002394: d12f bne.n 80023f6 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002396: 68fb ldr r3, [r7, #12] 8002398: 2202 movs r2, #2 800239a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800239e: 68fb ldr r3, [r7, #12] 80023a0: 2200 movs r2, #0 80023a2: 655a str r2, [r3, #84] @ 0x54 /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 80023a4: 683b ldr r3, [r7, #0] 80023a6: 687a ldr r2, [r7, #4] 80023a8: 68b9 ldr r1, [r7, #8] 80023aa: 68f8 ldr r0, [r7, #12] 80023ac: f000 fa4a bl 8002844 /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 80023b0: 68fb ldr r3, [r7, #12] 80023b2: 6ddb ldr r3, [r3, #92] @ 0x5c 80023b4: 223f movs r2, #63 @ 0x3f 80023b6: 409a lsls r2, r3 80023b8: 693b ldr r3, [r7, #16] 80023ba: 609a str r2, [r3, #8] /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 80023bc: 68fb ldr r3, [r7, #12] 80023be: 681b ldr r3, [r3, #0] 80023c0: 681a ldr r2, [r3, #0] 80023c2: 68fb ldr r3, [r7, #12] 80023c4: 681b ldr r3, [r3, #0] 80023c6: f042 0216 orr.w r2, r2, #22 80023ca: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 80023cc: 68fb ldr r3, [r7, #12] 80023ce: 6c1b ldr r3, [r3, #64] @ 0x40 80023d0: 2b00 cmp r3, #0 80023d2: d007 beq.n 80023e4 { hdma->Instance->CR |= DMA_IT_HT; 80023d4: 68fb ldr r3, [r7, #12] 80023d6: 681b ldr r3, [r3, #0] 80023d8: 681a ldr r2, [r3, #0] 80023da: 68fb ldr r3, [r7, #12] 80023dc: 681b ldr r3, [r3, #0] 80023de: f042 0208 orr.w r2, r2, #8 80023e2: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 80023e4: 68fb ldr r3, [r7, #12] 80023e6: 681b ldr r3, [r3, #0] 80023e8: 681a ldr r2, [r3, #0] 80023ea: 68fb ldr r3, [r7, #12] 80023ec: 681b ldr r3, [r3, #0] 80023ee: f042 0201 orr.w r2, r2, #1 80023f2: 601a str r2, [r3, #0] 80023f4: e005 b.n 8002402 } else { /* Process unlocked */ __HAL_UNLOCK(hdma); 80023f6: 68fb ldr r3, [r7, #12] 80023f8: 2200 movs r2, #0 80023fa: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_BUSY; 80023fe: 2302 movs r3, #2 8002400: 75fb strb r3, [r7, #23] } return status; 8002402: 7dfb ldrb r3, [r7, #23] } 8002404: 4618 mov r0, r3 8002406: 3718 adds r7, #24 8002408: 46bd mov sp, r7 800240a: bd80 pop {r7, pc} 0800240c : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800240c: b580 push {r7, lr} 800240e: b084 sub sp, #16 8002410: af00 add r7, sp, #0 8002412: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8002414: 687b ldr r3, [r7, #4] 8002416: 6d9b ldr r3, [r3, #88] @ 0x58 8002418: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 800241a: f7ff fdaf bl 8001f7c 800241e: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 8002420: 687b ldr r3, [r7, #4] 8002422: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8002426: b2db uxtb r3, r3 8002428: 2b02 cmp r3, #2 800242a: d008 beq.n 800243e { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800242c: 687b ldr r3, [r7, #4] 800242e: 2280 movs r2, #128 @ 0x80 8002430: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002432: 687b ldr r3, [r7, #4] 8002434: 2200 movs r2, #0 8002436: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 800243a: 2301 movs r3, #1 800243c: e052 b.n 80024e4 } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800243e: 687b ldr r3, [r7, #4] 8002440: 681b ldr r3, [r3, #0] 8002442: 681a ldr r2, [r3, #0] 8002444: 687b ldr r3, [r7, #4] 8002446: 681b ldr r3, [r3, #0] 8002448: f022 0216 bic.w r2, r2, #22 800244c: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 800244e: 687b ldr r3, [r7, #4] 8002450: 681b ldr r3, [r3, #0] 8002452: 695a ldr r2, [r3, #20] 8002454: 687b ldr r3, [r7, #4] 8002456: 681b ldr r3, [r3, #0] 8002458: f022 0280 bic.w r2, r2, #128 @ 0x80 800245c: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800245e: 687b ldr r3, [r7, #4] 8002460: 6c1b ldr r3, [r3, #64] @ 0x40 8002462: 2b00 cmp r3, #0 8002464: d103 bne.n 800246e 8002466: 687b ldr r3, [r7, #4] 8002468: 6c9b ldr r3, [r3, #72] @ 0x48 800246a: 2b00 cmp r3, #0 800246c: d007 beq.n 800247e { hdma->Instance->CR &= ~(DMA_IT_HT); 800246e: 687b ldr r3, [r7, #4] 8002470: 681b ldr r3, [r3, #0] 8002472: 681a ldr r2, [r3, #0] 8002474: 687b ldr r3, [r7, #4] 8002476: 681b ldr r3, [r3, #0] 8002478: f022 0208 bic.w r2, r2, #8 800247c: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800247e: 687b ldr r3, [r7, #4] 8002480: 681b ldr r3, [r3, #0] 8002482: 681a ldr r2, [r3, #0] 8002484: 687b ldr r3, [r7, #4] 8002486: 681b ldr r3, [r3, #0] 8002488: f022 0201 bic.w r2, r2, #1 800248c: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 800248e: e013 b.n 80024b8 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8002490: f7ff fd74 bl 8001f7c 8002494: 4602 mov r2, r0 8002496: 68bb ldr r3, [r7, #8] 8002498: 1ad3 subs r3, r2, r3 800249a: 2b05 cmp r3, #5 800249c: d90c bls.n 80024b8 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800249e: 687b ldr r3, [r7, #4] 80024a0: 2220 movs r2, #32 80024a2: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 80024a4: 687b ldr r3, [r7, #4] 80024a6: 2203 movs r2, #3 80024a8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80024ac: 687b ldr r3, [r7, #4] 80024ae: 2200 movs r2, #0 80024b0: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_TIMEOUT; 80024b4: 2303 movs r3, #3 80024b6: e015 b.n 80024e4 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 80024b8: 687b ldr r3, [r7, #4] 80024ba: 681b ldr r3, [r3, #0] 80024bc: 681b ldr r3, [r3, #0] 80024be: f003 0301 and.w r3, r3, #1 80024c2: 2b00 cmp r3, #0 80024c4: d1e4 bne.n 8002490 } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 80024c6: 687b ldr r3, [r7, #4] 80024c8: 6ddb ldr r3, [r3, #92] @ 0x5c 80024ca: 223f movs r2, #63 @ 0x3f 80024cc: 409a lsls r2, r3 80024ce: 68fb ldr r3, [r7, #12] 80024d0: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 80024d2: 687b ldr r3, [r7, #4] 80024d4: 2201 movs r2, #1 80024d6: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80024da: 687b ldr r3, [r7, #4] 80024dc: 2200 movs r2, #0 80024de: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 80024e2: 2300 movs r3, #0 } 80024e4: 4618 mov r0, r3 80024e6: 3710 adds r7, #16 80024e8: 46bd mov sp, r7 80024ea: bd80 pop {r7, pc} 080024ec : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80024ec: b480 push {r7} 80024ee: b083 sub sp, #12 80024f0: af00 add r7, sp, #0 80024f2: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 80024f4: 687b ldr r3, [r7, #4] 80024f6: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80024fa: b2db uxtb r3, r3 80024fc: 2b02 cmp r3, #2 80024fe: d004 beq.n 800250a { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002500: 687b ldr r3, [r7, #4] 8002502: 2280 movs r2, #128 @ 0x80 8002504: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8002506: 2301 movs r3, #1 8002508: e00c b.n 8002524 } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 800250a: 687b ldr r3, [r7, #4] 800250c: 2205 movs r2, #5 800250e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8002512: 687b ldr r3, [r7, #4] 8002514: 681b ldr r3, [r3, #0] 8002516: 681a ldr r2, [r3, #0] 8002518: 687b ldr r3, [r7, #4] 800251a: 681b ldr r3, [r3, #0] 800251c: f022 0201 bic.w r2, r2, #1 8002520: 601a str r2, [r3, #0] } return HAL_OK; 8002522: 2300 movs r3, #0 } 8002524: 4618 mov r0, r3 8002526: 370c adds r7, #12 8002528: 46bd mov sp, r7 800252a: f85d 7b04 ldr.w r7, [sp], #4 800252e: 4770 bx lr 08002530 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8002530: b580 push {r7, lr} 8002532: b086 sub sp, #24 8002534: af00 add r7, sp, #0 8002536: 6078 str r0, [r7, #4] uint32_t tmpisr; __IO uint32_t count = 0U; 8002538: 2300 movs r3, #0 800253a: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 800253c: 4b8e ldr r3, [pc, #568] @ (8002778 ) 800253e: 681b ldr r3, [r3, #0] 8002540: 4a8e ldr r2, [pc, #568] @ (800277c ) 8002542: fba2 2303 umull r2, r3, r2, r3 8002546: 0a9b lsrs r3, r3, #10 8002548: 617b str r3, [r7, #20] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800254a: 687b ldr r3, [r7, #4] 800254c: 6d9b ldr r3, [r3, #88] @ 0x58 800254e: 613b str r3, [r7, #16] tmpisr = regs->ISR; 8002550: 693b ldr r3, [r7, #16] 8002552: 681b ldr r3, [r3, #0] 8002554: 60fb str r3, [r7, #12] /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) 8002556: 687b ldr r3, [r7, #4] 8002558: 6ddb ldr r3, [r3, #92] @ 0x5c 800255a: 2208 movs r2, #8 800255c: 409a lsls r2, r3 800255e: 68fb ldr r3, [r7, #12] 8002560: 4013 ands r3, r2 8002562: 2b00 cmp r3, #0 8002564: d01a beq.n 800259c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) 8002566: 687b ldr r3, [r7, #4] 8002568: 681b ldr r3, [r3, #0] 800256a: 681b ldr r3, [r3, #0] 800256c: f003 0304 and.w r3, r3, #4 8002570: 2b00 cmp r3, #0 8002572: d013 beq.n 800259c { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); 8002574: 687b ldr r3, [r7, #4] 8002576: 681b ldr r3, [r3, #0] 8002578: 681a ldr r2, [r3, #0] 800257a: 687b ldr r3, [r7, #4] 800257c: 681b ldr r3, [r3, #0] 800257e: f022 0204 bic.w r2, r2, #4 8002582: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; 8002584: 687b ldr r3, [r7, #4] 8002586: 6ddb ldr r3, [r3, #92] @ 0x5c 8002588: 2208 movs r2, #8 800258a: 409a lsls r2, r3 800258c: 693b ldr r3, [r7, #16] 800258e: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8002590: 687b ldr r3, [r7, #4] 8002592: 6d5b ldr r3, [r3, #84] @ 0x54 8002594: f043 0201 orr.w r2, r3, #1 8002598: 687b ldr r3, [r7, #4] 800259a: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) 800259c: 687b ldr r3, [r7, #4] 800259e: 6ddb ldr r3, [r3, #92] @ 0x5c 80025a0: 2201 movs r2, #1 80025a2: 409a lsls r2, r3 80025a4: 68fb ldr r3, [r7, #12] 80025a6: 4013 ands r3, r2 80025a8: 2b00 cmp r3, #0 80025aa: d012 beq.n 80025d2 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) 80025ac: 687b ldr r3, [r7, #4] 80025ae: 681b ldr r3, [r3, #0] 80025b0: 695b ldr r3, [r3, #20] 80025b2: f003 0380 and.w r3, r3, #128 @ 0x80 80025b6: 2b00 cmp r3, #0 80025b8: d00b beq.n 80025d2 { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; 80025ba: 687b ldr r3, [r7, #4] 80025bc: 6ddb ldr r3, [r3, #92] @ 0x5c 80025be: 2201 movs r2, #1 80025c0: 409a lsls r2, r3 80025c2: 693b ldr r3, [r7, #16] 80025c4: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 80025c6: 687b ldr r3, [r7, #4] 80025c8: 6d5b ldr r3, [r3, #84] @ 0x54 80025ca: f043 0202 orr.w r2, r3, #2 80025ce: 687b ldr r3, [r7, #4] 80025d0: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) 80025d2: 687b ldr r3, [r7, #4] 80025d4: 6ddb ldr r3, [r3, #92] @ 0x5c 80025d6: 2204 movs r2, #4 80025d8: 409a lsls r2, r3 80025da: 68fb ldr r3, [r7, #12] 80025dc: 4013 ands r3, r2 80025de: 2b00 cmp r3, #0 80025e0: d012 beq.n 8002608 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) 80025e2: 687b ldr r3, [r7, #4] 80025e4: 681b ldr r3, [r3, #0] 80025e6: 681b ldr r3, [r3, #0] 80025e8: f003 0302 and.w r3, r3, #2 80025ec: 2b00 cmp r3, #0 80025ee: d00b beq.n 8002608 { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; 80025f0: 687b ldr r3, [r7, #4] 80025f2: 6ddb ldr r3, [r3, #92] @ 0x5c 80025f4: 2204 movs r2, #4 80025f6: 409a lsls r2, r3 80025f8: 693b ldr r3, [r7, #16] 80025fa: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 80025fc: 687b ldr r3, [r7, #4] 80025fe: 6d5b ldr r3, [r3, #84] @ 0x54 8002600: f043 0204 orr.w r2, r3, #4 8002604: 687b ldr r3, [r7, #4] 8002606: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) 8002608: 687b ldr r3, [r7, #4] 800260a: 6ddb ldr r3, [r3, #92] @ 0x5c 800260c: 2210 movs r2, #16 800260e: 409a lsls r2, r3 8002610: 68fb ldr r3, [r7, #12] 8002612: 4013 ands r3, r2 8002614: 2b00 cmp r3, #0 8002616: d043 beq.n 80026a0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) 8002618: 687b ldr r3, [r7, #4] 800261a: 681b ldr r3, [r3, #0] 800261c: 681b ldr r3, [r3, #0] 800261e: f003 0308 and.w r3, r3, #8 8002622: 2b00 cmp r3, #0 8002624: d03c beq.n 80026a0 { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; 8002626: 687b ldr r3, [r7, #4] 8002628: 6ddb ldr r3, [r3, #92] @ 0x5c 800262a: 2210 movs r2, #16 800262c: 409a lsls r2, r3 800262e: 693b ldr r3, [r7, #16] 8002630: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8002632: 687b ldr r3, [r7, #4] 8002634: 681b ldr r3, [r3, #0] 8002636: 681b ldr r3, [r3, #0] 8002638: f403 2380 and.w r3, r3, #262144 @ 0x40000 800263c: 2b00 cmp r3, #0 800263e: d018 beq.n 8002672 { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8002640: 687b ldr r3, [r7, #4] 8002642: 681b ldr r3, [r3, #0] 8002644: 681b ldr r3, [r3, #0] 8002646: f403 2300 and.w r3, r3, #524288 @ 0x80000 800264a: 2b00 cmp r3, #0 800264c: d108 bne.n 8002660 { if(hdma->XferHalfCpltCallback != NULL) 800264e: 687b ldr r3, [r7, #4] 8002650: 6c1b ldr r3, [r3, #64] @ 0x40 8002652: 2b00 cmp r3, #0 8002654: d024 beq.n 80026a0 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002656: 687b ldr r3, [r7, #4] 8002658: 6c1b ldr r3, [r3, #64] @ 0x40 800265a: 6878 ldr r0, [r7, #4] 800265c: 4798 blx r3 800265e: e01f b.n 80026a0 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 8002660: 687b ldr r3, [r7, #4] 8002662: 6c9b ldr r3, [r3, #72] @ 0x48 8002664: 2b00 cmp r3, #0 8002666: d01b beq.n 80026a0 { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8002668: 687b ldr r3, [r7, #4] 800266a: 6c9b ldr r3, [r3, #72] @ 0x48 800266c: 6878 ldr r0, [r7, #4] 800266e: 4798 blx r3 8002670: e016 b.n 80026a0 } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 8002672: 687b ldr r3, [r7, #4] 8002674: 681b ldr r3, [r3, #0] 8002676: 681b ldr r3, [r3, #0] 8002678: f403 7380 and.w r3, r3, #256 @ 0x100 800267c: 2b00 cmp r3, #0 800267e: d107 bne.n 8002690 { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); 8002680: 687b ldr r3, [r7, #4] 8002682: 681b ldr r3, [r3, #0] 8002684: 681a ldr r2, [r3, #0] 8002686: 687b ldr r3, [r7, #4] 8002688: 681b ldr r3, [r3, #0] 800268a: f022 0208 bic.w r2, r2, #8 800268e: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 8002690: 687b ldr r3, [r7, #4] 8002692: 6c1b ldr r3, [r3, #64] @ 0x40 8002694: 2b00 cmp r3, #0 8002696: d003 beq.n 80026a0 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002698: 687b ldr r3, [r7, #4] 800269a: 6c1b ldr r3, [r3, #64] @ 0x40 800269c: 6878 ldr r0, [r7, #4] 800269e: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) 80026a0: 687b ldr r3, [r7, #4] 80026a2: 6ddb ldr r3, [r3, #92] @ 0x5c 80026a4: 2220 movs r2, #32 80026a6: 409a lsls r2, r3 80026a8: 68fb ldr r3, [r7, #12] 80026aa: 4013 ands r3, r2 80026ac: 2b00 cmp r3, #0 80026ae: f000 808f beq.w 80027d0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) 80026b2: 687b ldr r3, [r7, #4] 80026b4: 681b ldr r3, [r3, #0] 80026b6: 681b ldr r3, [r3, #0] 80026b8: f003 0310 and.w r3, r3, #16 80026bc: 2b00 cmp r3, #0 80026be: f000 8087 beq.w 80027d0 { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; 80026c2: 687b ldr r3, [r7, #4] 80026c4: 6ddb ldr r3, [r3, #92] @ 0x5c 80026c6: 2220 movs r2, #32 80026c8: 409a lsls r2, r3 80026ca: 693b ldr r3, [r7, #16] 80026cc: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 80026ce: 687b ldr r3, [r7, #4] 80026d0: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80026d4: b2db uxtb r3, r3 80026d6: 2b05 cmp r3, #5 80026d8: d136 bne.n 8002748 { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 80026da: 687b ldr r3, [r7, #4] 80026dc: 681b ldr r3, [r3, #0] 80026de: 681a ldr r2, [r3, #0] 80026e0: 687b ldr r3, [r7, #4] 80026e2: 681b ldr r3, [r3, #0] 80026e4: f022 0216 bic.w r2, r2, #22 80026e8: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 80026ea: 687b ldr r3, [r7, #4] 80026ec: 681b ldr r3, [r3, #0] 80026ee: 695a ldr r2, [r3, #20] 80026f0: 687b ldr r3, [r7, #4] 80026f2: 681b ldr r3, [r3, #0] 80026f4: f022 0280 bic.w r2, r2, #128 @ 0x80 80026f8: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 80026fa: 687b ldr r3, [r7, #4] 80026fc: 6c1b ldr r3, [r3, #64] @ 0x40 80026fe: 2b00 cmp r3, #0 8002700: d103 bne.n 800270a 8002702: 687b ldr r3, [r7, #4] 8002704: 6c9b ldr r3, [r3, #72] @ 0x48 8002706: 2b00 cmp r3, #0 8002708: d007 beq.n 800271a { hdma->Instance->CR &= ~(DMA_IT_HT); 800270a: 687b ldr r3, [r7, #4] 800270c: 681b ldr r3, [r3, #0] 800270e: 681a ldr r2, [r3, #0] 8002710: 687b ldr r3, [r7, #4] 8002712: 681b ldr r3, [r3, #0] 8002714: f022 0208 bic.w r2, r2, #8 8002718: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 800271a: 687b ldr r3, [r7, #4] 800271c: 6ddb ldr r3, [r3, #92] @ 0x5c 800271e: 223f movs r2, #63 @ 0x3f 8002720: 409a lsls r2, r3 8002722: 693b ldr r3, [r7, #16] 8002724: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002726: 687b ldr r3, [r7, #4] 8002728: 2201 movs r2, #1 800272a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800272e: 687b ldr r3, [r7, #4] 8002730: 2200 movs r2, #0 8002732: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8002736: 687b ldr r3, [r7, #4] 8002738: 6d1b ldr r3, [r3, #80] @ 0x50 800273a: 2b00 cmp r3, #0 800273c: d07e beq.n 800283c { hdma->XferAbortCallback(hdma); 800273e: 687b ldr r3, [r7, #4] 8002740: 6d1b ldr r3, [r3, #80] @ 0x50 8002742: 6878 ldr r0, [r7, #4] 8002744: 4798 blx r3 } return; 8002746: e079 b.n 800283c } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8002748: 687b ldr r3, [r7, #4] 800274a: 681b ldr r3, [r3, #0] 800274c: 681b ldr r3, [r3, #0] 800274e: f403 2380 and.w r3, r3, #262144 @ 0x40000 8002752: 2b00 cmp r3, #0 8002754: d01d beq.n 8002792 { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8002756: 687b ldr r3, [r7, #4] 8002758: 681b ldr r3, [r3, #0] 800275a: 681b ldr r3, [r3, #0] 800275c: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002760: 2b00 cmp r3, #0 8002762: d10d bne.n 8002780 { if(hdma->XferM1CpltCallback != NULL) 8002764: 687b ldr r3, [r7, #4] 8002766: 6c5b ldr r3, [r3, #68] @ 0x44 8002768: 2b00 cmp r3, #0 800276a: d031 beq.n 80027d0 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 800276c: 687b ldr r3, [r7, #4] 800276e: 6c5b ldr r3, [r3, #68] @ 0x44 8002770: 6878 ldr r0, [r7, #4] 8002772: 4798 blx r3 8002774: e02c b.n 80027d0 8002776: bf00 nop 8002778: 20000090 .word 0x20000090 800277c: 1b4e81b5 .word 0x1b4e81b5 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8002780: 687b ldr r3, [r7, #4] 8002782: 6bdb ldr r3, [r3, #60] @ 0x3c 8002784: 2b00 cmp r3, #0 8002786: d023 beq.n 80027d0 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8002788: 687b ldr r3, [r7, #4] 800278a: 6bdb ldr r3, [r3, #60] @ 0x3c 800278c: 6878 ldr r0, [r7, #4] 800278e: 4798 blx r3 8002790: e01e b.n 80027d0 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 8002792: 687b ldr r3, [r7, #4] 8002794: 681b ldr r3, [r3, #0] 8002796: 681b ldr r3, [r3, #0] 8002798: f403 7380 and.w r3, r3, #256 @ 0x100 800279c: 2b00 cmp r3, #0 800279e: d10f bne.n 80027c0 { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); 80027a0: 687b ldr r3, [r7, #4] 80027a2: 681b ldr r3, [r3, #0] 80027a4: 681a ldr r2, [r3, #0] 80027a6: 687b ldr r3, [r7, #4] 80027a8: 681b ldr r3, [r3, #0] 80027aa: f022 0210 bic.w r2, r2, #16 80027ae: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80027b0: 687b ldr r3, [r7, #4] 80027b2: 2201 movs r2, #1 80027b4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80027b8: 687b ldr r3, [r7, #4] 80027ba: 2200 movs r2, #0 80027bc: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 80027c0: 687b ldr r3, [r7, #4] 80027c2: 6bdb ldr r3, [r3, #60] @ 0x3c 80027c4: 2b00 cmp r3, #0 80027c6: d003 beq.n 80027d0 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 80027c8: 687b ldr r3, [r7, #4] 80027ca: 6bdb ldr r3, [r3, #60] @ 0x3c 80027cc: 6878 ldr r0, [r7, #4] 80027ce: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 80027d0: 687b ldr r3, [r7, #4] 80027d2: 6d5b ldr r3, [r3, #84] @ 0x54 80027d4: 2b00 cmp r3, #0 80027d6: d032 beq.n 800283e { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) 80027d8: 687b ldr r3, [r7, #4] 80027da: 6d5b ldr r3, [r3, #84] @ 0x54 80027dc: f003 0301 and.w r3, r3, #1 80027e0: 2b00 cmp r3, #0 80027e2: d022 beq.n 800282a { hdma->State = HAL_DMA_STATE_ABORT; 80027e4: 687b ldr r3, [r7, #4] 80027e6: 2205 movs r2, #5 80027e8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80027ec: 687b ldr r3, [r7, #4] 80027ee: 681b ldr r3, [r3, #0] 80027f0: 681a ldr r2, [r3, #0] 80027f2: 687b ldr r3, [r7, #4] 80027f4: 681b ldr r3, [r3, #0] 80027f6: f022 0201 bic.w r2, r2, #1 80027fa: 601a str r2, [r3, #0] do { if (++count > timeout) 80027fc: 68bb ldr r3, [r7, #8] 80027fe: 3301 adds r3, #1 8002800: 60bb str r3, [r7, #8] 8002802: 697a ldr r2, [r7, #20] 8002804: 429a cmp r2, r3 8002806: d307 bcc.n 8002818 { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); 8002808: 687b ldr r3, [r7, #4] 800280a: 681b ldr r3, [r3, #0] 800280c: 681b ldr r3, [r3, #0] 800280e: f003 0301 and.w r3, r3, #1 8002812: 2b00 cmp r3, #0 8002814: d1f2 bne.n 80027fc 8002816: e000 b.n 800281a break; 8002818: bf00 nop /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800281a: 687b ldr r3, [r7, #4] 800281c: 2201 movs r2, #1 800281e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002822: 687b ldr r3, [r7, #4] 8002824: 2200 movs r2, #0 8002826: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 800282a: 687b ldr r3, [r7, #4] 800282c: 6cdb ldr r3, [r3, #76] @ 0x4c 800282e: 2b00 cmp r3, #0 8002830: d005 beq.n 800283e { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8002832: 687b ldr r3, [r7, #4] 8002834: 6cdb ldr r3, [r3, #76] @ 0x4c 8002836: 6878 ldr r0, [r7, #4] 8002838: 4798 blx r3 800283a: e000 b.n 800283e return; 800283c: bf00 nop } } } 800283e: 3718 adds r7, #24 8002840: 46bd mov sp, r7 8002842: bd80 pop {r7, pc} 08002844 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002844: b480 push {r7} 8002846: b085 sub sp, #20 8002848: af00 add r7, sp, #0 800284a: 60f8 str r0, [r7, #12] 800284c: 60b9 str r1, [r7, #8] 800284e: 607a str r2, [r7, #4] 8002850: 603b str r3, [r7, #0] /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); 8002852: 68fb ldr r3, [r7, #12] 8002854: 681b ldr r3, [r3, #0] 8002856: 681a ldr r2, [r3, #0] 8002858: 68fb ldr r3, [r7, #12] 800285a: 681b ldr r3, [r3, #0] 800285c: f422 2280 bic.w r2, r2, #262144 @ 0x40000 8002860: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; 8002862: 68fb ldr r3, [r7, #12] 8002864: 681b ldr r3, [r3, #0] 8002866: 683a ldr r2, [r7, #0] 8002868: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800286a: 68fb ldr r3, [r7, #12] 800286c: 689b ldr r3, [r3, #8] 800286e: 2b40 cmp r3, #64 @ 0x40 8002870: d108 bne.n 8002884 { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; 8002872: 68fb ldr r3, [r7, #12] 8002874: 681b ldr r3, [r3, #0] 8002876: 687a ldr r2, [r7, #4] 8002878: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; 800287a: 68fb ldr r3, [r7, #12] 800287c: 681b ldr r3, [r3, #0] 800287e: 68ba ldr r2, [r7, #8] 8002880: 60da str r2, [r3, #12] hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } 8002882: e007 b.n 8002894 hdma->Instance->PAR = SrcAddress; 8002884: 68fb ldr r3, [r7, #12] 8002886: 681b ldr r3, [r3, #0] 8002888: 68ba ldr r2, [r7, #8] 800288a: 609a str r2, [r3, #8] hdma->Instance->M0AR = DstAddress; 800288c: 68fb ldr r3, [r7, #12] 800288e: 681b ldr r3, [r3, #0] 8002890: 687a ldr r2, [r7, #4] 8002892: 60da str r2, [r3, #12] } 8002894: bf00 nop 8002896: 3714 adds r7, #20 8002898: 46bd mov sp, r7 800289a: f85d 7b04 ldr.w r7, [sp], #4 800289e: 4770 bx lr 080028a0 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 80028a0: b480 push {r7} 80028a2: b085 sub sp, #20 80028a4: af00 add r7, sp, #0 80028a6: 6078 str r0, [r7, #4] uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; 80028a8: 687b ldr r3, [r7, #4] 80028aa: 681b ldr r3, [r3, #0] 80028ac: b2db uxtb r3, r3 80028ae: 3b10 subs r3, #16 80028b0: 4a14 ldr r2, [pc, #80] @ (8002904 ) 80028b2: fba2 2303 umull r2, r3, r2, r3 80028b6: 091b lsrs r3, r3, #4 80028b8: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; 80028ba: 4a13 ldr r2, [pc, #76] @ (8002908 ) 80028bc: 68fb ldr r3, [r7, #12] 80028be: 4413 add r3, r2 80028c0: 781b ldrb r3, [r3, #0] 80028c2: 461a mov r2, r3 80028c4: 687b ldr r3, [r7, #4] 80028c6: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 80028c8: 68fb ldr r3, [r7, #12] 80028ca: 2b03 cmp r3, #3 80028cc: d909 bls.n 80028e2 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); 80028ce: 687b ldr r3, [r7, #4] 80028d0: 681b ldr r3, [r3, #0] 80028d2: f423 737f bic.w r3, r3, #1020 @ 0x3fc 80028d6: f023 0303 bic.w r3, r3, #3 80028da: 1d1a adds r2, r3, #4 80028dc: 687b ldr r3, [r7, #4] 80028de: 659a str r2, [r3, #88] @ 0x58 80028e0: e007 b.n 80028f2 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); 80028e2: 687b ldr r3, [r7, #4] 80028e4: 681b ldr r3, [r3, #0] 80028e6: f423 737f bic.w r3, r3, #1020 @ 0x3fc 80028ea: f023 0303 bic.w r3, r3, #3 80028ee: 687a ldr r2, [r7, #4] 80028f0: 6593 str r3, [r2, #88] @ 0x58 } return hdma->StreamBaseAddress; 80028f2: 687b ldr r3, [r7, #4] 80028f4: 6d9b ldr r3, [r3, #88] @ 0x58 } 80028f6: 4618 mov r0, r3 80028f8: 3714 adds r7, #20 80028fa: 46bd mov sp, r7 80028fc: f85d 7b04 ldr.w r7, [sp], #4 8002900: 4770 bx lr 8002902: bf00 nop 8002904: aaaaaaab .word 0xaaaaaaab 8002908: 0800b8a0 .word 0x0800b8a0 0800290c : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 800290c: b480 push {r7} 800290e: b085 sub sp, #20 8002910: af00 add r7, sp, #0 8002912: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002914: 2300 movs r3, #0 8002916: 73fb strb r3, [r7, #15] uint32_t tmp = hdma->Init.FIFOThreshold; 8002918: 687b ldr r3, [r7, #4] 800291a: 6a9b ldr r3, [r3, #40] @ 0x28 800291c: 60bb str r3, [r7, #8] /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800291e: 687b ldr r3, [r7, #4] 8002920: 699b ldr r3, [r3, #24] 8002922: 2b00 cmp r3, #0 8002924: d11f bne.n 8002966 { switch (tmp) 8002926: 68bb ldr r3, [r7, #8] 8002928: 2b03 cmp r3, #3 800292a: d856 bhi.n 80029da 800292c: a201 add r2, pc, #4 @ (adr r2, 8002934 ) 800292e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002932: bf00 nop 8002934: 08002945 .word 0x08002945 8002938: 08002957 .word 0x08002957 800293c: 08002945 .word 0x08002945 8002940: 080029db .word 0x080029db { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002944: 687b ldr r3, [r7, #4] 8002946: 6adb ldr r3, [r3, #44] @ 0x2c 8002948: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800294c: 2b00 cmp r3, #0 800294e: d046 beq.n 80029de { status = HAL_ERROR; 8002950: 2301 movs r3, #1 8002952: 73fb strb r3, [r7, #15] } break; 8002954: e043 b.n 80029de case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002956: 687b ldr r3, [r7, #4] 8002958: 6adb ldr r3, [r3, #44] @ 0x2c 800295a: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800295e: d140 bne.n 80029e2 { status = HAL_ERROR; 8002960: 2301 movs r3, #1 8002962: 73fb strb r3, [r7, #15] } break; 8002964: e03d b.n 80029e2 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8002966: 687b ldr r3, [r7, #4] 8002968: 699b ldr r3, [r3, #24] 800296a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800296e: d121 bne.n 80029b4 { switch (tmp) 8002970: 68bb ldr r3, [r7, #8] 8002972: 2b03 cmp r3, #3 8002974: d837 bhi.n 80029e6 8002976: a201 add r2, pc, #4 @ (adr r2, 800297c ) 8002978: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800297c: 0800298d .word 0x0800298d 8002980: 08002993 .word 0x08002993 8002984: 0800298d .word 0x0800298d 8002988: 080029a5 .word 0x080029a5 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800298c: 2301 movs r3, #1 800298e: 73fb strb r3, [r7, #15] break; 8002990: e030 b.n 80029f4 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002992: 687b ldr r3, [r7, #4] 8002994: 6adb ldr r3, [r3, #44] @ 0x2c 8002996: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800299a: 2b00 cmp r3, #0 800299c: d025 beq.n 80029ea { status = HAL_ERROR; 800299e: 2301 movs r3, #1 80029a0: 73fb strb r3, [r7, #15] } break; 80029a2: e022 b.n 80029ea case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 80029a4: 687b ldr r3, [r7, #4] 80029a6: 6adb ldr r3, [r3, #44] @ 0x2c 80029a8: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 80029ac: d11f bne.n 80029ee { status = HAL_ERROR; 80029ae: 2301 movs r3, #1 80029b0: 73fb strb r3, [r7, #15] } break; 80029b2: e01c b.n 80029ee } /* Memory Data size equal to Word */ else { switch (tmp) 80029b4: 68bb ldr r3, [r7, #8] 80029b6: 2b02 cmp r3, #2 80029b8: d903 bls.n 80029c2 80029ba: 68bb ldr r3, [r7, #8] 80029bc: 2b03 cmp r3, #3 80029be: d003 beq.n 80029c8 { status = HAL_ERROR; } break; default: break; 80029c0: e018 b.n 80029f4 status = HAL_ERROR; 80029c2: 2301 movs r3, #1 80029c4: 73fb strb r3, [r7, #15] break; 80029c6: e015 b.n 80029f4 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 80029c8: 687b ldr r3, [r7, #4] 80029ca: 6adb ldr r3, [r3, #44] @ 0x2c 80029cc: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80029d0: 2b00 cmp r3, #0 80029d2: d00e beq.n 80029f2 status = HAL_ERROR; 80029d4: 2301 movs r3, #1 80029d6: 73fb strb r3, [r7, #15] break; 80029d8: e00b b.n 80029f2 break; 80029da: bf00 nop 80029dc: e00a b.n 80029f4 break; 80029de: bf00 nop 80029e0: e008 b.n 80029f4 break; 80029e2: bf00 nop 80029e4: e006 b.n 80029f4 break; 80029e6: bf00 nop 80029e8: e004 b.n 80029f4 break; 80029ea: bf00 nop 80029ec: e002 b.n 80029f4 break; 80029ee: bf00 nop 80029f0: e000 b.n 80029f4 break; 80029f2: bf00 nop } } return status; 80029f4: 7bfb ldrb r3, [r7, #15] } 80029f6: 4618 mov r0, r3 80029f8: 3714 adds r7, #20 80029fa: 46bd mov sp, r7 80029fc: f85d 7b04 ldr.w r7, [sp], #4 8002a00: 4770 bx lr 8002a02: bf00 nop 08002a04 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002a04: b480 push {r7} 8002a06: b089 sub sp, #36 @ 0x24 8002a08: af00 add r7, sp, #0 8002a0a: 6078 str r0, [r7, #4] 8002a0c: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 8002a0e: 2300 movs r3, #0 8002a10: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8002a12: 2300 movs r3, #0 8002a14: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8002a16: 2300 movs r3, #0 8002a18: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8002a1a: 2300 movs r3, #0 8002a1c: 61fb str r3, [r7, #28] 8002a1e: e165 b.n 8002cec { /* Get the IO position */ ioposition = 0x01U << position; 8002a20: 2201 movs r2, #1 8002a22: 69fb ldr r3, [r7, #28] 8002a24: fa02 f303 lsl.w r3, r2, r3 8002a28: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8002a2a: 683b ldr r3, [r7, #0] 8002a2c: 681b ldr r3, [r3, #0] 8002a2e: 697a ldr r2, [r7, #20] 8002a30: 4013 ands r3, r2 8002a32: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8002a34: 693a ldr r2, [r7, #16] 8002a36: 697b ldr r3, [r7, #20] 8002a38: 429a cmp r2, r3 8002a3a: f040 8154 bne.w 8002ce6 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8002a3e: 683b ldr r3, [r7, #0] 8002a40: 685b ldr r3, [r3, #4] 8002a42: f003 0303 and.w r3, r3, #3 8002a46: 2b01 cmp r3, #1 8002a48: d005 beq.n 8002a56 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002a4a: 683b ldr r3, [r7, #0] 8002a4c: 685b ldr r3, [r3, #4] 8002a4e: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8002a52: 2b02 cmp r3, #2 8002a54: d130 bne.n 8002ab8 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002a56: 687b ldr r3, [r7, #4] 8002a58: 689b ldr r3, [r3, #8] 8002a5a: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8002a5c: 69fb ldr r3, [r7, #28] 8002a5e: 005b lsls r3, r3, #1 8002a60: 2203 movs r2, #3 8002a62: fa02 f303 lsl.w r3, r2, r3 8002a66: 43db mvns r3, r3 8002a68: 69ba ldr r2, [r7, #24] 8002a6a: 4013 ands r3, r2 8002a6c: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8002a6e: 683b ldr r3, [r7, #0] 8002a70: 68da ldr r2, [r3, #12] 8002a72: 69fb ldr r3, [r7, #28] 8002a74: 005b lsls r3, r3, #1 8002a76: fa02 f303 lsl.w r3, r2, r3 8002a7a: 69ba ldr r2, [r7, #24] 8002a7c: 4313 orrs r3, r2 8002a7e: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8002a80: 687b ldr r3, [r7, #4] 8002a82: 69ba ldr r2, [r7, #24] 8002a84: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8002a86: 687b ldr r3, [r7, #4] 8002a88: 685b ldr r3, [r3, #4] 8002a8a: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8002a8c: 2201 movs r2, #1 8002a8e: 69fb ldr r3, [r7, #28] 8002a90: fa02 f303 lsl.w r3, r2, r3 8002a94: 43db mvns r3, r3 8002a96: 69ba ldr r2, [r7, #24] 8002a98: 4013 ands r3, r2 8002a9a: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002a9c: 683b ldr r3, [r7, #0] 8002a9e: 685b ldr r3, [r3, #4] 8002aa0: 091b lsrs r3, r3, #4 8002aa2: f003 0201 and.w r2, r3, #1 8002aa6: 69fb ldr r3, [r7, #28] 8002aa8: fa02 f303 lsl.w r3, r2, r3 8002aac: 69ba ldr r2, [r7, #24] 8002aae: 4313 orrs r3, r2 8002ab0: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8002ab2: 687b ldr r3, [r7, #4] 8002ab4: 69ba ldr r2, [r7, #24] 8002ab6: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002ab8: 683b ldr r3, [r7, #0] 8002aba: 685b ldr r3, [r3, #4] 8002abc: f003 0303 and.w r3, r3, #3 8002ac0: 2b03 cmp r3, #3 8002ac2: d017 beq.n 8002af4 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8002ac4: 687b ldr r3, [r7, #4] 8002ac6: 68db ldr r3, [r3, #12] 8002ac8: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8002aca: 69fb ldr r3, [r7, #28] 8002acc: 005b lsls r3, r3, #1 8002ace: 2203 movs r2, #3 8002ad0: fa02 f303 lsl.w r3, r2, r3 8002ad4: 43db mvns r3, r3 8002ad6: 69ba ldr r2, [r7, #24] 8002ad8: 4013 ands r3, r2 8002ada: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002adc: 683b ldr r3, [r7, #0] 8002ade: 689a ldr r2, [r3, #8] 8002ae0: 69fb ldr r3, [r7, #28] 8002ae2: 005b lsls r3, r3, #1 8002ae4: fa02 f303 lsl.w r3, r2, r3 8002ae8: 69ba ldr r2, [r7, #24] 8002aea: 4313 orrs r3, r2 8002aec: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8002aee: 687b ldr r3, [r7, #4] 8002af0: 69ba ldr r2, [r7, #24] 8002af2: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002af4: 683b ldr r3, [r7, #0] 8002af6: 685b ldr r3, [r3, #4] 8002af8: f003 0303 and.w r3, r3, #3 8002afc: 2b02 cmp r3, #2 8002afe: d123 bne.n 8002b48 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8002b00: 69fb ldr r3, [r7, #28] 8002b02: 08da lsrs r2, r3, #3 8002b04: 687b ldr r3, [r7, #4] 8002b06: 3208 adds r2, #8 8002b08: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8002b0c: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 8002b0e: 69fb ldr r3, [r7, #28] 8002b10: f003 0307 and.w r3, r3, #7 8002b14: 009b lsls r3, r3, #2 8002b16: 220f movs r2, #15 8002b18: fa02 f303 lsl.w r3, r2, r3 8002b1c: 43db mvns r3, r3 8002b1e: 69ba ldr r2, [r7, #24] 8002b20: 4013 ands r3, r2 8002b22: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8002b24: 683b ldr r3, [r7, #0] 8002b26: 691a ldr r2, [r3, #16] 8002b28: 69fb ldr r3, [r7, #28] 8002b2a: f003 0307 and.w r3, r3, #7 8002b2e: 009b lsls r3, r3, #2 8002b30: fa02 f303 lsl.w r3, r2, r3 8002b34: 69ba ldr r2, [r7, #24] 8002b36: 4313 orrs r3, r2 8002b38: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8002b3a: 69fb ldr r3, [r7, #28] 8002b3c: 08da lsrs r2, r3, #3 8002b3e: 687b ldr r3, [r7, #4] 8002b40: 3208 adds r2, #8 8002b42: 69b9 ldr r1, [r7, #24] 8002b44: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002b48: 687b ldr r3, [r7, #4] 8002b4a: 681b ldr r3, [r3, #0] 8002b4c: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 8002b4e: 69fb ldr r3, [r7, #28] 8002b50: 005b lsls r3, r3, #1 8002b52: 2203 movs r2, #3 8002b54: fa02 f303 lsl.w r3, r2, r3 8002b58: 43db mvns r3, r3 8002b5a: 69ba ldr r2, [r7, #24] 8002b5c: 4013 ands r3, r2 8002b5e: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8002b60: 683b ldr r3, [r7, #0] 8002b62: 685b ldr r3, [r3, #4] 8002b64: f003 0203 and.w r2, r3, #3 8002b68: 69fb ldr r3, [r7, #28] 8002b6a: 005b lsls r3, r3, #1 8002b6c: fa02 f303 lsl.w r3, r2, r3 8002b70: 69ba ldr r2, [r7, #24] 8002b72: 4313 orrs r3, r2 8002b74: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8002b76: 687b ldr r3, [r7, #4] 8002b78: 69ba ldr r2, [r7, #24] 8002b7a: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8002b7c: 683b ldr r3, [r7, #0] 8002b7e: 685b ldr r3, [r3, #4] 8002b80: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002b84: 2b00 cmp r3, #0 8002b86: f000 80ae beq.w 8002ce6 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002b8a: 2300 movs r3, #0 8002b8c: 60fb str r3, [r7, #12] 8002b8e: 4b5d ldr r3, [pc, #372] @ (8002d04 ) 8002b90: 6c5b ldr r3, [r3, #68] @ 0x44 8002b92: 4a5c ldr r2, [pc, #368] @ (8002d04 ) 8002b94: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002b98: 6453 str r3, [r2, #68] @ 0x44 8002b9a: 4b5a ldr r3, [pc, #360] @ (8002d04 ) 8002b9c: 6c5b ldr r3, [r3, #68] @ 0x44 8002b9e: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002ba2: 60fb str r3, [r7, #12] 8002ba4: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8002ba6: 4a58 ldr r2, [pc, #352] @ (8002d08 ) 8002ba8: 69fb ldr r3, [r7, #28] 8002baa: 089b lsrs r3, r3, #2 8002bac: 3302 adds r3, #2 8002bae: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8002bb2: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8002bb4: 69fb ldr r3, [r7, #28] 8002bb6: f003 0303 and.w r3, r3, #3 8002bba: 009b lsls r3, r3, #2 8002bbc: 220f movs r2, #15 8002bbe: fa02 f303 lsl.w r3, r2, r3 8002bc2: 43db mvns r3, r3 8002bc4: 69ba ldr r2, [r7, #24] 8002bc6: 4013 ands r3, r2 8002bc8: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8002bca: 687b ldr r3, [r7, #4] 8002bcc: 4a4f ldr r2, [pc, #316] @ (8002d0c ) 8002bce: 4293 cmp r3, r2 8002bd0: d025 beq.n 8002c1e 8002bd2: 687b ldr r3, [r7, #4] 8002bd4: 4a4e ldr r2, [pc, #312] @ (8002d10 ) 8002bd6: 4293 cmp r3, r2 8002bd8: d01f beq.n 8002c1a 8002bda: 687b ldr r3, [r7, #4] 8002bdc: 4a4d ldr r2, [pc, #308] @ (8002d14 ) 8002bde: 4293 cmp r3, r2 8002be0: d019 beq.n 8002c16 8002be2: 687b ldr r3, [r7, #4] 8002be4: 4a4c ldr r2, [pc, #304] @ (8002d18 ) 8002be6: 4293 cmp r3, r2 8002be8: d013 beq.n 8002c12 8002bea: 687b ldr r3, [r7, #4] 8002bec: 4a4b ldr r2, [pc, #300] @ (8002d1c ) 8002bee: 4293 cmp r3, r2 8002bf0: d00d beq.n 8002c0e 8002bf2: 687b ldr r3, [r7, #4] 8002bf4: 4a4a ldr r2, [pc, #296] @ (8002d20 ) 8002bf6: 4293 cmp r3, r2 8002bf8: d007 beq.n 8002c0a 8002bfa: 687b ldr r3, [r7, #4] 8002bfc: 4a49 ldr r2, [pc, #292] @ (8002d24 ) 8002bfe: 4293 cmp r3, r2 8002c00: d101 bne.n 8002c06 8002c02: 2306 movs r3, #6 8002c04: e00c b.n 8002c20 8002c06: 2307 movs r3, #7 8002c08: e00a b.n 8002c20 8002c0a: 2305 movs r3, #5 8002c0c: e008 b.n 8002c20 8002c0e: 2304 movs r3, #4 8002c10: e006 b.n 8002c20 8002c12: 2303 movs r3, #3 8002c14: e004 b.n 8002c20 8002c16: 2302 movs r3, #2 8002c18: e002 b.n 8002c20 8002c1a: 2301 movs r3, #1 8002c1c: e000 b.n 8002c20 8002c1e: 2300 movs r3, #0 8002c20: 69fa ldr r2, [r7, #28] 8002c22: f002 0203 and.w r2, r2, #3 8002c26: 0092 lsls r2, r2, #2 8002c28: 4093 lsls r3, r2 8002c2a: 69ba ldr r2, [r7, #24] 8002c2c: 4313 orrs r3, r2 8002c2e: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8002c30: 4935 ldr r1, [pc, #212] @ (8002d08 ) 8002c32: 69fb ldr r3, [r7, #28] 8002c34: 089b lsrs r3, r3, #2 8002c36: 3302 adds r3, #2 8002c38: 69ba ldr r2, [r7, #24] 8002c3a: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8002c3e: 4b3a ldr r3, [pc, #232] @ (8002d28 ) 8002c40: 689b ldr r3, [r3, #8] 8002c42: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002c44: 693b ldr r3, [r7, #16] 8002c46: 43db mvns r3, r3 8002c48: 69ba ldr r2, [r7, #24] 8002c4a: 4013 ands r3, r2 8002c4c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8002c4e: 683b ldr r3, [r7, #0] 8002c50: 685b ldr r3, [r3, #4] 8002c52: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8002c56: 2b00 cmp r3, #0 8002c58: d003 beq.n 8002c62 { temp |= iocurrent; 8002c5a: 69ba ldr r2, [r7, #24] 8002c5c: 693b ldr r3, [r7, #16] 8002c5e: 4313 orrs r3, r2 8002c60: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8002c62: 4a31 ldr r2, [pc, #196] @ (8002d28 ) 8002c64: 69bb ldr r3, [r7, #24] 8002c66: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8002c68: 4b2f ldr r3, [pc, #188] @ (8002d28 ) 8002c6a: 68db ldr r3, [r3, #12] 8002c6c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002c6e: 693b ldr r3, [r7, #16] 8002c70: 43db mvns r3, r3 8002c72: 69ba ldr r2, [r7, #24] 8002c74: 4013 ands r3, r2 8002c76: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8002c78: 683b ldr r3, [r7, #0] 8002c7a: 685b ldr r3, [r3, #4] 8002c7c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8002c80: 2b00 cmp r3, #0 8002c82: d003 beq.n 8002c8c { temp |= iocurrent; 8002c84: 69ba ldr r2, [r7, #24] 8002c86: 693b ldr r3, [r7, #16] 8002c88: 4313 orrs r3, r2 8002c8a: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8002c8c: 4a26 ldr r2, [pc, #152] @ (8002d28 ) 8002c8e: 69bb ldr r3, [r7, #24] 8002c90: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 8002c92: 4b25 ldr r3, [pc, #148] @ (8002d28 ) 8002c94: 685b ldr r3, [r3, #4] 8002c96: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002c98: 693b ldr r3, [r7, #16] 8002c9a: 43db mvns r3, r3 8002c9c: 69ba ldr r2, [r7, #24] 8002c9e: 4013 ands r3, r2 8002ca0: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8002ca2: 683b ldr r3, [r7, #0] 8002ca4: 685b ldr r3, [r3, #4] 8002ca6: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002caa: 2b00 cmp r3, #0 8002cac: d003 beq.n 8002cb6 { temp |= iocurrent; 8002cae: 69ba ldr r2, [r7, #24] 8002cb0: 693b ldr r3, [r7, #16] 8002cb2: 4313 orrs r3, r2 8002cb4: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8002cb6: 4a1c ldr r2, [pc, #112] @ (8002d28 ) 8002cb8: 69bb ldr r3, [r7, #24] 8002cba: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8002cbc: 4b1a ldr r3, [pc, #104] @ (8002d28 ) 8002cbe: 681b ldr r3, [r3, #0] 8002cc0: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002cc2: 693b ldr r3, [r7, #16] 8002cc4: 43db mvns r3, r3 8002cc6: 69ba ldr r2, [r7, #24] 8002cc8: 4013 ands r3, r2 8002cca: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8002ccc: 683b ldr r3, [r7, #0] 8002cce: 685b ldr r3, [r3, #4] 8002cd0: f403 3380 and.w r3, r3, #65536 @ 0x10000 8002cd4: 2b00 cmp r3, #0 8002cd6: d003 beq.n 8002ce0 { temp |= iocurrent; 8002cd8: 69ba ldr r2, [r7, #24] 8002cda: 693b ldr r3, [r7, #16] 8002cdc: 4313 orrs r3, r2 8002cde: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8002ce0: 4a11 ldr r2, [pc, #68] @ (8002d28 ) 8002ce2: 69bb ldr r3, [r7, #24] 8002ce4: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 8002ce6: 69fb ldr r3, [r7, #28] 8002ce8: 3301 adds r3, #1 8002cea: 61fb str r3, [r7, #28] 8002cec: 69fb ldr r3, [r7, #28] 8002cee: 2b0f cmp r3, #15 8002cf0: f67f ae96 bls.w 8002a20 } } } } 8002cf4: bf00 nop 8002cf6: bf00 nop 8002cf8: 3724 adds r7, #36 @ 0x24 8002cfa: 46bd mov sp, r7 8002cfc: f85d 7b04 ldr.w r7, [sp], #4 8002d00: 4770 bx lr 8002d02: bf00 nop 8002d04: 40023800 .word 0x40023800 8002d08: 40013800 .word 0x40013800 8002d0c: 40020000 .word 0x40020000 8002d10: 40020400 .word 0x40020400 8002d14: 40020800 .word 0x40020800 8002d18: 40020c00 .word 0x40020c00 8002d1c: 40021000 .word 0x40021000 8002d20: 40021400 .word 0x40021400 8002d24: 40021800 .word 0x40021800 8002d28: 40013c00 .word 0x40013c00 08002d2c : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8002d2c: b480 push {r7} 8002d2e: b085 sub sp, #20 8002d30: af00 add r7, sp, #0 8002d32: 6078 str r0, [r7, #4] 8002d34: 460b mov r3, r1 8002d36: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8002d38: 687b ldr r3, [r7, #4] 8002d3a: 691a ldr r2, [r3, #16] 8002d3c: 887b ldrh r3, [r7, #2] 8002d3e: 4013 ands r3, r2 8002d40: 2b00 cmp r3, #0 8002d42: d002 beq.n 8002d4a { bitstatus = GPIO_PIN_SET; 8002d44: 2301 movs r3, #1 8002d46: 73fb strb r3, [r7, #15] 8002d48: e001 b.n 8002d4e } else { bitstatus = GPIO_PIN_RESET; 8002d4a: 2300 movs r3, #0 8002d4c: 73fb strb r3, [r7, #15] } return bitstatus; 8002d4e: 7bfb ldrb r3, [r7, #15] } 8002d50: 4618 mov r0, r3 8002d52: 3714 adds r7, #20 8002d54: 46bd mov sp, r7 8002d56: f85d 7b04 ldr.w r7, [sp], #4 8002d5a: 4770 bx lr 08002d5c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8002d5c: b480 push {r7} 8002d5e: b083 sub sp, #12 8002d60: af00 add r7, sp, #0 8002d62: 6078 str r0, [r7, #4] 8002d64: 460b mov r3, r1 8002d66: 807b strh r3, [r7, #2] 8002d68: 4613 mov r3, r2 8002d6a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8002d6c: 787b ldrb r3, [r7, #1] 8002d6e: 2b00 cmp r3, #0 8002d70: d003 beq.n 8002d7a { GPIOx->BSRR = GPIO_Pin; 8002d72: 887a ldrh r2, [r7, #2] 8002d74: 687b ldr r3, [r7, #4] 8002d76: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002d78: e003 b.n 8002d82 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8002d7a: 887b ldrh r3, [r7, #2] 8002d7c: 041a lsls r2, r3, #16 8002d7e: 687b ldr r3, [r7, #4] 8002d80: 619a str r2, [r3, #24] } 8002d82: bf00 nop 8002d84: 370c adds r7, #12 8002d86: 46bd mov sp, r7 8002d88: f85d 7b04 ldr.w r7, [sp], #4 8002d8c: 4770 bx lr ... 08002d90 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8002d90: b580 push {r7, lr} 8002d92: b084 sub sp, #16 8002d94: af00 add r7, sp, #0 8002d96: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8002d98: 687b ldr r3, [r7, #4] 8002d9a: 2b00 cmp r3, #0 8002d9c: d101 bne.n 8002da2 { return HAL_ERROR; 8002d9e: 2301 movs r3, #1 8002da0: e12b b.n 8002ffa assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8002da2: 687b ldr r3, [r7, #4] 8002da4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8002da8: b2db uxtb r3, r3 8002daa: 2b00 cmp r3, #0 8002dac: d106 bne.n 8002dbc { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8002dae: 687b ldr r3, [r7, #4] 8002db0: 2200 movs r2, #0 8002db2: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8002db6: 6878 ldr r0, [r7, #4] 8002db8: f7fd fcee bl 8000798 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8002dbc: 687b ldr r3, [r7, #4] 8002dbe: 2224 movs r2, #36 @ 0x24 8002dc0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8002dc4: 687b ldr r3, [r7, #4] 8002dc6: 681b ldr r3, [r3, #0] 8002dc8: 681a ldr r2, [r3, #0] 8002dca: 687b ldr r3, [r7, #4] 8002dcc: 681b ldr r3, [r3, #0] 8002dce: f022 0201 bic.w r2, r2, #1 8002dd2: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8002dd4: 687b ldr r3, [r7, #4] 8002dd6: 681b ldr r3, [r3, #0] 8002dd8: 681a ldr r2, [r3, #0] 8002dda: 687b ldr r3, [r7, #4] 8002ddc: 681b ldr r3, [r3, #0] 8002dde: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8002de2: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8002de4: 687b ldr r3, [r7, #4] 8002de6: 681b ldr r3, [r3, #0] 8002de8: 681a ldr r2, [r3, #0] 8002dea: 687b ldr r3, [r7, #4] 8002dec: 681b ldr r3, [r3, #0] 8002dee: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8002df2: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8002df4: f001 fc88 bl 8004708 8002df8: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8002dfa: 687b ldr r3, [r7, #4] 8002dfc: 685b ldr r3, [r3, #4] 8002dfe: 4a81 ldr r2, [pc, #516] @ (8003004 ) 8002e00: 4293 cmp r3, r2 8002e02: d807 bhi.n 8002e14 8002e04: 68fb ldr r3, [r7, #12] 8002e06: 4a80 ldr r2, [pc, #512] @ (8003008 ) 8002e08: 4293 cmp r3, r2 8002e0a: bf94 ite ls 8002e0c: 2301 movls r3, #1 8002e0e: 2300 movhi r3, #0 8002e10: b2db uxtb r3, r3 8002e12: e006 b.n 8002e22 8002e14: 68fb ldr r3, [r7, #12] 8002e16: 4a7d ldr r2, [pc, #500] @ (800300c ) 8002e18: 4293 cmp r3, r2 8002e1a: bf94 ite ls 8002e1c: 2301 movls r3, #1 8002e1e: 2300 movhi r3, #0 8002e20: b2db uxtb r3, r3 8002e22: 2b00 cmp r3, #0 8002e24: d001 beq.n 8002e2a { return HAL_ERROR; 8002e26: 2301 movs r3, #1 8002e28: e0e7 b.n 8002ffa } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8002e2a: 68fb ldr r3, [r7, #12] 8002e2c: 4a78 ldr r2, [pc, #480] @ (8003010 ) 8002e2e: fba2 2303 umull r2, r3, r2, r3 8002e32: 0c9b lsrs r3, r3, #18 8002e34: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8002e36: 687b ldr r3, [r7, #4] 8002e38: 681b ldr r3, [r3, #0] 8002e3a: 685b ldr r3, [r3, #4] 8002e3c: f023 013f bic.w r1, r3, #63 @ 0x3f 8002e40: 687b ldr r3, [r7, #4] 8002e42: 681b ldr r3, [r3, #0] 8002e44: 68ba ldr r2, [r7, #8] 8002e46: 430a orrs r2, r1 8002e48: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8002e4a: 687b ldr r3, [r7, #4] 8002e4c: 681b ldr r3, [r3, #0] 8002e4e: 6a1b ldr r3, [r3, #32] 8002e50: f023 013f bic.w r1, r3, #63 @ 0x3f 8002e54: 687b ldr r3, [r7, #4] 8002e56: 685b ldr r3, [r3, #4] 8002e58: 4a6a ldr r2, [pc, #424] @ (8003004 ) 8002e5a: 4293 cmp r3, r2 8002e5c: d802 bhi.n 8002e64 8002e5e: 68bb ldr r3, [r7, #8] 8002e60: 3301 adds r3, #1 8002e62: e009 b.n 8002e78 8002e64: 68bb ldr r3, [r7, #8] 8002e66: f44f 7296 mov.w r2, #300 @ 0x12c 8002e6a: fb02 f303 mul.w r3, r2, r3 8002e6e: 4a69 ldr r2, [pc, #420] @ (8003014 ) 8002e70: fba2 2303 umull r2, r3, r2, r3 8002e74: 099b lsrs r3, r3, #6 8002e76: 3301 adds r3, #1 8002e78: 687a ldr r2, [r7, #4] 8002e7a: 6812 ldr r2, [r2, #0] 8002e7c: 430b orrs r3, r1 8002e7e: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8002e80: 687b ldr r3, [r7, #4] 8002e82: 681b ldr r3, [r3, #0] 8002e84: 69db ldr r3, [r3, #28] 8002e86: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8002e8a: f022 02ff bic.w r2, r2, #255 @ 0xff 8002e8e: 687b ldr r3, [r7, #4] 8002e90: 685b ldr r3, [r3, #4] 8002e92: 495c ldr r1, [pc, #368] @ (8003004 ) 8002e94: 428b cmp r3, r1 8002e96: d819 bhi.n 8002ecc 8002e98: 68fb ldr r3, [r7, #12] 8002e9a: 1e59 subs r1, r3, #1 8002e9c: 687b ldr r3, [r7, #4] 8002e9e: 685b ldr r3, [r3, #4] 8002ea0: 005b lsls r3, r3, #1 8002ea2: fbb1 f3f3 udiv r3, r1, r3 8002ea6: 1c59 adds r1, r3, #1 8002ea8: f640 73fc movw r3, #4092 @ 0xffc 8002eac: 400b ands r3, r1 8002eae: 2b00 cmp r3, #0 8002eb0: d00a beq.n 8002ec8 8002eb2: 68fb ldr r3, [r7, #12] 8002eb4: 1e59 subs r1, r3, #1 8002eb6: 687b ldr r3, [r7, #4] 8002eb8: 685b ldr r3, [r3, #4] 8002eba: 005b lsls r3, r3, #1 8002ebc: fbb1 f3f3 udiv r3, r1, r3 8002ec0: 3301 adds r3, #1 8002ec2: f3c3 030b ubfx r3, r3, #0, #12 8002ec6: e051 b.n 8002f6c 8002ec8: 2304 movs r3, #4 8002eca: e04f b.n 8002f6c 8002ecc: 687b ldr r3, [r7, #4] 8002ece: 689b ldr r3, [r3, #8] 8002ed0: 2b00 cmp r3, #0 8002ed2: d111 bne.n 8002ef8 8002ed4: 68fb ldr r3, [r7, #12] 8002ed6: 1e58 subs r0, r3, #1 8002ed8: 687b ldr r3, [r7, #4] 8002eda: 6859 ldr r1, [r3, #4] 8002edc: 460b mov r3, r1 8002ede: 005b lsls r3, r3, #1 8002ee0: 440b add r3, r1 8002ee2: fbb0 f3f3 udiv r3, r0, r3 8002ee6: 3301 adds r3, #1 8002ee8: f3c3 030b ubfx r3, r3, #0, #12 8002eec: 2b00 cmp r3, #0 8002eee: bf0c ite eq 8002ef0: 2301 moveq r3, #1 8002ef2: 2300 movne r3, #0 8002ef4: b2db uxtb r3, r3 8002ef6: e012 b.n 8002f1e 8002ef8: 68fb ldr r3, [r7, #12] 8002efa: 1e58 subs r0, r3, #1 8002efc: 687b ldr r3, [r7, #4] 8002efe: 6859 ldr r1, [r3, #4] 8002f00: 460b mov r3, r1 8002f02: 009b lsls r3, r3, #2 8002f04: 440b add r3, r1 8002f06: 0099 lsls r1, r3, #2 8002f08: 440b add r3, r1 8002f0a: fbb0 f3f3 udiv r3, r0, r3 8002f0e: 3301 adds r3, #1 8002f10: f3c3 030b ubfx r3, r3, #0, #12 8002f14: 2b00 cmp r3, #0 8002f16: bf0c ite eq 8002f18: 2301 moveq r3, #1 8002f1a: 2300 movne r3, #0 8002f1c: b2db uxtb r3, r3 8002f1e: 2b00 cmp r3, #0 8002f20: d001 beq.n 8002f26 8002f22: 2301 movs r3, #1 8002f24: e022 b.n 8002f6c 8002f26: 687b ldr r3, [r7, #4] 8002f28: 689b ldr r3, [r3, #8] 8002f2a: 2b00 cmp r3, #0 8002f2c: d10e bne.n 8002f4c 8002f2e: 68fb ldr r3, [r7, #12] 8002f30: 1e58 subs r0, r3, #1 8002f32: 687b ldr r3, [r7, #4] 8002f34: 6859 ldr r1, [r3, #4] 8002f36: 460b mov r3, r1 8002f38: 005b lsls r3, r3, #1 8002f3a: 440b add r3, r1 8002f3c: fbb0 f3f3 udiv r3, r0, r3 8002f40: 3301 adds r3, #1 8002f42: f3c3 030b ubfx r3, r3, #0, #12 8002f46: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002f4a: e00f b.n 8002f6c 8002f4c: 68fb ldr r3, [r7, #12] 8002f4e: 1e58 subs r0, r3, #1 8002f50: 687b ldr r3, [r7, #4] 8002f52: 6859 ldr r1, [r3, #4] 8002f54: 460b mov r3, r1 8002f56: 009b lsls r3, r3, #2 8002f58: 440b add r3, r1 8002f5a: 0099 lsls r1, r3, #2 8002f5c: 440b add r3, r1 8002f5e: fbb0 f3f3 udiv r3, r0, r3 8002f62: 3301 adds r3, #1 8002f64: f3c3 030b ubfx r3, r3, #0, #12 8002f68: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8002f6c: 6879 ldr r1, [r7, #4] 8002f6e: 6809 ldr r1, [r1, #0] 8002f70: 4313 orrs r3, r2 8002f72: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002f74: 687b ldr r3, [r7, #4] 8002f76: 681b ldr r3, [r3, #0] 8002f78: 681b ldr r3, [r3, #0] 8002f7a: f023 01c0 bic.w r1, r3, #192 @ 0xc0 8002f7e: 687b ldr r3, [r7, #4] 8002f80: 69da ldr r2, [r3, #28] 8002f82: 687b ldr r3, [r7, #4] 8002f84: 6a1b ldr r3, [r3, #32] 8002f86: 431a orrs r2, r3 8002f88: 687b ldr r3, [r7, #4] 8002f8a: 681b ldr r3, [r3, #0] 8002f8c: 430a orrs r2, r1 8002f8e: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002f90: 687b ldr r3, [r7, #4] 8002f92: 681b ldr r3, [r3, #0] 8002f94: 689b ldr r3, [r3, #8] 8002f96: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8002f9a: f023 03ff bic.w r3, r3, #255 @ 0xff 8002f9e: 687a ldr r2, [r7, #4] 8002fa0: 6911 ldr r1, [r2, #16] 8002fa2: 687a ldr r2, [r7, #4] 8002fa4: 68d2 ldr r2, [r2, #12] 8002fa6: 4311 orrs r1, r2 8002fa8: 687a ldr r2, [r7, #4] 8002faa: 6812 ldr r2, [r2, #0] 8002fac: 430b orrs r3, r1 8002fae: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8002fb0: 687b ldr r3, [r7, #4] 8002fb2: 681b ldr r3, [r3, #0] 8002fb4: 68db ldr r3, [r3, #12] 8002fb6: f023 01ff bic.w r1, r3, #255 @ 0xff 8002fba: 687b ldr r3, [r7, #4] 8002fbc: 695a ldr r2, [r3, #20] 8002fbe: 687b ldr r3, [r7, #4] 8002fc0: 699b ldr r3, [r3, #24] 8002fc2: 431a orrs r2, r3 8002fc4: 687b ldr r3, [r7, #4] 8002fc6: 681b ldr r3, [r3, #0] 8002fc8: 430a orrs r2, r1 8002fca: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002fcc: 687b ldr r3, [r7, #4] 8002fce: 681b ldr r3, [r3, #0] 8002fd0: 681a ldr r2, [r3, #0] 8002fd2: 687b ldr r3, [r7, #4] 8002fd4: 681b ldr r3, [r3, #0] 8002fd6: f042 0201 orr.w r2, r2, #1 8002fda: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002fdc: 687b ldr r3, [r7, #4] 8002fde: 2200 movs r2, #0 8002fe0: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8002fe2: 687b ldr r3, [r7, #4] 8002fe4: 2220 movs r2, #32 8002fe6: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8002fea: 687b ldr r3, [r7, #4] 8002fec: 2200 movs r2, #0 8002fee: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002ff0: 687b ldr r3, [r7, #4] 8002ff2: 2200 movs r2, #0 8002ff4: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8002ff8: 2300 movs r3, #0 } 8002ffa: 4618 mov r0, r3 8002ffc: 3710 adds r7, #16 8002ffe: 46bd mov sp, r7 8003000: bd80 pop {r7, pc} 8003002: bf00 nop 8003004: 000186a0 .word 0x000186a0 8003008: 001e847f .word 0x001e847f 800300c: 003d08ff .word 0x003d08ff 8003010: 431bde83 .word 0x431bde83 8003014: 10624dd3 .word 0x10624dd3 08003018 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8003018: b580 push {r7, lr} 800301a: b086 sub sp, #24 800301c: af02 add r7, sp, #8 800301e: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8003020: 687b ldr r3, [r7, #4] 8003022: 2b00 cmp r3, #0 8003024: d101 bne.n 800302a { return HAL_ERROR; 8003026: 2301 movs r3, #1 8003028: e108 b.n 800323c /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); #if defined (USB_OTG_FS) USBx = hpcd->Instance; 800302a: 687b ldr r3, [r7, #4] 800302c: 681b ldr r3, [r3, #0] 800302e: 60bb str r3, [r7, #8] #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) 8003030: 687b ldr r3, [r7, #4] 8003032: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 8003036: b2db uxtb r3, r3 8003038: 2b00 cmp r3, #0 800303a: d106 bne.n 800304a { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 800303c: 687b ldr r3, [r7, #4] 800303e: 2200 movs r2, #0 8003040: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8003044: 6878 ldr r0, [r7, #4] 8003046: f008 f855 bl 800b0f4 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 800304a: 687b ldr r3, [r7, #4] 800304c: 2203 movs r2, #3 800304e: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ if (USBx == USB_OTG_FS) 8003052: 68bb ldr r3, [r7, #8] 8003054: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8003058: d102 bne.n 8003060 { hpcd->Init.dma_enable = 0U; 800305a: 687b ldr r3, [r7, #4] 800305c: 2200 movs r2, #0 800305e: 719a strb r2, [r3, #6] } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8003060: 687b ldr r3, [r7, #4] 8003062: 681b ldr r3, [r3, #0] 8003064: 4618 mov r0, r3 8003066: f004 ff4a bl 8007efe /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 800306a: 687b ldr r3, [r7, #4] 800306c: 6818 ldr r0, [r3, #0] 800306e: 687b ldr r3, [r7, #4] 8003070: 7c1a ldrb r2, [r3, #16] 8003072: f88d 2000 strb.w r2, [sp] 8003076: 3304 adds r3, #4 8003078: cb0e ldmia r3, {r1, r2, r3} 800307a: f004 fe29 bl 8007cd0 800307e: 4603 mov r3, r0 8003080: 2b00 cmp r3, #0 8003082: d005 beq.n 8003090 { hpcd->State = HAL_PCD_STATE_ERROR; 8003084: 687b ldr r3, [r7, #4] 8003086: 2202 movs r2, #2 8003088: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 800308c: 2301 movs r3, #1 800308e: e0d5 b.n 800323c } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 8003090: 687b ldr r3, [r7, #4] 8003092: 681b ldr r3, [r3, #0] 8003094: 2100 movs r1, #0 8003096: 4618 mov r0, r3 8003098: f004 ff42 bl 8007f20 800309c: 4603 mov r3, r0 800309e: 2b00 cmp r3, #0 80030a0: d005 beq.n 80030ae { hpcd->State = HAL_PCD_STATE_ERROR; 80030a2: 687b ldr r3, [r7, #4] 80030a4: 2202 movs r2, #2 80030a6: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 80030aa: 2301 movs r3, #1 80030ac: e0c6 b.n 800323c } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80030ae: 2300 movs r3, #0 80030b0: 73fb strb r3, [r7, #15] 80030b2: e04a b.n 800314a { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 80030b4: 7bfa ldrb r2, [r7, #15] 80030b6: 6879 ldr r1, [r7, #4] 80030b8: 4613 mov r3, r2 80030ba: 00db lsls r3, r3, #3 80030bc: 4413 add r3, r2 80030be: 009b lsls r3, r3, #2 80030c0: 440b add r3, r1 80030c2: 3315 adds r3, #21 80030c4: 2201 movs r2, #1 80030c6: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 80030c8: 7bfa ldrb r2, [r7, #15] 80030ca: 6879 ldr r1, [r7, #4] 80030cc: 4613 mov r3, r2 80030ce: 00db lsls r3, r3, #3 80030d0: 4413 add r3, r2 80030d2: 009b lsls r3, r3, #2 80030d4: 440b add r3, r1 80030d6: 3314 adds r3, #20 80030d8: 7bfa ldrb r2, [r7, #15] 80030da: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 80030dc: 7bfa ldrb r2, [r7, #15] 80030de: 7bfb ldrb r3, [r7, #15] 80030e0: b298 uxth r0, r3 80030e2: 6879 ldr r1, [r7, #4] 80030e4: 4613 mov r3, r2 80030e6: 00db lsls r3, r3, #3 80030e8: 4413 add r3, r2 80030ea: 009b lsls r3, r3, #2 80030ec: 440b add r3, r1 80030ee: 332e adds r3, #46 @ 0x2e 80030f0: 4602 mov r2, r0 80030f2: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 80030f4: 7bfa ldrb r2, [r7, #15] 80030f6: 6879 ldr r1, [r7, #4] 80030f8: 4613 mov r3, r2 80030fa: 00db lsls r3, r3, #3 80030fc: 4413 add r3, r2 80030fe: 009b lsls r3, r3, #2 8003100: 440b add r3, r1 8003102: 3318 adds r3, #24 8003104: 2200 movs r2, #0 8003106: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8003108: 7bfa ldrb r2, [r7, #15] 800310a: 6879 ldr r1, [r7, #4] 800310c: 4613 mov r3, r2 800310e: 00db lsls r3, r3, #3 8003110: 4413 add r3, r2 8003112: 009b lsls r3, r3, #2 8003114: 440b add r3, r1 8003116: 331c adds r3, #28 8003118: 2200 movs r2, #0 800311a: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 800311c: 7bfa ldrb r2, [r7, #15] 800311e: 6879 ldr r1, [r7, #4] 8003120: 4613 mov r3, r2 8003122: 00db lsls r3, r3, #3 8003124: 4413 add r3, r2 8003126: 009b lsls r3, r3, #2 8003128: 440b add r3, r1 800312a: 3320 adds r3, #32 800312c: 2200 movs r2, #0 800312e: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8003130: 7bfa ldrb r2, [r7, #15] 8003132: 6879 ldr r1, [r7, #4] 8003134: 4613 mov r3, r2 8003136: 00db lsls r3, r3, #3 8003138: 4413 add r3, r2 800313a: 009b lsls r3, r3, #2 800313c: 440b add r3, r1 800313e: 3324 adds r3, #36 @ 0x24 8003140: 2200 movs r2, #0 8003142: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8003144: 7bfb ldrb r3, [r7, #15] 8003146: 3301 adds r3, #1 8003148: 73fb strb r3, [r7, #15] 800314a: 687b ldr r3, [r7, #4] 800314c: 791b ldrb r3, [r3, #4] 800314e: 7bfa ldrb r2, [r7, #15] 8003150: 429a cmp r2, r3 8003152: d3af bcc.n 80030b4 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8003154: 2300 movs r3, #0 8003156: 73fb strb r3, [r7, #15] 8003158: e044 b.n 80031e4 { hpcd->OUT_ep[i].is_in = 0U; 800315a: 7bfa ldrb r2, [r7, #15] 800315c: 6879 ldr r1, [r7, #4] 800315e: 4613 mov r3, r2 8003160: 00db lsls r3, r3, #3 8003162: 4413 add r3, r2 8003164: 009b lsls r3, r3, #2 8003166: 440b add r3, r1 8003168: f203 2355 addw r3, r3, #597 @ 0x255 800316c: 2200 movs r2, #0 800316e: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8003170: 7bfa ldrb r2, [r7, #15] 8003172: 6879 ldr r1, [r7, #4] 8003174: 4613 mov r3, r2 8003176: 00db lsls r3, r3, #3 8003178: 4413 add r3, r2 800317a: 009b lsls r3, r3, #2 800317c: 440b add r3, r1 800317e: f503 7315 add.w r3, r3, #596 @ 0x254 8003182: 7bfa ldrb r2, [r7, #15] 8003184: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8003186: 7bfa ldrb r2, [r7, #15] 8003188: 6879 ldr r1, [r7, #4] 800318a: 4613 mov r3, r2 800318c: 00db lsls r3, r3, #3 800318e: 4413 add r3, r2 8003190: 009b lsls r3, r3, #2 8003192: 440b add r3, r1 8003194: f503 7316 add.w r3, r3, #600 @ 0x258 8003198: 2200 movs r2, #0 800319a: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 800319c: 7bfa ldrb r2, [r7, #15] 800319e: 6879 ldr r1, [r7, #4] 80031a0: 4613 mov r3, r2 80031a2: 00db lsls r3, r3, #3 80031a4: 4413 add r3, r2 80031a6: 009b lsls r3, r3, #2 80031a8: 440b add r3, r1 80031aa: f503 7317 add.w r3, r3, #604 @ 0x25c 80031ae: 2200 movs r2, #0 80031b0: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 80031b2: 7bfa ldrb r2, [r7, #15] 80031b4: 6879 ldr r1, [r7, #4] 80031b6: 4613 mov r3, r2 80031b8: 00db lsls r3, r3, #3 80031ba: 4413 add r3, r2 80031bc: 009b lsls r3, r3, #2 80031be: 440b add r3, r1 80031c0: f503 7318 add.w r3, r3, #608 @ 0x260 80031c4: 2200 movs r2, #0 80031c6: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 80031c8: 7bfa ldrb r2, [r7, #15] 80031ca: 6879 ldr r1, [r7, #4] 80031cc: 4613 mov r3, r2 80031ce: 00db lsls r3, r3, #3 80031d0: 4413 add r3, r2 80031d2: 009b lsls r3, r3, #2 80031d4: 440b add r3, r1 80031d6: f503 7319 add.w r3, r3, #612 @ 0x264 80031da: 2200 movs r2, #0 80031dc: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80031de: 7bfb ldrb r3, [r7, #15] 80031e0: 3301 adds r3, #1 80031e2: 73fb strb r3, [r7, #15] 80031e4: 687b ldr r3, [r7, #4] 80031e6: 791b ldrb r3, [r3, #4] 80031e8: 7bfa ldrb r2, [r7, #15] 80031ea: 429a cmp r2, r3 80031ec: d3b5 bcc.n 800315a } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 80031ee: 687b ldr r3, [r7, #4] 80031f0: 6818 ldr r0, [r3, #0] 80031f2: 687b ldr r3, [r7, #4] 80031f4: 7c1a ldrb r2, [r3, #16] 80031f6: f88d 2000 strb.w r2, [sp] 80031fa: 3304 adds r3, #4 80031fc: cb0e ldmia r3, {r1, r2, r3} 80031fe: f004 fedb bl 8007fb8 8003202: 4603 mov r3, r0 8003204: 2b00 cmp r3, #0 8003206: d005 beq.n 8003214 { hpcd->State = HAL_PCD_STATE_ERROR; 8003208: 687b ldr r3, [r7, #4] 800320a: 2202 movs r2, #2 800320c: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8003210: 2301 movs r3, #1 8003212: e013 b.n 800323c } hpcd->USB_Address = 0U; 8003214: 687b ldr r3, [r7, #4] 8003216: 2200 movs r2, #0 8003218: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 800321a: 687b ldr r3, [r7, #4] 800321c: 2201 movs r2, #1 800321e: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8003222: 687b ldr r3, [r7, #4] 8003224: 7b1b ldrb r3, [r3, #12] 8003226: 2b01 cmp r3, #1 8003228: d102 bne.n 8003230 { (void)HAL_PCDEx_ActivateLPM(hpcd); 800322a: 6878 ldr r0, [r7, #4] 800322c: f001 f956 bl 80044dc } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 8003230: 687b ldr r3, [r7, #4] 8003232: 681b ldr r3, [r3, #0] 8003234: 4618 mov r0, r3 8003236: f005 ff18 bl 800906a return HAL_OK; 800323a: 2300 movs r3, #0 } 800323c: 4618 mov r0, r3 800323e: 3710 adds r7, #16 8003240: 46bd mov sp, r7 8003242: bd80 pop {r7, pc} 08003244 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8003244: b580 push {r7, lr} 8003246: b084 sub sp, #16 8003248: af00 add r7, sp, #0 800324a: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 800324c: 687b ldr r3, [r7, #4] 800324e: 681b ldr r3, [r3, #0] 8003250: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8003252: 687b ldr r3, [r7, #4] 8003254: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003258: 2b01 cmp r3, #1 800325a: d101 bne.n 8003260 800325c: 2302 movs r3, #2 800325e: e022 b.n 80032a6 8003260: 687b ldr r3, [r7, #4] 8003262: 2201 movs r2, #1 8003264: f883 2494 strb.w r2, [r3, #1172] @ 0x494 if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8003268: 68fb ldr r3, [r7, #12] 800326a: 68db ldr r3, [r3, #12] 800326c: f003 0340 and.w r3, r3, #64 @ 0x40 8003270: 2b00 cmp r3, #0 8003272: d009 beq.n 8003288 (hpcd->Init.battery_charging_enable == 1U)) 8003274: 687b ldr r3, [r7, #4] 8003276: 7b5b ldrb r3, [r3, #13] if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8003278: 2b01 cmp r3, #1 800327a: d105 bne.n 8003288 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 800327c: 68fb ldr r3, [r7, #12] 800327e: 6b9b ldr r3, [r3, #56] @ 0x38 8003280: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8003284: 68fb ldr r3, [r7, #12] 8003286: 639a str r2, [r3, #56] @ 0x38 } __HAL_PCD_ENABLE(hpcd); 8003288: 687b ldr r3, [r7, #4] 800328a: 681b ldr r3, [r3, #0] 800328c: 4618 mov r0, r3 800328e: f004 fe25 bl 8007edc (void)USB_DevConnect(hpcd->Instance); 8003292: 687b ldr r3, [r7, #4] 8003294: 681b ldr r3, [r3, #0] 8003296: 4618 mov r0, r3 8003298: f005 fec6 bl 8009028 __HAL_UNLOCK(hpcd); 800329c: 687b ldr r3, [r7, #4] 800329e: 2200 movs r2, #0 80032a0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 80032a4: 2300 movs r3, #0 } 80032a6: 4618 mov r0, r3 80032a8: 3710 adds r7, #16 80032aa: 46bd mov sp, r7 80032ac: bd80 pop {r7, pc} 080032ae : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 80032ae: b590 push {r4, r7, lr} 80032b0: b08d sub sp, #52 @ 0x34 80032b2: af00 add r7, sp, #0 80032b4: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80032b6: 687b ldr r3, [r7, #4] 80032b8: 681b ldr r3, [r3, #0] 80032ba: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 80032bc: 6a3b ldr r3, [r7, #32] 80032be: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 80032c0: 687b ldr r3, [r7, #4] 80032c2: 681b ldr r3, [r3, #0] 80032c4: 4618 mov r0, r3 80032c6: f005 ff84 bl 80091d2 80032ca: 4603 mov r3, r0 80032cc: 2b00 cmp r3, #0 80032ce: f040 84b9 bne.w 8003c44 { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 80032d2: 687b ldr r3, [r7, #4] 80032d4: 681b ldr r3, [r3, #0] 80032d6: 4618 mov r0, r3 80032d8: f005 fee8 bl 80090ac 80032dc: 4603 mov r3, r0 80032de: 2b00 cmp r3, #0 80032e0: f000 84af beq.w 8003c42 { return; } /* store current frame number */ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; 80032e4: 69fb ldr r3, [r7, #28] 80032e6: f503 6300 add.w r3, r3, #2048 @ 0x800 80032ea: 689b ldr r3, [r3, #8] 80032ec: 0a1b lsrs r3, r3, #8 80032ee: f3c3 020d ubfx r2, r3, #0, #14 80032f2: 687b ldr r3, [r7, #4] 80032f4: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 80032f8: 687b ldr r3, [r7, #4] 80032fa: 681b ldr r3, [r3, #0] 80032fc: 4618 mov r0, r3 80032fe: f005 fed5 bl 80090ac 8003302: 4603 mov r3, r0 8003304: f003 0302 and.w r3, r3, #2 8003308: 2b02 cmp r3, #2 800330a: d107 bne.n 800331c { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 800330c: 687b ldr r3, [r7, #4] 800330e: 681b ldr r3, [r3, #0] 8003310: 695a ldr r2, [r3, #20] 8003312: 687b ldr r3, [r7, #4] 8003314: 681b ldr r3, [r3, #0] 8003316: f002 0202 and.w r2, r2, #2 800331a: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 800331c: 687b ldr r3, [r7, #4] 800331e: 681b ldr r3, [r3, #0] 8003320: 4618 mov r0, r3 8003322: f005 fec3 bl 80090ac 8003326: 4603 mov r3, r0 8003328: f003 0310 and.w r3, r3, #16 800332c: 2b10 cmp r3, #16 800332e: d161 bne.n 80033f4 { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8003330: 687b ldr r3, [r7, #4] 8003332: 681b ldr r3, [r3, #0] 8003334: 699a ldr r2, [r3, #24] 8003336: 687b ldr r3, [r7, #4] 8003338: 681b ldr r3, [r3, #0] 800333a: f022 0210 bic.w r2, r2, #16 800333e: 619a str r2, [r3, #24] RegVal = USBx->GRXSTSP; 8003340: 6a3b ldr r3, [r7, #32] 8003342: 6a1b ldr r3, [r3, #32] 8003344: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; 8003346: 69bb ldr r3, [r7, #24] 8003348: f003 020f and.w r2, r3, #15 800334c: 4613 mov r3, r2 800334e: 00db lsls r3, r3, #3 8003350: 4413 add r3, r2 8003352: 009b lsls r3, r3, #2 8003354: f503 7314 add.w r3, r3, #592 @ 0x250 8003358: 687a ldr r2, [r7, #4] 800335a: 4413 add r3, r2 800335c: 3304 adds r3, #4 800335e: 617b str r3, [r7, #20] if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 8003360: 69bb ldr r3, [r7, #24] 8003362: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8003366: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800336a: d124 bne.n 80033b6 { if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) 800336c: 69ba ldr r2, [r7, #24] 800336e: f647 73f0 movw r3, #32752 @ 0x7ff0 8003372: 4013 ands r3, r2 8003374: 2b00 cmp r3, #0 8003376: d035 beq.n 80033e4 { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8003378: 697b ldr r3, [r7, #20] 800337a: 68d9 ldr r1, [r3, #12] (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); 800337c: 69bb ldr r3, [r7, #24] 800337e: 091b lsrs r3, r3, #4 8003380: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 8003382: f3c3 030a ubfx r3, r3, #0, #11 8003386: b29b uxth r3, r3 8003388: 461a mov r2, r3 800338a: 6a38 ldr r0, [r7, #32] 800338c: f005 fcfa bl 8008d84 ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8003390: 697b ldr r3, [r7, #20] 8003392: 68da ldr r2, [r3, #12] 8003394: 69bb ldr r3, [r7, #24] 8003396: 091b lsrs r3, r3, #4 8003398: f3c3 030a ubfx r3, r3, #0, #11 800339c: 441a add r2, r3 800339e: 697b ldr r3, [r7, #20] 80033a0: 60da str r2, [r3, #12] ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 80033a2: 697b ldr r3, [r7, #20] 80033a4: 695a ldr r2, [r3, #20] 80033a6: 69bb ldr r3, [r7, #24] 80033a8: 091b lsrs r3, r3, #4 80033aa: f3c3 030a ubfx r3, r3, #0, #11 80033ae: 441a add r2, r3 80033b0: 697b ldr r3, [r7, #20] 80033b2: 615a str r2, [r3, #20] 80033b4: e016 b.n 80033e4 } } else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 80033b6: 69bb ldr r3, [r7, #24] 80033b8: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 80033bc: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 80033c0: d110 bne.n 80033e4 { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 80033c2: 687b ldr r3, [r7, #4] 80033c4: f203 439c addw r3, r3, #1180 @ 0x49c 80033c8: 2208 movs r2, #8 80033ca: 4619 mov r1, r3 80033cc: 6a38 ldr r0, [r7, #32] 80033ce: f005 fcd9 bl 8008d84 ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 80033d2: 697b ldr r3, [r7, #20] 80033d4: 695a ldr r2, [r3, #20] 80033d6: 69bb ldr r3, [r7, #24] 80033d8: 091b lsrs r3, r3, #4 80033da: f3c3 030a ubfx r3, r3, #0, #11 80033de: 441a add r2, r3 80033e0: 697b ldr r3, [r7, #20] 80033e2: 615a str r2, [r3, #20] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 80033e4: 687b ldr r3, [r7, #4] 80033e6: 681b ldr r3, [r3, #0] 80033e8: 699a ldr r2, [r3, #24] 80033ea: 687b ldr r3, [r7, #4] 80033ec: 681b ldr r3, [r3, #0] 80033ee: f042 0210 orr.w r2, r2, #16 80033f2: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 80033f4: 687b ldr r3, [r7, #4] 80033f6: 681b ldr r3, [r3, #0] 80033f8: 4618 mov r0, r3 80033fa: f005 fe57 bl 80090ac 80033fe: 4603 mov r3, r0 8003400: f403 2300 and.w r3, r3, #524288 @ 0x80000 8003404: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8003408: f040 80a7 bne.w 800355a { epnum = 0U; 800340c: 2300 movs r3, #0 800340e: 627b str r3, [r7, #36] @ 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8003410: 687b ldr r3, [r7, #4] 8003412: 681b ldr r3, [r3, #0] 8003414: 4618 mov r0, r3 8003416: f005 fe5c bl 80090d2 800341a: 62b8 str r0, [r7, #40] @ 0x28 while (ep_intr != 0U) 800341c: e099 b.n 8003552 { if ((ep_intr & 0x1U) != 0U) 800341e: 6abb ldr r3, [r7, #40] @ 0x28 8003420: f003 0301 and.w r3, r3, #1 8003424: 2b00 cmp r3, #0 8003426: f000 808e beq.w 8003546 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 800342a: 687b ldr r3, [r7, #4] 800342c: 681b ldr r3, [r3, #0] 800342e: 6a7a ldr r2, [r7, #36] @ 0x24 8003430: b2d2 uxtb r2, r2 8003432: 4611 mov r1, r2 8003434: 4618 mov r0, r3 8003436: f005 fe80 bl 800913a 800343a: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 800343c: 693b ldr r3, [r7, #16] 800343e: f003 0301 and.w r3, r3, #1 8003442: 2b00 cmp r3, #0 8003444: d00c beq.n 8003460 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 8003446: 6a7b ldr r3, [r7, #36] @ 0x24 8003448: 015a lsls r2, r3, #5 800344a: 69fb ldr r3, [r7, #28] 800344c: 4413 add r3, r2 800344e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003452: 461a mov r2, r3 8003454: 2301 movs r3, #1 8003456: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 8003458: 6a79 ldr r1, [r7, #36] @ 0x24 800345a: 6878 ldr r0, [r7, #4] 800345c: f000 feb8 bl 80041d0 } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 8003460: 693b ldr r3, [r7, #16] 8003462: f003 0308 and.w r3, r3, #8 8003466: 2b00 cmp r3, #0 8003468: d00c beq.n 8003484 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 800346a: 6a7b ldr r3, [r7, #36] @ 0x24 800346c: 015a lsls r2, r3, #5 800346e: 69fb ldr r3, [r7, #28] 8003470: 4413 add r3, r2 8003472: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003476: 461a mov r2, r3 8003478: 2308 movs r3, #8 800347a: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 800347c: 6a79 ldr r1, [r7, #36] @ 0x24 800347e: 6878 ldr r0, [r7, #4] 8003480: f000 ff8e bl 80043a0 } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 8003484: 693b ldr r3, [r7, #16] 8003486: f003 0310 and.w r3, r3, #16 800348a: 2b00 cmp r3, #0 800348c: d008 beq.n 80034a0 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 800348e: 6a7b ldr r3, [r7, #36] @ 0x24 8003490: 015a lsls r2, r3, #5 8003492: 69fb ldr r3, [r7, #28] 8003494: 4413 add r3, r2 8003496: f503 6330 add.w r3, r3, #2816 @ 0xb00 800349a: 461a mov r2, r3 800349c: 2310 movs r3, #16 800349e: 6093 str r3, [r2, #8] } /* Clear OUT Endpoint disable interrupt */ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) 80034a0: 693b ldr r3, [r7, #16] 80034a2: f003 0302 and.w r3, r3, #2 80034a6: 2b00 cmp r3, #0 80034a8: d030 beq.n 800350c { if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) 80034aa: 6a3b ldr r3, [r7, #32] 80034ac: 695b ldr r3, [r3, #20] 80034ae: f003 0380 and.w r3, r3, #128 @ 0x80 80034b2: 2b80 cmp r3, #128 @ 0x80 80034b4: d109 bne.n 80034ca { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; 80034b6: 69fb ldr r3, [r7, #28] 80034b8: f503 6300 add.w r3, r3, #2048 @ 0x800 80034bc: 685b ldr r3, [r3, #4] 80034be: 69fa ldr r2, [r7, #28] 80034c0: f502 6200 add.w r2, r2, #2048 @ 0x800 80034c4: f443 6380 orr.w r3, r3, #1024 @ 0x400 80034c8: 6053 str r3, [r2, #4] } ep = &hpcd->OUT_ep[epnum]; 80034ca: 6a7a ldr r2, [r7, #36] @ 0x24 80034cc: 4613 mov r3, r2 80034ce: 00db lsls r3, r3, #3 80034d0: 4413 add r3, r2 80034d2: 009b lsls r3, r3, #2 80034d4: f503 7314 add.w r3, r3, #592 @ 0x250 80034d8: 687a ldr r2, [r7, #4] 80034da: 4413 add r3, r2 80034dc: 3304 adds r3, #4 80034de: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 80034e0: 697b ldr r3, [r7, #20] 80034e2: 78db ldrb r3, [r3, #3] 80034e4: 2b01 cmp r3, #1 80034e6: d108 bne.n 80034fa { ep->is_iso_incomplete = 0U; 80034e8: 697b ldr r3, [r7, #20] 80034ea: 2200 movs r2, #0 80034ec: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 80034ee: 6a7b ldr r3, [r7, #36] @ 0x24 80034f0: b2db uxtb r3, r3 80034f2: 4619 mov r1, r3 80034f4: 6878 ldr r0, [r7, #4] 80034f6: f007 ff19 bl 800b32c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); 80034fa: 6a7b ldr r3, [r7, #36] @ 0x24 80034fc: 015a lsls r2, r3, #5 80034fe: 69fb ldr r3, [r7, #28] 8003500: 4413 add r3, r2 8003502: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003506: 461a mov r2, r3 8003508: 2302 movs r3, #2 800350a: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 800350c: 693b ldr r3, [r7, #16] 800350e: f003 0320 and.w r3, r3, #32 8003512: 2b00 cmp r3, #0 8003514: d008 beq.n 8003528 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003516: 6a7b ldr r3, [r7, #36] @ 0x24 8003518: 015a lsls r2, r3, #5 800351a: 69fb ldr r3, [r7, #28] 800351c: 4413 add r3, r2 800351e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003522: 461a mov r2, r3 8003524: 2320 movs r3, #32 8003526: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 8003528: 693b ldr r3, [r7, #16] 800352a: f403 5300 and.w r3, r3, #8192 @ 0x2000 800352e: 2b00 cmp r3, #0 8003530: d009 beq.n 8003546 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 8003532: 6a7b ldr r3, [r7, #36] @ 0x24 8003534: 015a lsls r2, r3, #5 8003536: 69fb ldr r3, [r7, #28] 8003538: 4413 add r3, r2 800353a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800353e: 461a mov r2, r3 8003540: f44f 5300 mov.w r3, #8192 @ 0x2000 8003544: 6093 str r3, [r2, #8] } } epnum++; 8003546: 6a7b ldr r3, [r7, #36] @ 0x24 8003548: 3301 adds r3, #1 800354a: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 800354c: 6abb ldr r3, [r7, #40] @ 0x28 800354e: 085b lsrs r3, r3, #1 8003550: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 8003552: 6abb ldr r3, [r7, #40] @ 0x28 8003554: 2b00 cmp r3, #0 8003556: f47f af62 bne.w 800341e } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 800355a: 687b ldr r3, [r7, #4] 800355c: 681b ldr r3, [r3, #0] 800355e: 4618 mov r0, r3 8003560: f005 fda4 bl 80090ac 8003564: 4603 mov r3, r0 8003566: f403 2380 and.w r3, r3, #262144 @ 0x40000 800356a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800356e: f040 80db bne.w 8003728 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 8003572: 687b ldr r3, [r7, #4] 8003574: 681b ldr r3, [r3, #0] 8003576: 4618 mov r0, r3 8003578: f005 fdc5 bl 8009106 800357c: 62b8 str r0, [r7, #40] @ 0x28 epnum = 0U; 800357e: 2300 movs r3, #0 8003580: 627b str r3, [r7, #36] @ 0x24 while (ep_intr != 0U) 8003582: e0cd b.n 8003720 { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 8003584: 6abb ldr r3, [r7, #40] @ 0x28 8003586: f003 0301 and.w r3, r3, #1 800358a: 2b00 cmp r3, #0 800358c: f000 80c2 beq.w 8003714 { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8003590: 687b ldr r3, [r7, #4] 8003592: 681b ldr r3, [r3, #0] 8003594: 6a7a ldr r2, [r7, #36] @ 0x24 8003596: b2d2 uxtb r2, r2 8003598: 4611 mov r1, r2 800359a: 4618 mov r0, r3 800359c: f005 fdeb bl 8009176 80035a0: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 80035a2: 693b ldr r3, [r7, #16] 80035a4: f003 0301 and.w r3, r3, #1 80035a8: 2b00 cmp r3, #0 80035aa: d057 beq.n 800365c { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 80035ac: 6a7b ldr r3, [r7, #36] @ 0x24 80035ae: f003 030f and.w r3, r3, #15 80035b2: 2201 movs r2, #1 80035b4: fa02 f303 lsl.w r3, r2, r3 80035b8: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 80035ba: 69fb ldr r3, [r7, #28] 80035bc: f503 6300 add.w r3, r3, #2048 @ 0x800 80035c0: 6b5a ldr r2, [r3, #52] @ 0x34 80035c2: 68fb ldr r3, [r7, #12] 80035c4: 43db mvns r3, r3 80035c6: 69f9 ldr r1, [r7, #28] 80035c8: f501 6100 add.w r1, r1, #2048 @ 0x800 80035cc: 4013 ands r3, r2 80035ce: 634b str r3, [r1, #52] @ 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 80035d0: 6a7b ldr r3, [r7, #36] @ 0x24 80035d2: 015a lsls r2, r3, #5 80035d4: 69fb ldr r3, [r7, #28] 80035d6: 4413 add r3, r2 80035d8: f503 6310 add.w r3, r3, #2304 @ 0x900 80035dc: 461a mov r2, r3 80035de: 2301 movs r3, #1 80035e0: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 80035e2: 687b ldr r3, [r7, #4] 80035e4: 799b ldrb r3, [r3, #6] 80035e6: 2b01 cmp r3, #1 80035e8: d132 bne.n 8003650 { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 80035ea: 6879 ldr r1, [r7, #4] 80035ec: 6a7a ldr r2, [r7, #36] @ 0x24 80035ee: 4613 mov r3, r2 80035f0: 00db lsls r3, r3, #3 80035f2: 4413 add r3, r2 80035f4: 009b lsls r3, r3, #2 80035f6: 440b add r3, r1 80035f8: 3320 adds r3, #32 80035fa: 6819 ldr r1, [r3, #0] 80035fc: 6878 ldr r0, [r7, #4] 80035fe: 6a7a ldr r2, [r7, #36] @ 0x24 8003600: 4613 mov r3, r2 8003602: 00db lsls r3, r3, #3 8003604: 4413 add r3, r2 8003606: 009b lsls r3, r3, #2 8003608: 4403 add r3, r0 800360a: 331c adds r3, #28 800360c: 681b ldr r3, [r3, #0] 800360e: 4419 add r1, r3 8003610: 6878 ldr r0, [r7, #4] 8003612: 6a7a ldr r2, [r7, #36] @ 0x24 8003614: 4613 mov r3, r2 8003616: 00db lsls r3, r3, #3 8003618: 4413 add r3, r2 800361a: 009b lsls r3, r3, #2 800361c: 4403 add r3, r0 800361e: 3320 adds r3, #32 8003620: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 8003622: 6a7b ldr r3, [r7, #36] @ 0x24 8003624: 2b00 cmp r3, #0 8003626: d113 bne.n 8003650 8003628: 6879 ldr r1, [r7, #4] 800362a: 6a7a ldr r2, [r7, #36] @ 0x24 800362c: 4613 mov r3, r2 800362e: 00db lsls r3, r3, #3 8003630: 4413 add r3, r2 8003632: 009b lsls r3, r3, #2 8003634: 440b add r3, r1 8003636: 3324 adds r3, #36 @ 0x24 8003638: 681b ldr r3, [r3, #0] 800363a: 2b00 cmp r3, #0 800363c: d108 bne.n 8003650 { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 800363e: 687b ldr r3, [r7, #4] 8003640: 6818 ldr r0, [r3, #0] 8003642: 687b ldr r3, [r7, #4] 8003644: f203 439c addw r3, r3, #1180 @ 0x49c 8003648: 461a mov r2, r3 800364a: 2101 movs r1, #1 800364c: f005 fdf2 bl 8009234 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 8003650: 6a7b ldr r3, [r7, #36] @ 0x24 8003652: b2db uxtb r3, r3 8003654: 4619 mov r1, r3 8003656: 6878 ldr r0, [r7, #4] 8003658: f007 fde3 bl 800b222 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 800365c: 693b ldr r3, [r7, #16] 800365e: f003 0308 and.w r3, r3, #8 8003662: 2b00 cmp r3, #0 8003664: d008 beq.n 8003678 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 8003666: 6a7b ldr r3, [r7, #36] @ 0x24 8003668: 015a lsls r2, r3, #5 800366a: 69fb ldr r3, [r7, #28] 800366c: 4413 add r3, r2 800366e: f503 6310 add.w r3, r3, #2304 @ 0x900 8003672: 461a mov r2, r3 8003674: 2308 movs r3, #8 8003676: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 8003678: 693b ldr r3, [r7, #16] 800367a: f003 0310 and.w r3, r3, #16 800367e: 2b00 cmp r3, #0 8003680: d008 beq.n 8003694 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 8003682: 6a7b ldr r3, [r7, #36] @ 0x24 8003684: 015a lsls r2, r3, #5 8003686: 69fb ldr r3, [r7, #28] 8003688: 4413 add r3, r2 800368a: f503 6310 add.w r3, r3, #2304 @ 0x900 800368e: 461a mov r2, r3 8003690: 2310 movs r3, #16 8003692: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 8003694: 693b ldr r3, [r7, #16] 8003696: f003 0340 and.w r3, r3, #64 @ 0x40 800369a: 2b00 cmp r3, #0 800369c: d008 beq.n 80036b0 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 800369e: 6a7b ldr r3, [r7, #36] @ 0x24 80036a0: 015a lsls r2, r3, #5 80036a2: 69fb ldr r3, [r7, #28] 80036a4: 4413 add r3, r2 80036a6: f503 6310 add.w r3, r3, #2304 @ 0x900 80036aa: 461a mov r2, r3 80036ac: 2340 movs r3, #64 @ 0x40 80036ae: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 80036b0: 693b ldr r3, [r7, #16] 80036b2: f003 0302 and.w r3, r3, #2 80036b6: 2b00 cmp r3, #0 80036b8: d023 beq.n 8003702 { (void)USB_FlushTxFifo(USBx, epnum); 80036ba: 6a79 ldr r1, [r7, #36] @ 0x24 80036bc: 6a38 ldr r0, [r7, #32] 80036be: f004 fdd9 bl 8008274 ep = &hpcd->IN_ep[epnum]; 80036c2: 6a7a ldr r2, [r7, #36] @ 0x24 80036c4: 4613 mov r3, r2 80036c6: 00db lsls r3, r3, #3 80036c8: 4413 add r3, r2 80036ca: 009b lsls r3, r3, #2 80036cc: 3310 adds r3, #16 80036ce: 687a ldr r2, [r7, #4] 80036d0: 4413 add r3, r2 80036d2: 3304 adds r3, #4 80036d4: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 80036d6: 697b ldr r3, [r7, #20] 80036d8: 78db ldrb r3, [r3, #3] 80036da: 2b01 cmp r3, #1 80036dc: d108 bne.n 80036f0 { ep->is_iso_incomplete = 0U; 80036de: 697b ldr r3, [r7, #20] 80036e0: 2200 movs r2, #0 80036e2: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 80036e4: 6a7b ldr r3, [r7, #36] @ 0x24 80036e6: b2db uxtb r3, r3 80036e8: 4619 mov r1, r3 80036ea: 6878 ldr r0, [r7, #4] 80036ec: f007 fe30 bl 800b350 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 80036f0: 6a7b ldr r3, [r7, #36] @ 0x24 80036f2: 015a lsls r2, r3, #5 80036f4: 69fb ldr r3, [r7, #28] 80036f6: 4413 add r3, r2 80036f8: f503 6310 add.w r3, r3, #2304 @ 0x900 80036fc: 461a mov r2, r3 80036fe: 2302 movs r3, #2 8003700: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 8003702: 693b ldr r3, [r7, #16] 8003704: f003 0380 and.w r3, r3, #128 @ 0x80 8003708: 2b00 cmp r3, #0 800370a: d003 beq.n 8003714 { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 800370c: 6a79 ldr r1, [r7, #36] @ 0x24 800370e: 6878 ldr r0, [r7, #4] 8003710: f000 fcd2 bl 80040b8 } } epnum++; 8003714: 6a7b ldr r3, [r7, #36] @ 0x24 8003716: 3301 adds r3, #1 8003718: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 800371a: 6abb ldr r3, [r7, #40] @ 0x28 800371c: 085b lsrs r3, r3, #1 800371e: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 8003720: 6abb ldr r3, [r7, #40] @ 0x28 8003722: 2b00 cmp r3, #0 8003724: f47f af2e bne.w 8003584 } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 8003728: 687b ldr r3, [r7, #4] 800372a: 681b ldr r3, [r3, #0] 800372c: 4618 mov r0, r3 800372e: f005 fcbd bl 80090ac 8003732: 4603 mov r3, r0 8003734: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8003738: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800373c: d122 bne.n 8003784 { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 800373e: 69fb ldr r3, [r7, #28] 8003740: f503 6300 add.w r3, r3, #2048 @ 0x800 8003744: 685b ldr r3, [r3, #4] 8003746: 69fa ldr r2, [r7, #28] 8003748: f502 6200 add.w r2, r2, #2048 @ 0x800 800374c: f023 0301 bic.w r3, r3, #1 8003750: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 8003752: 687b ldr r3, [r7, #4] 8003754: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003758: 2b01 cmp r3, #1 800375a: d108 bne.n 800376e { hpcd->LPM_State = LPM_L0; 800375c: 687b ldr r3, [r7, #4] 800375e: 2200 movs r2, #0 8003760: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 8003764: 2100 movs r1, #0 8003766: 6878 ldr r0, [r7, #4] 8003768: f007 ff98 bl 800b69c 800376c: e002 b.n 8003774 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 800376e: 6878 ldr r0, [r7, #4] 8003770: f007 fdce bl 800b310 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 8003774: 687b ldr r3, [r7, #4] 8003776: 681b ldr r3, [r3, #0] 8003778: 695a ldr r2, [r3, #20] 800377a: 687b ldr r3, [r7, #4] 800377c: 681b ldr r3, [r3, #0] 800377e: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 8003782: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 8003784: 687b ldr r3, [r7, #4] 8003786: 681b ldr r3, [r3, #0] 8003788: 4618 mov r0, r3 800378a: f005 fc8f bl 80090ac 800378e: 4603 mov r3, r0 8003790: f403 6300 and.w r3, r3, #2048 @ 0x800 8003794: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8003798: d112 bne.n 80037c0 { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 800379a: 69fb ldr r3, [r7, #28] 800379c: f503 6300 add.w r3, r3, #2048 @ 0x800 80037a0: 689b ldr r3, [r3, #8] 80037a2: f003 0301 and.w r3, r3, #1 80037a6: 2b01 cmp r3, #1 80037a8: d102 bne.n 80037b0 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80037aa: 6878 ldr r0, [r7, #4] 80037ac: f007 fd8a bl 800b2c4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 80037b0: 687b ldr r3, [r7, #4] 80037b2: 681b ldr r3, [r3, #0] 80037b4: 695a ldr r2, [r3, #20] 80037b6: 687b ldr r3, [r7, #4] 80037b8: 681b ldr r3, [r3, #0] 80037ba: f402 6200 and.w r2, r2, #2048 @ 0x800 80037be: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 80037c0: 687b ldr r3, [r7, #4] 80037c2: 681b ldr r3, [r3, #0] 80037c4: 4618 mov r0, r3 80037c6: f005 fc71 bl 80090ac 80037ca: 4603 mov r3, r0 80037cc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80037d0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80037d4: d121 bne.n 800381a { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 80037d6: 687b ldr r3, [r7, #4] 80037d8: 681b ldr r3, [r3, #0] 80037da: 695a ldr r2, [r3, #20] 80037dc: 687b ldr r3, [r7, #4] 80037de: 681b ldr r3, [r3, #0] 80037e0: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 80037e4: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 80037e6: 687b ldr r3, [r7, #4] 80037e8: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 80037ec: 2b00 cmp r3, #0 80037ee: d111 bne.n 8003814 { hpcd->LPM_State = LPM_L1; 80037f0: 687b ldr r3, [r7, #4] 80037f2: 2201 movs r2, #1 80037f4: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 80037f8: 687b ldr r3, [r7, #4] 80037fa: 681b ldr r3, [r3, #0] 80037fc: 6d5b ldr r3, [r3, #84] @ 0x54 80037fe: 089b lsrs r3, r3, #2 8003800: f003 020f and.w r2, r3, #15 8003804: 687b ldr r3, [r7, #4] 8003806: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 800380a: 2101 movs r1, #1 800380c: 6878 ldr r0, [r7, #4] 800380e: f007 ff45 bl 800b69c 8003812: e002 b.n 800381a else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8003814: 6878 ldr r0, [r7, #4] 8003816: f007 fd55 bl 800b2c4 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 800381a: 687b ldr r3, [r7, #4] 800381c: 681b ldr r3, [r3, #0] 800381e: 4618 mov r0, r3 8003820: f005 fc44 bl 80090ac 8003824: 4603 mov r3, r0 8003826: f403 5380 and.w r3, r3, #4096 @ 0x1000 800382a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800382e: f040 80b7 bne.w 80039a0 { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 8003832: 69fb ldr r3, [r7, #28] 8003834: f503 6300 add.w r3, r3, #2048 @ 0x800 8003838: 685b ldr r3, [r3, #4] 800383a: 69fa ldr r2, [r7, #28] 800383c: f502 6200 add.w r2, r2, #2048 @ 0x800 8003840: f023 0301 bic.w r3, r3, #1 8003844: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 8003846: 687b ldr r3, [r7, #4] 8003848: 681b ldr r3, [r3, #0] 800384a: 2110 movs r1, #16 800384c: 4618 mov r0, r3 800384e: f004 fd11 bl 8008274 for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8003852: 2300 movs r3, #0 8003854: 62fb str r3, [r7, #44] @ 0x2c 8003856: e046 b.n 80038e6 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 8003858: 6afb ldr r3, [r7, #44] @ 0x2c 800385a: 015a lsls r2, r3, #5 800385c: 69fb ldr r3, [r7, #28] 800385e: 4413 add r3, r2 8003860: f503 6310 add.w r3, r3, #2304 @ 0x900 8003864: 461a mov r2, r3 8003866: f64f 337f movw r3, #64383 @ 0xfb7f 800386a: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 800386c: 6afb ldr r3, [r7, #44] @ 0x2c 800386e: 015a lsls r2, r3, #5 8003870: 69fb ldr r3, [r7, #28] 8003872: 4413 add r3, r2 8003874: f503 6310 add.w r3, r3, #2304 @ 0x900 8003878: 681b ldr r3, [r3, #0] 800387a: 6afa ldr r2, [r7, #44] @ 0x2c 800387c: 0151 lsls r1, r2, #5 800387e: 69fa ldr r2, [r7, #28] 8003880: 440a add r2, r1 8003882: f502 6210 add.w r2, r2, #2304 @ 0x900 8003886: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800388a: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 800388c: 6afb ldr r3, [r7, #44] @ 0x2c 800388e: 015a lsls r2, r3, #5 8003890: 69fb ldr r3, [r7, #28] 8003892: 4413 add r3, r2 8003894: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003898: 461a mov r2, r3 800389a: f64f 337f movw r3, #64383 @ 0xfb7f 800389e: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 80038a0: 6afb ldr r3, [r7, #44] @ 0x2c 80038a2: 015a lsls r2, r3, #5 80038a4: 69fb ldr r3, [r7, #28] 80038a6: 4413 add r3, r2 80038a8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80038ac: 681b ldr r3, [r3, #0] 80038ae: 6afa ldr r2, [r7, #44] @ 0x2c 80038b0: 0151 lsls r1, r2, #5 80038b2: 69fa ldr r2, [r7, #28] 80038b4: 440a add r2, r1 80038b6: f502 6230 add.w r2, r2, #2816 @ 0xb00 80038ba: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80038be: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 80038c0: 6afb ldr r3, [r7, #44] @ 0x2c 80038c2: 015a lsls r2, r3, #5 80038c4: 69fb ldr r3, [r7, #28] 80038c6: 4413 add r3, r2 80038c8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80038cc: 681b ldr r3, [r3, #0] 80038ce: 6afa ldr r2, [r7, #44] @ 0x2c 80038d0: 0151 lsls r1, r2, #5 80038d2: 69fa ldr r2, [r7, #28] 80038d4: 440a add r2, r1 80038d6: f502 6230 add.w r2, r2, #2816 @ 0xb00 80038da: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80038de: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80038e0: 6afb ldr r3, [r7, #44] @ 0x2c 80038e2: 3301 adds r3, #1 80038e4: 62fb str r3, [r7, #44] @ 0x2c 80038e6: 687b ldr r3, [r7, #4] 80038e8: 791b ldrb r3, [r3, #4] 80038ea: 461a mov r2, r3 80038ec: 6afb ldr r3, [r7, #44] @ 0x2c 80038ee: 4293 cmp r3, r2 80038f0: d3b2 bcc.n 8003858 } USBx_DEVICE->DAINTMSK |= 0x10001U; 80038f2: 69fb ldr r3, [r7, #28] 80038f4: f503 6300 add.w r3, r3, #2048 @ 0x800 80038f8: 69db ldr r3, [r3, #28] 80038fa: 69fa ldr r2, [r7, #28] 80038fc: f502 6200 add.w r2, r2, #2048 @ 0x800 8003900: f043 1301 orr.w r3, r3, #65537 @ 0x10001 8003904: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 8003906: 687b ldr r3, [r7, #4] 8003908: 7bdb ldrb r3, [r3, #15] 800390a: 2b00 cmp r3, #0 800390c: d016 beq.n 800393c { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 800390e: 69fb ldr r3, [r7, #28] 8003910: f503 6300 add.w r3, r3, #2048 @ 0x800 8003914: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8003918: 69fa ldr r2, [r7, #28] 800391a: f502 6200 add.w r2, r2, #2048 @ 0x800 800391e: f043 030b orr.w r3, r3, #11 8003922: f8c2 3084 str.w r3, [r2, #132] @ 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 8003926: 69fb ldr r3, [r7, #28] 8003928: f503 6300 add.w r3, r3, #2048 @ 0x800 800392c: 6c5b ldr r3, [r3, #68] @ 0x44 800392e: 69fa ldr r2, [r7, #28] 8003930: f502 6200 add.w r2, r2, #2048 @ 0x800 8003934: f043 030b orr.w r3, r3, #11 8003938: 6453 str r3, [r2, #68] @ 0x44 800393a: e015 b.n 8003968 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 800393c: 69fb ldr r3, [r7, #28] 800393e: f503 6300 add.w r3, r3, #2048 @ 0x800 8003942: 695b ldr r3, [r3, #20] 8003944: 69fa ldr r2, [r7, #28] 8003946: f502 6200 add.w r2, r2, #2048 @ 0x800 800394a: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800394e: f043 032b orr.w r3, r3, #43 @ 0x2b 8003952: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 8003954: 69fb ldr r3, [r7, #28] 8003956: f503 6300 add.w r3, r3, #2048 @ 0x800 800395a: 691b ldr r3, [r3, #16] 800395c: 69fa ldr r2, [r7, #28] 800395e: f502 6200 add.w r2, r2, #2048 @ 0x800 8003962: f043 030b orr.w r3, r3, #11 8003966: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8003968: 69fb ldr r3, [r7, #28] 800396a: f503 6300 add.w r3, r3, #2048 @ 0x800 800396e: 681b ldr r3, [r3, #0] 8003970: 69fa ldr r2, [r7, #28] 8003972: f502 6200 add.w r2, r2, #2048 @ 0x800 8003976: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 800397a: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 800397c: 687b ldr r3, [r7, #4] 800397e: 6818 ldr r0, [r3, #0] 8003980: 687b ldr r3, [r7, #4] 8003982: 7999 ldrb r1, [r3, #6] (uint8_t *)hpcd->Setup); 8003984: 687b ldr r3, [r7, #4] 8003986: f203 439c addw r3, r3, #1180 @ 0x49c (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 800398a: 461a mov r2, r3 800398c: f005 fc52 bl 8009234 __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 8003990: 687b ldr r3, [r7, #4] 8003992: 681b ldr r3, [r3, #0] 8003994: 695a ldr r2, [r3, #20] 8003996: 687b ldr r3, [r7, #4] 8003998: 681b ldr r3, [r3, #0] 800399a: f402 5280 and.w r2, r2, #4096 @ 0x1000 800399e: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 80039a0: 687b ldr r3, [r7, #4] 80039a2: 681b ldr r3, [r3, #0] 80039a4: 4618 mov r0, r3 80039a6: f005 fb81 bl 80090ac 80039aa: 4603 mov r3, r0 80039ac: f403 5300 and.w r3, r3, #8192 @ 0x2000 80039b0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80039b4: d123 bne.n 80039fe { (void)USB_ActivateSetup(hpcd->Instance); 80039b6: 687b ldr r3, [r7, #4] 80039b8: 681b ldr r3, [r3, #0] 80039ba: 4618 mov r0, r3 80039bc: f005 fc17 bl 80091ee hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 80039c0: 687b ldr r3, [r7, #4] 80039c2: 681b ldr r3, [r3, #0] 80039c4: 4618 mov r0, r3 80039c6: f004 fcce bl 8008366 80039ca: 4603 mov r3, r0 80039cc: 461a mov r2, r3 80039ce: 687b ldr r3, [r7, #4] 80039d0: 71da strb r2, [r3, #7] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 80039d2: 687b ldr r3, [r7, #4] 80039d4: 681c ldr r4, [r3, #0] 80039d6: f000 fe8b bl 80046f0 80039da: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 80039dc: 687b ldr r3, [r7, #4] 80039de: 79db ldrb r3, [r3, #7] (void)USB_SetTurnaroundTime(hpcd->Instance, 80039e0: 461a mov r2, r3 80039e2: 4620 mov r0, r4 80039e4: f004 f9d8 bl 8007d98 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 80039e8: 6878 ldr r0, [r7, #4] 80039ea: f007 fc42 bl 800b272 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 80039ee: 687b ldr r3, [r7, #4] 80039f0: 681b ldr r3, [r3, #0] 80039f2: 695a ldr r2, [r3, #20] 80039f4: 687b ldr r3, [r7, #4] 80039f6: 681b ldr r3, [r3, #0] 80039f8: f402 5200 and.w r2, r2, #8192 @ 0x2000 80039fc: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 80039fe: 687b ldr r3, [r7, #4] 8003a00: 681b ldr r3, [r3, #0] 8003a02: 4618 mov r0, r3 8003a04: f005 fb52 bl 80090ac 8003a08: 4603 mov r3, r0 8003a0a: f003 0308 and.w r3, r3, #8 8003a0e: 2b08 cmp r3, #8 8003a10: d10a bne.n 8003a28 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 8003a12: 6878 ldr r0, [r7, #4] 8003a14: f007 fc1f bl 800b256 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 8003a18: 687b ldr r3, [r7, #4] 8003a1a: 681b ldr r3, [r3, #0] 8003a1c: 695a ldr r2, [r3, #20] 8003a1e: 687b ldr r3, [r7, #4] 8003a20: 681b ldr r3, [r3, #0] 8003a22: f002 0208 and.w r2, r2, #8 8003a26: 615a str r2, [r3, #20] } /* Handle Global OUT NAK effective Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) 8003a28: 687b ldr r3, [r7, #4] 8003a2a: 681b ldr r3, [r3, #0] 8003a2c: 4618 mov r0, r3 8003a2e: f005 fb3d bl 80090ac 8003a32: 4603 mov r3, r0 8003a34: f003 0380 and.w r3, r3, #128 @ 0x80 8003a38: 2b80 cmp r3, #128 @ 0x80 8003a3a: d123 bne.n 8003a84 { USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; 8003a3c: 6a3b ldr r3, [r7, #32] 8003a3e: 699b ldr r3, [r3, #24] 8003a40: f023 0280 bic.w r2, r3, #128 @ 0x80 8003a44: 6a3b ldr r3, [r7, #32] 8003a46: 619a str r2, [r3, #24] for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003a48: 2301 movs r3, #1 8003a4a: 627b str r3, [r7, #36] @ 0x24 8003a4c: e014 b.n 8003a78 { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) 8003a4e: 6879 ldr r1, [r7, #4] 8003a50: 6a7a ldr r2, [r7, #36] @ 0x24 8003a52: 4613 mov r3, r2 8003a54: 00db lsls r3, r3, #3 8003a56: 4413 add r3, r2 8003a58: 009b lsls r3, r3, #2 8003a5a: 440b add r3, r1 8003a5c: f203 2357 addw r3, r3, #599 @ 0x257 8003a60: 781b ldrb r3, [r3, #0] 8003a62: 2b01 cmp r3, #1 8003a64: d105 bne.n 8003a72 { /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); 8003a66: 6a7b ldr r3, [r7, #36] @ 0x24 8003a68: b2db uxtb r3, r3 8003a6a: 4619 mov r1, r3 8003a6c: 6878 ldr r0, [r7, #4] 8003a6e: f000 faf2 bl 8004056 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003a72: 6a7b ldr r3, [r7, #36] @ 0x24 8003a74: 3301 adds r3, #1 8003a76: 627b str r3, [r7, #36] @ 0x24 8003a78: 687b ldr r3, [r7, #4] 8003a7a: 791b ldrb r3, [r3, #4] 8003a7c: 461a mov r2, r3 8003a7e: 6a7b ldr r3, [r7, #36] @ 0x24 8003a80: 4293 cmp r3, r2 8003a82: d3e4 bcc.n 8003a4e } } } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 8003a84: 687b ldr r3, [r7, #4] 8003a86: 681b ldr r3, [r3, #0] 8003a88: 4618 mov r0, r3 8003a8a: f005 fb0f bl 80090ac 8003a8e: 4603 mov r3, r0 8003a90: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003a94: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003a98: d13c bne.n 8003b14 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003a9a: 2301 movs r3, #1 8003a9c: 627b str r3, [r7, #36] @ 0x24 8003a9e: e02b b.n 8003af8 { RegVal = USBx_INEP(epnum)->DIEPCTL; 8003aa0: 6a7b ldr r3, [r7, #36] @ 0x24 8003aa2: 015a lsls r2, r3, #5 8003aa4: 69fb ldr r3, [r7, #28] 8003aa6: 4413 add r3, r2 8003aa8: f503 6310 add.w r3, r3, #2304 @ 0x900 8003aac: 681b ldr r3, [r3, #0] 8003aae: 61bb str r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003ab0: 6879 ldr r1, [r7, #4] 8003ab2: 6a7a ldr r2, [r7, #36] @ 0x24 8003ab4: 4613 mov r3, r2 8003ab6: 00db lsls r3, r3, #3 8003ab8: 4413 add r3, r2 8003aba: 009b lsls r3, r3, #2 8003abc: 440b add r3, r1 8003abe: 3318 adds r3, #24 8003ac0: 781b ldrb r3, [r3, #0] 8003ac2: 2b01 cmp r3, #1 8003ac4: d115 bne.n 8003af2 ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) 8003ac6: 69bb ldr r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003ac8: 2b00 cmp r3, #0 8003aca: da12 bge.n 8003af2 { hpcd->IN_ep[epnum].is_iso_incomplete = 1U; 8003acc: 6879 ldr r1, [r7, #4] 8003ace: 6a7a ldr r2, [r7, #36] @ 0x24 8003ad0: 4613 mov r3, r2 8003ad2: 00db lsls r3, r3, #3 8003ad4: 4413 add r3, r2 8003ad6: 009b lsls r3, r3, #2 8003ad8: 440b add r3, r1 8003ada: 3317 adds r3, #23 8003adc: 2201 movs r2, #1 8003ade: 701a strb r2, [r3, #0] /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); 8003ae0: 6a7b ldr r3, [r7, #36] @ 0x24 8003ae2: b2db uxtb r3, r3 8003ae4: f063 037f orn r3, r3, #127 @ 0x7f 8003ae8: b2db uxtb r3, r3 8003aea: 4619 mov r1, r3 8003aec: 6878 ldr r0, [r7, #4] 8003aee: f000 fab2 bl 8004056 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003af2: 6a7b ldr r3, [r7, #36] @ 0x24 8003af4: 3301 adds r3, #1 8003af6: 627b str r3, [r7, #36] @ 0x24 8003af8: 687b ldr r3, [r7, #4] 8003afa: 791b ldrb r3, [r3, #4] 8003afc: 461a mov r2, r3 8003afe: 6a7b ldr r3, [r7, #36] @ 0x24 8003b00: 4293 cmp r3, r2 8003b02: d3cd bcc.n 8003aa0 } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 8003b04: 687b ldr r3, [r7, #4] 8003b06: 681b ldr r3, [r3, #0] 8003b08: 695a ldr r2, [r3, #20] 8003b0a: 687b ldr r3, [r7, #4] 8003b0c: 681b ldr r3, [r3, #0] 8003b0e: f402 1280 and.w r2, r2, #1048576 @ 0x100000 8003b12: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 8003b14: 687b ldr r3, [r7, #4] 8003b16: 681b ldr r3, [r3, #0] 8003b18: 4618 mov r0, r3 8003b1a: f005 fac7 bl 80090ac 8003b1e: 4603 mov r3, r0 8003b20: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003b24: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003b28: d156 bne.n 8003bd8 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003b2a: 2301 movs r3, #1 8003b2c: 627b str r3, [r7, #36] @ 0x24 8003b2e: e045 b.n 8003bbc { RegVal = USBx_OUTEP(epnum)->DOEPCTL; 8003b30: 6a7b ldr r3, [r7, #36] @ 0x24 8003b32: 015a lsls r2, r3, #5 8003b34: 69fb ldr r3, [r7, #28] 8003b36: 4413 add r3, r2 8003b38: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003b3c: 681b ldr r3, [r3, #0] 8003b3e: 61bb str r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003b40: 6879 ldr r1, [r7, #4] 8003b42: 6a7a ldr r2, [r7, #36] @ 0x24 8003b44: 4613 mov r3, r2 8003b46: 00db lsls r3, r3, #3 8003b48: 4413 add r3, r2 8003b4a: 009b lsls r3, r3, #2 8003b4c: 440b add r3, r1 8003b4e: f503 7316 add.w r3, r3, #600 @ 0x258 8003b52: 781b ldrb r3, [r3, #0] 8003b54: 2b01 cmp r3, #1 8003b56: d12e bne.n 8003bb6 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003b58: 69bb ldr r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003b5a: 2b00 cmp r3, #0 8003b5c: da2b bge.n 8003bb6 (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) 8003b5e: 69bb ldr r3, [r7, #24] 8003b60: 0c1a lsrs r2, r3, #16 8003b62: 687b ldr r3, [r7, #4] 8003b64: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 8003b68: 4053 eors r3, r2 8003b6a: f003 0301 and.w r3, r3, #1 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003b6e: 2b00 cmp r3, #0 8003b70: d121 bne.n 8003bb6 { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; 8003b72: 6879 ldr r1, [r7, #4] 8003b74: 6a7a ldr r2, [r7, #36] @ 0x24 8003b76: 4613 mov r3, r2 8003b78: 00db lsls r3, r3, #3 8003b7a: 4413 add r3, r2 8003b7c: 009b lsls r3, r3, #2 8003b7e: 440b add r3, r1 8003b80: f203 2357 addw r3, r3, #599 @ 0x257 8003b84: 2201 movs r2, #1 8003b86: 701a strb r2, [r3, #0] USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; 8003b88: 6a3b ldr r3, [r7, #32] 8003b8a: 699b ldr r3, [r3, #24] 8003b8c: f043 0280 orr.w r2, r3, #128 @ 0x80 8003b90: 6a3b ldr r3, [r7, #32] 8003b92: 619a str r2, [r3, #24] if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) 8003b94: 6a3b ldr r3, [r7, #32] 8003b96: 695b ldr r3, [r3, #20] 8003b98: f003 0380 and.w r3, r3, #128 @ 0x80 8003b9c: 2b00 cmp r3, #0 8003b9e: d10a bne.n 8003bb6 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; 8003ba0: 69fb ldr r3, [r7, #28] 8003ba2: f503 6300 add.w r3, r3, #2048 @ 0x800 8003ba6: 685b ldr r3, [r3, #4] 8003ba8: 69fa ldr r2, [r7, #28] 8003baa: f502 6200 add.w r2, r2, #2048 @ 0x800 8003bae: f443 7300 orr.w r3, r3, #512 @ 0x200 8003bb2: 6053 str r3, [r2, #4] break; 8003bb4: e008 b.n 8003bc8 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003bb6: 6a7b ldr r3, [r7, #36] @ 0x24 8003bb8: 3301 adds r3, #1 8003bba: 627b str r3, [r7, #36] @ 0x24 8003bbc: 687b ldr r3, [r7, #4] 8003bbe: 791b ldrb r3, [r3, #4] 8003bc0: 461a mov r2, r3 8003bc2: 6a7b ldr r3, [r7, #36] @ 0x24 8003bc4: 4293 cmp r3, r2 8003bc6: d3b3 bcc.n 8003b30 } } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8003bc8: 687b ldr r3, [r7, #4] 8003bca: 681b ldr r3, [r3, #0] 8003bcc: 695a ldr r2, [r3, #20] 8003bce: 687b ldr r3, [r7, #4] 8003bd0: 681b ldr r3, [r3, #0] 8003bd2: f402 1200 and.w r2, r2, #2097152 @ 0x200000 8003bd6: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 8003bd8: 687b ldr r3, [r7, #4] 8003bda: 681b ldr r3, [r3, #0] 8003bdc: 4618 mov r0, r3 8003bde: f005 fa65 bl 80090ac 8003be2: 4603 mov r3, r0 8003be4: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8003be8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003bec: d10a bne.n 8003c04 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 8003bee: 6878 ldr r0, [r7, #4] 8003bf0: f007 fbc0 bl 800b374 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 8003bf4: 687b ldr r3, [r7, #4] 8003bf6: 681b ldr r3, [r3, #0] 8003bf8: 695a ldr r2, [r3, #20] 8003bfa: 687b ldr r3, [r7, #4] 8003bfc: 681b ldr r3, [r3, #0] 8003bfe: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 8003c02: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 8003c04: 687b ldr r3, [r7, #4] 8003c06: 681b ldr r3, [r3, #0] 8003c08: 4618 mov r0, r3 8003c0a: f005 fa4f bl 80090ac 8003c0e: 4603 mov r3, r0 8003c10: f003 0304 and.w r3, r3, #4 8003c14: 2b04 cmp r3, #4 8003c16: d115 bne.n 8003c44 { RegVal = hpcd->Instance->GOTGINT; 8003c18: 687b ldr r3, [r7, #4] 8003c1a: 681b ldr r3, [r3, #0] 8003c1c: 685b ldr r3, [r3, #4] 8003c1e: 61bb str r3, [r7, #24] if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 8003c20: 69bb ldr r3, [r7, #24] 8003c22: f003 0304 and.w r3, r3, #4 8003c26: 2b00 cmp r3, #0 8003c28: d002 beq.n 8003c30 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 8003c2a: 6878 ldr r0, [r7, #4] 8003c2c: f007 fbb0 bl 800b390 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= RegVal; 8003c30: 687b ldr r3, [r7, #4] 8003c32: 681b ldr r3, [r3, #0] 8003c34: 6859 ldr r1, [r3, #4] 8003c36: 687b ldr r3, [r7, #4] 8003c38: 681b ldr r3, [r3, #0] 8003c3a: 69ba ldr r2, [r7, #24] 8003c3c: 430a orrs r2, r1 8003c3e: 605a str r2, [r3, #4] 8003c40: e000 b.n 8003c44 return; 8003c42: bf00 nop } } } 8003c44: 3734 adds r7, #52 @ 0x34 8003c46: 46bd mov sp, r7 8003c48: bd90 pop {r4, r7, pc} 08003c4a : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 8003c4a: b580 push {r7, lr} 8003c4c: b082 sub sp, #8 8003c4e: af00 add r7, sp, #0 8003c50: 6078 str r0, [r7, #4] 8003c52: 460b mov r3, r1 8003c54: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 8003c56: 687b ldr r3, [r7, #4] 8003c58: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003c5c: 2b01 cmp r3, #1 8003c5e: d101 bne.n 8003c64 8003c60: 2302 movs r3, #2 8003c62: e012 b.n 8003c8a 8003c64: 687b ldr r3, [r7, #4] 8003c66: 2201 movs r2, #1 8003c68: f883 2494 strb.w r2, [r3, #1172] @ 0x494 hpcd->USB_Address = address; 8003c6c: 687b ldr r3, [r7, #4] 8003c6e: 78fa ldrb r2, [r7, #3] 8003c70: 745a strb r2, [r3, #17] (void)USB_SetDevAddress(hpcd->Instance, address); 8003c72: 687b ldr r3, [r7, #4] 8003c74: 681b ldr r3, [r3, #0] 8003c76: 78fa ldrb r2, [r7, #3] 8003c78: 4611 mov r1, r2 8003c7a: 4618 mov r0, r3 8003c7c: f005 f9ae bl 8008fdc __HAL_UNLOCK(hpcd); 8003c80: 687b ldr r3, [r7, #4] 8003c82: 2200 movs r2, #0 8003c84: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003c88: 2300 movs r3, #0 } 8003c8a: 4618 mov r0, r3 8003c8c: 3708 adds r7, #8 8003c8e: 46bd mov sp, r7 8003c90: bd80 pop {r7, pc} 08003c92 : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 8003c92: b580 push {r7, lr} 8003c94: b084 sub sp, #16 8003c96: af00 add r7, sp, #0 8003c98: 6078 str r0, [r7, #4] 8003c9a: 4608 mov r0, r1 8003c9c: 4611 mov r1, r2 8003c9e: 461a mov r2, r3 8003ca0: 4603 mov r3, r0 8003ca2: 70fb strb r3, [r7, #3] 8003ca4: 460b mov r3, r1 8003ca6: 803b strh r3, [r7, #0] 8003ca8: 4613 mov r3, r2 8003caa: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8003cac: 2300 movs r3, #0 8003cae: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8003cb0: f997 3003 ldrsb.w r3, [r7, #3] 8003cb4: 2b00 cmp r3, #0 8003cb6: da0f bge.n 8003cd8 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003cb8: 78fb ldrb r3, [r7, #3] 8003cba: f003 020f and.w r2, r3, #15 8003cbe: 4613 mov r3, r2 8003cc0: 00db lsls r3, r3, #3 8003cc2: 4413 add r3, r2 8003cc4: 009b lsls r3, r3, #2 8003cc6: 3310 adds r3, #16 8003cc8: 687a ldr r2, [r7, #4] 8003cca: 4413 add r3, r2 8003ccc: 3304 adds r3, #4 8003cce: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003cd0: 68fb ldr r3, [r7, #12] 8003cd2: 2201 movs r2, #1 8003cd4: 705a strb r2, [r3, #1] 8003cd6: e00f b.n 8003cf8 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003cd8: 78fb ldrb r3, [r7, #3] 8003cda: f003 020f and.w r2, r3, #15 8003cde: 4613 mov r3, r2 8003ce0: 00db lsls r3, r3, #3 8003ce2: 4413 add r3, r2 8003ce4: 009b lsls r3, r3, #2 8003ce6: f503 7314 add.w r3, r3, #592 @ 0x250 8003cea: 687a ldr r2, [r7, #4] 8003cec: 4413 add r3, r2 8003cee: 3304 adds r3, #4 8003cf0: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003cf2: 68fb ldr r3, [r7, #12] 8003cf4: 2200 movs r2, #0 8003cf6: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003cf8: 78fb ldrb r3, [r7, #3] 8003cfa: f003 030f and.w r3, r3, #15 8003cfe: b2da uxtb r2, r3 8003d00: 68fb ldr r3, [r7, #12] 8003d02: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 8003d04: 883b ldrh r3, [r7, #0] 8003d06: f3c3 020a ubfx r2, r3, #0, #11 8003d0a: 68fb ldr r3, [r7, #12] 8003d0c: 609a str r2, [r3, #8] ep->type = ep_type; 8003d0e: 68fb ldr r3, [r7, #12] 8003d10: 78ba ldrb r2, [r7, #2] 8003d12: 711a strb r2, [r3, #4] if (ep->is_in != 0U) 8003d14: 68fb ldr r3, [r7, #12] 8003d16: 785b ldrb r3, [r3, #1] 8003d18: 2b00 cmp r3, #0 8003d1a: d004 beq.n 8003d26 { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 8003d1c: 68fb ldr r3, [r7, #12] 8003d1e: 781b ldrb r3, [r3, #0] 8003d20: 461a mov r2, r3 8003d22: 68fb ldr r3, [r7, #12] 8003d24: 835a strh r2, [r3, #26] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8003d26: 78bb ldrb r3, [r7, #2] 8003d28: 2b02 cmp r3, #2 8003d2a: d102 bne.n 8003d32 { ep->data_pid_start = 0U; 8003d2c: 68fb ldr r3, [r7, #12] 8003d2e: 2200 movs r2, #0 8003d30: 715a strb r2, [r3, #5] } __HAL_LOCK(hpcd); 8003d32: 687b ldr r3, [r7, #4] 8003d34: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003d38: 2b01 cmp r3, #1 8003d3a: d101 bne.n 8003d40 8003d3c: 2302 movs r3, #2 8003d3e: e00e b.n 8003d5e 8003d40: 687b ldr r3, [r7, #4] 8003d42: 2201 movs r2, #1 8003d44: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 8003d48: 687b ldr r3, [r7, #4] 8003d4a: 681b ldr r3, [r3, #0] 8003d4c: 68f9 ldr r1, [r7, #12] 8003d4e: 4618 mov r0, r3 8003d50: f004 fb2e bl 80083b0 __HAL_UNLOCK(hpcd); 8003d54: 687b ldr r3, [r7, #4] 8003d56: 2200 movs r2, #0 8003d58: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return ret; 8003d5c: 7afb ldrb r3, [r7, #11] } 8003d5e: 4618 mov r0, r3 8003d60: 3710 adds r7, #16 8003d62: 46bd mov sp, r7 8003d64: bd80 pop {r7, pc} 08003d66 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003d66: b580 push {r7, lr} 8003d68: b084 sub sp, #16 8003d6a: af00 add r7, sp, #0 8003d6c: 6078 str r0, [r7, #4] 8003d6e: 460b mov r3, r1 8003d70: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8003d72: f997 3003 ldrsb.w r3, [r7, #3] 8003d76: 2b00 cmp r3, #0 8003d78: da0f bge.n 8003d9a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003d7a: 78fb ldrb r3, [r7, #3] 8003d7c: f003 020f and.w r2, r3, #15 8003d80: 4613 mov r3, r2 8003d82: 00db lsls r3, r3, #3 8003d84: 4413 add r3, r2 8003d86: 009b lsls r3, r3, #2 8003d88: 3310 adds r3, #16 8003d8a: 687a ldr r2, [r7, #4] 8003d8c: 4413 add r3, r2 8003d8e: 3304 adds r3, #4 8003d90: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003d92: 68fb ldr r3, [r7, #12] 8003d94: 2201 movs r2, #1 8003d96: 705a strb r2, [r3, #1] 8003d98: e00f b.n 8003dba } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003d9a: 78fb ldrb r3, [r7, #3] 8003d9c: f003 020f and.w r2, r3, #15 8003da0: 4613 mov r3, r2 8003da2: 00db lsls r3, r3, #3 8003da4: 4413 add r3, r2 8003da6: 009b lsls r3, r3, #2 8003da8: f503 7314 add.w r3, r3, #592 @ 0x250 8003dac: 687a ldr r2, [r7, #4] 8003dae: 4413 add r3, r2 8003db0: 3304 adds r3, #4 8003db2: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003db4: 68fb ldr r3, [r7, #12] 8003db6: 2200 movs r2, #0 8003db8: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003dba: 78fb ldrb r3, [r7, #3] 8003dbc: f003 030f and.w r3, r3, #15 8003dc0: b2da uxtb r2, r3 8003dc2: 68fb ldr r3, [r7, #12] 8003dc4: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003dc6: 687b ldr r3, [r7, #4] 8003dc8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003dcc: 2b01 cmp r3, #1 8003dce: d101 bne.n 8003dd4 8003dd0: 2302 movs r3, #2 8003dd2: e00e b.n 8003df2 8003dd4: 687b ldr r3, [r7, #4] 8003dd6: 2201 movs r2, #1 8003dd8: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8003ddc: 687b ldr r3, [r7, #4] 8003dde: 681b ldr r3, [r3, #0] 8003de0: 68f9 ldr r1, [r7, #12] 8003de2: 4618 mov r0, r3 8003de4: f004 fb6c bl 80084c0 __HAL_UNLOCK(hpcd); 8003de8: 687b ldr r3, [r7, #4] 8003dea: 2200 movs r2, #0 8003dec: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003df0: 2300 movs r3, #0 } 8003df2: 4618 mov r0, r3 8003df4: 3710 adds r7, #16 8003df6: 46bd mov sp, r7 8003df8: bd80 pop {r7, pc} 08003dfa : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003dfa: b580 push {r7, lr} 8003dfc: b086 sub sp, #24 8003dfe: af00 add r7, sp, #0 8003e00: 60f8 str r0, [r7, #12] 8003e02: 607a str r2, [r7, #4] 8003e04: 603b str r3, [r7, #0] 8003e06: 460b mov r3, r1 8003e08: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003e0a: 7afb ldrb r3, [r7, #11] 8003e0c: f003 020f and.w r2, r3, #15 8003e10: 4613 mov r3, r2 8003e12: 00db lsls r3, r3, #3 8003e14: 4413 add r3, r2 8003e16: 009b lsls r3, r3, #2 8003e18: f503 7314 add.w r3, r3, #592 @ 0x250 8003e1c: 68fa ldr r2, [r7, #12] 8003e1e: 4413 add r3, r2 8003e20: 3304 adds r3, #4 8003e22: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003e24: 697b ldr r3, [r7, #20] 8003e26: 687a ldr r2, [r7, #4] 8003e28: 60da str r2, [r3, #12] ep->xfer_len = len; 8003e2a: 697b ldr r3, [r7, #20] 8003e2c: 683a ldr r2, [r7, #0] 8003e2e: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003e30: 697b ldr r3, [r7, #20] 8003e32: 2200 movs r2, #0 8003e34: 615a str r2, [r3, #20] ep->is_in = 0U; 8003e36: 697b ldr r3, [r7, #20] 8003e38: 2200 movs r2, #0 8003e3a: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003e3c: 7afb ldrb r3, [r7, #11] 8003e3e: f003 030f and.w r3, r3, #15 8003e42: b2da uxtb r2, r3 8003e44: 697b ldr r3, [r7, #20] 8003e46: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003e48: 68fb ldr r3, [r7, #12] 8003e4a: 799b ldrb r3, [r3, #6] 8003e4c: 2b01 cmp r3, #1 8003e4e: d102 bne.n 8003e56 { ep->dma_addr = (uint32_t)pBuf; 8003e50: 687a ldr r2, [r7, #4] 8003e52: 697b ldr r3, [r7, #20] 8003e54: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003e56: 68fb ldr r3, [r7, #12] 8003e58: 6818 ldr r0, [r3, #0] 8003e5a: 68fb ldr r3, [r7, #12] 8003e5c: 799b ldrb r3, [r3, #6] 8003e5e: 461a mov r2, r3 8003e60: 6979 ldr r1, [r7, #20] 8003e62: f004 fc09 bl 8008678 return HAL_OK; 8003e66: 2300 movs r3, #0 } 8003e68: 4618 mov r0, r3 8003e6a: 3718 adds r7, #24 8003e6c: 46bd mov sp, r7 8003e6e: bd80 pop {r7, pc} 08003e70 : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003e70: b580 push {r7, lr} 8003e72: b086 sub sp, #24 8003e74: af00 add r7, sp, #0 8003e76: 60f8 str r0, [r7, #12] 8003e78: 607a str r2, [r7, #4] 8003e7a: 603b str r3, [r7, #0] 8003e7c: 460b mov r3, r1 8003e7e: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003e80: 7afb ldrb r3, [r7, #11] 8003e82: f003 020f and.w r2, r3, #15 8003e86: 4613 mov r3, r2 8003e88: 00db lsls r3, r3, #3 8003e8a: 4413 add r3, r2 8003e8c: 009b lsls r3, r3, #2 8003e8e: 3310 adds r3, #16 8003e90: 68fa ldr r2, [r7, #12] 8003e92: 4413 add r3, r2 8003e94: 3304 adds r3, #4 8003e96: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003e98: 697b ldr r3, [r7, #20] 8003e9a: 687a ldr r2, [r7, #4] 8003e9c: 60da str r2, [r3, #12] ep->xfer_len = len; 8003e9e: 697b ldr r3, [r7, #20] 8003ea0: 683a ldr r2, [r7, #0] 8003ea2: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003ea4: 697b ldr r3, [r7, #20] 8003ea6: 2200 movs r2, #0 8003ea8: 615a str r2, [r3, #20] ep->is_in = 1U; 8003eaa: 697b ldr r3, [r7, #20] 8003eac: 2201 movs r2, #1 8003eae: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003eb0: 7afb ldrb r3, [r7, #11] 8003eb2: f003 030f and.w r3, r3, #15 8003eb6: b2da uxtb r2, r3 8003eb8: 697b ldr r3, [r7, #20] 8003eba: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003ebc: 68fb ldr r3, [r7, #12] 8003ebe: 799b ldrb r3, [r3, #6] 8003ec0: 2b01 cmp r3, #1 8003ec2: d102 bne.n 8003eca { ep->dma_addr = (uint32_t)pBuf; 8003ec4: 687a ldr r2, [r7, #4] 8003ec6: 697b ldr r3, [r7, #20] 8003ec8: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003eca: 68fb ldr r3, [r7, #12] 8003ecc: 6818 ldr r0, [r3, #0] 8003ece: 68fb ldr r3, [r7, #12] 8003ed0: 799b ldrb r3, [r3, #6] 8003ed2: 461a mov r2, r3 8003ed4: 6979 ldr r1, [r7, #20] 8003ed6: f004 fbcf bl 8008678 return HAL_OK; 8003eda: 2300 movs r3, #0 } 8003edc: 4618 mov r0, r3 8003ede: 3718 adds r7, #24 8003ee0: 46bd mov sp, r7 8003ee2: bd80 pop {r7, pc} 08003ee4 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003ee4: b580 push {r7, lr} 8003ee6: b084 sub sp, #16 8003ee8: af00 add r7, sp, #0 8003eea: 6078 str r0, [r7, #4] 8003eec: 460b mov r3, r1 8003eee: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 8003ef0: 78fb ldrb r3, [r7, #3] 8003ef2: f003 030f and.w r3, r3, #15 8003ef6: 687a ldr r2, [r7, #4] 8003ef8: 7912 ldrb r2, [r2, #4] 8003efa: 4293 cmp r3, r2 8003efc: d901 bls.n 8003f02 { return HAL_ERROR; 8003efe: 2301 movs r3, #1 8003f00: e04f b.n 8003fa2 } if ((0x80U & ep_addr) == 0x80U) 8003f02: f997 3003 ldrsb.w r3, [r7, #3] 8003f06: 2b00 cmp r3, #0 8003f08: da0f bge.n 8003f2a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003f0a: 78fb ldrb r3, [r7, #3] 8003f0c: f003 020f and.w r2, r3, #15 8003f10: 4613 mov r3, r2 8003f12: 00db lsls r3, r3, #3 8003f14: 4413 add r3, r2 8003f16: 009b lsls r3, r3, #2 8003f18: 3310 adds r3, #16 8003f1a: 687a ldr r2, [r7, #4] 8003f1c: 4413 add r3, r2 8003f1e: 3304 adds r3, #4 8003f20: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003f22: 68fb ldr r3, [r7, #12] 8003f24: 2201 movs r2, #1 8003f26: 705a strb r2, [r3, #1] 8003f28: e00d b.n 8003f46 } else { ep = &hpcd->OUT_ep[ep_addr]; 8003f2a: 78fa ldrb r2, [r7, #3] 8003f2c: 4613 mov r3, r2 8003f2e: 00db lsls r3, r3, #3 8003f30: 4413 add r3, r2 8003f32: 009b lsls r3, r3, #2 8003f34: f503 7314 add.w r3, r3, #592 @ 0x250 8003f38: 687a ldr r2, [r7, #4] 8003f3a: 4413 add r3, r2 8003f3c: 3304 adds r3, #4 8003f3e: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003f40: 68fb ldr r3, [r7, #12] 8003f42: 2200 movs r2, #0 8003f44: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8003f46: 68fb ldr r3, [r7, #12] 8003f48: 2201 movs r2, #1 8003f4a: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003f4c: 78fb ldrb r3, [r7, #3] 8003f4e: f003 030f and.w r3, r3, #15 8003f52: b2da uxtb r2, r3 8003f54: 68fb ldr r3, [r7, #12] 8003f56: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003f58: 687b ldr r3, [r7, #4] 8003f5a: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003f5e: 2b01 cmp r3, #1 8003f60: d101 bne.n 8003f66 8003f62: 2302 movs r3, #2 8003f64: e01d b.n 8003fa2 8003f66: 687b ldr r3, [r7, #4] 8003f68: 2201 movs r2, #1 8003f6a: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPSetStall(hpcd->Instance, ep); 8003f6e: 687b ldr r3, [r7, #4] 8003f70: 681b ldr r3, [r3, #0] 8003f72: 68f9 ldr r1, [r7, #12] 8003f74: 4618 mov r0, r3 8003f76: f004 ff5d bl 8008e34 if ((ep_addr & EP_ADDR_MSK) == 0U) 8003f7a: 78fb ldrb r3, [r7, #3] 8003f7c: f003 030f and.w r3, r3, #15 8003f80: 2b00 cmp r3, #0 8003f82: d109 bne.n 8003f98 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8003f84: 687b ldr r3, [r7, #4] 8003f86: 6818 ldr r0, [r3, #0] 8003f88: 687b ldr r3, [r7, #4] 8003f8a: 7999 ldrb r1, [r3, #6] 8003f8c: 687b ldr r3, [r7, #4] 8003f8e: f203 439c addw r3, r3, #1180 @ 0x49c 8003f92: 461a mov r2, r3 8003f94: f005 f94e bl 8009234 } __HAL_UNLOCK(hpcd); 8003f98: 687b ldr r3, [r7, #4] 8003f9a: 2200 movs r2, #0 8003f9c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003fa0: 2300 movs r3, #0 } 8003fa2: 4618 mov r0, r3 8003fa4: 3710 adds r7, #16 8003fa6: 46bd mov sp, r7 8003fa8: bd80 pop {r7, pc} 08003faa : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003faa: b580 push {r7, lr} 8003fac: b084 sub sp, #16 8003fae: af00 add r7, sp, #0 8003fb0: 6078 str r0, [r7, #4] 8003fb2: 460b mov r3, r1 8003fb4: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8003fb6: 78fb ldrb r3, [r7, #3] 8003fb8: f003 030f and.w r3, r3, #15 8003fbc: 687a ldr r2, [r7, #4] 8003fbe: 7912 ldrb r2, [r2, #4] 8003fc0: 4293 cmp r3, r2 8003fc2: d901 bls.n 8003fc8 { return HAL_ERROR; 8003fc4: 2301 movs r3, #1 8003fc6: e042 b.n 800404e } if ((0x80U & ep_addr) == 0x80U) 8003fc8: f997 3003 ldrsb.w r3, [r7, #3] 8003fcc: 2b00 cmp r3, #0 8003fce: da0f bge.n 8003ff0 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003fd0: 78fb ldrb r3, [r7, #3] 8003fd2: f003 020f and.w r2, r3, #15 8003fd6: 4613 mov r3, r2 8003fd8: 00db lsls r3, r3, #3 8003fda: 4413 add r3, r2 8003fdc: 009b lsls r3, r3, #2 8003fde: 3310 adds r3, #16 8003fe0: 687a ldr r2, [r7, #4] 8003fe2: 4413 add r3, r2 8003fe4: 3304 adds r3, #4 8003fe6: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003fe8: 68fb ldr r3, [r7, #12] 8003fea: 2201 movs r2, #1 8003fec: 705a strb r2, [r3, #1] 8003fee: e00f b.n 8004010 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003ff0: 78fb ldrb r3, [r7, #3] 8003ff2: f003 020f and.w r2, r3, #15 8003ff6: 4613 mov r3, r2 8003ff8: 00db lsls r3, r3, #3 8003ffa: 4413 add r3, r2 8003ffc: 009b lsls r3, r3, #2 8003ffe: f503 7314 add.w r3, r3, #592 @ 0x250 8004002: 687a ldr r2, [r7, #4] 8004004: 4413 add r3, r2 8004006: 3304 adds r3, #4 8004008: 60fb str r3, [r7, #12] ep->is_in = 0U; 800400a: 68fb ldr r3, [r7, #12] 800400c: 2200 movs r2, #0 800400e: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8004010: 68fb ldr r3, [r7, #12] 8004012: 2200 movs r2, #0 8004014: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8004016: 78fb ldrb r3, [r7, #3] 8004018: f003 030f and.w r3, r3, #15 800401c: b2da uxtb r2, r3 800401e: 68fb ldr r3, [r7, #12] 8004020: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8004022: 687b ldr r3, [r7, #4] 8004024: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8004028: 2b01 cmp r3, #1 800402a: d101 bne.n 8004030 800402c: 2302 movs r3, #2 800402e: e00e b.n 800404e 8004030: 687b ldr r3, [r7, #4] 8004032: 2201 movs r2, #1 8004034: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPClearStall(hpcd->Instance, ep); 8004038: 687b ldr r3, [r7, #4] 800403a: 681b ldr r3, [r3, #0] 800403c: 68f9 ldr r1, [r7, #12] 800403e: 4618 mov r0, r3 8004040: f004 ff66 bl 8008f10 __HAL_UNLOCK(hpcd); 8004044: 687b ldr r3, [r7, #4] 8004046: 2200 movs r2, #0 8004048: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 800404c: 2300 movs r3, #0 } 800404e: 4618 mov r0, r3 8004050: 3710 adds r7, #16 8004052: 46bd mov sp, r7 8004054: bd80 pop {r7, pc} 08004056 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8004056: b580 push {r7, lr} 8004058: b084 sub sp, #16 800405a: af00 add r7, sp, #0 800405c: 6078 str r0, [r7, #4] 800405e: 460b mov r3, r1 8004060: 70fb strb r3, [r7, #3] HAL_StatusTypeDef ret; PCD_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) 8004062: f997 3003 ldrsb.w r3, [r7, #3] 8004066: 2b00 cmp r3, #0 8004068: da0c bge.n 8004084 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800406a: 78fb ldrb r3, [r7, #3] 800406c: f003 020f and.w r2, r3, #15 8004070: 4613 mov r3, r2 8004072: 00db lsls r3, r3, #3 8004074: 4413 add r3, r2 8004076: 009b lsls r3, r3, #2 8004078: 3310 adds r3, #16 800407a: 687a ldr r2, [r7, #4] 800407c: 4413 add r3, r2 800407e: 3304 adds r3, #4 8004080: 60fb str r3, [r7, #12] 8004082: e00c b.n 800409e } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8004084: 78fb ldrb r3, [r7, #3] 8004086: f003 020f and.w r2, r3, #15 800408a: 4613 mov r3, r2 800408c: 00db lsls r3, r3, #3 800408e: 4413 add r3, r2 8004090: 009b lsls r3, r3, #2 8004092: f503 7314 add.w r3, r3, #592 @ 0x250 8004096: 687a ldr r2, [r7, #4] 8004098: 4413 add r3, r2 800409a: 3304 adds r3, #4 800409c: 60fb str r3, [r7, #12] } /* Stop Xfer */ ret = USB_EPStopXfer(hpcd->Instance, ep); 800409e: 687b ldr r3, [r7, #4] 80040a0: 681b ldr r3, [r3, #0] 80040a2: 68f9 ldr r1, [r7, #12] 80040a4: 4618 mov r0, r3 80040a6: f004 fd85 bl 8008bb4 80040aa: 4603 mov r3, r0 80040ac: 72fb strb r3, [r7, #11] return ret; 80040ae: 7afb ldrb r3, [r7, #11] } 80040b0: 4618 mov r0, r3 80040b2: 3710 adds r7, #16 80040b4: 46bd mov sp, r7 80040b6: bd80 pop {r7, pc} 080040b8 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 80040b8: b580 push {r7, lr} 80040ba: b08a sub sp, #40 @ 0x28 80040bc: af02 add r7, sp, #8 80040be: 6078 str r0, [r7, #4] 80040c0: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80040c2: 687b ldr r3, [r7, #4] 80040c4: 681b ldr r3, [r3, #0] 80040c6: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 80040c8: 697b ldr r3, [r7, #20] 80040ca: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 80040cc: 683a ldr r2, [r7, #0] 80040ce: 4613 mov r3, r2 80040d0: 00db lsls r3, r3, #3 80040d2: 4413 add r3, r2 80040d4: 009b lsls r3, r3, #2 80040d6: 3310 adds r3, #16 80040d8: 687a ldr r2, [r7, #4] 80040da: 4413 add r3, r2 80040dc: 3304 adds r3, #4 80040de: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 80040e0: 68fb ldr r3, [r7, #12] 80040e2: 695a ldr r2, [r3, #20] 80040e4: 68fb ldr r3, [r7, #12] 80040e6: 691b ldr r3, [r3, #16] 80040e8: 429a cmp r2, r3 80040ea: d901 bls.n 80040f0 { return HAL_ERROR; 80040ec: 2301 movs r3, #1 80040ee: e06b b.n 80041c8 } len = ep->xfer_len - ep->xfer_count; 80040f0: 68fb ldr r3, [r7, #12] 80040f2: 691a ldr r2, [r3, #16] 80040f4: 68fb ldr r3, [r7, #12] 80040f6: 695b ldr r3, [r3, #20] 80040f8: 1ad3 subs r3, r2, r3 80040fa: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 80040fc: 68fb ldr r3, [r7, #12] 80040fe: 689b ldr r3, [r3, #8] 8004100: 69fa ldr r2, [r7, #28] 8004102: 429a cmp r2, r3 8004104: d902 bls.n 800410c { len = ep->maxpacket; 8004106: 68fb ldr r3, [r7, #12] 8004108: 689b ldr r3, [r3, #8] 800410a: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 800410c: 69fb ldr r3, [r7, #28] 800410e: 3303 adds r3, #3 8004110: 089b lsrs r3, r3, #2 8004112: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8004114: e02a b.n 800416c (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 8004116: 68fb ldr r3, [r7, #12] 8004118: 691a ldr r2, [r3, #16] 800411a: 68fb ldr r3, [r7, #12] 800411c: 695b ldr r3, [r3, #20] 800411e: 1ad3 subs r3, r2, r3 8004120: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8004122: 68fb ldr r3, [r7, #12] 8004124: 689b ldr r3, [r3, #8] 8004126: 69fa ldr r2, [r7, #28] 8004128: 429a cmp r2, r3 800412a: d902 bls.n 8004132 { len = ep->maxpacket; 800412c: 68fb ldr r3, [r7, #12] 800412e: 689b ldr r3, [r3, #8] 8004130: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8004132: 69fb ldr r3, [r7, #28] 8004134: 3303 adds r3, #3 8004136: 089b lsrs r3, r3, #2 8004138: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 800413a: 68fb ldr r3, [r7, #12] 800413c: 68d9 ldr r1, [r3, #12] 800413e: 683b ldr r3, [r7, #0] 8004140: b2da uxtb r2, r3 8004142: 69fb ldr r3, [r7, #28] 8004144: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8004146: 687b ldr r3, [r7, #4] 8004148: 799b ldrb r3, [r3, #6] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 800414a: 9300 str r3, [sp, #0] 800414c: 4603 mov r3, r0 800414e: 6978 ldr r0, [r7, #20] 8004150: f004 fdda bl 8008d08 ep->xfer_buff += len; 8004154: 68fb ldr r3, [r7, #12] 8004156: 68da ldr r2, [r3, #12] 8004158: 69fb ldr r3, [r7, #28] 800415a: 441a add r2, r3 800415c: 68fb ldr r3, [r7, #12] 800415e: 60da str r2, [r3, #12] ep->xfer_count += len; 8004160: 68fb ldr r3, [r7, #12] 8004162: 695a ldr r2, [r3, #20] 8004164: 69fb ldr r3, [r7, #28] 8004166: 441a add r2, r3 8004168: 68fb ldr r3, [r7, #12] 800416a: 615a str r2, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 800416c: 683b ldr r3, [r7, #0] 800416e: 015a lsls r2, r3, #5 8004170: 693b ldr r3, [r7, #16] 8004172: 4413 add r3, r2 8004174: f503 6310 add.w r3, r3, #2304 @ 0x900 8004178: 699b ldr r3, [r3, #24] 800417a: b29b uxth r3, r3 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 800417c: 69ba ldr r2, [r7, #24] 800417e: 429a cmp r2, r3 8004180: d809 bhi.n 8004196 8004182: 68fb ldr r3, [r7, #12] 8004184: 695a ldr r2, [r3, #20] 8004186: 68fb ldr r3, [r7, #12] 8004188: 691b ldr r3, [r3, #16] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 800418a: 429a cmp r2, r3 800418c: d203 bcs.n 8004196 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 800418e: 68fb ldr r3, [r7, #12] 8004190: 691b ldr r3, [r3, #16] 8004192: 2b00 cmp r3, #0 8004194: d1bf bne.n 8004116 } if (ep->xfer_len <= ep->xfer_count) 8004196: 68fb ldr r3, [r7, #12] 8004198: 691a ldr r2, [r3, #16] 800419a: 68fb ldr r3, [r7, #12] 800419c: 695b ldr r3, [r3, #20] 800419e: 429a cmp r2, r3 80041a0: d811 bhi.n 80041c6 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 80041a2: 683b ldr r3, [r7, #0] 80041a4: f003 030f and.w r3, r3, #15 80041a8: 2201 movs r2, #1 80041aa: fa02 f303 lsl.w r3, r2, r3 80041ae: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 80041b0: 693b ldr r3, [r7, #16] 80041b2: f503 6300 add.w r3, r3, #2048 @ 0x800 80041b6: 6b5a ldr r2, [r3, #52] @ 0x34 80041b8: 68bb ldr r3, [r7, #8] 80041ba: 43db mvns r3, r3 80041bc: 6939 ldr r1, [r7, #16] 80041be: f501 6100 add.w r1, r1, #2048 @ 0x800 80041c2: 4013 ands r3, r2 80041c4: 634b str r3, [r1, #52] @ 0x34 } return HAL_OK; 80041c6: 2300 movs r3, #0 } 80041c8: 4618 mov r0, r3 80041ca: 3720 adds r7, #32 80041cc: 46bd mov sp, r7 80041ce: bd80 pop {r7, pc} 080041d0 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 80041d0: b580 push {r7, lr} 80041d2: b088 sub sp, #32 80041d4: af00 add r7, sp, #0 80041d6: 6078 str r0, [r7, #4] 80041d8: 6039 str r1, [r7, #0] USB_OTG_EPTypeDef *ep; const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80041da: 687b ldr r3, [r7, #4] 80041dc: 681b ldr r3, [r3, #0] 80041de: 61fb str r3, [r7, #28] uint32_t USBx_BASE = (uint32_t)USBx; 80041e0: 69fb ldr r3, [r7, #28] 80041e2: 61bb str r3, [r7, #24] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 80041e4: 69fb ldr r3, [r7, #28] 80041e6: 333c adds r3, #60 @ 0x3c 80041e8: 3304 adds r3, #4 80041ea: 681b ldr r3, [r3, #0] 80041ec: 617b str r3, [r7, #20] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 80041ee: 683b ldr r3, [r7, #0] 80041f0: 015a lsls r2, r3, #5 80041f2: 69bb ldr r3, [r7, #24] 80041f4: 4413 add r3, r2 80041f6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80041fa: 689b ldr r3, [r3, #8] 80041fc: 613b str r3, [r7, #16] if (hpcd->Init.dma_enable == 1U) 80041fe: 687b ldr r3, [r7, #4] 8004200: 799b ldrb r3, [r3, #6] 8004202: 2b01 cmp r3, #1 8004204: d17b bne.n 80042fe { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8004206: 693b ldr r3, [r7, #16] 8004208: f003 0308 and.w r3, r3, #8 800420c: 2b00 cmp r3, #0 800420e: d015 beq.n 800423c { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004210: 697b ldr r3, [r7, #20] 8004212: 4a61 ldr r2, [pc, #388] @ (8004398 ) 8004214: 4293 cmp r3, r2 8004216: f240 80b9 bls.w 800438c ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 800421a: 693b ldr r3, [r7, #16] 800421c: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004220: 2b00 cmp r3, #0 8004222: f000 80b3 beq.w 800438c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8004226: 683b ldr r3, [r7, #0] 8004228: 015a lsls r2, r3, #5 800422a: 69bb ldr r3, [r7, #24] 800422c: 4413 add r3, r2 800422e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004232: 461a mov r2, r3 8004234: f44f 4300 mov.w r3, #32768 @ 0x8000 8004238: 6093 str r3, [r2, #8] 800423a: e0a7 b.n 800438c } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 800423c: 693b ldr r3, [r7, #16] 800423e: f003 0320 and.w r3, r3, #32 8004242: 2b00 cmp r3, #0 8004244: d009 beq.n 800425a { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8004246: 683b ldr r3, [r7, #0] 8004248: 015a lsls r2, r3, #5 800424a: 69bb ldr r3, [r7, #24] 800424c: 4413 add r3, r2 800424e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004252: 461a mov r2, r3 8004254: 2320 movs r3, #32 8004256: 6093 str r3, [r2, #8] 8004258: e098 b.n 800438c } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 800425a: 693b ldr r3, [r7, #16] 800425c: f003 0328 and.w r3, r3, #40 @ 0x28 8004260: 2b00 cmp r3, #0 8004262: f040 8093 bne.w 800438c { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004266: 697b ldr r3, [r7, #20] 8004268: 4a4b ldr r2, [pc, #300] @ (8004398 ) 800426a: 4293 cmp r3, r2 800426c: d90f bls.n 800428e ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 800426e: 693b ldr r3, [r7, #16] 8004270: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004274: 2b00 cmp r3, #0 8004276: d00a beq.n 800428e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8004278: 683b ldr r3, [r7, #0] 800427a: 015a lsls r2, r3, #5 800427c: 69bb ldr r3, [r7, #24] 800427e: 4413 add r3, r2 8004280: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004284: 461a mov r2, r3 8004286: f44f 4300 mov.w r3, #32768 @ 0x8000 800428a: 6093 str r3, [r2, #8] 800428c: e07e b.n 800438c } else { ep = &hpcd->OUT_ep[epnum]; 800428e: 683a ldr r2, [r7, #0] 8004290: 4613 mov r3, r2 8004292: 00db lsls r3, r3, #3 8004294: 4413 add r3, r2 8004296: 009b lsls r3, r3, #2 8004298: f503 7314 add.w r3, r3, #592 @ 0x250 800429c: 687a ldr r2, [r7, #4] 800429e: 4413 add r3, r2 80042a0: 3304 adds r3, #4 80042a2: 60fb str r3, [r7, #12] /* out data packet received over EP */ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 80042a4: 68fb ldr r3, [r7, #12] 80042a6: 6a1a ldr r2, [r3, #32] 80042a8: 683b ldr r3, [r7, #0] 80042aa: 0159 lsls r1, r3, #5 80042ac: 69bb ldr r3, [r7, #24] 80042ae: 440b add r3, r1 80042b0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80042b4: 691b ldr r3, [r3, #16] 80042b6: f3c3 0312 ubfx r3, r3, #0, #19 80042ba: 1ad2 subs r2, r2, r3 80042bc: 68fb ldr r3, [r7, #12] 80042be: 615a str r2, [r3, #20] if (epnum == 0U) 80042c0: 683b ldr r3, [r7, #0] 80042c2: 2b00 cmp r3, #0 80042c4: d114 bne.n 80042f0 { if (ep->xfer_len == 0U) 80042c6: 68fb ldr r3, [r7, #12] 80042c8: 691b ldr r3, [r3, #16] 80042ca: 2b00 cmp r3, #0 80042cc: d109 bne.n 80042e2 { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 80042ce: 687b ldr r3, [r7, #4] 80042d0: 6818 ldr r0, [r3, #0] 80042d2: 687b ldr r3, [r7, #4] 80042d4: f203 439c addw r3, r3, #1180 @ 0x49c 80042d8: 461a mov r2, r3 80042da: 2101 movs r1, #1 80042dc: f004 ffaa bl 8009234 80042e0: e006 b.n 80042f0 } else { ep->xfer_buff += ep->xfer_count; 80042e2: 68fb ldr r3, [r7, #12] 80042e4: 68da ldr r2, [r3, #12] 80042e6: 68fb ldr r3, [r7, #12] 80042e8: 695b ldr r3, [r3, #20] 80042ea: 441a add r2, r3 80042ec: 68fb ldr r3, [r7, #12] 80042ee: 60da str r2, [r3, #12] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 80042f0: 683b ldr r3, [r7, #0] 80042f2: b2db uxtb r3, r3 80042f4: 4619 mov r1, r3 80042f6: 6878 ldr r0, [r7, #4] 80042f8: f006 ff78 bl 800b1ec 80042fc: e046 b.n 800438c /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 80042fe: 697b ldr r3, [r7, #20] 8004300: 4a26 ldr r2, [pc, #152] @ (800439c ) 8004302: 4293 cmp r3, r2 8004304: d124 bne.n 8004350 { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8004306: 693b ldr r3, [r7, #16] 8004308: f403 4300 and.w r3, r3, #32768 @ 0x8000 800430c: 2b00 cmp r3, #0 800430e: d00a beq.n 8004326 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8004310: 683b ldr r3, [r7, #0] 8004312: 015a lsls r2, r3, #5 8004314: 69bb ldr r3, [r7, #24] 8004316: 4413 add r3, r2 8004318: f503 6330 add.w r3, r3, #2816 @ 0xb00 800431c: 461a mov r2, r3 800431e: f44f 4300 mov.w r3, #32768 @ 0x8000 8004322: 6093 str r3, [r2, #8] 8004324: e032 b.n 800438c } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8004326: 693b ldr r3, [r7, #16] 8004328: f003 0320 and.w r3, r3, #32 800432c: 2b00 cmp r3, #0 800432e: d008 beq.n 8004342 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8004330: 683b ldr r3, [r7, #0] 8004332: 015a lsls r2, r3, #5 8004334: 69bb ldr r3, [r7, #24] 8004336: 4413 add r3, r2 8004338: f503 6330 add.w r3, r3, #2816 @ 0xb00 800433c: 461a mov r2, r3 800433e: 2320 movs r3, #32 8004340: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8004342: 683b ldr r3, [r7, #0] 8004344: b2db uxtb r3, r3 8004346: 4619 mov r1, r3 8004348: 6878 ldr r0, [r7, #4] 800434a: f006 ff4f bl 800b1ec 800434e: e01d b.n 800438c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8004350: 683b ldr r3, [r7, #0] 8004352: 2b00 cmp r3, #0 8004354: d114 bne.n 8004380 8004356: 6879 ldr r1, [r7, #4] 8004358: 683a ldr r2, [r7, #0] 800435a: 4613 mov r3, r2 800435c: 00db lsls r3, r3, #3 800435e: 4413 add r3, r2 8004360: 009b lsls r3, r3, #2 8004362: 440b add r3, r1 8004364: f503 7319 add.w r3, r3, #612 @ 0x264 8004368: 681b ldr r3, [r3, #0] 800436a: 2b00 cmp r3, #0 800436c: d108 bne.n 8004380 { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 800436e: 687b ldr r3, [r7, #4] 8004370: 6818 ldr r0, [r3, #0] 8004372: 687b ldr r3, [r7, #4] 8004374: f203 439c addw r3, r3, #1180 @ 0x49c 8004378: 461a mov r2, r3 800437a: 2100 movs r1, #0 800437c: f004 ff5a bl 8009234 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8004380: 683b ldr r3, [r7, #0] 8004382: b2db uxtb r3, r3 8004384: 4619 mov r1, r3 8004386: 6878 ldr r0, [r7, #4] 8004388: f006 ff30 bl 800b1ec #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 800438c: 2300 movs r3, #0 } 800438e: 4618 mov r0, r3 8004390: 3720 adds r7, #32 8004392: 46bd mov sp, r7 8004394: bd80 pop {r7, pc} 8004396: bf00 nop 8004398: 4f54300a .word 0x4f54300a 800439c: 4f54310a .word 0x4f54310a 080043a0 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 80043a0: b580 push {r7, lr} 80043a2: b086 sub sp, #24 80043a4: af00 add r7, sp, #0 80043a6: 6078 str r0, [r7, #4] 80043a8: 6039 str r1, [r7, #0] const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80043aa: 687b ldr r3, [r7, #4] 80043ac: 681b ldr r3, [r3, #0] 80043ae: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 80043b0: 697b ldr r3, [r7, #20] 80043b2: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 80043b4: 697b ldr r3, [r7, #20] 80043b6: 333c adds r3, #60 @ 0x3c 80043b8: 3304 adds r3, #4 80043ba: 681b ldr r3, [r3, #0] 80043bc: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 80043be: 683b ldr r3, [r7, #0] 80043c0: 015a lsls r2, r3, #5 80043c2: 693b ldr r3, [r7, #16] 80043c4: 4413 add r3, r2 80043c6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80043ca: 689b ldr r3, [r3, #8] 80043cc: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 80043ce: 68fb ldr r3, [r7, #12] 80043d0: 4a15 ldr r2, [pc, #84] @ (8004428 ) 80043d2: 4293 cmp r3, r2 80043d4: d90e bls.n 80043f4 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 80043d6: 68bb ldr r3, [r7, #8] 80043d8: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 80043dc: 2b00 cmp r3, #0 80043de: d009 beq.n 80043f4 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 80043e0: 683b ldr r3, [r7, #0] 80043e2: 015a lsls r2, r3, #5 80043e4: 693b ldr r3, [r7, #16] 80043e6: 4413 add r3, r2 80043e8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80043ec: 461a mov r2, r3 80043ee: f44f 4300 mov.w r3, #32768 @ 0x8000 80043f2: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 80043f4: 6878 ldr r0, [r7, #4] 80043f6: f006 fee7 bl 800b1c8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 80043fa: 68fb ldr r3, [r7, #12] 80043fc: 4a0a ldr r2, [pc, #40] @ (8004428 ) 80043fe: 4293 cmp r3, r2 8004400: d90c bls.n 800441c 8004402: 687b ldr r3, [r7, #4] 8004404: 799b ldrb r3, [r3, #6] 8004406: 2b01 cmp r3, #1 8004408: d108 bne.n 800441c { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 800440a: 687b ldr r3, [r7, #4] 800440c: 6818 ldr r0, [r3, #0] 800440e: 687b ldr r3, [r7, #4] 8004410: f203 439c addw r3, r3, #1180 @ 0x49c 8004414: 461a mov r2, r3 8004416: 2101 movs r1, #1 8004418: f004 ff0c bl 8009234 } return HAL_OK; 800441c: 2300 movs r3, #0 } 800441e: 4618 mov r0, r3 8004420: 3718 adds r7, #24 8004422: 46bd mov sp, r7 8004424: bd80 pop {r7, pc} 8004426: bf00 nop 8004428: 4f54300a .word 0x4f54300a 0800442c : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 800442c: b480 push {r7} 800442e: b085 sub sp, #20 8004430: af00 add r7, sp, #0 8004432: 6078 str r0, [r7, #4] 8004434: 460b mov r3, r1 8004436: 70fb strb r3, [r7, #3] 8004438: 4613 mov r3, r2 800443a: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 800443c: 687b ldr r3, [r7, #4] 800443e: 681b ldr r3, [r3, #0] 8004440: 6a5b ldr r3, [r3, #36] @ 0x24 8004442: 60bb str r3, [r7, #8] if (fifo == 0U) 8004444: 78fb ldrb r3, [r7, #3] 8004446: 2b00 cmp r3, #0 8004448: d107 bne.n 800445a { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 800444a: 883b ldrh r3, [r7, #0] 800444c: 0419 lsls r1, r3, #16 800444e: 687b ldr r3, [r7, #4] 8004450: 681b ldr r3, [r3, #0] 8004452: 68ba ldr r2, [r7, #8] 8004454: 430a orrs r2, r1 8004456: 629a str r2, [r3, #40] @ 0x28 8004458: e028 b.n 80044ac } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 800445a: 687b ldr r3, [r7, #4] 800445c: 681b ldr r3, [r3, #0] 800445e: 6a9b ldr r3, [r3, #40] @ 0x28 8004460: 0c1b lsrs r3, r3, #16 8004462: 68ba ldr r2, [r7, #8] 8004464: 4413 add r3, r2 8004466: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8004468: 2300 movs r3, #0 800446a: 73fb strb r3, [r7, #15] 800446c: e00d b.n 800448a { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 800446e: 687b ldr r3, [r7, #4] 8004470: 681a ldr r2, [r3, #0] 8004472: 7bfb ldrb r3, [r7, #15] 8004474: 3340 adds r3, #64 @ 0x40 8004476: 009b lsls r3, r3, #2 8004478: 4413 add r3, r2 800447a: 685b ldr r3, [r3, #4] 800447c: 0c1b lsrs r3, r3, #16 800447e: 68ba ldr r2, [r7, #8] 8004480: 4413 add r3, r2 8004482: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8004484: 7bfb ldrb r3, [r7, #15] 8004486: 3301 adds r3, #1 8004488: 73fb strb r3, [r7, #15] 800448a: 7bfa ldrb r2, [r7, #15] 800448c: 78fb ldrb r3, [r7, #3] 800448e: 3b01 subs r3, #1 8004490: 429a cmp r2, r3 8004492: d3ec bcc.n 800446e } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 8004494: 883b ldrh r3, [r7, #0] 8004496: 0418 lsls r0, r3, #16 8004498: 687b ldr r3, [r7, #4] 800449a: 6819 ldr r1, [r3, #0] 800449c: 78fb ldrb r3, [r7, #3] 800449e: 3b01 subs r3, #1 80044a0: 68ba ldr r2, [r7, #8] 80044a2: 4302 orrs r2, r0 80044a4: 3340 adds r3, #64 @ 0x40 80044a6: 009b lsls r3, r3, #2 80044a8: 440b add r3, r1 80044aa: 605a str r2, [r3, #4] } return HAL_OK; 80044ac: 2300 movs r3, #0 } 80044ae: 4618 mov r0, r3 80044b0: 3714 adds r7, #20 80044b2: 46bd mov sp, r7 80044b4: f85d 7b04 ldr.w r7, [sp], #4 80044b8: 4770 bx lr 080044ba : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 80044ba: b480 push {r7} 80044bc: b083 sub sp, #12 80044be: af00 add r7, sp, #0 80044c0: 6078 str r0, [r7, #4] 80044c2: 460b mov r3, r1 80044c4: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 80044c6: 687b ldr r3, [r7, #4] 80044c8: 681b ldr r3, [r3, #0] 80044ca: 887a ldrh r2, [r7, #2] 80044cc: 625a str r2, [r3, #36] @ 0x24 return HAL_OK; 80044ce: 2300 movs r3, #0 } 80044d0: 4618 mov r0, r3 80044d2: 370c adds r7, #12 80044d4: 46bd mov sp, r7 80044d6: f85d 7b04 ldr.w r7, [sp], #4 80044da: 4770 bx lr 080044dc : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 80044dc: b480 push {r7} 80044de: b085 sub sp, #20 80044e0: af00 add r7, sp, #0 80044e2: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80044e4: 687b ldr r3, [r7, #4] 80044e6: 681b ldr r3, [r3, #0] 80044e8: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 80044ea: 687b ldr r3, [r7, #4] 80044ec: 2201 movs r2, #1 80044ee: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 80044f2: 687b ldr r3, [r7, #4] 80044f4: 2200 movs r2, #0 80044f6: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 80044fa: 68fb ldr r3, [r7, #12] 80044fc: 699b ldr r3, [r3, #24] 80044fe: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 8004502: 68fb ldr r3, [r7, #12] 8004504: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 8004506: 68fb ldr r3, [r7, #12] 8004508: 6d5b ldr r3, [r3, #84] @ 0x54 800450a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800450e: f043 0303 orr.w r3, r3, #3 8004512: 68fa ldr r2, [r7, #12] 8004514: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 8004516: 2300 movs r3, #0 } 8004518: 4618 mov r0, r3 800451a: 3714 adds r7, #20 800451c: 46bd mov sp, r7 800451e: f85d 7b04 ldr.w r7, [sp], #4 8004522: 4770 bx lr 08004524 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8004524: b580 push {r7, lr} 8004526: b084 sub sp, #16 8004528: af00 add r7, sp, #0 800452a: 6078 str r0, [r7, #4] 800452c: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800452e: 687b ldr r3, [r7, #4] 8004530: 2b00 cmp r3, #0 8004532: d101 bne.n 8004538 { return HAL_ERROR; 8004534: 2301 movs r3, #1 8004536: e0cc b.n 80046d2 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004538: 4b68 ldr r3, [pc, #416] @ (80046dc ) 800453a: 681b ldr r3, [r3, #0] 800453c: f003 030f and.w r3, r3, #15 8004540: 683a ldr r2, [r7, #0] 8004542: 429a cmp r2, r3 8004544: d90c bls.n 8004560 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004546: 4b65 ldr r3, [pc, #404] @ (80046dc ) 8004548: 683a ldr r2, [r7, #0] 800454a: b2d2 uxtb r2, r2 800454c: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800454e: 4b63 ldr r3, [pc, #396] @ (80046dc ) 8004550: 681b ldr r3, [r3, #0] 8004552: f003 030f and.w r3, r3, #15 8004556: 683a ldr r2, [r7, #0] 8004558: 429a cmp r2, r3 800455a: d001 beq.n 8004560 { return HAL_ERROR; 800455c: 2301 movs r3, #1 800455e: e0b8 b.n 80046d2 } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8004560: 687b ldr r3, [r7, #4] 8004562: 681b ldr r3, [r3, #0] 8004564: f003 0302 and.w r3, r3, #2 8004568: 2b00 cmp r3, #0 800456a: d020 beq.n 80045ae { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800456c: 687b ldr r3, [r7, #4] 800456e: 681b ldr r3, [r3, #0] 8004570: f003 0304 and.w r3, r3, #4 8004574: 2b00 cmp r3, #0 8004576: d005 beq.n 8004584 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004578: 4b59 ldr r3, [pc, #356] @ (80046e0 ) 800457a: 689b ldr r3, [r3, #8] 800457c: 4a58 ldr r2, [pc, #352] @ (80046e0 ) 800457e: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 8004582: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004584: 687b ldr r3, [r7, #4] 8004586: 681b ldr r3, [r3, #0] 8004588: f003 0308 and.w r3, r3, #8 800458c: 2b00 cmp r3, #0 800458e: d005 beq.n 800459c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8004590: 4b53 ldr r3, [pc, #332] @ (80046e0 ) 8004592: 689b ldr r3, [r3, #8] 8004594: 4a52 ldr r2, [pc, #328] @ (80046e0 ) 8004596: f443 4360 orr.w r3, r3, #57344 @ 0xe000 800459a: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800459c: 4b50 ldr r3, [pc, #320] @ (80046e0 ) 800459e: 689b ldr r3, [r3, #8] 80045a0: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80045a4: 687b ldr r3, [r7, #4] 80045a6: 689b ldr r3, [r3, #8] 80045a8: 494d ldr r1, [pc, #308] @ (80046e0 ) 80045aa: 4313 orrs r3, r2 80045ac: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80045ae: 687b ldr r3, [r7, #4] 80045b0: 681b ldr r3, [r3, #0] 80045b2: f003 0301 and.w r3, r3, #1 80045b6: 2b00 cmp r3, #0 80045b8: d044 beq.n 8004644 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80045ba: 687b ldr r3, [r7, #4] 80045bc: 685b ldr r3, [r3, #4] 80045be: 2b01 cmp r3, #1 80045c0: d107 bne.n 80045d2 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80045c2: 4b47 ldr r3, [pc, #284] @ (80046e0 ) 80045c4: 681b ldr r3, [r3, #0] 80045c6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80045ca: 2b00 cmp r3, #0 80045cc: d119 bne.n 8004602 { return HAL_ERROR; 80045ce: 2301 movs r3, #1 80045d0: e07f b.n 80046d2 } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80045d2: 687b ldr r3, [r7, #4] 80045d4: 685b ldr r3, [r3, #4] 80045d6: 2b02 cmp r3, #2 80045d8: d003 beq.n 80045e2 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 80045da: 687b ldr r3, [r7, #4] 80045dc: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80045de: 2b03 cmp r3, #3 80045e0: d107 bne.n 80045f2 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80045e2: 4b3f ldr r3, [pc, #252] @ (80046e0 ) 80045e4: 681b ldr r3, [r3, #0] 80045e6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80045ea: 2b00 cmp r3, #0 80045ec: d109 bne.n 8004602 { return HAL_ERROR; 80045ee: 2301 movs r3, #1 80045f0: e06f b.n 80046d2 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80045f2: 4b3b ldr r3, [pc, #236] @ (80046e0 ) 80045f4: 681b ldr r3, [r3, #0] 80045f6: f003 0302 and.w r3, r3, #2 80045fa: 2b00 cmp r3, #0 80045fc: d101 bne.n 8004602 { return HAL_ERROR; 80045fe: 2301 movs r3, #1 8004600: e067 b.n 80046d2 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8004602: 4b37 ldr r3, [pc, #220] @ (80046e0 ) 8004604: 689b ldr r3, [r3, #8] 8004606: f023 0203 bic.w r2, r3, #3 800460a: 687b ldr r3, [r7, #4] 800460c: 685b ldr r3, [r3, #4] 800460e: 4934 ldr r1, [pc, #208] @ (80046e0 ) 8004610: 4313 orrs r3, r2 8004612: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004614: f7fd fcb2 bl 8001f7c 8004618: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800461a: e00a b.n 8004632 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800461c: f7fd fcae bl 8001f7c 8004620: 4602 mov r2, r0 8004622: 68fb ldr r3, [r7, #12] 8004624: 1ad3 subs r3, r2, r3 8004626: f241 3288 movw r2, #5000 @ 0x1388 800462a: 4293 cmp r3, r2 800462c: d901 bls.n 8004632 { return HAL_TIMEOUT; 800462e: 2303 movs r3, #3 8004630: e04f b.n 80046d2 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004632: 4b2b ldr r3, [pc, #172] @ (80046e0 ) 8004634: 689b ldr r3, [r3, #8] 8004636: f003 020c and.w r2, r3, #12 800463a: 687b ldr r3, [r7, #4] 800463c: 685b ldr r3, [r3, #4] 800463e: 009b lsls r3, r3, #2 8004640: 429a cmp r2, r3 8004642: d1eb bne.n 800461c } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004644: 4b25 ldr r3, [pc, #148] @ (80046dc ) 8004646: 681b ldr r3, [r3, #0] 8004648: f003 030f and.w r3, r3, #15 800464c: 683a ldr r2, [r7, #0] 800464e: 429a cmp r2, r3 8004650: d20c bcs.n 800466c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004652: 4b22 ldr r3, [pc, #136] @ (80046dc ) 8004654: 683a ldr r2, [r7, #0] 8004656: b2d2 uxtb r2, r2 8004658: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800465a: 4b20 ldr r3, [pc, #128] @ (80046dc ) 800465c: 681b ldr r3, [r3, #0] 800465e: f003 030f and.w r3, r3, #15 8004662: 683a ldr r2, [r7, #0] 8004664: 429a cmp r2, r3 8004666: d001 beq.n 800466c { return HAL_ERROR; 8004668: 2301 movs r3, #1 800466a: e032 b.n 80046d2 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800466c: 687b ldr r3, [r7, #4] 800466e: 681b ldr r3, [r3, #0] 8004670: f003 0304 and.w r3, r3, #4 8004674: 2b00 cmp r3, #0 8004676: d008 beq.n 800468a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004678: 4b19 ldr r3, [pc, #100] @ (80046e0 ) 800467a: 689b ldr r3, [r3, #8] 800467c: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 8004680: 687b ldr r3, [r7, #4] 8004682: 68db ldr r3, [r3, #12] 8004684: 4916 ldr r1, [pc, #88] @ (80046e0 ) 8004686: 4313 orrs r3, r2 8004688: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800468a: 687b ldr r3, [r7, #4] 800468c: 681b ldr r3, [r3, #0] 800468e: f003 0308 and.w r3, r3, #8 8004692: 2b00 cmp r3, #0 8004694: d009 beq.n 80046aa { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8004696: 4b12 ldr r3, [pc, #72] @ (80046e0 ) 8004698: 689b ldr r3, [r3, #8] 800469a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 800469e: 687b ldr r3, [r7, #4] 80046a0: 691b ldr r3, [r3, #16] 80046a2: 00db lsls r3, r3, #3 80046a4: 490e ldr r1, [pc, #56] @ (80046e0 ) 80046a6: 4313 orrs r3, r2 80046a8: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80046aa: f000 fb7f bl 8004dac 80046ae: 4602 mov r2, r0 80046b0: 4b0b ldr r3, [pc, #44] @ (80046e0 ) 80046b2: 689b ldr r3, [r3, #8] 80046b4: 091b lsrs r3, r3, #4 80046b6: f003 030f and.w r3, r3, #15 80046ba: 490a ldr r1, [pc, #40] @ (80046e4 ) 80046bc: 5ccb ldrb r3, [r1, r3] 80046be: fa22 f303 lsr.w r3, r2, r3 80046c2: 4a09 ldr r2, [pc, #36] @ (80046e8 ) 80046c4: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 80046c6: 4b09 ldr r3, [pc, #36] @ (80046ec ) 80046c8: 681b ldr r3, [r3, #0] 80046ca: 4618 mov r0, r3 80046cc: f7fd fc12 bl 8001ef4 return HAL_OK; 80046d0: 2300 movs r3, #0 } 80046d2: 4618 mov r0, r3 80046d4: 3710 adds r7, #16 80046d6: 46bd mov sp, r7 80046d8: bd80 pop {r7, pc} 80046da: bf00 nop 80046dc: 40023c00 .word 0x40023c00 80046e0: 40023800 .word 0x40023800 80046e4: 0800b888 .word 0x0800b888 80046e8: 20000090 .word 0x20000090 80046ec: 20000094 .word 0x20000094 080046f0 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80046f0: b480 push {r7} 80046f2: af00 add r7, sp, #0 return SystemCoreClock; 80046f4: 4b03 ldr r3, [pc, #12] @ (8004704 ) 80046f6: 681b ldr r3, [r3, #0] } 80046f8: 4618 mov r0, r3 80046fa: 46bd mov sp, r7 80046fc: f85d 7b04 ldr.w r7, [sp], #4 8004700: 4770 bx lr 8004702: bf00 nop 8004704: 20000090 .word 0x20000090 08004708 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8004708: b580 push {r7, lr} 800470a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 800470c: f7ff fff0 bl 80046f0 8004710: 4602 mov r2, r0 8004712: 4b05 ldr r3, [pc, #20] @ (8004728 ) 8004714: 689b ldr r3, [r3, #8] 8004716: 0a9b lsrs r3, r3, #10 8004718: f003 0307 and.w r3, r3, #7 800471c: 4903 ldr r1, [pc, #12] @ (800472c ) 800471e: 5ccb ldrb r3, [r1, r3] 8004720: fa22 f303 lsr.w r3, r2, r3 } 8004724: 4618 mov r0, r3 8004726: bd80 pop {r7, pc} 8004728: 40023800 .word 0x40023800 800472c: 0800b898 .word 0x0800b898 08004730 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8004730: b580 push {r7, lr} 8004732: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8004734: f7ff ffdc bl 80046f0 8004738: 4602 mov r2, r0 800473a: 4b05 ldr r3, [pc, #20] @ (8004750 ) 800473c: 689b ldr r3, [r3, #8] 800473e: 0b5b lsrs r3, r3, #13 8004740: f003 0307 and.w r3, r3, #7 8004744: 4903 ldr r1, [pc, #12] @ (8004754 ) 8004746: 5ccb ldrb r3, [r1, r3] 8004748: fa22 f303 lsr.w r3, r2, r3 } 800474c: 4618 mov r0, r3 800474e: bd80 pop {r7, pc} 8004750: 40023800 .word 0x40023800 8004754: 0800b898 .word 0x0800b898 08004758 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004758: b580 push {r7, lr} 800475a: b08c sub sp, #48 @ 0x30 800475c: af00 add r7, sp, #0 800475e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8004760: 2300 movs r3, #0 8004762: 627b str r3, [r7, #36] @ 0x24 uint32_t tmpreg1 = 0U; 8004764: 2300 movs r3, #0 8004766: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 8004768: 2300 movs r3, #0 800476a: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 800476c: 2300 movs r3, #0 800476e: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 8004770: 2300 movs r3, #0 8004772: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 8004774: 2300 movs r3, #0 8004776: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 8004778: 2300 movs r3, #0 800477a: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 800477c: 2300 movs r3, #0 800477e: 62fb str r3, [r7, #44] @ 0x2c uint32_t pllsaiused = 0U; 8004780: 2300 movs r3, #0 8004782: 62bb str r3, [r7, #40] @ 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 8004784: 687b ldr r3, [r7, #4] 8004786: 681b ldr r3, [r3, #0] 8004788: f003 0301 and.w r3, r3, #1 800478c: 2b00 cmp r3, #0 800478e: d010 beq.n 80047b2 { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 8004790: 4b6f ldr r3, [pc, #444] @ (8004950 ) 8004792: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004796: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 800479a: 687b ldr r3, [r7, #4] 800479c: 6b9b ldr r3, [r3, #56] @ 0x38 800479e: 496c ldr r1, [pc, #432] @ (8004950 ) 80047a0: 4313 orrs r3, r2 80047a2: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 80047a6: 687b ldr r3, [r7, #4] 80047a8: 6b9b ldr r3, [r3, #56] @ 0x38 80047aa: 2b00 cmp r3, #0 80047ac: d101 bne.n 80047b2 { plli2sused = 1U; 80047ae: 2301 movs r3, #1 80047b0: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 80047b2: 687b ldr r3, [r7, #4] 80047b4: 681b ldr r3, [r3, #0] 80047b6: f003 0302 and.w r3, r3, #2 80047ba: 2b00 cmp r3, #0 80047bc: d010 beq.n 80047e0 { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 80047be: 4b64 ldr r3, [pc, #400] @ (8004950 ) 80047c0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80047c4: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 80047c8: 687b ldr r3, [r7, #4] 80047ca: 6bdb ldr r3, [r3, #60] @ 0x3c 80047cc: 4960 ldr r1, [pc, #384] @ (8004950 ) 80047ce: 4313 orrs r3, r2 80047d0: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 80047d4: 687b ldr r3, [r7, #4] 80047d6: 6bdb ldr r3, [r3, #60] @ 0x3c 80047d8: 2b00 cmp r3, #0 80047da: d101 bne.n 80047e0 { plli2sused = 1U; 80047dc: 2301 movs r3, #1 80047de: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 80047e0: 687b ldr r3, [r7, #4] 80047e2: 681b ldr r3, [r3, #0] 80047e4: f003 0304 and.w r3, r3, #4 80047e8: 2b00 cmp r3, #0 80047ea: d017 beq.n 800481c { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80047ec: 4b58 ldr r3, [pc, #352] @ (8004950 ) 80047ee: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80047f2: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 80047f6: 687b ldr r3, [r7, #4] 80047f8: 6b1b ldr r3, [r3, #48] @ 0x30 80047fa: 4955 ldr r1, [pc, #340] @ (8004950 ) 80047fc: 4313 orrs r3, r2 80047fe: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 8004802: 687b ldr r3, [r7, #4] 8004804: 6b1b ldr r3, [r3, #48] @ 0x30 8004806: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800480a: d101 bne.n 8004810 { plli2sused = 1U; 800480c: 2301 movs r3, #1 800480e: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 8004810: 687b ldr r3, [r7, #4] 8004812: 6b1b ldr r3, [r3, #48] @ 0x30 8004814: 2b00 cmp r3, #0 8004816: d101 bne.n 800481c { pllsaiused = 1U; 8004818: 2301 movs r3, #1 800481a: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 800481c: 687b ldr r3, [r7, #4] 800481e: 681b ldr r3, [r3, #0] 8004820: f003 0308 and.w r3, r3, #8 8004824: 2b00 cmp r3, #0 8004826: d017 beq.n 8004858 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 8004828: 4b49 ldr r3, [pc, #292] @ (8004950 ) 800482a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800482e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 8004832: 687b ldr r3, [r7, #4] 8004834: 6b5b ldr r3, [r3, #52] @ 0x34 8004836: 4946 ldr r1, [pc, #280] @ (8004950 ) 8004838: 4313 orrs r3, r2 800483a: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 800483e: 687b ldr r3, [r7, #4] 8004840: 6b5b ldr r3, [r3, #52] @ 0x34 8004842: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004846: d101 bne.n 800484c { plli2sused = 1U; 8004848: 2301 movs r3, #1 800484a: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 800484c: 687b ldr r3, [r7, #4] 800484e: 6b5b ldr r3, [r3, #52] @ 0x34 8004850: 2b00 cmp r3, #0 8004852: d101 bne.n 8004858 { pllsaiused = 1U; 8004854: 2301 movs r3, #1 8004856: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8004858: 687b ldr r3, [r7, #4] 800485a: 681b ldr r3, [r3, #0] 800485c: f003 0320 and.w r3, r3, #32 8004860: 2b00 cmp r3, #0 8004862: f000 808a beq.w 800497a { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 8004866: 2300 movs r3, #0 8004868: 60bb str r3, [r7, #8] 800486a: 4b39 ldr r3, [pc, #228] @ (8004950 ) 800486c: 6c1b ldr r3, [r3, #64] @ 0x40 800486e: 4a38 ldr r2, [pc, #224] @ (8004950 ) 8004870: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004874: 6413 str r3, [r2, #64] @ 0x40 8004876: 4b36 ldr r3, [pc, #216] @ (8004950 ) 8004878: 6c1b ldr r3, [r3, #64] @ 0x40 800487a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800487e: 60bb str r3, [r7, #8] 8004880: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 8004882: 4b34 ldr r3, [pc, #208] @ (8004954 ) 8004884: 681b ldr r3, [r3, #0] 8004886: 4a33 ldr r2, [pc, #204] @ (8004954 ) 8004888: f443 7380 orr.w r3, r3, #256 @ 0x100 800488c: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 800488e: f7fd fb75 bl 8001f7c 8004892: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004894: e008 b.n 80048a8 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004896: f7fd fb71 bl 8001f7c 800489a: 4602 mov r2, r0 800489c: 6a7b ldr r3, [r7, #36] @ 0x24 800489e: 1ad3 subs r3, r2, r3 80048a0: 2b02 cmp r3, #2 80048a2: d901 bls.n 80048a8 { return HAL_TIMEOUT; 80048a4: 2303 movs r3, #3 80048a6: e278 b.n 8004d9a while ((PWR->CR & PWR_CR_DBP) == RESET) 80048a8: 4b2a ldr r3, [pc, #168] @ (8004954 ) 80048aa: 681b ldr r3, [r3, #0] 80048ac: f403 7380 and.w r3, r3, #256 @ 0x100 80048b0: 2b00 cmp r3, #0 80048b2: d0f0 beq.n 8004896 } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 80048b4: 4b26 ldr r3, [pc, #152] @ (8004950 ) 80048b6: 6f1b ldr r3, [r3, #112] @ 0x70 80048b8: f403 7340 and.w r3, r3, #768 @ 0x300 80048bc: 623b str r3, [r7, #32] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 80048be: 6a3b ldr r3, [r7, #32] 80048c0: 2b00 cmp r3, #0 80048c2: d02f beq.n 8004924 80048c4: 687b ldr r3, [r7, #4] 80048c6: 6c1b ldr r3, [r3, #64] @ 0x40 80048c8: f403 7340 and.w r3, r3, #768 @ 0x300 80048cc: 6a3a ldr r2, [r7, #32] 80048ce: 429a cmp r2, r3 80048d0: d028 beq.n 8004924 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80048d2: 4b1f ldr r3, [pc, #124] @ (8004950 ) 80048d4: 6f1b ldr r3, [r3, #112] @ 0x70 80048d6: f423 7340 bic.w r3, r3, #768 @ 0x300 80048da: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80048dc: 4b1e ldr r3, [pc, #120] @ (8004958 ) 80048de: 2201 movs r2, #1 80048e0: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 80048e2: 4b1d ldr r3, [pc, #116] @ (8004958 ) 80048e4: 2200 movs r2, #0 80048e6: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 80048e8: 4a19 ldr r2, [pc, #100] @ (8004950 ) 80048ea: 6a3b ldr r3, [r7, #32] 80048ec: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 80048ee: 4b18 ldr r3, [pc, #96] @ (8004950 ) 80048f0: 6f1b ldr r3, [r3, #112] @ 0x70 80048f2: f003 0301 and.w r3, r3, #1 80048f6: 2b01 cmp r3, #1 80048f8: d114 bne.n 8004924 { /* Get tick */ tickstart = HAL_GetTick(); 80048fa: f7fd fb3f bl 8001f7c 80048fe: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004900: e00a b.n 8004918 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004902: f7fd fb3b bl 8001f7c 8004906: 4602 mov r2, r0 8004908: 6a7b ldr r3, [r7, #36] @ 0x24 800490a: 1ad3 subs r3, r2, r3 800490c: f241 3288 movw r2, #5000 @ 0x1388 8004910: 4293 cmp r3, r2 8004912: d901 bls.n 8004918 { return HAL_TIMEOUT; 8004914: 2303 movs r3, #3 8004916: e240 b.n 8004d9a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004918: 4b0d ldr r3, [pc, #52] @ (8004950 ) 800491a: 6f1b ldr r3, [r3, #112] @ 0x70 800491c: f003 0302 and.w r3, r3, #2 8004920: 2b00 cmp r3, #0 8004922: d0ee beq.n 8004902 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8004924: 687b ldr r3, [r7, #4] 8004926: 6c1b ldr r3, [r3, #64] @ 0x40 8004928: f403 7340 and.w r3, r3, #768 @ 0x300 800492c: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004930: d114 bne.n 800495c 8004932: 4b07 ldr r3, [pc, #28] @ (8004950 ) 8004934: 689b ldr r3, [r3, #8] 8004936: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 800493a: 687b ldr r3, [r7, #4] 800493c: 6c1b ldr r3, [r3, #64] @ 0x40 800493e: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 8004942: f423 7340 bic.w r3, r3, #768 @ 0x300 8004946: 4902 ldr r1, [pc, #8] @ (8004950 ) 8004948: 4313 orrs r3, r2 800494a: 608b str r3, [r1, #8] 800494c: e00c b.n 8004968 800494e: bf00 nop 8004950: 40023800 .word 0x40023800 8004954: 40007000 .word 0x40007000 8004958: 42470e40 .word 0x42470e40 800495c: 4b4a ldr r3, [pc, #296] @ (8004a88 ) 800495e: 689b ldr r3, [r3, #8] 8004960: 4a49 ldr r2, [pc, #292] @ (8004a88 ) 8004962: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 8004966: 6093 str r3, [r2, #8] 8004968: 4b47 ldr r3, [pc, #284] @ (8004a88 ) 800496a: 6f1a ldr r2, [r3, #112] @ 0x70 800496c: 687b ldr r3, [r7, #4] 800496e: 6c1b ldr r3, [r3, #64] @ 0x40 8004970: f3c3 030b ubfx r3, r3, #0, #12 8004974: 4944 ldr r1, [pc, #272] @ (8004a88 ) 8004976: 4313 orrs r3, r2 8004978: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 800497a: 687b ldr r3, [r7, #4] 800497c: 681b ldr r3, [r3, #0] 800497e: f003 0310 and.w r3, r3, #16 8004982: 2b00 cmp r3, #0 8004984: d004 beq.n 8004990 { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8004986: 687b ldr r3, [r7, #4] 8004988: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 800498c: 4b3f ldr r3, [pc, #252] @ (8004a8c ) 800498e: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 8004990: 687b ldr r3, [r7, #4] 8004992: 681b ldr r3, [r3, #0] 8004994: f003 0380 and.w r3, r3, #128 @ 0x80 8004998: 2b00 cmp r3, #0 800499a: d00a beq.n 80049b2 { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 800499c: 4b3a ldr r3, [pc, #232] @ (8004a88 ) 800499e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80049a2: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80049a6: 687b ldr r3, [r7, #4] 80049a8: 6cdb ldr r3, [r3, #76] @ 0x4c 80049aa: 4937 ldr r1, [pc, #220] @ (8004a88 ) 80049ac: 4313 orrs r3, r2 80049ae: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80049b2: 687b ldr r3, [r7, #4] 80049b4: 681b ldr r3, [r3, #0] 80049b6: f003 0340 and.w r3, r3, #64 @ 0x40 80049ba: 2b00 cmp r3, #0 80049bc: d00a beq.n 80049d4 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 80049be: 4b32 ldr r3, [pc, #200] @ (8004a88 ) 80049c0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80049c4: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 80049c8: 687b ldr r3, [r7, #4] 80049ca: 6c9b ldr r3, [r3, #72] @ 0x48 80049cc: 492e ldr r1, [pc, #184] @ (8004a88 ) 80049ce: 4313 orrs r3, r2 80049d0: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 80049d4: 687b ldr r3, [r7, #4] 80049d6: 681b ldr r3, [r3, #0] 80049d8: f403 7380 and.w r3, r3, #256 @ 0x100 80049dc: 2b00 cmp r3, #0 80049de: d011 beq.n 8004a04 { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 80049e0: 4b29 ldr r3, [pc, #164] @ (8004a88 ) 80049e2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80049e6: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 80049ea: 687b ldr r3, [r7, #4] 80049ec: 6d5b ldr r3, [r3, #84] @ 0x54 80049ee: 4926 ldr r1, [pc, #152] @ (8004a88 ) 80049f0: 4313 orrs r3, r2 80049f2: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 80049f6: 687b ldr r3, [r7, #4] 80049f8: 6d5b ldr r3, [r3, #84] @ 0x54 80049fa: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80049fe: d101 bne.n 8004a04 { pllsaiused = 1U; 8004a00: 2301 movs r3, #1 8004a02: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 8004a04: 687b ldr r3, [r7, #4] 8004a06: 681b ldr r3, [r3, #0] 8004a08: f403 7300 and.w r3, r3, #512 @ 0x200 8004a0c: 2b00 cmp r3, #0 8004a0e: d00a beq.n 8004a26 { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 8004a10: 4b1d ldr r3, [pc, #116] @ (8004a88 ) 8004a12: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004a16: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 8004a1a: 687b ldr r3, [r7, #4] 8004a1c: 6c5b ldr r3, [r3, #68] @ 0x44 8004a1e: 491a ldr r1, [pc, #104] @ (8004a88 ) 8004a20: 4313 orrs r3, r2 8004a22: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004a26: 687b ldr r3, [r7, #4] 8004a28: 681b ldr r3, [r3, #0] 8004a2a: f403 6380 and.w r3, r3, #1024 @ 0x400 8004a2e: 2b00 cmp r3, #0 8004a30: d011 beq.n 8004a56 { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 8004a32: 4b15 ldr r3, [pc, #84] @ (8004a88 ) 8004a34: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004a38: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 8004a3c: 687b ldr r3, [r7, #4] 8004a3e: 6d1b ldr r3, [r3, #80] @ 0x50 8004a40: 4911 ldr r1, [pc, #68] @ (8004a88 ) 8004a42: 4313 orrs r3, r2 8004a44: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 8004a48: 687b ldr r3, [r7, #4] 8004a4a: 6d1b ldr r3, [r3, #80] @ 0x50 8004a4c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004a50: d101 bne.n 8004a56 { plli2sused = 1U; 8004a52: 2301 movs r3, #1 8004a54: 62fb str r3, [r7, #44] @ 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 8004a56: 6afb ldr r3, [r7, #44] @ 0x2c 8004a58: 2b01 cmp r3, #1 8004a5a: d005 beq.n 8004a68 8004a5c: 687b ldr r3, [r7, #4] 8004a5e: 681b ldr r3, [r3, #0] 8004a60: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004a64: f040 80ff bne.w 8004c66 { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8004a68: 4b09 ldr r3, [pc, #36] @ (8004a90 ) 8004a6a: 2200 movs r2, #0 8004a6c: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004a6e: f7fd fa85 bl 8001f7c 8004a72: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004a74: e00e b.n 8004a94 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004a76: f7fd fa81 bl 8001f7c 8004a7a: 4602 mov r2, r0 8004a7c: 6a7b ldr r3, [r7, #36] @ 0x24 8004a7e: 1ad3 subs r3, r2, r3 8004a80: 2b02 cmp r3, #2 8004a82: d907 bls.n 8004a94 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004a84: 2303 movs r3, #3 8004a86: e188 b.n 8004d9a 8004a88: 40023800 .word 0x40023800 8004a8c: 424711e0 .word 0x424711e0 8004a90: 42470068 .word 0x42470068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004a94: 4b7e ldr r3, [pc, #504] @ (8004c90 ) 8004a96: 681b ldr r3, [r3, #0] 8004a98: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004a9c: 2b00 cmp r3, #0 8004a9e: d1ea bne.n 8004a76 /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) 8004aa0: 687b ldr r3, [r7, #4] 8004aa2: 681b ldr r3, [r3, #0] 8004aa4: f003 0301 and.w r3, r3, #1 8004aa8: 2b00 cmp r3, #0 8004aaa: d003 beq.n 8004ab4 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004aac: 687b ldr r3, [r7, #4] 8004aae: 6b9b ldr r3, [r3, #56] @ 0x38 8004ab0: 2b00 cmp r3, #0 8004ab2: d009 beq.n 8004ac8 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8004ab4: 687b ldr r3, [r7, #4] 8004ab6: 681b ldr r3, [r3, #0] 8004ab8: f003 0302 and.w r3, r3, #2 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004abc: 2b00 cmp r3, #0 8004abe: d028 beq.n 8004b12 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8004ac0: 687b ldr r3, [r7, #4] 8004ac2: 6bdb ldr r3, [r3, #60] @ 0x3c 8004ac4: 2b00 cmp r3, #0 8004ac6: d124 bne.n 8004b12 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004ac8: 4b71 ldr r3, [pc, #452] @ (8004c90 ) 8004aca: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004ace: 0c1b lsrs r3, r3, #16 8004ad0: f003 0303 and.w r3, r3, #3 8004ad4: 3301 adds r3, #1 8004ad6: 005b lsls r3, r3, #1 8004ad8: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8004ada: 4b6d ldr r3, [pc, #436] @ (8004c90 ) 8004adc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004ae0: 0e1b lsrs r3, r3, #24 8004ae2: f003 030f and.w r3, r3, #15 8004ae6: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, 8004ae8: 687b ldr r3, [r7, #4] 8004aea: 685a ldr r2, [r3, #4] 8004aec: 687b ldr r3, [r7, #4] 8004aee: 689b ldr r3, [r3, #8] 8004af0: 019b lsls r3, r3, #6 8004af2: 431a orrs r2, r3 8004af4: 69fb ldr r3, [r7, #28] 8004af6: 085b lsrs r3, r3, #1 8004af8: 3b01 subs r3, #1 8004afa: 041b lsls r3, r3, #16 8004afc: 431a orrs r2, r3 8004afe: 69bb ldr r3, [r7, #24] 8004b00: 061b lsls r3, r3, #24 8004b02: 431a orrs r2, r3 8004b04: 687b ldr r3, [r7, #4] 8004b06: 695b ldr r3, [r3, #20] 8004b08: 071b lsls r3, r3, #28 8004b0a: 4961 ldr r1, [pc, #388] @ (8004c90 ) 8004b0c: 4313 orrs r3, r2 8004b0e: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004b12: 687b ldr r3, [r7, #4] 8004b14: 681b ldr r3, [r3, #0] 8004b16: f003 0304 and.w r3, r3, #4 8004b1a: 2b00 cmp r3, #0 8004b1c: d004 beq.n 8004b28 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 8004b1e: 687b ldr r3, [r7, #4] 8004b20: 6b1b ldr r3, [r3, #48] @ 0x30 8004b22: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8004b26: d00a beq.n 8004b3e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004b28: 687b ldr r3, [r7, #4] 8004b2a: 681b ldr r3, [r3, #0] 8004b2c: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 8004b30: 2b00 cmp r3, #0 8004b32: d035 beq.n 8004ba0 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004b34: 687b ldr r3, [r7, #4] 8004b36: 6b5b ldr r3, [r3, #52] @ 0x34 8004b38: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004b3c: d130 bne.n 8004ba0 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004b3e: 4b54 ldr r3, [pc, #336] @ (8004c90 ) 8004b40: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004b44: 0c1b lsrs r3, r3, #16 8004b46: f003 0303 and.w r3, r3, #3 8004b4a: 3301 adds r3, #1 8004b4c: 005b lsls r3, r3, #1 8004b4e: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004b50: 4b4f ldr r3, [pc, #316] @ (8004c90 ) 8004b52: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004b56: 0f1b lsrs r3, r3, #28 8004b58: f003 0307 and.w r3, r3, #7 8004b5c: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, 8004b5e: 687b ldr r3, [r7, #4] 8004b60: 685a ldr r2, [r3, #4] 8004b62: 687b ldr r3, [r7, #4] 8004b64: 689b ldr r3, [r3, #8] 8004b66: 019b lsls r3, r3, #6 8004b68: 431a orrs r2, r3 8004b6a: 69fb ldr r3, [r7, #28] 8004b6c: 085b lsrs r3, r3, #1 8004b6e: 3b01 subs r3, #1 8004b70: 041b lsls r3, r3, #16 8004b72: 431a orrs r2, r3 8004b74: 687b ldr r3, [r7, #4] 8004b76: 691b ldr r3, [r3, #16] 8004b78: 061b lsls r3, r3, #24 8004b7a: 431a orrs r2, r3 8004b7c: 697b ldr r3, [r7, #20] 8004b7e: 071b lsls r3, r3, #28 8004b80: 4943 ldr r1, [pc, #268] @ (8004c90 ) 8004b82: 4313 orrs r3, r2 8004b84: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004b88: 4b41 ldr r3, [pc, #260] @ (8004c90 ) 8004b8a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004b8e: f023 021f bic.w r2, r3, #31 8004b92: 687b ldr r3, [r7, #4] 8004b94: 6a9b ldr r3, [r3, #40] @ 0x28 8004b96: 3b01 subs r3, #1 8004b98: 493d ldr r1, [pc, #244] @ (8004c90 ) 8004b9a: 4313 orrs r3, r2 8004b9c: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004ba0: 687b ldr r3, [r7, #4] 8004ba2: 681b ldr r3, [r3, #0] 8004ba4: f403 6380 and.w r3, r3, #1024 @ 0x400 8004ba8: 2b00 cmp r3, #0 8004baa: d029 beq.n 8004c00 && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 8004bac: 687b ldr r3, [r7, #4] 8004bae: 6d1b ldr r3, [r3, #80] @ 0x50 8004bb0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004bb4: d124 bne.n 8004c00 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004bb6: 4b36 ldr r3, [pc, #216] @ (8004c90 ) 8004bb8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004bbc: 0c1b lsrs r3, r3, #16 8004bbe: f003 0303 and.w r3, r3, #3 8004bc2: 3301 adds r3, #1 8004bc4: 005b lsls r3, r3, #1 8004bc6: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004bc8: 4b31 ldr r3, [pc, #196] @ (8004c90 ) 8004bca: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004bce: 0f1b lsrs r3, r3, #28 8004bd0: f003 0307 and.w r3, r3, #7 8004bd4: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004bd6: 687b ldr r3, [r7, #4] 8004bd8: 685a ldr r2, [r3, #4] 8004bda: 687b ldr r3, [r7, #4] 8004bdc: 689b ldr r3, [r3, #8] 8004bde: 019b lsls r3, r3, #6 8004be0: 431a orrs r2, r3 8004be2: 687b ldr r3, [r7, #4] 8004be4: 68db ldr r3, [r3, #12] 8004be6: 085b lsrs r3, r3, #1 8004be8: 3b01 subs r3, #1 8004bea: 041b lsls r3, r3, #16 8004bec: 431a orrs r2, r3 8004bee: 69bb ldr r3, [r7, #24] 8004bf0: 061b lsls r3, r3, #24 8004bf2: 431a orrs r2, r3 8004bf4: 697b ldr r3, [r7, #20] 8004bf6: 071b lsls r3, r3, #28 8004bf8: 4925 ldr r1, [pc, #148] @ (8004c90 ) 8004bfa: 4313 orrs r3, r2 8004bfc: f8c1 3084 str.w r3, [r1, #132] @ 0x84 plli2sq, plli2sr); } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 8004c00: 687b ldr r3, [r7, #4] 8004c02: 681b ldr r3, [r3, #0] 8004c04: f403 6300 and.w r3, r3, #2048 @ 0x800 8004c08: 2b00 cmp r3, #0 8004c0a: d016 beq.n 8004c3a assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004c0c: 687b ldr r3, [r7, #4] 8004c0e: 685a ldr r2, [r3, #4] 8004c10: 687b ldr r3, [r7, #4] 8004c12: 689b ldr r3, [r3, #8] 8004c14: 019b lsls r3, r3, #6 8004c16: 431a orrs r2, r3 8004c18: 687b ldr r3, [r7, #4] 8004c1a: 68db ldr r3, [r3, #12] 8004c1c: 085b lsrs r3, r3, #1 8004c1e: 3b01 subs r3, #1 8004c20: 041b lsls r3, r3, #16 8004c22: 431a orrs r2, r3 8004c24: 687b ldr r3, [r7, #4] 8004c26: 691b ldr r3, [r3, #16] 8004c28: 061b lsls r3, r3, #24 8004c2a: 431a orrs r2, r3 8004c2c: 687b ldr r3, [r7, #4] 8004c2e: 695b ldr r3, [r3, #20] 8004c30: 071b lsls r3, r3, #28 8004c32: 4917 ldr r1, [pc, #92] @ (8004c90 ) 8004c34: 4313 orrs r3, r2 8004c36: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 8004c3a: 4b16 ldr r3, [pc, #88] @ (8004c94 ) 8004c3c: 2201 movs r2, #1 8004c3e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004c40: f7fd f99c bl 8001f7c 8004c44: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004c46: e008 b.n 8004c5a { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004c48: f7fd f998 bl 8001f7c 8004c4c: 4602 mov r2, r0 8004c4e: 6a7b ldr r3, [r7, #36] @ 0x24 8004c50: 1ad3 subs r3, r2, r3 8004c52: 2b02 cmp r3, #2 8004c54: d901 bls.n 8004c5a { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004c56: 2303 movs r3, #3 8004c58: e09f b.n 8004d9a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004c5a: 4b0d ldr r3, [pc, #52] @ (8004c90 ) 8004c5c: 681b ldr r3, [r3, #0] 8004c5e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004c62: 2b00 cmp r3, #0 8004c64: d0f0 beq.n 8004c48 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if (pllsaiused == 1U) 8004c66: 6abb ldr r3, [r7, #40] @ 0x28 8004c68: 2b01 cmp r3, #1 8004c6a: f040 8095 bne.w 8004d98 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 8004c6e: 4b0a ldr r3, [pc, #40] @ (8004c98 ) 8004c70: 2200 movs r2, #0 8004c72: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004c74: f7fd f982 bl 8001f7c 8004c78: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004c7a: e00f b.n 8004c9c { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004c7c: f7fd f97e bl 8001f7c 8004c80: 4602 mov r2, r0 8004c82: 6a7b ldr r3, [r7, #36] @ 0x24 8004c84: 1ad3 subs r3, r2, r3 8004c86: 2b02 cmp r3, #2 8004c88: d908 bls.n 8004c9c { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004c8a: 2303 movs r3, #3 8004c8c: e085 b.n 8004d9a 8004c8e: bf00 nop 8004c90: 40023800 .word 0x40023800 8004c94: 42470068 .word 0x42470068 8004c98: 42470070 .word 0x42470070 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004c9c: 4b41 ldr r3, [pc, #260] @ (8004da4 ) 8004c9e: 681b ldr r3, [r3, #0] 8004ca0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004ca4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004ca8: d0e8 beq.n 8004c7c /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004caa: 687b ldr r3, [r7, #4] 8004cac: 681b ldr r3, [r3, #0] 8004cae: f003 0304 and.w r3, r3, #4 8004cb2: 2b00 cmp r3, #0 8004cb4: d003 beq.n 8004cbe && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004cb6: 687b ldr r3, [r7, #4] 8004cb8: 6b1b ldr r3, [r3, #48] @ 0x30 8004cba: 2b00 cmp r3, #0 8004cbc: d009 beq.n 8004cd2 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004cbe: 687b ldr r3, [r7, #4] 8004cc0: 681b ldr r3, [r3, #0] 8004cc2: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004cc6: 2b00 cmp r3, #0 8004cc8: d02b beq.n 8004d22 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004cca: 687b ldr r3, [r7, #4] 8004ccc: 6b5b ldr r3, [r3, #52] @ 0x34 8004cce: 2b00 cmp r3, #0 8004cd0: d127 bne.n 8004d22 assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 8004cd2: 4b34 ldr r3, [pc, #208] @ (8004da4 ) 8004cd4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004cd8: 0c1b lsrs r3, r3, #16 8004cda: f003 0303 and.w r3, r3, #3 8004cde: 3301 adds r3, #1 8004ce0: 005b lsls r3, r3, #1 8004ce2: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, 8004ce4: 687b ldr r3, [r7, #4] 8004ce6: 699a ldr r2, [r3, #24] 8004ce8: 687b ldr r3, [r7, #4] 8004cea: 69db ldr r3, [r3, #28] 8004cec: 019b lsls r3, r3, #6 8004cee: 431a orrs r2, r3 8004cf0: 693b ldr r3, [r7, #16] 8004cf2: 085b lsrs r3, r3, #1 8004cf4: 3b01 subs r3, #1 8004cf6: 041b lsls r3, r3, #16 8004cf8: 431a orrs r2, r3 8004cfa: 687b ldr r3, [r7, #4] 8004cfc: 6a5b ldr r3, [r3, #36] @ 0x24 8004cfe: 061b lsls r3, r3, #24 8004d00: 4928 ldr r1, [pc, #160] @ (8004da4 ) 8004d02: 4313 orrs r3, r2 8004d04: f8c1 3088 str.w r3, [r1, #136] @ 0x88 PeriphClkInit->PLLSAI.PLLSAIQ, 0U); /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 8004d08: 4b26 ldr r3, [pc, #152] @ (8004da4 ) 8004d0a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004d0e: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 8004d12: 687b ldr r3, [r7, #4] 8004d14: 6adb ldr r3, [r3, #44] @ 0x2c 8004d16: 3b01 subs r3, #1 8004d18: 021b lsls r3, r3, #8 8004d1a: 4922 ldr r1, [pc, #136] @ (8004da4 ) 8004d1c: 4313 orrs r3, r2 8004d1e: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 8004d22: 687b ldr r3, [r7, #4] 8004d24: 681b ldr r3, [r3, #0] 8004d26: f403 7380 and.w r3, r3, #256 @ 0x100 8004d2a: 2b00 cmp r3, #0 8004d2c: d01d beq.n 8004d6a && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 8004d2e: 687b ldr r3, [r7, #4] 8004d30: 6d5b ldr r3, [r3, #84] @ 0x54 8004d32: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004d36: d118 bne.n 8004d6a { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 8004d38: 4b1a ldr r3, [pc, #104] @ (8004da4 ) 8004d3a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004d3e: 0e1b lsrs r3, r3, #24 8004d40: f003 030f and.w r3, r3, #15 8004d44: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, 8004d46: 687b ldr r3, [r7, #4] 8004d48: 699a ldr r2, [r3, #24] 8004d4a: 687b ldr r3, [r7, #4] 8004d4c: 69db ldr r3, [r3, #28] 8004d4e: 019b lsls r3, r3, #6 8004d50: 431a orrs r2, r3 8004d52: 687b ldr r3, [r7, #4] 8004d54: 6a1b ldr r3, [r3, #32] 8004d56: 085b lsrs r3, r3, #1 8004d58: 3b01 subs r3, #1 8004d5a: 041b lsls r3, r3, #16 8004d5c: 431a orrs r2, r3 8004d5e: 68fb ldr r3, [r7, #12] 8004d60: 061b lsls r3, r3, #24 8004d62: 4910 ldr r1, [pc, #64] @ (8004da4 ) 8004d64: 4313 orrs r3, r2 8004d66: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pllsaiq, 0U); } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 8004d6a: 4b0f ldr r3, [pc, #60] @ (8004da8 ) 8004d6c: 2201 movs r2, #1 8004d6e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004d70: f7fd f904 bl 8001f7c 8004d74: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004d76: e008 b.n 8004d8a { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004d78: f7fd f900 bl 8001f7c 8004d7c: 4602 mov r2, r0 8004d7e: 6a7b ldr r3, [r7, #36] @ 0x24 8004d80: 1ad3 subs r3, r2, r3 8004d82: 2b02 cmp r3, #2 8004d84: d901 bls.n 8004d8a { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004d86: 2303 movs r3, #3 8004d88: e007 b.n 8004d9a while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004d8a: 4b06 ldr r3, [pc, #24] @ (8004da4 ) 8004d8c: 681b ldr r3, [r3, #0] 8004d8e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004d92: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004d96: d1ef bne.n 8004d78 } } } return HAL_OK; 8004d98: 2300 movs r3, #0 } 8004d9a: 4618 mov r0, r3 8004d9c: 3730 adds r7, #48 @ 0x30 8004d9e: 46bd mov sp, r7 8004da0: bd80 pop {r7, pc} 8004da2: bf00 nop 8004da4: 40023800 .word 0x40023800 8004da8: 42470070 .word 0x42470070 08004dac : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8004dac: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8004db0: b0ae sub sp, #184 @ 0xb8 8004db2: af00 add r7, sp, #0 uint32_t pllm = 0U; 8004db4: 2300 movs r3, #0 8004db6: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t pllvco = 0U; 8004dba: 2300 movs r3, #0 8004dbc: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t pllp = 0U; 8004dc0: 2300 movs r3, #0 8004dc2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 uint32_t pllr = 0U; 8004dc6: 2300 movs r3, #0 8004dc8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t sysclockfreq = 0U; 8004dcc: 2300 movs r3, #0 8004dce: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8004dd2: 4bcb ldr r3, [pc, #812] @ (8005100 ) 8004dd4: 689b ldr r3, [r3, #8] 8004dd6: f003 030c and.w r3, r3, #12 8004dda: 2b0c cmp r3, #12 8004ddc: f200 8206 bhi.w 80051ec 8004de0: a201 add r2, pc, #4 @ (adr r2, 8004de8 ) 8004de2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004de6: bf00 nop 8004de8: 08004e1d .word 0x08004e1d 8004dec: 080051ed .word 0x080051ed 8004df0: 080051ed .word 0x080051ed 8004df4: 080051ed .word 0x080051ed 8004df8: 08004e25 .word 0x08004e25 8004dfc: 080051ed .word 0x080051ed 8004e00: 080051ed .word 0x080051ed 8004e04: 080051ed .word 0x080051ed 8004e08: 08004e2d .word 0x08004e2d 8004e0c: 080051ed .word 0x080051ed 8004e10: 080051ed .word 0x080051ed 8004e14: 080051ed .word 0x080051ed 8004e18: 0800501d .word 0x0800501d { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8004e1c: 4bb9 ldr r3, [pc, #740] @ (8005104 ) 8004e1e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004e22: e1e7 b.n 80051f4 } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8004e24: 4bb8 ldr r3, [pc, #736] @ (8005108 ) 8004e26: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004e2a: e1e3 b.n 80051f4 } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004e2c: 4bb4 ldr r3, [pc, #720] @ (8005100 ) 8004e2e: 685b ldr r3, [r3, #4] 8004e30: f003 033f and.w r3, r3, #63 @ 0x3f 8004e34: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004e38: 4bb1 ldr r3, [pc, #708] @ (8005100 ) 8004e3a: 685b ldr r3, [r3, #4] 8004e3c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004e40: 2b00 cmp r3, #0 8004e42: d071 beq.n 8004f28 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004e44: 4bae ldr r3, [pc, #696] @ (8005100 ) 8004e46: 685b ldr r3, [r3, #4] 8004e48: 099b lsrs r3, r3, #6 8004e4a: 2200 movs r2, #0 8004e4c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8004e50: f8c7 209c str.w r2, [r7, #156] @ 0x9c 8004e54: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8004e58: f3c3 0308 ubfx r3, r3, #0, #9 8004e5c: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8004e60: 2300 movs r3, #0 8004e62: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8004e66: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8004e6a: 4622 mov r2, r4 8004e6c: 462b mov r3, r5 8004e6e: f04f 0000 mov.w r0, #0 8004e72: f04f 0100 mov.w r1, #0 8004e76: 0159 lsls r1, r3, #5 8004e78: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004e7c: 0150 lsls r0, r2, #5 8004e7e: 4602 mov r2, r0 8004e80: 460b mov r3, r1 8004e82: 4621 mov r1, r4 8004e84: 1a51 subs r1, r2, r1 8004e86: 6439 str r1, [r7, #64] @ 0x40 8004e88: 4629 mov r1, r5 8004e8a: eb63 0301 sbc.w r3, r3, r1 8004e8e: 647b str r3, [r7, #68] @ 0x44 8004e90: f04f 0200 mov.w r2, #0 8004e94: f04f 0300 mov.w r3, #0 8004e98: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 8004e9c: 4649 mov r1, r9 8004e9e: 018b lsls r3, r1, #6 8004ea0: 4641 mov r1, r8 8004ea2: ea43 6391 orr.w r3, r3, r1, lsr #26 8004ea6: 4641 mov r1, r8 8004ea8: 018a lsls r2, r1, #6 8004eaa: 4641 mov r1, r8 8004eac: 1a51 subs r1, r2, r1 8004eae: 63b9 str r1, [r7, #56] @ 0x38 8004eb0: 4649 mov r1, r9 8004eb2: eb63 0301 sbc.w r3, r3, r1 8004eb6: 63fb str r3, [r7, #60] @ 0x3c 8004eb8: f04f 0200 mov.w r2, #0 8004ebc: f04f 0300 mov.w r3, #0 8004ec0: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 8004ec4: 4649 mov r1, r9 8004ec6: 00cb lsls r3, r1, #3 8004ec8: 4641 mov r1, r8 8004eca: ea43 7351 orr.w r3, r3, r1, lsr #29 8004ece: 4641 mov r1, r8 8004ed0: 00ca lsls r2, r1, #3 8004ed2: 4610 mov r0, r2 8004ed4: 4619 mov r1, r3 8004ed6: 4603 mov r3, r0 8004ed8: 4622 mov r2, r4 8004eda: 189b adds r3, r3, r2 8004edc: 633b str r3, [r7, #48] @ 0x30 8004ede: 462b mov r3, r5 8004ee0: 460a mov r2, r1 8004ee2: eb42 0303 adc.w r3, r2, r3 8004ee6: 637b str r3, [r7, #52] @ 0x34 8004ee8: f04f 0200 mov.w r2, #0 8004eec: f04f 0300 mov.w r3, #0 8004ef0: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 8004ef4: 4629 mov r1, r5 8004ef6: 024b lsls r3, r1, #9 8004ef8: 4621 mov r1, r4 8004efa: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004efe: 4621 mov r1, r4 8004f00: 024a lsls r2, r1, #9 8004f02: 4610 mov r0, r2 8004f04: 4619 mov r1, r3 8004f06: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004f0a: 2200 movs r2, #0 8004f0c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8004f10: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8004f14: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 8004f18: f7fb f974 bl 8000204 <__aeabi_uldivmod> 8004f1c: 4602 mov r2, r0 8004f1e: 460b mov r3, r1 8004f20: 4613 mov r3, r2 8004f22: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004f26: e067 b.n 8004ff8 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004f28: 4b75 ldr r3, [pc, #468] @ (8005100 ) 8004f2a: 685b ldr r3, [r3, #4] 8004f2c: 099b lsrs r3, r3, #6 8004f2e: 2200 movs r2, #0 8004f30: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004f34: f8c7 2084 str.w r2, [r7, #132] @ 0x84 8004f38: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004f3c: f3c3 0308 ubfx r3, r3, #0, #9 8004f40: 67bb str r3, [r7, #120] @ 0x78 8004f42: 2300 movs r3, #0 8004f44: 67fb str r3, [r7, #124] @ 0x7c 8004f46: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 8004f4a: 4622 mov r2, r4 8004f4c: 462b mov r3, r5 8004f4e: f04f 0000 mov.w r0, #0 8004f52: f04f 0100 mov.w r1, #0 8004f56: 0159 lsls r1, r3, #5 8004f58: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004f5c: 0150 lsls r0, r2, #5 8004f5e: 4602 mov r2, r0 8004f60: 460b mov r3, r1 8004f62: 4621 mov r1, r4 8004f64: 1a51 subs r1, r2, r1 8004f66: 62b9 str r1, [r7, #40] @ 0x28 8004f68: 4629 mov r1, r5 8004f6a: eb63 0301 sbc.w r3, r3, r1 8004f6e: 62fb str r3, [r7, #44] @ 0x2c 8004f70: f04f 0200 mov.w r2, #0 8004f74: f04f 0300 mov.w r3, #0 8004f78: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 8004f7c: 4649 mov r1, r9 8004f7e: 018b lsls r3, r1, #6 8004f80: 4641 mov r1, r8 8004f82: ea43 6391 orr.w r3, r3, r1, lsr #26 8004f86: 4641 mov r1, r8 8004f88: 018a lsls r2, r1, #6 8004f8a: 4641 mov r1, r8 8004f8c: ebb2 0a01 subs.w sl, r2, r1 8004f90: 4649 mov r1, r9 8004f92: eb63 0b01 sbc.w fp, r3, r1 8004f96: f04f 0200 mov.w r2, #0 8004f9a: f04f 0300 mov.w r3, #0 8004f9e: ea4f 03cb mov.w r3, fp, lsl #3 8004fa2: ea43 735a orr.w r3, r3, sl, lsr #29 8004fa6: ea4f 02ca mov.w r2, sl, lsl #3 8004faa: 4692 mov sl, r2 8004fac: 469b mov fp, r3 8004fae: 4623 mov r3, r4 8004fb0: eb1a 0303 adds.w r3, sl, r3 8004fb4: 623b str r3, [r7, #32] 8004fb6: 462b mov r3, r5 8004fb8: eb4b 0303 adc.w r3, fp, r3 8004fbc: 627b str r3, [r7, #36] @ 0x24 8004fbe: f04f 0200 mov.w r2, #0 8004fc2: f04f 0300 mov.w r3, #0 8004fc6: e9d7 4508 ldrd r4, r5, [r7, #32] 8004fca: 4629 mov r1, r5 8004fcc: 028b lsls r3, r1, #10 8004fce: 4621 mov r1, r4 8004fd0: ea43 5391 orr.w r3, r3, r1, lsr #22 8004fd4: 4621 mov r1, r4 8004fd6: 028a lsls r2, r1, #10 8004fd8: 4610 mov r0, r2 8004fda: 4619 mov r1, r3 8004fdc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004fe0: 2200 movs r2, #0 8004fe2: 673b str r3, [r7, #112] @ 0x70 8004fe4: 677a str r2, [r7, #116] @ 0x74 8004fe6: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 8004fea: f7fb f90b bl 8000204 <__aeabi_uldivmod> 8004fee: 4602 mov r2, r0 8004ff0: 460b mov r3, r1 8004ff2: 4613 mov r3, r2 8004ff4: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004ff8: 4b41 ldr r3, [pc, #260] @ (8005100 ) 8004ffa: 685b ldr r3, [r3, #4] 8004ffc: 0c1b lsrs r3, r3, #16 8004ffe: f003 0303 and.w r3, r3, #3 8005002: 3301 adds r3, #1 8005004: 005b lsls r3, r3, #1 8005006: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 sysclockfreq = pllvco / pllp; 800500a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 800500e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8005012: fbb2 f3f3 udiv r3, r2, r3 8005016: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 800501a: e0eb b.n 80051f4 } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 800501c: 4b38 ldr r3, [pc, #224] @ (8005100 ) 800501e: 685b ldr r3, [r3, #4] 8005020: f003 033f and.w r3, r3, #63 @ 0x3f 8005024: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8005028: 4b35 ldr r3, [pc, #212] @ (8005100 ) 800502a: 685b ldr r3, [r3, #4] 800502c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8005030: 2b00 cmp r3, #0 8005032: d06b beq.n 800510c { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8005034: 4b32 ldr r3, [pc, #200] @ (8005100 ) 8005036: 685b ldr r3, [r3, #4] 8005038: 099b lsrs r3, r3, #6 800503a: 2200 movs r2, #0 800503c: 66bb str r3, [r7, #104] @ 0x68 800503e: 66fa str r2, [r7, #108] @ 0x6c 8005040: 6ebb ldr r3, [r7, #104] @ 0x68 8005042: f3c3 0308 ubfx r3, r3, #0, #9 8005046: 663b str r3, [r7, #96] @ 0x60 8005048: 2300 movs r3, #0 800504a: 667b str r3, [r7, #100] @ 0x64 800504c: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 8005050: 4622 mov r2, r4 8005052: 462b mov r3, r5 8005054: f04f 0000 mov.w r0, #0 8005058: f04f 0100 mov.w r1, #0 800505c: 0159 lsls r1, r3, #5 800505e: ea41 61d2 orr.w r1, r1, r2, lsr #27 8005062: 0150 lsls r0, r2, #5 8005064: 4602 mov r2, r0 8005066: 460b mov r3, r1 8005068: 4621 mov r1, r4 800506a: 1a51 subs r1, r2, r1 800506c: 61b9 str r1, [r7, #24] 800506e: 4629 mov r1, r5 8005070: eb63 0301 sbc.w r3, r3, r1 8005074: 61fb str r3, [r7, #28] 8005076: f04f 0200 mov.w r2, #0 800507a: f04f 0300 mov.w r3, #0 800507e: e9d7 ab06 ldrd sl, fp, [r7, #24] 8005082: 4659 mov r1, fp 8005084: 018b lsls r3, r1, #6 8005086: 4651 mov r1, sl 8005088: ea43 6391 orr.w r3, r3, r1, lsr #26 800508c: 4651 mov r1, sl 800508e: 018a lsls r2, r1, #6 8005090: 4651 mov r1, sl 8005092: ebb2 0801 subs.w r8, r2, r1 8005096: 4659 mov r1, fp 8005098: eb63 0901 sbc.w r9, r3, r1 800509c: f04f 0200 mov.w r2, #0 80050a0: f04f 0300 mov.w r3, #0 80050a4: ea4f 03c9 mov.w r3, r9, lsl #3 80050a8: ea43 7358 orr.w r3, r3, r8, lsr #29 80050ac: ea4f 02c8 mov.w r2, r8, lsl #3 80050b0: 4690 mov r8, r2 80050b2: 4699 mov r9, r3 80050b4: 4623 mov r3, r4 80050b6: eb18 0303 adds.w r3, r8, r3 80050ba: 613b str r3, [r7, #16] 80050bc: 462b mov r3, r5 80050be: eb49 0303 adc.w r3, r9, r3 80050c2: 617b str r3, [r7, #20] 80050c4: f04f 0200 mov.w r2, #0 80050c8: f04f 0300 mov.w r3, #0 80050cc: e9d7 4504 ldrd r4, r5, [r7, #16] 80050d0: 4629 mov r1, r5 80050d2: 024b lsls r3, r1, #9 80050d4: 4621 mov r1, r4 80050d6: ea43 53d1 orr.w r3, r3, r1, lsr #23 80050da: 4621 mov r1, r4 80050dc: 024a lsls r2, r1, #9 80050de: 4610 mov r0, r2 80050e0: 4619 mov r1, r3 80050e2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80050e6: 2200 movs r2, #0 80050e8: 65bb str r3, [r7, #88] @ 0x58 80050ea: 65fa str r2, [r7, #92] @ 0x5c 80050ec: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 80050f0: f7fb f888 bl 8000204 <__aeabi_uldivmod> 80050f4: 4602 mov r2, r0 80050f6: 460b mov r3, r1 80050f8: 4613 mov r3, r2 80050fa: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80050fe: e065 b.n 80051cc 8005100: 40023800 .word 0x40023800 8005104: 00f42400 .word 0x00f42400 8005108: 007a1200 .word 0x007a1200 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 800510c: 4b3d ldr r3, [pc, #244] @ (8005204 ) 800510e: 685b ldr r3, [r3, #4] 8005110: 099b lsrs r3, r3, #6 8005112: 2200 movs r2, #0 8005114: 4618 mov r0, r3 8005116: 4611 mov r1, r2 8005118: f3c0 0308 ubfx r3, r0, #0, #9 800511c: 653b str r3, [r7, #80] @ 0x50 800511e: 2300 movs r3, #0 8005120: 657b str r3, [r7, #84] @ 0x54 8005122: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 8005126: 4642 mov r2, r8 8005128: 464b mov r3, r9 800512a: f04f 0000 mov.w r0, #0 800512e: f04f 0100 mov.w r1, #0 8005132: 0159 lsls r1, r3, #5 8005134: ea41 61d2 orr.w r1, r1, r2, lsr #27 8005138: 0150 lsls r0, r2, #5 800513a: 4602 mov r2, r0 800513c: 460b mov r3, r1 800513e: 4641 mov r1, r8 8005140: 1a51 subs r1, r2, r1 8005142: 60b9 str r1, [r7, #8] 8005144: 4649 mov r1, r9 8005146: eb63 0301 sbc.w r3, r3, r1 800514a: 60fb str r3, [r7, #12] 800514c: f04f 0200 mov.w r2, #0 8005150: f04f 0300 mov.w r3, #0 8005154: e9d7 ab02 ldrd sl, fp, [r7, #8] 8005158: 4659 mov r1, fp 800515a: 018b lsls r3, r1, #6 800515c: 4651 mov r1, sl 800515e: ea43 6391 orr.w r3, r3, r1, lsr #26 8005162: 4651 mov r1, sl 8005164: 018a lsls r2, r1, #6 8005166: 4651 mov r1, sl 8005168: 1a54 subs r4, r2, r1 800516a: 4659 mov r1, fp 800516c: eb63 0501 sbc.w r5, r3, r1 8005170: f04f 0200 mov.w r2, #0 8005174: f04f 0300 mov.w r3, #0 8005178: 00eb lsls r3, r5, #3 800517a: ea43 7354 orr.w r3, r3, r4, lsr #29 800517e: 00e2 lsls r2, r4, #3 8005180: 4614 mov r4, r2 8005182: 461d mov r5, r3 8005184: 4643 mov r3, r8 8005186: 18e3 adds r3, r4, r3 8005188: 603b str r3, [r7, #0] 800518a: 464b mov r3, r9 800518c: eb45 0303 adc.w r3, r5, r3 8005190: 607b str r3, [r7, #4] 8005192: f04f 0200 mov.w r2, #0 8005196: f04f 0300 mov.w r3, #0 800519a: e9d7 4500 ldrd r4, r5, [r7] 800519e: 4629 mov r1, r5 80051a0: 028b lsls r3, r1, #10 80051a2: 4621 mov r1, r4 80051a4: ea43 5391 orr.w r3, r3, r1, lsr #22 80051a8: 4621 mov r1, r4 80051aa: 028a lsls r2, r1, #10 80051ac: 4610 mov r0, r2 80051ae: 4619 mov r1, r3 80051b0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80051b4: 2200 movs r2, #0 80051b6: 64bb str r3, [r7, #72] @ 0x48 80051b8: 64fa str r2, [r7, #76] @ 0x4c 80051ba: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 80051be: f7fb f821 bl 8000204 <__aeabi_uldivmod> 80051c2: 4602 mov r2, r0 80051c4: 460b mov r3, r1 80051c6: 4613 mov r3, r2 80051c8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 80051cc: 4b0d ldr r3, [pc, #52] @ (8005204 ) 80051ce: 685b ldr r3, [r3, #4] 80051d0: 0f1b lsrs r3, r3, #28 80051d2: f003 0307 and.w r3, r3, #7 80051d6: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 sysclockfreq = pllvco / pllr; 80051da: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 80051de: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 80051e2: fbb2 f3f3 udiv r3, r2, r3 80051e6: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80051ea: e003 b.n 80051f4 } default: { sysclockfreq = HSI_VALUE; 80051ec: 4b06 ldr r3, [pc, #24] @ (8005208 ) 80051ee: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80051f2: bf00 nop } } return sysclockfreq; 80051f4: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 } 80051f8: 4618 mov r0, r3 80051fa: 37b8 adds r7, #184 @ 0xb8 80051fc: 46bd mov sp, r7 80051fe: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8005202: bf00 nop 8005204: 40023800 .word 0x40023800 8005208: 00f42400 .word 0x00f42400 0800520c : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 800520c: b580 push {r7, lr} 800520e: b086 sub sp, #24 8005210: af00 add r7, sp, #0 8005212: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8005214: 687b ldr r3, [r7, #4] 8005216: 2b00 cmp r3, #0 8005218: d101 bne.n 800521e { return HAL_ERROR; 800521a: 2301 movs r3, #1 800521c: e28d b.n 800573a } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800521e: 687b ldr r3, [r7, #4] 8005220: 681b ldr r3, [r3, #0] 8005222: f003 0301 and.w r3, r3, #1 8005226: 2b00 cmp r3, #0 8005228: f000 8083 beq.w 8005332 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 800522c: 4b94 ldr r3, [pc, #592] @ (8005480 ) 800522e: 689b ldr r3, [r3, #8] 8005230: f003 030c and.w r3, r3, #12 8005234: 2b04 cmp r3, #4 8005236: d019 beq.n 800526c || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8005238: 4b91 ldr r3, [pc, #580] @ (8005480 ) 800523a: 689b ldr r3, [r3, #8] 800523c: f003 030c and.w r3, r3, #12 || \ 8005240: 2b08 cmp r3, #8 8005242: d106 bne.n 8005252 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8005244: 4b8e ldr r3, [pc, #568] @ (8005480 ) 8005246: 685b ldr r3, [r3, #4] 8005248: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800524c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8005250: d00c beq.n 800526c ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8005252: 4b8b ldr r3, [pc, #556] @ (8005480 ) 8005254: 689b ldr r3, [r3, #8] 8005256: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 800525a: 2b0c cmp r3, #12 800525c: d112 bne.n 8005284 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 800525e: 4b88 ldr r3, [pc, #544] @ (8005480 ) 8005260: 685b ldr r3, [r3, #4] 8005262: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8005266: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800526a: d10b bne.n 8005284 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800526c: 4b84 ldr r3, [pc, #528] @ (8005480 ) 800526e: 681b ldr r3, [r3, #0] 8005270: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005274: 2b00 cmp r3, #0 8005276: d05b beq.n 8005330 8005278: 687b ldr r3, [r7, #4] 800527a: 685b ldr r3, [r3, #4] 800527c: 2b00 cmp r3, #0 800527e: d157 bne.n 8005330 { return HAL_ERROR; 8005280: 2301 movs r3, #1 8005282: e25a b.n 800573a } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8005284: 687b ldr r3, [r7, #4] 8005286: 685b ldr r3, [r3, #4] 8005288: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800528c: d106 bne.n 800529c 800528e: 4b7c ldr r3, [pc, #496] @ (8005480 ) 8005290: 681b ldr r3, [r3, #0] 8005292: 4a7b ldr r2, [pc, #492] @ (8005480 ) 8005294: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8005298: 6013 str r3, [r2, #0] 800529a: e01d b.n 80052d8 800529c: 687b ldr r3, [r7, #4] 800529e: 685b ldr r3, [r3, #4] 80052a0: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 80052a4: d10c bne.n 80052c0 80052a6: 4b76 ldr r3, [pc, #472] @ (8005480 ) 80052a8: 681b ldr r3, [r3, #0] 80052aa: 4a75 ldr r2, [pc, #468] @ (8005480 ) 80052ac: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80052b0: 6013 str r3, [r2, #0] 80052b2: 4b73 ldr r3, [pc, #460] @ (8005480 ) 80052b4: 681b ldr r3, [r3, #0] 80052b6: 4a72 ldr r2, [pc, #456] @ (8005480 ) 80052b8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80052bc: 6013 str r3, [r2, #0] 80052be: e00b b.n 80052d8 80052c0: 4b6f ldr r3, [pc, #444] @ (8005480 ) 80052c2: 681b ldr r3, [r3, #0] 80052c4: 4a6e ldr r2, [pc, #440] @ (8005480 ) 80052c6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80052ca: 6013 str r3, [r2, #0] 80052cc: 4b6c ldr r3, [pc, #432] @ (8005480 ) 80052ce: 681b ldr r3, [r3, #0] 80052d0: 4a6b ldr r2, [pc, #428] @ (8005480 ) 80052d2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 80052d6: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 80052d8: 687b ldr r3, [r7, #4] 80052da: 685b ldr r3, [r3, #4] 80052dc: 2b00 cmp r3, #0 80052de: d013 beq.n 8005308 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80052e0: f7fc fe4c bl 8001f7c 80052e4: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80052e6: e008 b.n 80052fa { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80052e8: f7fc fe48 bl 8001f7c 80052ec: 4602 mov r2, r0 80052ee: 693b ldr r3, [r7, #16] 80052f0: 1ad3 subs r3, r2, r3 80052f2: 2b64 cmp r3, #100 @ 0x64 80052f4: d901 bls.n 80052fa { return HAL_TIMEOUT; 80052f6: 2303 movs r3, #3 80052f8: e21f b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80052fa: 4b61 ldr r3, [pc, #388] @ (8005480 ) 80052fc: 681b ldr r3, [r3, #0] 80052fe: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005302: 2b00 cmp r3, #0 8005304: d0f0 beq.n 80052e8 8005306: e014 b.n 8005332 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005308: f7fc fe38 bl 8001f7c 800530c: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800530e: e008 b.n 8005322 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8005310: f7fc fe34 bl 8001f7c 8005314: 4602 mov r2, r0 8005316: 693b ldr r3, [r7, #16] 8005318: 1ad3 subs r3, r2, r3 800531a: 2b64 cmp r3, #100 @ 0x64 800531c: d901 bls.n 8005322 { return HAL_TIMEOUT; 800531e: 2303 movs r3, #3 8005320: e20b b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8005322: 4b57 ldr r3, [pc, #348] @ (8005480 ) 8005324: 681b ldr r3, [r3, #0] 8005326: f403 3300 and.w r3, r3, #131072 @ 0x20000 800532a: 2b00 cmp r3, #0 800532c: d1f0 bne.n 8005310 800532e: e000 b.n 8005332 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8005330: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8005332: 687b ldr r3, [r7, #4] 8005334: 681b ldr r3, [r3, #0] 8005336: f003 0302 and.w r3, r3, #2 800533a: 2b00 cmp r3, #0 800533c: d06f beq.n 800541e assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 800533e: 4b50 ldr r3, [pc, #320] @ (8005480 ) 8005340: 689b ldr r3, [r3, #8] 8005342: f003 030c and.w r3, r3, #12 8005346: 2b00 cmp r3, #0 8005348: d017 beq.n 800537a || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 800534a: 4b4d ldr r3, [pc, #308] @ (8005480 ) 800534c: 689b ldr r3, [r3, #8] 800534e: f003 030c and.w r3, r3, #12 || \ 8005352: 2b08 cmp r3, #8 8005354: d105 bne.n 8005362 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8005356: 4b4a ldr r3, [pc, #296] @ (8005480 ) 8005358: 685b ldr r3, [r3, #4] 800535a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800535e: 2b00 cmp r3, #0 8005360: d00b beq.n 800537a ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8005362: 4b47 ldr r3, [pc, #284] @ (8005480 ) 8005364: 689b ldr r3, [r3, #8] 8005366: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 800536a: 2b0c cmp r3, #12 800536c: d11c bne.n 80053a8 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 800536e: 4b44 ldr r3, [pc, #272] @ (8005480 ) 8005370: 685b ldr r3, [r3, #4] 8005372: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8005376: 2b00 cmp r3, #0 8005378: d116 bne.n 80053a8 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800537a: 4b41 ldr r3, [pc, #260] @ (8005480 ) 800537c: 681b ldr r3, [r3, #0] 800537e: f003 0302 and.w r3, r3, #2 8005382: 2b00 cmp r3, #0 8005384: d005 beq.n 8005392 8005386: 687b ldr r3, [r7, #4] 8005388: 68db ldr r3, [r3, #12] 800538a: 2b01 cmp r3, #1 800538c: d001 beq.n 8005392 { return HAL_ERROR; 800538e: 2301 movs r3, #1 8005390: e1d3 b.n 800573a } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005392: 4b3b ldr r3, [pc, #236] @ (8005480 ) 8005394: 681b ldr r3, [r3, #0] 8005396: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800539a: 687b ldr r3, [r7, #4] 800539c: 691b ldr r3, [r3, #16] 800539e: 00db lsls r3, r3, #3 80053a0: 4937 ldr r1, [pc, #220] @ (8005480 ) 80053a2: 4313 orrs r3, r2 80053a4: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80053a6: e03a b.n 800541e } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 80053a8: 687b ldr r3, [r7, #4] 80053aa: 68db ldr r3, [r3, #12] 80053ac: 2b00 cmp r3, #0 80053ae: d020 beq.n 80053f2 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80053b0: 4b34 ldr r3, [pc, #208] @ (8005484 ) 80053b2: 2201 movs r2, #1 80053b4: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80053b6: f7fc fde1 bl 8001f7c 80053ba: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80053bc: e008 b.n 80053d0 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80053be: f7fc fddd bl 8001f7c 80053c2: 4602 mov r2, r0 80053c4: 693b ldr r3, [r7, #16] 80053c6: 1ad3 subs r3, r2, r3 80053c8: 2b02 cmp r3, #2 80053ca: d901 bls.n 80053d0 { return HAL_TIMEOUT; 80053cc: 2303 movs r3, #3 80053ce: e1b4 b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80053d0: 4b2b ldr r3, [pc, #172] @ (8005480 ) 80053d2: 681b ldr r3, [r3, #0] 80053d4: f003 0302 and.w r3, r3, #2 80053d8: 2b00 cmp r3, #0 80053da: d0f0 beq.n 80053be } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80053dc: 4b28 ldr r3, [pc, #160] @ (8005480 ) 80053de: 681b ldr r3, [r3, #0] 80053e0: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80053e4: 687b ldr r3, [r7, #4] 80053e6: 691b ldr r3, [r3, #16] 80053e8: 00db lsls r3, r3, #3 80053ea: 4925 ldr r1, [pc, #148] @ (8005480 ) 80053ec: 4313 orrs r3, r2 80053ee: 600b str r3, [r1, #0] 80053f0: e015 b.n 800541e } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80053f2: 4b24 ldr r3, [pc, #144] @ (8005484 ) 80053f4: 2200 movs r2, #0 80053f6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80053f8: f7fc fdc0 bl 8001f7c 80053fc: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80053fe: e008 b.n 8005412 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005400: f7fc fdbc bl 8001f7c 8005404: 4602 mov r2, r0 8005406: 693b ldr r3, [r7, #16] 8005408: 1ad3 subs r3, r2, r3 800540a: 2b02 cmp r3, #2 800540c: d901 bls.n 8005412 { return HAL_TIMEOUT; 800540e: 2303 movs r3, #3 8005410: e193 b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8005412: 4b1b ldr r3, [pc, #108] @ (8005480 ) 8005414: 681b ldr r3, [r3, #0] 8005416: f003 0302 and.w r3, r3, #2 800541a: 2b00 cmp r3, #0 800541c: d1f0 bne.n 8005400 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800541e: 687b ldr r3, [r7, #4] 8005420: 681b ldr r3, [r3, #0] 8005422: f003 0308 and.w r3, r3, #8 8005426: 2b00 cmp r3, #0 8005428: d036 beq.n 8005498 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800542a: 687b ldr r3, [r7, #4] 800542c: 695b ldr r3, [r3, #20] 800542e: 2b00 cmp r3, #0 8005430: d016 beq.n 8005460 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8005432: 4b15 ldr r3, [pc, #84] @ (8005488 ) 8005434: 2201 movs r2, #1 8005436: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005438: f7fc fda0 bl 8001f7c 800543c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800543e: e008 b.n 8005452 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8005440: f7fc fd9c bl 8001f7c 8005444: 4602 mov r2, r0 8005446: 693b ldr r3, [r7, #16] 8005448: 1ad3 subs r3, r2, r3 800544a: 2b02 cmp r3, #2 800544c: d901 bls.n 8005452 { return HAL_TIMEOUT; 800544e: 2303 movs r3, #3 8005450: e173 b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8005452: 4b0b ldr r3, [pc, #44] @ (8005480 ) 8005454: 6f5b ldr r3, [r3, #116] @ 0x74 8005456: f003 0302 and.w r3, r3, #2 800545a: 2b00 cmp r3, #0 800545c: d0f0 beq.n 8005440 800545e: e01b b.n 8005498 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8005460: 4b09 ldr r3, [pc, #36] @ (8005488 ) 8005462: 2200 movs r2, #0 8005464: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005466: f7fc fd89 bl 8001f7c 800546a: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800546c: e00e b.n 800548c { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800546e: f7fc fd85 bl 8001f7c 8005472: 4602 mov r2, r0 8005474: 693b ldr r3, [r7, #16] 8005476: 1ad3 subs r3, r2, r3 8005478: 2b02 cmp r3, #2 800547a: d907 bls.n 800548c { return HAL_TIMEOUT; 800547c: 2303 movs r3, #3 800547e: e15c b.n 800573a 8005480: 40023800 .word 0x40023800 8005484: 42470000 .word 0x42470000 8005488: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800548c: 4b8a ldr r3, [pc, #552] @ (80056b8 ) 800548e: 6f5b ldr r3, [r3, #116] @ 0x74 8005490: f003 0302 and.w r3, r3, #2 8005494: 2b00 cmp r3, #0 8005496: d1ea bne.n 800546e } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8005498: 687b ldr r3, [r7, #4] 800549a: 681b ldr r3, [r3, #0] 800549c: f003 0304 and.w r3, r3, #4 80054a0: 2b00 cmp r3, #0 80054a2: f000 8097 beq.w 80055d4 { FlagStatus pwrclkchanged = RESET; 80054a6: 2300 movs r3, #0 80054a8: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80054aa: 4b83 ldr r3, [pc, #524] @ (80056b8 ) 80054ac: 6c1b ldr r3, [r3, #64] @ 0x40 80054ae: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80054b2: 2b00 cmp r3, #0 80054b4: d10f bne.n 80054d6 { __HAL_RCC_PWR_CLK_ENABLE(); 80054b6: 2300 movs r3, #0 80054b8: 60bb str r3, [r7, #8] 80054ba: 4b7f ldr r3, [pc, #508] @ (80056b8 ) 80054bc: 6c1b ldr r3, [r3, #64] @ 0x40 80054be: 4a7e ldr r2, [pc, #504] @ (80056b8 ) 80054c0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80054c4: 6413 str r3, [r2, #64] @ 0x40 80054c6: 4b7c ldr r3, [pc, #496] @ (80056b8 ) 80054c8: 6c1b ldr r3, [r3, #64] @ 0x40 80054ca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80054ce: 60bb str r3, [r7, #8] 80054d0: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80054d2: 2301 movs r3, #1 80054d4: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80054d6: 4b79 ldr r3, [pc, #484] @ (80056bc ) 80054d8: 681b ldr r3, [r3, #0] 80054da: f403 7380 and.w r3, r3, #256 @ 0x100 80054de: 2b00 cmp r3, #0 80054e0: d118 bne.n 8005514 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80054e2: 4b76 ldr r3, [pc, #472] @ (80056bc ) 80054e4: 681b ldr r3, [r3, #0] 80054e6: 4a75 ldr r2, [pc, #468] @ (80056bc ) 80054e8: f443 7380 orr.w r3, r3, #256 @ 0x100 80054ec: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80054ee: f7fc fd45 bl 8001f7c 80054f2: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80054f4: e008 b.n 8005508 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80054f6: f7fc fd41 bl 8001f7c 80054fa: 4602 mov r2, r0 80054fc: 693b ldr r3, [r7, #16] 80054fe: 1ad3 subs r3, r2, r3 8005500: 2b02 cmp r3, #2 8005502: d901 bls.n 8005508 { return HAL_TIMEOUT; 8005504: 2303 movs r3, #3 8005506: e118 b.n 800573a while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005508: 4b6c ldr r3, [pc, #432] @ (80056bc ) 800550a: 681b ldr r3, [r3, #0] 800550c: f403 7380 and.w r3, r3, #256 @ 0x100 8005510: 2b00 cmp r3, #0 8005512: d0f0 beq.n 80054f6 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8005514: 687b ldr r3, [r7, #4] 8005516: 689b ldr r3, [r3, #8] 8005518: 2b01 cmp r3, #1 800551a: d106 bne.n 800552a 800551c: 4b66 ldr r3, [pc, #408] @ (80056b8 ) 800551e: 6f1b ldr r3, [r3, #112] @ 0x70 8005520: 4a65 ldr r2, [pc, #404] @ (80056b8 ) 8005522: f043 0301 orr.w r3, r3, #1 8005526: 6713 str r3, [r2, #112] @ 0x70 8005528: e01c b.n 8005564 800552a: 687b ldr r3, [r7, #4] 800552c: 689b ldr r3, [r3, #8] 800552e: 2b05 cmp r3, #5 8005530: d10c bne.n 800554c 8005532: 4b61 ldr r3, [pc, #388] @ (80056b8 ) 8005534: 6f1b ldr r3, [r3, #112] @ 0x70 8005536: 4a60 ldr r2, [pc, #384] @ (80056b8 ) 8005538: f043 0304 orr.w r3, r3, #4 800553c: 6713 str r3, [r2, #112] @ 0x70 800553e: 4b5e ldr r3, [pc, #376] @ (80056b8 ) 8005540: 6f1b ldr r3, [r3, #112] @ 0x70 8005542: 4a5d ldr r2, [pc, #372] @ (80056b8 ) 8005544: f043 0301 orr.w r3, r3, #1 8005548: 6713 str r3, [r2, #112] @ 0x70 800554a: e00b b.n 8005564 800554c: 4b5a ldr r3, [pc, #360] @ (80056b8 ) 800554e: 6f1b ldr r3, [r3, #112] @ 0x70 8005550: 4a59 ldr r2, [pc, #356] @ (80056b8 ) 8005552: f023 0301 bic.w r3, r3, #1 8005556: 6713 str r3, [r2, #112] @ 0x70 8005558: 4b57 ldr r3, [pc, #348] @ (80056b8 ) 800555a: 6f1b ldr r3, [r3, #112] @ 0x70 800555c: 4a56 ldr r2, [pc, #344] @ (80056b8 ) 800555e: f023 0304 bic.w r3, r3, #4 8005562: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8005564: 687b ldr r3, [r7, #4] 8005566: 689b ldr r3, [r3, #8] 8005568: 2b00 cmp r3, #0 800556a: d015 beq.n 8005598 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800556c: f7fc fd06 bl 8001f7c 8005570: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005572: e00a b.n 800558a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005574: f7fc fd02 bl 8001f7c 8005578: 4602 mov r2, r0 800557a: 693b ldr r3, [r7, #16] 800557c: 1ad3 subs r3, r2, r3 800557e: f241 3288 movw r2, #5000 @ 0x1388 8005582: 4293 cmp r3, r2 8005584: d901 bls.n 800558a { return HAL_TIMEOUT; 8005586: 2303 movs r3, #3 8005588: e0d7 b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800558a: 4b4b ldr r3, [pc, #300] @ (80056b8 ) 800558c: 6f1b ldr r3, [r3, #112] @ 0x70 800558e: f003 0302 and.w r3, r3, #2 8005592: 2b00 cmp r3, #0 8005594: d0ee beq.n 8005574 8005596: e014 b.n 80055c2 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005598: f7fc fcf0 bl 8001f7c 800559c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800559e: e00a b.n 80055b6 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80055a0: f7fc fcec bl 8001f7c 80055a4: 4602 mov r2, r0 80055a6: 693b ldr r3, [r7, #16] 80055a8: 1ad3 subs r3, r2, r3 80055aa: f241 3288 movw r2, #5000 @ 0x1388 80055ae: 4293 cmp r3, r2 80055b0: d901 bls.n 80055b6 { return HAL_TIMEOUT; 80055b2: 2303 movs r3, #3 80055b4: e0c1 b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80055b6: 4b40 ldr r3, [pc, #256] @ (80056b8 ) 80055b8: 6f1b ldr r3, [r3, #112] @ 0x70 80055ba: f003 0302 and.w r3, r3, #2 80055be: 2b00 cmp r3, #0 80055c0: d1ee bne.n 80055a0 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80055c2: 7dfb ldrb r3, [r7, #23] 80055c4: 2b01 cmp r3, #1 80055c6: d105 bne.n 80055d4 { __HAL_RCC_PWR_CLK_DISABLE(); 80055c8: 4b3b ldr r3, [pc, #236] @ (80056b8 ) 80055ca: 6c1b ldr r3, [r3, #64] @ 0x40 80055cc: 4a3a ldr r2, [pc, #232] @ (80056b8 ) 80055ce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80055d2: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80055d4: 687b ldr r3, [r7, #4] 80055d6: 699b ldr r3, [r3, #24] 80055d8: 2b00 cmp r3, #0 80055da: f000 80ad beq.w 8005738 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 80055de: 4b36 ldr r3, [pc, #216] @ (80056b8 ) 80055e0: 689b ldr r3, [r3, #8] 80055e2: f003 030c and.w r3, r3, #12 80055e6: 2b08 cmp r3, #8 80055e8: d060 beq.n 80056ac { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80055ea: 687b ldr r3, [r7, #4] 80055ec: 699b ldr r3, [r3, #24] 80055ee: 2b02 cmp r3, #2 80055f0: d145 bne.n 800567e assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80055f2: 4b33 ldr r3, [pc, #204] @ (80056c0 ) 80055f4: 2200 movs r2, #0 80055f6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80055f8: f7fc fcc0 bl 8001f7c 80055fc: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80055fe: e008 b.n 8005612 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005600: f7fc fcbc bl 8001f7c 8005604: 4602 mov r2, r0 8005606: 693b ldr r3, [r7, #16] 8005608: 1ad3 subs r3, r2, r3 800560a: 2b02 cmp r3, #2 800560c: d901 bls.n 8005612 { return HAL_TIMEOUT; 800560e: 2303 movs r3, #3 8005610: e093 b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005612: 4b29 ldr r3, [pc, #164] @ (80056b8 ) 8005614: 681b ldr r3, [r3, #0] 8005616: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800561a: 2b00 cmp r3, #0 800561c: d1f0 bne.n 8005600 } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 800561e: 687b ldr r3, [r7, #4] 8005620: 69da ldr r2, [r3, #28] 8005622: 687b ldr r3, [r7, #4] 8005624: 6a1b ldr r3, [r3, #32] 8005626: 431a orrs r2, r3 8005628: 687b ldr r3, [r7, #4] 800562a: 6a5b ldr r3, [r3, #36] @ 0x24 800562c: 019b lsls r3, r3, #6 800562e: 431a orrs r2, r3 8005630: 687b ldr r3, [r7, #4] 8005632: 6a9b ldr r3, [r3, #40] @ 0x28 8005634: 085b lsrs r3, r3, #1 8005636: 3b01 subs r3, #1 8005638: 041b lsls r3, r3, #16 800563a: 431a orrs r2, r3 800563c: 687b ldr r3, [r7, #4] 800563e: 6adb ldr r3, [r3, #44] @ 0x2c 8005640: 061b lsls r3, r3, #24 8005642: 431a orrs r2, r3 8005644: 687b ldr r3, [r7, #4] 8005646: 6b1b ldr r3, [r3, #48] @ 0x30 8005648: 071b lsls r3, r3, #28 800564a: 491b ldr r1, [pc, #108] @ (80056b8 ) 800564c: 4313 orrs r3, r2 800564e: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8005650: 4b1b ldr r3, [pc, #108] @ (80056c0 ) 8005652: 2201 movs r2, #1 8005654: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005656: f7fc fc91 bl 8001f7c 800565a: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800565c: e008 b.n 8005670 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800565e: f7fc fc8d bl 8001f7c 8005662: 4602 mov r2, r0 8005664: 693b ldr r3, [r7, #16] 8005666: 1ad3 subs r3, r2, r3 8005668: 2b02 cmp r3, #2 800566a: d901 bls.n 8005670 { return HAL_TIMEOUT; 800566c: 2303 movs r3, #3 800566e: e064 b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005670: 4b11 ldr r3, [pc, #68] @ (80056b8 ) 8005672: 681b ldr r3, [r3, #0] 8005674: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005678: 2b00 cmp r3, #0 800567a: d0f0 beq.n 800565e 800567c: e05c b.n 8005738 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800567e: 4b10 ldr r3, [pc, #64] @ (80056c0 ) 8005680: 2200 movs r2, #0 8005682: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005684: f7fc fc7a bl 8001f7c 8005688: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800568a: e008 b.n 800569e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800568c: f7fc fc76 bl 8001f7c 8005690: 4602 mov r2, r0 8005692: 693b ldr r3, [r7, #16] 8005694: 1ad3 subs r3, r2, r3 8005696: 2b02 cmp r3, #2 8005698: d901 bls.n 800569e { return HAL_TIMEOUT; 800569a: 2303 movs r3, #3 800569c: e04d b.n 800573a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800569e: 4b06 ldr r3, [pc, #24] @ (80056b8 ) 80056a0: 681b ldr r3, [r3, #0] 80056a2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80056a6: 2b00 cmp r3, #0 80056a8: d1f0 bne.n 800568c 80056aa: e045 b.n 8005738 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80056ac: 687b ldr r3, [r7, #4] 80056ae: 699b ldr r3, [r3, #24] 80056b0: 2b01 cmp r3, #1 80056b2: d107 bne.n 80056c4 { return HAL_ERROR; 80056b4: 2301 movs r3, #1 80056b6: e040 b.n 800573a 80056b8: 40023800 .word 0x40023800 80056bc: 40007000 .word 0x40007000 80056c0: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 80056c4: 4b1f ldr r3, [pc, #124] @ (8005744 ) 80056c6: 685b ldr r3, [r3, #4] 80056c8: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80056ca: 687b ldr r3, [r7, #4] 80056cc: 699b ldr r3, [r3, #24] 80056ce: 2b01 cmp r3, #1 80056d0: d030 beq.n 8005734 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80056d2: 68fb ldr r3, [r7, #12] 80056d4: f403 0280 and.w r2, r3, #4194304 @ 0x400000 80056d8: 687b ldr r3, [r7, #4] 80056da: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80056dc: 429a cmp r2, r3 80056de: d129 bne.n 8005734 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80056e0: 68fb ldr r3, [r7, #12] 80056e2: f003 023f and.w r2, r3, #63 @ 0x3f 80056e6: 687b ldr r3, [r7, #4] 80056e8: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80056ea: 429a cmp r2, r3 80056ec: d122 bne.n 8005734 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80056ee: 68fa ldr r2, [r7, #12] 80056f0: f647 73c0 movw r3, #32704 @ 0x7fc0 80056f4: 4013 ands r3, r2 80056f6: 687a ldr r2, [r7, #4] 80056f8: 6a52 ldr r2, [r2, #36] @ 0x24 80056fa: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80056fc: 4293 cmp r3, r2 80056fe: d119 bne.n 8005734 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8005700: 68fb ldr r3, [r7, #12] 8005702: f403 3240 and.w r2, r3, #196608 @ 0x30000 8005706: 687b ldr r3, [r7, #4] 8005708: 6a9b ldr r3, [r3, #40] @ 0x28 800570a: 085b lsrs r3, r3, #1 800570c: 3b01 subs r3, #1 800570e: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8005710: 429a cmp r2, r3 8005712: d10f bne.n 8005734 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8005714: 68fb ldr r3, [r7, #12] 8005716: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 800571a: 687b ldr r3, [r7, #4] 800571c: 6adb ldr r3, [r3, #44] @ 0x2c 800571e: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8005720: 429a cmp r2, r3 8005722: d107 bne.n 8005734 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 8005724: 68fb ldr r3, [r7, #12] 8005726: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 800572a: 687b ldr r3, [r7, #4] 800572c: 6b1b ldr r3, [r3, #48] @ 0x30 800572e: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8005730: 429a cmp r2, r3 8005732: d001 beq.n 8005738 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 8005734: 2301 movs r3, #1 8005736: e000 b.n 800573a } } } } return HAL_OK; 8005738: 2300 movs r3, #0 } 800573a: 4618 mov r0, r3 800573c: 3718 adds r7, #24 800573e: 46bd mov sp, r7 8005740: bd80 pop {r7, pc} 8005742: bf00 nop 8005744: 40023800 .word 0x40023800 08005748 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8005748: b580 push {r7, lr} 800574a: b082 sub sp, #8 800574c: af00 add r7, sp, #0 800574e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8005750: 687b ldr r3, [r7, #4] 8005752: 2b00 cmp r3, #0 8005754: d101 bne.n 800575a { return HAL_ERROR; 8005756: 2301 movs r3, #1 8005758: e041 b.n 80057de assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800575a: 687b ldr r3, [r7, #4] 800575c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8005760: b2db uxtb r3, r3 8005762: 2b00 cmp r3, #0 8005764: d106 bne.n 8005774 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005766: 687b ldr r3, [r7, #4] 8005768: 2200 movs r2, #0 800576a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800576e: 6878 ldr r0, [r7, #4] 8005770: f000 f839 bl 80057e6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005774: 687b ldr r3, [r7, #4] 8005776: 2202 movs r2, #2 8005778: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800577c: 687b ldr r3, [r7, #4] 800577e: 681a ldr r2, [r3, #0] 8005780: 687b ldr r3, [r7, #4] 8005782: 3304 adds r3, #4 8005784: 4619 mov r1, r3 8005786: 4610 mov r0, r2 8005788: f000 fdae bl 80062e8 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800578c: 687b ldr r3, [r7, #4] 800578e: 2201 movs r2, #1 8005790: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005794: 687b ldr r3, [r7, #4] 8005796: 2201 movs r2, #1 8005798: f883 203e strb.w r2, [r3, #62] @ 0x3e 800579c: 687b ldr r3, [r7, #4] 800579e: 2201 movs r2, #1 80057a0: f883 203f strb.w r2, [r3, #63] @ 0x3f 80057a4: 687b ldr r3, [r7, #4] 80057a6: 2201 movs r2, #1 80057a8: f883 2040 strb.w r2, [r3, #64] @ 0x40 80057ac: 687b ldr r3, [r7, #4] 80057ae: 2201 movs r2, #1 80057b0: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80057b4: 687b ldr r3, [r7, #4] 80057b6: 2201 movs r2, #1 80057b8: f883 2042 strb.w r2, [r3, #66] @ 0x42 80057bc: 687b ldr r3, [r7, #4] 80057be: 2201 movs r2, #1 80057c0: f883 2043 strb.w r2, [r3, #67] @ 0x43 80057c4: 687b ldr r3, [r7, #4] 80057c6: 2201 movs r2, #1 80057c8: f883 2044 strb.w r2, [r3, #68] @ 0x44 80057cc: 687b ldr r3, [r7, #4] 80057ce: 2201 movs r2, #1 80057d0: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80057d4: 687b ldr r3, [r7, #4] 80057d6: 2201 movs r2, #1 80057d8: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80057dc: 2300 movs r3, #0 } 80057de: 4618 mov r0, r3 80057e0: 3708 adds r7, #8 80057e2: 46bd mov sp, r7 80057e4: bd80 pop {r7, pc} 080057e6 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 80057e6: b480 push {r7} 80057e8: b083 sub sp, #12 80057ea: af00 add r7, sp, #0 80057ec: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 80057ee: bf00 nop 80057f0: 370c adds r7, #12 80057f2: 46bd mov sp, r7 80057f4: f85d 7b04 ldr.w r7, [sp], #4 80057f8: 4770 bx lr ... 080057fc : * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length) { 80057fc: b580 push {r7, lr} 80057fe: b086 sub sp, #24 8005800: af00 add r7, sp, #0 8005802: 60f8 str r0, [r7, #12] 8005804: 60b9 str r1, [r7, #8] 8005806: 607a str r2, [r7, #4] 8005808: 807b strh r3, [r7, #2] HAL_StatusTypeDef status = HAL_OK; 800580a: 2300 movs r3, #0 800580c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) 800580e: 68bb ldr r3, [r7, #8] 8005810: 2b00 cmp r3, #0 8005812: d109 bne.n 8005828 8005814: 68fb ldr r3, [r7, #12] 8005816: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800581a: b2db uxtb r3, r3 800581c: 2b02 cmp r3, #2 800581e: bf0c ite eq 8005820: 2301 moveq r3, #1 8005822: 2300 movne r3, #0 8005824: b2db uxtb r3, r3 8005826: e022 b.n 800586e 8005828: 68bb ldr r3, [r7, #8] 800582a: 2b04 cmp r3, #4 800582c: d109 bne.n 8005842 800582e: 68fb ldr r3, [r7, #12] 8005830: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8005834: b2db uxtb r3, r3 8005836: 2b02 cmp r3, #2 8005838: bf0c ite eq 800583a: 2301 moveq r3, #1 800583c: 2300 movne r3, #0 800583e: b2db uxtb r3, r3 8005840: e015 b.n 800586e 8005842: 68bb ldr r3, [r7, #8] 8005844: 2b08 cmp r3, #8 8005846: d109 bne.n 800585c 8005848: 68fb ldr r3, [r7, #12] 800584a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800584e: b2db uxtb r3, r3 8005850: 2b02 cmp r3, #2 8005852: bf0c ite eq 8005854: 2301 moveq r3, #1 8005856: 2300 movne r3, #0 8005858: b2db uxtb r3, r3 800585a: e008 b.n 800586e 800585c: 68fb ldr r3, [r7, #12] 800585e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005862: b2db uxtb r3, r3 8005864: 2b02 cmp r3, #2 8005866: bf0c ite eq 8005868: 2301 moveq r3, #1 800586a: 2300 movne r3, #0 800586c: b2db uxtb r3, r3 800586e: 2b00 cmp r3, #0 8005870: d001 beq.n 8005876 { return HAL_BUSY; 8005872: 2302 movs r3, #2 8005874: e171 b.n 8005b5a } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) 8005876: 68bb ldr r3, [r7, #8] 8005878: 2b00 cmp r3, #0 800587a: d109 bne.n 8005890 800587c: 68fb ldr r3, [r7, #12] 800587e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8005882: b2db uxtb r3, r3 8005884: 2b01 cmp r3, #1 8005886: bf0c ite eq 8005888: 2301 moveq r3, #1 800588a: 2300 movne r3, #0 800588c: b2db uxtb r3, r3 800588e: e022 b.n 80058d6 8005890: 68bb ldr r3, [r7, #8] 8005892: 2b04 cmp r3, #4 8005894: d109 bne.n 80058aa 8005896: 68fb ldr r3, [r7, #12] 8005898: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800589c: b2db uxtb r3, r3 800589e: 2b01 cmp r3, #1 80058a0: bf0c ite eq 80058a2: 2301 moveq r3, #1 80058a4: 2300 movne r3, #0 80058a6: b2db uxtb r3, r3 80058a8: e015 b.n 80058d6 80058aa: 68bb ldr r3, [r7, #8] 80058ac: 2b08 cmp r3, #8 80058ae: d109 bne.n 80058c4 80058b0: 68fb ldr r3, [r7, #12] 80058b2: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80058b6: b2db uxtb r3, r3 80058b8: 2b01 cmp r3, #1 80058ba: bf0c ite eq 80058bc: 2301 moveq r3, #1 80058be: 2300 movne r3, #0 80058c0: b2db uxtb r3, r3 80058c2: e008 b.n 80058d6 80058c4: 68fb ldr r3, [r7, #12] 80058c6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80058ca: b2db uxtb r3, r3 80058cc: 2b01 cmp r3, #1 80058ce: bf0c ite eq 80058d0: 2301 moveq r3, #1 80058d2: 2300 movne r3, #0 80058d4: b2db uxtb r3, r3 80058d6: 2b00 cmp r3, #0 80058d8: d024 beq.n 8005924 { if ((pData == NULL) || (Length == 0U)) 80058da: 687b ldr r3, [r7, #4] 80058dc: 2b00 cmp r3, #0 80058de: d002 beq.n 80058e6 80058e0: 887b ldrh r3, [r7, #2] 80058e2: 2b00 cmp r3, #0 80058e4: d101 bne.n 80058ea { return HAL_ERROR; 80058e6: 2301 movs r3, #1 80058e8: e137 b.n 8005b5a } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 80058ea: 68bb ldr r3, [r7, #8] 80058ec: 2b00 cmp r3, #0 80058ee: d104 bne.n 80058fa 80058f0: 68fb ldr r3, [r7, #12] 80058f2: 2202 movs r2, #2 80058f4: f883 203e strb.w r2, [r3, #62] @ 0x3e 80058f8: e016 b.n 8005928 80058fa: 68bb ldr r3, [r7, #8] 80058fc: 2b04 cmp r3, #4 80058fe: d104 bne.n 800590a 8005900: 68fb ldr r3, [r7, #12] 8005902: 2202 movs r2, #2 8005904: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005908: e00e b.n 8005928 800590a: 68bb ldr r3, [r7, #8] 800590c: 2b08 cmp r3, #8 800590e: d104 bne.n 800591a 8005910: 68fb ldr r3, [r7, #12] 8005912: 2202 movs r2, #2 8005914: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005918: e006 b.n 8005928 800591a: 68fb ldr r3, [r7, #12] 800591c: 2202 movs r2, #2 800591e: f883 2041 strb.w r2, [r3, #65] @ 0x41 8005922: e001 b.n 8005928 } } else { return HAL_ERROR; 8005924: 2301 movs r3, #1 8005926: e118 b.n 8005b5a } switch (Channel) 8005928: 68bb ldr r3, [r7, #8] 800592a: 2b0c cmp r3, #12 800592c: f200 80ae bhi.w 8005a8c 8005930: a201 add r2, pc, #4 @ (adr r2, 8005938 ) 8005932: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005936: bf00 nop 8005938: 0800596d .word 0x0800596d 800593c: 08005a8d .word 0x08005a8d 8005940: 08005a8d .word 0x08005a8d 8005944: 08005a8d .word 0x08005a8d 8005948: 080059b5 .word 0x080059b5 800594c: 08005a8d .word 0x08005a8d 8005950: 08005a8d .word 0x08005a8d 8005954: 08005a8d .word 0x08005a8d 8005958: 080059fd .word 0x080059fd 800595c: 08005a8d .word 0x08005a8d 8005960: 08005a8d .word 0x08005a8d 8005964: 08005a8d .word 0x08005a8d 8005968: 08005a45 .word 0x08005a45 { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 800596c: 68fb ldr r3, [r7, #12] 800596e: 6a5b ldr r3, [r3, #36] @ 0x24 8005970: 4a7c ldr r2, [pc, #496] @ (8005b64 ) 8005972: 63da str r2, [r3, #60] @ 0x3c htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; 8005974: 68fb ldr r3, [r7, #12] 8005976: 6a5b ldr r3, [r3, #36] @ 0x24 8005978: 4a7b ldr r2, [pc, #492] @ (8005b68 ) 800597a: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 800597c: 68fb ldr r3, [r7, #12] 800597e: 6a5b ldr r3, [r3, #36] @ 0x24 8005980: 4a7a ldr r2, [pc, #488] @ (8005b6c ) 8005982: 64da str r2, [r3, #76] @ 0x4c /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, 8005984: 68fb ldr r3, [r7, #12] 8005986: 6a58 ldr r0, [r3, #36] @ 0x24 8005988: 6879 ldr r1, [r7, #4] 800598a: 68fb ldr r3, [r7, #12] 800598c: 681b ldr r3, [r3, #0] 800598e: 3334 adds r3, #52 @ 0x34 8005990: 461a mov r2, r3 8005992: 887b ldrh r3, [r7, #2] 8005994: f7fc fce2 bl 800235c 8005998: 4603 mov r3, r0 800599a: 2b00 cmp r3, #0 800599c: d001 beq.n 80059a2 Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; 800599e: 2301 movs r3, #1 80059a0: e0db b.n 8005b5a } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 80059a2: 68fb ldr r3, [r7, #12] 80059a4: 681b ldr r3, [r3, #0] 80059a6: 68da ldr r2, [r3, #12] 80059a8: 68fb ldr r3, [r7, #12] 80059aa: 681b ldr r3, [r3, #0] 80059ac: f442 7200 orr.w r2, r2, #512 @ 0x200 80059b0: 60da str r2, [r3, #12] break; 80059b2: e06e b.n 8005a92 } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 80059b4: 68fb ldr r3, [r7, #12] 80059b6: 6a9b ldr r3, [r3, #40] @ 0x28 80059b8: 4a6a ldr r2, [pc, #424] @ (8005b64 ) 80059ba: 63da str r2, [r3, #60] @ 0x3c htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; 80059bc: 68fb ldr r3, [r7, #12] 80059be: 6a9b ldr r3, [r3, #40] @ 0x28 80059c0: 4a69 ldr r2, [pc, #420] @ (8005b68 ) 80059c2: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 80059c4: 68fb ldr r3, [r7, #12] 80059c6: 6a9b ldr r3, [r3, #40] @ 0x28 80059c8: 4a68 ldr r2, [pc, #416] @ (8005b6c ) 80059ca: 64da str r2, [r3, #76] @ 0x4c /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, 80059cc: 68fb ldr r3, [r7, #12] 80059ce: 6a98 ldr r0, [r3, #40] @ 0x28 80059d0: 6879 ldr r1, [r7, #4] 80059d2: 68fb ldr r3, [r7, #12] 80059d4: 681b ldr r3, [r3, #0] 80059d6: 3338 adds r3, #56 @ 0x38 80059d8: 461a mov r2, r3 80059da: 887b ldrh r3, [r7, #2] 80059dc: f7fc fcbe bl 800235c 80059e0: 4603 mov r3, r0 80059e2: 2b00 cmp r3, #0 80059e4: d001 beq.n 80059ea Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; 80059e6: 2301 movs r3, #1 80059e8: e0b7 b.n 8005b5a } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 80059ea: 68fb ldr r3, [r7, #12] 80059ec: 681b ldr r3, [r3, #0] 80059ee: 68da ldr r2, [r3, #12] 80059f0: 68fb ldr r3, [r7, #12] 80059f2: 681b ldr r3, [r3, #0] 80059f4: f442 6280 orr.w r2, r2, #1024 @ 0x400 80059f8: 60da str r2, [r3, #12] break; 80059fa: e04a b.n 8005a92 } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 80059fc: 68fb ldr r3, [r7, #12] 80059fe: 6adb ldr r3, [r3, #44] @ 0x2c 8005a00: 4a58 ldr r2, [pc, #352] @ (8005b64 ) 8005a02: 63da str r2, [r3, #60] @ 0x3c htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; 8005a04: 68fb ldr r3, [r7, #12] 8005a06: 6adb ldr r3, [r3, #44] @ 0x2c 8005a08: 4a57 ldr r2, [pc, #348] @ (8005b68 ) 8005a0a: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 8005a0c: 68fb ldr r3, [r7, #12] 8005a0e: 6adb ldr r3, [r3, #44] @ 0x2c 8005a10: 4a56 ldr r2, [pc, #344] @ (8005b6c ) 8005a12: 64da str r2, [r3, #76] @ 0x4c /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, 8005a14: 68fb ldr r3, [r7, #12] 8005a16: 6ad8 ldr r0, [r3, #44] @ 0x2c 8005a18: 6879 ldr r1, [r7, #4] 8005a1a: 68fb ldr r3, [r7, #12] 8005a1c: 681b ldr r3, [r3, #0] 8005a1e: 333c adds r3, #60 @ 0x3c 8005a20: 461a mov r2, r3 8005a22: 887b ldrh r3, [r7, #2] 8005a24: f7fc fc9a bl 800235c 8005a28: 4603 mov r3, r0 8005a2a: 2b00 cmp r3, #0 8005a2c: d001 beq.n 8005a32 Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; 8005a2e: 2301 movs r3, #1 8005a30: e093 b.n 8005b5a } /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 8005a32: 68fb ldr r3, [r7, #12] 8005a34: 681b ldr r3, [r3, #0] 8005a36: 68da ldr r2, [r3, #12] 8005a38: 68fb ldr r3, [r7, #12] 8005a3a: 681b ldr r3, [r3, #0] 8005a3c: f442 6200 orr.w r2, r2, #2048 @ 0x800 8005a40: 60da str r2, [r3, #12] break; 8005a42: e026 b.n 8005a92 } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 8005a44: 68fb ldr r3, [r7, #12] 8005a46: 6b1b ldr r3, [r3, #48] @ 0x30 8005a48: 4a46 ldr r2, [pc, #280] @ (8005b64 ) 8005a4a: 63da str r2, [r3, #60] @ 0x3c htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; 8005a4c: 68fb ldr r3, [r7, #12] 8005a4e: 6b1b ldr r3, [r3, #48] @ 0x30 8005a50: 4a45 ldr r2, [pc, #276] @ (8005b68 ) 8005a52: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 8005a54: 68fb ldr r3, [r7, #12] 8005a56: 6b1b ldr r3, [r3, #48] @ 0x30 8005a58: 4a44 ldr r2, [pc, #272] @ (8005b6c ) 8005a5a: 64da str r2, [r3, #76] @ 0x4c /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, 8005a5c: 68fb ldr r3, [r7, #12] 8005a5e: 6b18 ldr r0, [r3, #48] @ 0x30 8005a60: 6879 ldr r1, [r7, #4] 8005a62: 68fb ldr r3, [r7, #12] 8005a64: 681b ldr r3, [r3, #0] 8005a66: 3340 adds r3, #64 @ 0x40 8005a68: 461a mov r2, r3 8005a6a: 887b ldrh r3, [r7, #2] 8005a6c: f7fc fc76 bl 800235c 8005a70: 4603 mov r3, r0 8005a72: 2b00 cmp r3, #0 8005a74: d001 beq.n 8005a7a Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; 8005a76: 2301 movs r3, #1 8005a78: e06f b.n 8005b5a } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 8005a7a: 68fb ldr r3, [r7, #12] 8005a7c: 681b ldr r3, [r3, #0] 8005a7e: 68da ldr r2, [r3, #12] 8005a80: 68fb ldr r3, [r7, #12] 8005a82: 681b ldr r3, [r3, #0] 8005a84: f442 5280 orr.w r2, r2, #4096 @ 0x1000 8005a88: 60da str r2, [r3, #12] break; 8005a8a: e002 b.n 8005a92 } default: status = HAL_ERROR; 8005a8c: 2301 movs r3, #1 8005a8e: 75fb strb r3, [r7, #23] break; 8005a90: bf00 nop } if (status == HAL_OK) 8005a92: 7dfb ldrb r3, [r7, #23] 8005a94: 2b00 cmp r3, #0 8005a96: d15f bne.n 8005b58 { /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8005a98: 68fb ldr r3, [r7, #12] 8005a9a: 681b ldr r3, [r3, #0] 8005a9c: 2201 movs r2, #1 8005a9e: 68b9 ldr r1, [r7, #8] 8005aa0: 4618 mov r0, r3 8005aa2: f000 fe77 bl 8006794 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8005aa6: 68fb ldr r3, [r7, #12] 8005aa8: 681b ldr r3, [r3, #0] 8005aaa: 4a31 ldr r2, [pc, #196] @ (8005b70 ) 8005aac: 4293 cmp r3, r2 8005aae: d004 beq.n 8005aba 8005ab0: 68fb ldr r3, [r7, #12] 8005ab2: 681b ldr r3, [r3, #0] 8005ab4: 4a2f ldr r2, [pc, #188] @ (8005b74 ) 8005ab6: 4293 cmp r3, r2 8005ab8: d101 bne.n 8005abe 8005aba: 2301 movs r3, #1 8005abc: e000 b.n 8005ac0 8005abe: 2300 movs r3, #0 8005ac0: 2b00 cmp r3, #0 8005ac2: d007 beq.n 8005ad4 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8005ac4: 68fb ldr r3, [r7, #12] 8005ac6: 681b ldr r3, [r3, #0] 8005ac8: 6c5a ldr r2, [r3, #68] @ 0x44 8005aca: 68fb ldr r3, [r7, #12] 8005acc: 681b ldr r3, [r3, #0] 8005ace: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8005ad2: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005ad4: 68fb ldr r3, [r7, #12] 8005ad6: 681b ldr r3, [r3, #0] 8005ad8: 4a25 ldr r2, [pc, #148] @ (8005b70 ) 8005ada: 4293 cmp r3, r2 8005adc: d022 beq.n 8005b24 8005ade: 68fb ldr r3, [r7, #12] 8005ae0: 681b ldr r3, [r3, #0] 8005ae2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005ae6: d01d beq.n 8005b24 8005ae8: 68fb ldr r3, [r7, #12] 8005aea: 681b ldr r3, [r3, #0] 8005aec: 4a22 ldr r2, [pc, #136] @ (8005b78 ) 8005aee: 4293 cmp r3, r2 8005af0: d018 beq.n 8005b24 8005af2: 68fb ldr r3, [r7, #12] 8005af4: 681b ldr r3, [r3, #0] 8005af6: 4a21 ldr r2, [pc, #132] @ (8005b7c ) 8005af8: 4293 cmp r3, r2 8005afa: d013 beq.n 8005b24 8005afc: 68fb ldr r3, [r7, #12] 8005afe: 681b ldr r3, [r3, #0] 8005b00: 4a1f ldr r2, [pc, #124] @ (8005b80 ) 8005b02: 4293 cmp r3, r2 8005b04: d00e beq.n 8005b24 8005b06: 68fb ldr r3, [r7, #12] 8005b08: 681b ldr r3, [r3, #0] 8005b0a: 4a1a ldr r2, [pc, #104] @ (8005b74 ) 8005b0c: 4293 cmp r3, r2 8005b0e: d009 beq.n 8005b24 8005b10: 68fb ldr r3, [r7, #12] 8005b12: 681b ldr r3, [r3, #0] 8005b14: 4a1b ldr r2, [pc, #108] @ (8005b84 ) 8005b16: 4293 cmp r3, r2 8005b18: d004 beq.n 8005b24 8005b1a: 68fb ldr r3, [r7, #12] 8005b1c: 681b ldr r3, [r3, #0] 8005b1e: 4a1a ldr r2, [pc, #104] @ (8005b88 ) 8005b20: 4293 cmp r3, r2 8005b22: d111 bne.n 8005b48 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8005b24: 68fb ldr r3, [r7, #12] 8005b26: 681b ldr r3, [r3, #0] 8005b28: 689b ldr r3, [r3, #8] 8005b2a: f003 0307 and.w r3, r3, #7 8005b2e: 613b str r3, [r7, #16] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005b30: 693b ldr r3, [r7, #16] 8005b32: 2b06 cmp r3, #6 8005b34: d010 beq.n 8005b58 { __HAL_TIM_ENABLE(htim); 8005b36: 68fb ldr r3, [r7, #12] 8005b38: 681b ldr r3, [r3, #0] 8005b3a: 681a ldr r2, [r3, #0] 8005b3c: 68fb ldr r3, [r7, #12] 8005b3e: 681b ldr r3, [r3, #0] 8005b40: f042 0201 orr.w r2, r2, #1 8005b44: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005b46: e007 b.n 8005b58 } } else { __HAL_TIM_ENABLE(htim); 8005b48: 68fb ldr r3, [r7, #12] 8005b4a: 681b ldr r3, [r3, #0] 8005b4c: 681a ldr r2, [r3, #0] 8005b4e: 68fb ldr r3, [r7, #12] 8005b50: 681b ldr r3, [r3, #0] 8005b52: f042 0201 orr.w r2, r2, #1 8005b56: 601a str r2, [r3, #0] } } /* Return function status */ return status; 8005b58: 7dfb ldrb r3, [r7, #23] } 8005b5a: 4618 mov r0, r3 8005b5c: 3718 adds r7, #24 8005b5e: 46bd mov sp, r7 8005b60: bd80 pop {r7, pc} 8005b62: bf00 nop 8005b64: 080061d7 .word 0x080061d7 8005b68: 0800627f .word 0x0800627f 8005b6c: 08006145 .word 0x08006145 8005b70: 40010000 .word 0x40010000 8005b74: 40010400 .word 0x40010400 8005b78: 40000400 .word 0x40000400 8005b7c: 40000800 .word 0x40000800 8005b80: 40000c00 .word 0x40000c00 8005b84: 40014000 .word 0x40014000 8005b88: 40001800 .word 0x40001800 08005b8c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { 8005b8c: b580 push {r7, lr} 8005b8e: b084 sub sp, #16 8005b90: af00 add r7, sp, #0 8005b92: 6078 str r0, [r7, #4] 8005b94: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8005b96: 2300 movs r3, #0 8005b98: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) 8005b9a: 683b ldr r3, [r7, #0] 8005b9c: 2b0c cmp r3, #12 8005b9e: d855 bhi.n 8005c4c 8005ba0: a201 add r2, pc, #4 @ (adr r2, 8005ba8 ) 8005ba2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005ba6: bf00 nop 8005ba8: 08005bdd .word 0x08005bdd 8005bac: 08005c4d .word 0x08005c4d 8005bb0: 08005c4d .word 0x08005c4d 8005bb4: 08005c4d .word 0x08005c4d 8005bb8: 08005bf9 .word 0x08005bf9 8005bbc: 08005c4d .word 0x08005c4d 8005bc0: 08005c4d .word 0x08005c4d 8005bc4: 08005c4d .word 0x08005c4d 8005bc8: 08005c15 .word 0x08005c15 8005bcc: 08005c4d .word 0x08005c4d 8005bd0: 08005c4d .word 0x08005c4d 8005bd4: 08005c4d .word 0x08005c4d 8005bd8: 08005c31 .word 0x08005c31 { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 681b ldr r3, [r3, #0] 8005be0: 68da ldr r2, [r3, #12] 8005be2: 687b ldr r3, [r7, #4] 8005be4: 681b ldr r3, [r3, #0] 8005be6: f422 7200 bic.w r2, r2, #512 @ 0x200 8005bea: 60da str r2, [r3, #12] (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); 8005bec: 687b ldr r3, [r7, #4] 8005bee: 6a5b ldr r3, [r3, #36] @ 0x24 8005bf0: 4618 mov r0, r3 8005bf2: f7fc fc7b bl 80024ec break; 8005bf6: e02c b.n 8005c52 } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 8005bf8: 687b ldr r3, [r7, #4] 8005bfa: 681b ldr r3, [r3, #0] 8005bfc: 68da ldr r2, [r3, #12] 8005bfe: 687b ldr r3, [r7, #4] 8005c00: 681b ldr r3, [r3, #0] 8005c02: f422 6280 bic.w r2, r2, #1024 @ 0x400 8005c06: 60da str r2, [r3, #12] (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); 8005c08: 687b ldr r3, [r7, #4] 8005c0a: 6a9b ldr r3, [r3, #40] @ 0x28 8005c0c: 4618 mov r0, r3 8005c0e: f7fc fc6d bl 80024ec break; 8005c12: e01e b.n 8005c52 } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 8005c14: 687b ldr r3, [r7, #4] 8005c16: 681b ldr r3, [r3, #0] 8005c18: 68da ldr r2, [r3, #12] 8005c1a: 687b ldr r3, [r7, #4] 8005c1c: 681b ldr r3, [r3, #0] 8005c1e: f422 6200 bic.w r2, r2, #2048 @ 0x800 8005c22: 60da str r2, [r3, #12] (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); 8005c24: 687b ldr r3, [r7, #4] 8005c26: 6adb ldr r3, [r3, #44] @ 0x2c 8005c28: 4618 mov r0, r3 8005c2a: f7fc fc5f bl 80024ec break; 8005c2e: e010 b.n 8005c52 } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 8005c30: 687b ldr r3, [r7, #4] 8005c32: 681b ldr r3, [r3, #0] 8005c34: 68da ldr r2, [r3, #12] 8005c36: 687b ldr r3, [r7, #4] 8005c38: 681b ldr r3, [r3, #0] 8005c3a: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8005c3e: 60da str r2, [r3, #12] (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); 8005c40: 687b ldr r3, [r7, #4] 8005c42: 6b1b ldr r3, [r3, #48] @ 0x30 8005c44: 4618 mov r0, r3 8005c46: f7fc fc51 bl 80024ec break; 8005c4a: e002 b.n 8005c52 } default: status = HAL_ERROR; 8005c4c: 2301 movs r3, #1 8005c4e: 73fb strb r3, [r7, #15] break; 8005c50: bf00 nop } if (status == HAL_OK) 8005c52: 7bfb ldrb r3, [r7, #15] 8005c54: 2b00 cmp r3, #0 8005c56: d161 bne.n 8005d1c { /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 8005c58: 687b ldr r3, [r7, #4] 8005c5a: 681b ldr r3, [r3, #0] 8005c5c: 2200 movs r2, #0 8005c5e: 6839 ldr r1, [r7, #0] 8005c60: 4618 mov r0, r3 8005c62: f000 fd97 bl 8006794 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8005c66: 687b ldr r3, [r7, #4] 8005c68: 681b ldr r3, [r3, #0] 8005c6a: 4a2f ldr r2, [pc, #188] @ (8005d28 ) 8005c6c: 4293 cmp r3, r2 8005c6e: d004 beq.n 8005c7a 8005c70: 687b ldr r3, [r7, #4] 8005c72: 681b ldr r3, [r3, #0] 8005c74: 4a2d ldr r2, [pc, #180] @ (8005d2c ) 8005c76: 4293 cmp r3, r2 8005c78: d101 bne.n 8005c7e 8005c7a: 2301 movs r3, #1 8005c7c: e000 b.n 8005c80 8005c7e: 2300 movs r3, #0 8005c80: 2b00 cmp r3, #0 8005c82: d017 beq.n 8005cb4 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 8005c84: 687b ldr r3, [r7, #4] 8005c86: 681b ldr r3, [r3, #0] 8005c88: 6a1a ldr r2, [r3, #32] 8005c8a: f241 1311 movw r3, #4369 @ 0x1111 8005c8e: 4013 ands r3, r2 8005c90: 2b00 cmp r3, #0 8005c92: d10f bne.n 8005cb4 8005c94: 687b ldr r3, [r7, #4] 8005c96: 681b ldr r3, [r3, #0] 8005c98: 6a1a ldr r2, [r3, #32] 8005c9a: f240 4344 movw r3, #1092 @ 0x444 8005c9e: 4013 ands r3, r2 8005ca0: 2b00 cmp r3, #0 8005ca2: d107 bne.n 8005cb4 8005ca4: 687b ldr r3, [r7, #4] 8005ca6: 681b ldr r3, [r3, #0] 8005ca8: 6c5a ldr r2, [r3, #68] @ 0x44 8005caa: 687b ldr r3, [r7, #4] 8005cac: 681b ldr r3, [r3, #0] 8005cae: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8005cb2: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 8005cb4: 687b ldr r3, [r7, #4] 8005cb6: 681b ldr r3, [r3, #0] 8005cb8: 6a1a ldr r2, [r3, #32] 8005cba: f241 1311 movw r3, #4369 @ 0x1111 8005cbe: 4013 ands r3, r2 8005cc0: 2b00 cmp r3, #0 8005cc2: d10f bne.n 8005ce4 8005cc4: 687b ldr r3, [r7, #4] 8005cc6: 681b ldr r3, [r3, #0] 8005cc8: 6a1a ldr r2, [r3, #32] 8005cca: f240 4344 movw r3, #1092 @ 0x444 8005cce: 4013 ands r3, r2 8005cd0: 2b00 cmp r3, #0 8005cd2: d107 bne.n 8005ce4 8005cd4: 687b ldr r3, [r7, #4] 8005cd6: 681b ldr r3, [r3, #0] 8005cd8: 681a ldr r2, [r3, #0] 8005cda: 687b ldr r3, [r7, #4] 8005cdc: 681b ldr r3, [r3, #0] 8005cde: f022 0201 bic.w r2, r2, #1 8005ce2: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 8005ce4: 683b ldr r3, [r7, #0] 8005ce6: 2b00 cmp r3, #0 8005ce8: d104 bne.n 8005cf4 8005cea: 687b ldr r3, [r7, #4] 8005cec: 2201 movs r2, #1 8005cee: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005cf2: e013 b.n 8005d1c 8005cf4: 683b ldr r3, [r7, #0] 8005cf6: 2b04 cmp r3, #4 8005cf8: d104 bne.n 8005d04 8005cfa: 687b ldr r3, [r7, #4] 8005cfc: 2201 movs r2, #1 8005cfe: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005d02: e00b b.n 8005d1c 8005d04: 683b ldr r3, [r7, #0] 8005d06: 2b08 cmp r3, #8 8005d08: d104 bne.n 8005d14 8005d0a: 687b ldr r3, [r7, #4] 8005d0c: 2201 movs r2, #1 8005d0e: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005d12: e003 b.n 8005d1c 8005d14: 687b ldr r3, [r7, #4] 8005d16: 2201 movs r2, #1 8005d18: f883 2041 strb.w r2, [r3, #65] @ 0x41 } /* Return function status */ return status; 8005d1c: 7bfb ldrb r3, [r7, #15] } 8005d1e: 4618 mov r0, r3 8005d20: 3710 adds r7, #16 8005d22: 46bd mov sp, r7 8005d24: bd80 pop {r7, pc} 8005d26: bf00 nop 8005d28: 40010000 .word 0x40010000 8005d2c: 40010400 .word 0x40010400 08005d30 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 8005d30: b580 push {r7, lr} 8005d32: b086 sub sp, #24 8005d34: af00 add r7, sp, #0 8005d36: 6078 str r0, [r7, #4] 8005d38: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 8005d3a: 687b ldr r3, [r7, #4] 8005d3c: 2b00 cmp r3, #0 8005d3e: d101 bne.n 8005d44 { return HAL_ERROR; 8005d40: 2301 movs r3, #1 8005d42: e097 b.n 8005e74 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 8005d44: 687b ldr r3, [r7, #4] 8005d46: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8005d4a: b2db uxtb r3, r3 8005d4c: 2b00 cmp r3, #0 8005d4e: d106 bne.n 8005d5e { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005d50: 687b ldr r3, [r7, #4] 8005d52: 2200 movs r2, #0 8005d54: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 8005d58: 6878 ldr r0, [r7, #4] 8005d5a: f7fb fc95 bl 8001688 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005d5e: 687b ldr r3, [r7, #4] 8005d60: 2202 movs r2, #2 8005d62: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 8005d66: 687b ldr r3, [r7, #4] 8005d68: 681b ldr r3, [r3, #0] 8005d6a: 689b ldr r3, [r3, #8] 8005d6c: 687a ldr r2, [r7, #4] 8005d6e: 6812 ldr r2, [r2, #0] 8005d70: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8005d74: f023 0307 bic.w r3, r3, #7 8005d78: 6093 str r3, [r2, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005d7a: 687b ldr r3, [r7, #4] 8005d7c: 681a ldr r2, [r3, #0] 8005d7e: 687b ldr r3, [r7, #4] 8005d80: 3304 adds r3, #4 8005d82: 4619 mov r1, r3 8005d84: 4610 mov r0, r2 8005d86: f000 faaf bl 80062e8 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005d8a: 687b ldr r3, [r7, #4] 8005d8c: 681b ldr r3, [r3, #0] 8005d8e: 689b ldr r3, [r3, #8] 8005d90: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 8005d92: 687b ldr r3, [r7, #4] 8005d94: 681b ldr r3, [r3, #0] 8005d96: 699b ldr r3, [r3, #24] 8005d98: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 8005d9a: 687b ldr r3, [r7, #4] 8005d9c: 681b ldr r3, [r3, #0] 8005d9e: 6a1b ldr r3, [r3, #32] 8005da0: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 8005da2: 683b ldr r3, [r7, #0] 8005da4: 681b ldr r3, [r3, #0] 8005da6: 697a ldr r2, [r7, #20] 8005da8: 4313 orrs r3, r2 8005daa: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 8005dac: 693b ldr r3, [r7, #16] 8005dae: f423 7340 bic.w r3, r3, #768 @ 0x300 8005db2: f023 0303 bic.w r3, r3, #3 8005db6: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 8005db8: 683b ldr r3, [r7, #0] 8005dba: 689a ldr r2, [r3, #8] 8005dbc: 683b ldr r3, [r7, #0] 8005dbe: 699b ldr r3, [r3, #24] 8005dc0: 021b lsls r3, r3, #8 8005dc2: 4313 orrs r3, r2 8005dc4: 693a ldr r2, [r7, #16] 8005dc6: 4313 orrs r3, r2 8005dc8: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 8005dca: 693b ldr r3, [r7, #16] 8005dcc: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8005dd0: f023 030c bic.w r3, r3, #12 8005dd4: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 8005dd6: 693b ldr r3, [r7, #16] 8005dd8: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8005ddc: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8005de0: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 8005de2: 683b ldr r3, [r7, #0] 8005de4: 68da ldr r2, [r3, #12] 8005de6: 683b ldr r3, [r7, #0] 8005de8: 69db ldr r3, [r3, #28] 8005dea: 021b lsls r3, r3, #8 8005dec: 4313 orrs r3, r2 8005dee: 693a ldr r2, [r7, #16] 8005df0: 4313 orrs r3, r2 8005df2: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 8005df4: 683b ldr r3, [r7, #0] 8005df6: 691b ldr r3, [r3, #16] 8005df8: 011a lsls r2, r3, #4 8005dfa: 683b ldr r3, [r7, #0] 8005dfc: 6a1b ldr r3, [r3, #32] 8005dfe: 031b lsls r3, r3, #12 8005e00: 4313 orrs r3, r2 8005e02: 693a ldr r2, [r7, #16] 8005e04: 4313 orrs r3, r2 8005e06: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 8005e08: 68fb ldr r3, [r7, #12] 8005e0a: f023 0322 bic.w r3, r3, #34 @ 0x22 8005e0e: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 8005e10: 68fb ldr r3, [r7, #12] 8005e12: f023 0388 bic.w r3, r3, #136 @ 0x88 8005e16: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 8005e18: 683b ldr r3, [r7, #0] 8005e1a: 685a ldr r2, [r3, #4] 8005e1c: 683b ldr r3, [r7, #0] 8005e1e: 695b ldr r3, [r3, #20] 8005e20: 011b lsls r3, r3, #4 8005e22: 4313 orrs r3, r2 8005e24: 68fa ldr r2, [r7, #12] 8005e26: 4313 orrs r3, r2 8005e28: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005e2a: 687b ldr r3, [r7, #4] 8005e2c: 681b ldr r3, [r3, #0] 8005e2e: 697a ldr r2, [r7, #20] 8005e30: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 8005e32: 687b ldr r3, [r7, #4] 8005e34: 681b ldr r3, [r3, #0] 8005e36: 693a ldr r2, [r7, #16] 8005e38: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 8005e3a: 687b ldr r3, [r7, #4] 8005e3c: 681b ldr r3, [r3, #0] 8005e3e: 68fa ldr r2, [r7, #12] 8005e40: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005e42: 687b ldr r3, [r7, #4] 8005e44: 2201 movs r2, #1 8005e46: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005e4a: 687b ldr r3, [r7, #4] 8005e4c: 2201 movs r2, #1 8005e4e: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005e52: 687b ldr r3, [r7, #4] 8005e54: 2201 movs r2, #1 8005e56: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005e5a: 687b ldr r3, [r7, #4] 8005e5c: 2201 movs r2, #1 8005e5e: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005e62: 687b ldr r3, [r7, #4] 8005e64: 2201 movs r2, #1 8005e66: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005e6a: 687b ldr r3, [r7, #4] 8005e6c: 2201 movs r2, #1 8005e6e: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005e72: 2300 movs r3, #0 } 8005e74: 4618 mov r0, r3 8005e76: 3718 adds r7, #24 8005e78: 46bd mov sp, r7 8005e7a: bd80 pop {r7, pc} 08005e7c : * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8005e7c: b580 push {r7, lr} 8005e7e: b084 sub sp, #16 8005e80: af00 add r7, sp, #0 8005e82: 6078 str r0, [r7, #4] 8005e84: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); 8005e86: 687b ldr r3, [r7, #4] 8005e88: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8005e8c: 73fb strb r3, [r7, #15] HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); 8005e8e: 687b ldr r3, [r7, #4] 8005e90: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8005e94: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); 8005e96: 687b ldr r3, [r7, #4] 8005e98: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8005e9c: 737b strb r3, [r7, #13] HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); 8005e9e: 687b ldr r3, [r7, #4] 8005ea0: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 8005ea4: 733b strb r3, [r7, #12] /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) 8005ea6: 683b ldr r3, [r7, #0] 8005ea8: 2b00 cmp r3, #0 8005eaa: d110 bne.n 8005ece { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005eac: 7bfb ldrb r3, [r7, #15] 8005eae: 2b01 cmp r3, #1 8005eb0: d102 bne.n 8005eb8 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) 8005eb2: 7b7b ldrb r3, [r7, #13] 8005eb4: 2b01 cmp r3, #1 8005eb6: d001 beq.n 8005ebc { return HAL_ERROR; 8005eb8: 2301 movs r3, #1 8005eba: e069 b.n 8005f90 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005ebc: 687b ldr r3, [r7, #4] 8005ebe: 2202 movs r2, #2 8005ec0: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005ec4: 687b ldr r3, [r7, #4] 8005ec6: 2202 movs r2, #2 8005ec8: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005ecc: e031 b.n 8005f32 } } else if (Channel == TIM_CHANNEL_2) 8005ece: 683b ldr r3, [r7, #0] 8005ed0: 2b04 cmp r3, #4 8005ed2: d110 bne.n 8005ef6 { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 8005ed4: 7bbb ldrb r3, [r7, #14] 8005ed6: 2b01 cmp r3, #1 8005ed8: d102 bne.n 8005ee0 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 8005eda: 7b3b ldrb r3, [r7, #12] 8005edc: 2b01 cmp r3, #1 8005ede: d001 beq.n 8005ee4 { return HAL_ERROR; 8005ee0: 2301 movs r3, #1 8005ee2: e055 b.n 8005f90 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005ee4: 687b ldr r3, [r7, #4] 8005ee6: 2202 movs r2, #2 8005ee8: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005eec: 687b ldr r3, [r7, #4] 8005eee: 2202 movs r2, #2 8005ef0: f883 2043 strb.w r2, [r3, #67] @ 0x43 8005ef4: e01d b.n 8005f32 } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005ef6: 7bfb ldrb r3, [r7, #15] 8005ef8: 2b01 cmp r3, #1 8005efa: d108 bne.n 8005f0e || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 8005efc: 7bbb ldrb r3, [r7, #14] 8005efe: 2b01 cmp r3, #1 8005f00: d105 bne.n 8005f0e || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005f02: 7b7b ldrb r3, [r7, #13] 8005f04: 2b01 cmp r3, #1 8005f06: d102 bne.n 8005f0e || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 8005f08: 7b3b ldrb r3, [r7, #12] 8005f0a: 2b01 cmp r3, #1 8005f0c: d001 beq.n 8005f12 { return HAL_ERROR; 8005f0e: 2301 movs r3, #1 8005f10: e03e b.n 8005f90 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005f12: 687b ldr r3, [r7, #4] 8005f14: 2202 movs r2, #2 8005f16: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005f1a: 687b ldr r3, [r7, #4] 8005f1c: 2202 movs r2, #2 8005f1e: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005f22: 687b ldr r3, [r7, #4] 8005f24: 2202 movs r2, #2 8005f26: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005f2a: 687b ldr r3, [r7, #4] 8005f2c: 2202 movs r2, #2 8005f2e: f883 2043 strb.w r2, [r3, #67] @ 0x43 } } /* Enable the encoder interface channels */ switch (Channel) 8005f32: 683b ldr r3, [r7, #0] 8005f34: 2b00 cmp r3, #0 8005f36: d003 beq.n 8005f40 8005f38: 683b ldr r3, [r7, #0] 8005f3a: 2b04 cmp r3, #4 8005f3c: d008 beq.n 8005f50 8005f3e: e00f b.n 8005f60 { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005f40: 687b ldr r3, [r7, #4] 8005f42: 681b ldr r3, [r3, #0] 8005f44: 2201 movs r2, #1 8005f46: 2100 movs r1, #0 8005f48: 4618 mov r0, r3 8005f4a: f000 fc23 bl 8006794 break; 8005f4e: e016 b.n 8005f7e } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005f50: 687b ldr r3, [r7, #4] 8005f52: 681b ldr r3, [r3, #0] 8005f54: 2201 movs r2, #1 8005f56: 2104 movs r1, #4 8005f58: 4618 mov r0, r3 8005f5a: f000 fc1b bl 8006794 break; 8005f5e: e00e b.n 8005f7e } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005f60: 687b ldr r3, [r7, #4] 8005f62: 681b ldr r3, [r3, #0] 8005f64: 2201 movs r2, #1 8005f66: 2100 movs r1, #0 8005f68: 4618 mov r0, r3 8005f6a: f000 fc13 bl 8006794 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005f6e: 687b ldr r3, [r7, #4] 8005f70: 681b ldr r3, [r3, #0] 8005f72: 2201 movs r2, #1 8005f74: 2104 movs r1, #4 8005f76: 4618 mov r0, r3 8005f78: f000 fc0c bl 8006794 break; 8005f7c: bf00 nop } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); 8005f7e: 687b ldr r3, [r7, #4] 8005f80: 681b ldr r3, [r3, #0] 8005f82: 681a ldr r2, [r3, #0] 8005f84: 687b ldr r3, [r7, #4] 8005f86: 681b ldr r3, [r3, #0] 8005f88: f042 0201 orr.w r2, r2, #1 8005f8c: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 8005f8e: 2300 movs r3, #0 } 8005f90: 4618 mov r0, r3 8005f92: 3710 adds r7, #16 8005f94: 46bd mov sp, r7 8005f96: bd80 pop {r7, pc} 08005f98 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8005f98: b580 push {r7, lr} 8005f9a: b086 sub sp, #24 8005f9c: af00 add r7, sp, #0 8005f9e: 60f8 str r0, [r7, #12] 8005fa0: 60b9 str r1, [r7, #8] 8005fa2: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8005fa4: 2300 movs r3, #0 8005fa6: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8005fa8: 68fb ldr r3, [r7, #12] 8005faa: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005fae: 2b01 cmp r3, #1 8005fb0: d101 bne.n 8005fb6 8005fb2: 2302 movs r3, #2 8005fb4: e0ae b.n 8006114 8005fb6: 68fb ldr r3, [r7, #12] 8005fb8: 2201 movs r2, #1 8005fba: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8005fbe: 687b ldr r3, [r7, #4] 8005fc0: 2b0c cmp r3, #12 8005fc2: f200 809f bhi.w 8006104 8005fc6: a201 add r2, pc, #4 @ (adr r2, 8005fcc ) 8005fc8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005fcc: 08006001 .word 0x08006001 8005fd0: 08006105 .word 0x08006105 8005fd4: 08006105 .word 0x08006105 8005fd8: 08006105 .word 0x08006105 8005fdc: 08006041 .word 0x08006041 8005fe0: 08006105 .word 0x08006105 8005fe4: 08006105 .word 0x08006105 8005fe8: 08006105 .word 0x08006105 8005fec: 08006083 .word 0x08006083 8005ff0: 08006105 .word 0x08006105 8005ff4: 08006105 .word 0x08006105 8005ff8: 08006105 .word 0x08006105 8005ffc: 080060c3 .word 0x080060c3 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8006000: 68fb ldr r3, [r7, #12] 8006002: 681b ldr r3, [r3, #0] 8006004: 68b9 ldr r1, [r7, #8] 8006006: 4618 mov r0, r3 8006008: f000 fa14 bl 8006434 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800600c: 68fb ldr r3, [r7, #12] 800600e: 681b ldr r3, [r3, #0] 8006010: 699a ldr r2, [r3, #24] 8006012: 68fb ldr r3, [r7, #12] 8006014: 681b ldr r3, [r3, #0] 8006016: f042 0208 orr.w r2, r2, #8 800601a: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 800601c: 68fb ldr r3, [r7, #12] 800601e: 681b ldr r3, [r3, #0] 8006020: 699a ldr r2, [r3, #24] 8006022: 68fb ldr r3, [r7, #12] 8006024: 681b ldr r3, [r3, #0] 8006026: f022 0204 bic.w r2, r2, #4 800602a: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 800602c: 68fb ldr r3, [r7, #12] 800602e: 681b ldr r3, [r3, #0] 8006030: 6999 ldr r1, [r3, #24] 8006032: 68bb ldr r3, [r7, #8] 8006034: 691a ldr r2, [r3, #16] 8006036: 68fb ldr r3, [r7, #12] 8006038: 681b ldr r3, [r3, #0] 800603a: 430a orrs r2, r1 800603c: 619a str r2, [r3, #24] break; 800603e: e064 b.n 800610a { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8006040: 68fb ldr r3, [r7, #12] 8006042: 681b ldr r3, [r3, #0] 8006044: 68b9 ldr r1, [r7, #8] 8006046: 4618 mov r0, r3 8006048: f000 fa64 bl 8006514 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 800604c: 68fb ldr r3, [r7, #12] 800604e: 681b ldr r3, [r3, #0] 8006050: 699a ldr r2, [r3, #24] 8006052: 68fb ldr r3, [r7, #12] 8006054: 681b ldr r3, [r3, #0] 8006056: f442 6200 orr.w r2, r2, #2048 @ 0x800 800605a: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 800605c: 68fb ldr r3, [r7, #12] 800605e: 681b ldr r3, [r3, #0] 8006060: 699a ldr r2, [r3, #24] 8006062: 68fb ldr r3, [r7, #12] 8006064: 681b ldr r3, [r3, #0] 8006066: f422 6280 bic.w r2, r2, #1024 @ 0x400 800606a: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 800606c: 68fb ldr r3, [r7, #12] 800606e: 681b ldr r3, [r3, #0] 8006070: 6999 ldr r1, [r3, #24] 8006072: 68bb ldr r3, [r7, #8] 8006074: 691b ldr r3, [r3, #16] 8006076: 021a lsls r2, r3, #8 8006078: 68fb ldr r3, [r7, #12] 800607a: 681b ldr r3, [r3, #0] 800607c: 430a orrs r2, r1 800607e: 619a str r2, [r3, #24] break; 8006080: e043 b.n 800610a { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8006082: 68fb ldr r3, [r7, #12] 8006084: 681b ldr r3, [r3, #0] 8006086: 68b9 ldr r1, [r7, #8] 8006088: 4618 mov r0, r3 800608a: f000 fab9 bl 8006600 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800608e: 68fb ldr r3, [r7, #12] 8006090: 681b ldr r3, [r3, #0] 8006092: 69da ldr r2, [r3, #28] 8006094: 68fb ldr r3, [r7, #12] 8006096: 681b ldr r3, [r3, #0] 8006098: f042 0208 orr.w r2, r2, #8 800609c: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800609e: 68fb ldr r3, [r7, #12] 80060a0: 681b ldr r3, [r3, #0] 80060a2: 69da ldr r2, [r3, #28] 80060a4: 68fb ldr r3, [r7, #12] 80060a6: 681b ldr r3, [r3, #0] 80060a8: f022 0204 bic.w r2, r2, #4 80060ac: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80060ae: 68fb ldr r3, [r7, #12] 80060b0: 681b ldr r3, [r3, #0] 80060b2: 69d9 ldr r1, [r3, #28] 80060b4: 68bb ldr r3, [r7, #8] 80060b6: 691a ldr r2, [r3, #16] 80060b8: 68fb ldr r3, [r7, #12] 80060ba: 681b ldr r3, [r3, #0] 80060bc: 430a orrs r2, r1 80060be: 61da str r2, [r3, #28] break; 80060c0: e023 b.n 800610a { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80060c2: 68fb ldr r3, [r7, #12] 80060c4: 681b ldr r3, [r3, #0] 80060c6: 68b9 ldr r1, [r7, #8] 80060c8: 4618 mov r0, r3 80060ca: f000 fb0d bl 80066e8 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80060ce: 68fb ldr r3, [r7, #12] 80060d0: 681b ldr r3, [r3, #0] 80060d2: 69da ldr r2, [r3, #28] 80060d4: 68fb ldr r3, [r7, #12] 80060d6: 681b ldr r3, [r3, #0] 80060d8: f442 6200 orr.w r2, r2, #2048 @ 0x800 80060dc: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80060de: 68fb ldr r3, [r7, #12] 80060e0: 681b ldr r3, [r3, #0] 80060e2: 69da ldr r2, [r3, #28] 80060e4: 68fb ldr r3, [r7, #12] 80060e6: 681b ldr r3, [r3, #0] 80060e8: f422 6280 bic.w r2, r2, #1024 @ 0x400 80060ec: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80060ee: 68fb ldr r3, [r7, #12] 80060f0: 681b ldr r3, [r3, #0] 80060f2: 69d9 ldr r1, [r3, #28] 80060f4: 68bb ldr r3, [r7, #8] 80060f6: 691b ldr r3, [r3, #16] 80060f8: 021a lsls r2, r3, #8 80060fa: 68fb ldr r3, [r7, #12] 80060fc: 681b ldr r3, [r3, #0] 80060fe: 430a orrs r2, r1 8006100: 61da str r2, [r3, #28] break; 8006102: e002 b.n 800610a } default: status = HAL_ERROR; 8006104: 2301 movs r3, #1 8006106: 75fb strb r3, [r7, #23] break; 8006108: bf00 nop } __HAL_UNLOCK(htim); 800610a: 68fb ldr r3, [r7, #12] 800610c: 2200 movs r2, #0 800610e: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8006112: 7dfb ldrb r3, [r7, #23] } 8006114: 4618 mov r0, r3 8006116: 3718 adds r7, #24 8006118: 46bd mov sp, r7 800611a: bd80 pop {r7, pc} 0800611c : * @brief PWM Pulse finished half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) { 800611c: b480 push {r7} 800611e: b083 sub sp, #12 8006120: af00 add r7, sp, #0 8006122: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file */ } 8006124: bf00 nop 8006126: 370c adds r7, #12 8006128: 46bd mov sp, r7 800612a: f85d 7b04 ldr.w r7, [sp], #4 800612e: 4770 bx lr 08006130 : * @brief Timer error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) { 8006130: b480 push {r7} 8006132: b083 sub sp, #12 8006134: af00 add r7, sp, #0 8006136: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_ErrorCallback could be implemented in the user file */ } 8006138: bf00 nop 800613a: 370c adds r7, #12 800613c: 46bd mov sp, r7 800613e: f85d 7b04 ldr.w r7, [sp], #4 8006142: 4770 bx lr 08006144 : * @brief TIM DMA error callback * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { 8006144: b580 push {r7, lr} 8006146: b084 sub sp, #16 8006148: af00 add r7, sp, #0 800614a: 6078 str r0, [r7, #4] TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800614c: 687b ldr r3, [r7, #4] 800614e: 6b9b ldr r3, [r3, #56] @ 0x38 8006150: 60fb str r3, [r7, #12] if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 8006152: 68fb ldr r3, [r7, #12] 8006154: 6a5b ldr r3, [r3, #36] @ 0x24 8006156: 687a ldr r2, [r7, #4] 8006158: 429a cmp r2, r3 800615a: d107 bne.n 800616c { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800615c: 68fb ldr r3, [r7, #12] 800615e: 2201 movs r2, #1 8006160: 771a strb r2, [r3, #28] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8006162: 68fb ldr r3, [r7, #12] 8006164: 2201 movs r2, #1 8006166: f883 203e strb.w r2, [r3, #62] @ 0x3e 800616a: e02a b.n 80061c2 } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 800616c: 68fb ldr r3, [r7, #12] 800616e: 6a9b ldr r3, [r3, #40] @ 0x28 8006170: 687a ldr r2, [r7, #4] 8006172: 429a cmp r2, r3 8006174: d107 bne.n 8006186 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8006176: 68fb ldr r3, [r7, #12] 8006178: 2202 movs r2, #2 800617a: 771a strb r2, [r3, #28] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 800617c: 68fb ldr r3, [r7, #12] 800617e: 2201 movs r2, #1 8006180: f883 203f strb.w r2, [r3, #63] @ 0x3f 8006184: e01d b.n 80061c2 } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 8006186: 68fb ldr r3, [r7, #12] 8006188: 6adb ldr r3, [r3, #44] @ 0x2c 800618a: 687a ldr r2, [r7, #4] 800618c: 429a cmp r2, r3 800618e: d107 bne.n 80061a0 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8006190: 68fb ldr r3, [r7, #12] 8006192: 2204 movs r2, #4 8006194: 771a strb r2, [r3, #28] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); 8006196: 68fb ldr r3, [r7, #12] 8006198: 2201 movs r2, #1 800619a: f883 2040 strb.w r2, [r3, #64] @ 0x40 800619e: e010 b.n 80061c2 } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 80061a0: 68fb ldr r3, [r7, #12] 80061a2: 6b1b ldr r3, [r3, #48] @ 0x30 80061a4: 687a ldr r2, [r7, #4] 80061a6: 429a cmp r2, r3 80061a8: d107 bne.n 80061ba { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80061aa: 68fb ldr r3, [r7, #12] 80061ac: 2208 movs r2, #8 80061ae: 771a strb r2, [r3, #28] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); 80061b0: 68fb ldr r3, [r7, #12] 80061b2: 2201 movs r2, #1 80061b4: f883 2041 strb.w r2, [r3, #65] @ 0x41 80061b8: e003 b.n 80061c2 } else { htim->State = HAL_TIM_STATE_READY; 80061ba: 68fb ldr r3, [r7, #12] 80061bc: 2201 movs r2, #1 80061be: f883 203d strb.w r2, [r3, #61] @ 0x3d } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); 80061c2: 68f8 ldr r0, [r7, #12] 80061c4: f7ff ffb4 bl 8006130 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80061c8: 68fb ldr r3, [r7, #12] 80061ca: 2200 movs r2, #0 80061cc: 771a strb r2, [r3, #28] } 80061ce: bf00 nop 80061d0: 3710 adds r7, #16 80061d2: 46bd mov sp, r7 80061d4: bd80 pop {r7, pc} 080061d6 : * @brief TIM DMA Delay Pulse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { 80061d6: b580 push {r7, lr} 80061d8: b084 sub sp, #16 80061da: af00 add r7, sp, #0 80061dc: 6078 str r0, [r7, #4] TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80061de: 687b ldr r3, [r7, #4] 80061e0: 6b9b ldr r3, [r3, #56] @ 0x38 80061e2: 60fb str r3, [r7, #12] if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 80061e4: 68fb ldr r3, [r7, #12] 80061e6: 6a5b ldr r3, [r3, #36] @ 0x24 80061e8: 687a ldr r2, [r7, #4] 80061ea: 429a cmp r2, r3 80061ec: d10b bne.n 8006206 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80061ee: 68fb ldr r3, [r7, #12] 80061f0: 2201 movs r2, #1 80061f2: 771a strb r2, [r3, #28] if (hdma->Init.Mode == DMA_NORMAL) 80061f4: 687b ldr r3, [r7, #4] 80061f6: 69db ldr r3, [r3, #28] 80061f8: 2b00 cmp r3, #0 80061fa: d136 bne.n 800626a { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 80061fc: 68fb ldr r3, [r7, #12] 80061fe: 2201 movs r2, #1 8006200: f883 203e strb.w r2, [r3, #62] @ 0x3e 8006204: e031 b.n 800626a } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 8006206: 68fb ldr r3, [r7, #12] 8006208: 6a9b ldr r3, [r3, #40] @ 0x28 800620a: 687a ldr r2, [r7, #4] 800620c: 429a cmp r2, r3 800620e: d10b bne.n 8006228 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8006210: 68fb ldr r3, [r7, #12] 8006212: 2202 movs r2, #2 8006214: 771a strb r2, [r3, #28] if (hdma->Init.Mode == DMA_NORMAL) 8006216: 687b ldr r3, [r7, #4] 8006218: 69db ldr r3, [r3, #28] 800621a: 2b00 cmp r3, #0 800621c: d125 bne.n 800626a { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 800621e: 68fb ldr r3, [r7, #12] 8006220: 2201 movs r2, #1 8006222: f883 203f strb.w r2, [r3, #63] @ 0x3f 8006226: e020 b.n 800626a } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 8006228: 68fb ldr r3, [r7, #12] 800622a: 6adb ldr r3, [r3, #44] @ 0x2c 800622c: 687a ldr r2, [r7, #4] 800622e: 429a cmp r2, r3 8006230: d10b bne.n 800624a { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8006232: 68fb ldr r3, [r7, #12] 8006234: 2204 movs r2, #4 8006236: 771a strb r2, [r3, #28] if (hdma->Init.Mode == DMA_NORMAL) 8006238: 687b ldr r3, [r7, #4] 800623a: 69db ldr r3, [r3, #28] 800623c: 2b00 cmp r3, #0 800623e: d114 bne.n 800626a { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); 8006240: 68fb ldr r3, [r7, #12] 8006242: 2201 movs r2, #1 8006244: f883 2040 strb.w r2, [r3, #64] @ 0x40 8006248: e00f b.n 800626a } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 800624a: 68fb ldr r3, [r7, #12] 800624c: 6b1b ldr r3, [r3, #48] @ 0x30 800624e: 687a ldr r2, [r7, #4] 8006250: 429a cmp r2, r3 8006252: d10a bne.n 800626a { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8006254: 68fb ldr r3, [r7, #12] 8006256: 2208 movs r2, #8 8006258: 771a strb r2, [r3, #28] if (hdma->Init.Mode == DMA_NORMAL) 800625a: 687b ldr r3, [r7, #4] 800625c: 69db ldr r3, [r3, #28] 800625e: 2b00 cmp r3, #0 8006260: d103 bne.n 800626a { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); 8006262: 68fb ldr r3, [r7, #12] 8006264: 2201 movs r2, #1 8006266: f883 2041 strb.w r2, [r3, #65] @ 0x41 } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); 800626a: 68f8 ldr r0, [r7, #12] 800626c: f7fb f9a4 bl 80015b8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8006270: 68fb ldr r3, [r7, #12] 8006272: 2200 movs r2, #0 8006274: 771a strb r2, [r3, #28] } 8006276: bf00 nop 8006278: 3710 adds r7, #16 800627a: 46bd mov sp, r7 800627c: bd80 pop {r7, pc} 0800627e : * @brief TIM DMA Delay Pulse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { 800627e: b580 push {r7, lr} 8006280: b084 sub sp, #16 8006282: af00 add r7, sp, #0 8006284: 6078 str r0, [r7, #4] TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006286: 687b ldr r3, [r7, #4] 8006288: 6b9b ldr r3, [r3, #56] @ 0x38 800628a: 60fb str r3, [r7, #12] if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 800628c: 68fb ldr r3, [r7, #12] 800628e: 6a5b ldr r3, [r3, #36] @ 0x24 8006290: 687a ldr r2, [r7, #4] 8006292: 429a cmp r2, r3 8006294: d103 bne.n 800629e { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8006296: 68fb ldr r3, [r7, #12] 8006298: 2201 movs r2, #1 800629a: 771a strb r2, [r3, #28] 800629c: e019 b.n 80062d2 } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 800629e: 68fb ldr r3, [r7, #12] 80062a0: 6a9b ldr r3, [r3, #40] @ 0x28 80062a2: 687a ldr r2, [r7, #4] 80062a4: 429a cmp r2, r3 80062a6: d103 bne.n 80062b0 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80062a8: 68fb ldr r3, [r7, #12] 80062aa: 2202 movs r2, #2 80062ac: 771a strb r2, [r3, #28] 80062ae: e010 b.n 80062d2 } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 80062b0: 68fb ldr r3, [r7, #12] 80062b2: 6adb ldr r3, [r3, #44] @ 0x2c 80062b4: 687a ldr r2, [r7, #4] 80062b6: 429a cmp r2, r3 80062b8: d103 bne.n 80062c2 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 80062ba: 68fb ldr r3, [r7, #12] 80062bc: 2204 movs r2, #4 80062be: 771a strb r2, [r3, #28] 80062c0: e007 b.n 80062d2 } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 80062c2: 68fb ldr r3, [r7, #12] 80062c4: 6b1b ldr r3, [r3, #48] @ 0x30 80062c6: 687a ldr r2, [r7, #4] 80062c8: 429a cmp r2, r3 80062ca: d102 bne.n 80062d2 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80062cc: 68fb ldr r3, [r7, #12] 80062ce: 2208 movs r2, #8 80062d0: 771a strb r2, [r3, #28] } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedHalfCpltCallback(htim); #else HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); 80062d2: 68f8 ldr r0, [r7, #12] 80062d4: f7ff ff22 bl 800611c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80062d8: 68fb ldr r3, [r7, #12] 80062da: 2200 movs r2, #0 80062dc: 771a strb r2, [r3, #28] } 80062de: bf00 nop 80062e0: 3710 adds r7, #16 80062e2: 46bd mov sp, r7 80062e4: bd80 pop {r7, pc} ... 080062e8 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80062e8: b480 push {r7} 80062ea: b085 sub sp, #20 80062ec: af00 add r7, sp, #0 80062ee: 6078 str r0, [r7, #4] 80062f0: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80062f2: 687b ldr r3, [r7, #4] 80062f4: 681b ldr r3, [r3, #0] 80062f6: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80062f8: 687b ldr r3, [r7, #4] 80062fa: 4a43 ldr r2, [pc, #268] @ (8006408 ) 80062fc: 4293 cmp r3, r2 80062fe: d013 beq.n 8006328 8006300: 687b ldr r3, [r7, #4] 8006302: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006306: d00f beq.n 8006328 8006308: 687b ldr r3, [r7, #4] 800630a: 4a40 ldr r2, [pc, #256] @ (800640c ) 800630c: 4293 cmp r3, r2 800630e: d00b beq.n 8006328 8006310: 687b ldr r3, [r7, #4] 8006312: 4a3f ldr r2, [pc, #252] @ (8006410 ) 8006314: 4293 cmp r3, r2 8006316: d007 beq.n 8006328 8006318: 687b ldr r3, [r7, #4] 800631a: 4a3e ldr r2, [pc, #248] @ (8006414 ) 800631c: 4293 cmp r3, r2 800631e: d003 beq.n 8006328 8006320: 687b ldr r3, [r7, #4] 8006322: 4a3d ldr r2, [pc, #244] @ (8006418 ) 8006324: 4293 cmp r3, r2 8006326: d108 bne.n 800633a { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8006328: 68fb ldr r3, [r7, #12] 800632a: f023 0370 bic.w r3, r3, #112 @ 0x70 800632e: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8006330: 683b ldr r3, [r7, #0] 8006332: 685b ldr r3, [r3, #4] 8006334: 68fa ldr r2, [r7, #12] 8006336: 4313 orrs r3, r2 8006338: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800633a: 687b ldr r3, [r7, #4] 800633c: 4a32 ldr r2, [pc, #200] @ (8006408 ) 800633e: 4293 cmp r3, r2 8006340: d02b beq.n 800639a 8006342: 687b ldr r3, [r7, #4] 8006344: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006348: d027 beq.n 800639a 800634a: 687b ldr r3, [r7, #4] 800634c: 4a2f ldr r2, [pc, #188] @ (800640c ) 800634e: 4293 cmp r3, r2 8006350: d023 beq.n 800639a 8006352: 687b ldr r3, [r7, #4] 8006354: 4a2e ldr r2, [pc, #184] @ (8006410 ) 8006356: 4293 cmp r3, r2 8006358: d01f beq.n 800639a 800635a: 687b ldr r3, [r7, #4] 800635c: 4a2d ldr r2, [pc, #180] @ (8006414 ) 800635e: 4293 cmp r3, r2 8006360: d01b beq.n 800639a 8006362: 687b ldr r3, [r7, #4] 8006364: 4a2c ldr r2, [pc, #176] @ (8006418 ) 8006366: 4293 cmp r3, r2 8006368: d017 beq.n 800639a 800636a: 687b ldr r3, [r7, #4] 800636c: 4a2b ldr r2, [pc, #172] @ (800641c ) 800636e: 4293 cmp r3, r2 8006370: d013 beq.n 800639a 8006372: 687b ldr r3, [r7, #4] 8006374: 4a2a ldr r2, [pc, #168] @ (8006420 ) 8006376: 4293 cmp r3, r2 8006378: d00f beq.n 800639a 800637a: 687b ldr r3, [r7, #4] 800637c: 4a29 ldr r2, [pc, #164] @ (8006424 ) 800637e: 4293 cmp r3, r2 8006380: d00b beq.n 800639a 8006382: 687b ldr r3, [r7, #4] 8006384: 4a28 ldr r2, [pc, #160] @ (8006428 ) 8006386: 4293 cmp r3, r2 8006388: d007 beq.n 800639a 800638a: 687b ldr r3, [r7, #4] 800638c: 4a27 ldr r2, [pc, #156] @ (800642c ) 800638e: 4293 cmp r3, r2 8006390: d003 beq.n 800639a 8006392: 687b ldr r3, [r7, #4] 8006394: 4a26 ldr r2, [pc, #152] @ (8006430 ) 8006396: 4293 cmp r3, r2 8006398: d108 bne.n 80063ac { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800639a: 68fb ldr r3, [r7, #12] 800639c: f423 7340 bic.w r3, r3, #768 @ 0x300 80063a0: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80063a2: 683b ldr r3, [r7, #0] 80063a4: 68db ldr r3, [r3, #12] 80063a6: 68fa ldr r2, [r7, #12] 80063a8: 4313 orrs r3, r2 80063aa: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80063ac: 68fb ldr r3, [r7, #12] 80063ae: f023 0280 bic.w r2, r3, #128 @ 0x80 80063b2: 683b ldr r3, [r7, #0] 80063b4: 695b ldr r3, [r3, #20] 80063b6: 4313 orrs r3, r2 80063b8: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80063ba: 683b ldr r3, [r7, #0] 80063bc: 689a ldr r2, [r3, #8] 80063be: 687b ldr r3, [r7, #4] 80063c0: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80063c2: 683b ldr r3, [r7, #0] 80063c4: 681a ldr r2, [r3, #0] 80063c6: 687b ldr r3, [r7, #4] 80063c8: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80063ca: 687b ldr r3, [r7, #4] 80063cc: 4a0e ldr r2, [pc, #56] @ (8006408 ) 80063ce: 4293 cmp r3, r2 80063d0: d003 beq.n 80063da 80063d2: 687b ldr r3, [r7, #4] 80063d4: 4a10 ldr r2, [pc, #64] @ (8006418 ) 80063d6: 4293 cmp r3, r2 80063d8: d103 bne.n 80063e2 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80063da: 683b ldr r3, [r7, #0] 80063dc: 691a ldr r2, [r3, #16] 80063de: 687b ldr r3, [r7, #4] 80063e0: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 80063e2: 687b ldr r3, [r7, #4] 80063e4: 681b ldr r3, [r3, #0] 80063e6: f043 0204 orr.w r2, r3, #4 80063ea: 687b ldr r3, [r7, #4] 80063ec: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80063ee: 687b ldr r3, [r7, #4] 80063f0: 2201 movs r2, #1 80063f2: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 80063f4: 687b ldr r3, [r7, #4] 80063f6: 68fa ldr r2, [r7, #12] 80063f8: 601a str r2, [r3, #0] } 80063fa: bf00 nop 80063fc: 3714 adds r7, #20 80063fe: 46bd mov sp, r7 8006400: f85d 7b04 ldr.w r7, [sp], #4 8006404: 4770 bx lr 8006406: bf00 nop 8006408: 40010000 .word 0x40010000 800640c: 40000400 .word 0x40000400 8006410: 40000800 .word 0x40000800 8006414: 40000c00 .word 0x40000c00 8006418: 40010400 .word 0x40010400 800641c: 40014000 .word 0x40014000 8006420: 40014400 .word 0x40014400 8006424: 40014800 .word 0x40014800 8006428: 40001800 .word 0x40001800 800642c: 40001c00 .word 0x40001c00 8006430: 40002000 .word 0x40002000 08006434 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006434: b480 push {r7} 8006436: b087 sub sp, #28 8006438: af00 add r7, sp, #0 800643a: 6078 str r0, [r7, #4] 800643c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800643e: 687b ldr r3, [r7, #4] 8006440: 6a1b ldr r3, [r3, #32] 8006442: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8006444: 687b ldr r3, [r7, #4] 8006446: 6a1b ldr r3, [r3, #32] 8006448: f023 0201 bic.w r2, r3, #1 800644c: 687b ldr r3, [r7, #4] 800644e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006450: 687b ldr r3, [r7, #4] 8006452: 685b ldr r3, [r3, #4] 8006454: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8006456: 687b ldr r3, [r7, #4] 8006458: 699b ldr r3, [r3, #24] 800645a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800645c: 68fb ldr r3, [r7, #12] 800645e: f023 0370 bic.w r3, r3, #112 @ 0x70 8006462: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8006464: 68fb ldr r3, [r7, #12] 8006466: f023 0303 bic.w r3, r3, #3 800646a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800646c: 683b ldr r3, [r7, #0] 800646e: 681b ldr r3, [r3, #0] 8006470: 68fa ldr r2, [r7, #12] 8006472: 4313 orrs r3, r2 8006474: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8006476: 697b ldr r3, [r7, #20] 8006478: f023 0302 bic.w r3, r3, #2 800647c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800647e: 683b ldr r3, [r7, #0] 8006480: 689b ldr r3, [r3, #8] 8006482: 697a ldr r2, [r7, #20] 8006484: 4313 orrs r3, r2 8006486: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8006488: 687b ldr r3, [r7, #4] 800648a: 4a20 ldr r2, [pc, #128] @ (800650c ) 800648c: 4293 cmp r3, r2 800648e: d003 beq.n 8006498 8006490: 687b ldr r3, [r7, #4] 8006492: 4a1f ldr r2, [pc, #124] @ (8006510 ) 8006494: 4293 cmp r3, r2 8006496: d10c bne.n 80064b2 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8006498: 697b ldr r3, [r7, #20] 800649a: f023 0308 bic.w r3, r3, #8 800649e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80064a0: 683b ldr r3, [r7, #0] 80064a2: 68db ldr r3, [r3, #12] 80064a4: 697a ldr r2, [r7, #20] 80064a6: 4313 orrs r3, r2 80064a8: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 80064aa: 697b ldr r3, [r7, #20] 80064ac: f023 0304 bic.w r3, r3, #4 80064b0: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80064b2: 687b ldr r3, [r7, #4] 80064b4: 4a15 ldr r2, [pc, #84] @ (800650c ) 80064b6: 4293 cmp r3, r2 80064b8: d003 beq.n 80064c2 80064ba: 687b ldr r3, [r7, #4] 80064bc: 4a14 ldr r2, [pc, #80] @ (8006510 ) 80064be: 4293 cmp r3, r2 80064c0: d111 bne.n 80064e6 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 80064c2: 693b ldr r3, [r7, #16] 80064c4: f423 7380 bic.w r3, r3, #256 @ 0x100 80064c8: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 80064ca: 693b ldr r3, [r7, #16] 80064cc: f423 7300 bic.w r3, r3, #512 @ 0x200 80064d0: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 80064d2: 683b ldr r3, [r7, #0] 80064d4: 695b ldr r3, [r3, #20] 80064d6: 693a ldr r2, [r7, #16] 80064d8: 4313 orrs r3, r2 80064da: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 80064dc: 683b ldr r3, [r7, #0] 80064de: 699b ldr r3, [r3, #24] 80064e0: 693a ldr r2, [r7, #16] 80064e2: 4313 orrs r3, r2 80064e4: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80064e6: 687b ldr r3, [r7, #4] 80064e8: 693a ldr r2, [r7, #16] 80064ea: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80064ec: 687b ldr r3, [r7, #4] 80064ee: 68fa ldr r2, [r7, #12] 80064f0: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80064f2: 683b ldr r3, [r7, #0] 80064f4: 685a ldr r2, [r3, #4] 80064f6: 687b ldr r3, [r7, #4] 80064f8: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80064fa: 687b ldr r3, [r7, #4] 80064fc: 697a ldr r2, [r7, #20] 80064fe: 621a str r2, [r3, #32] } 8006500: bf00 nop 8006502: 371c adds r7, #28 8006504: 46bd mov sp, r7 8006506: f85d 7b04 ldr.w r7, [sp], #4 800650a: 4770 bx lr 800650c: 40010000 .word 0x40010000 8006510: 40010400 .word 0x40010400 08006514 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006514: b480 push {r7} 8006516: b087 sub sp, #28 8006518: af00 add r7, sp, #0 800651a: 6078 str r0, [r7, #4] 800651c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800651e: 687b ldr r3, [r7, #4] 8006520: 6a1b ldr r3, [r3, #32] 8006522: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8006524: 687b ldr r3, [r7, #4] 8006526: 6a1b ldr r3, [r3, #32] 8006528: f023 0210 bic.w r2, r3, #16 800652c: 687b ldr r3, [r7, #4] 800652e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006530: 687b ldr r3, [r7, #4] 8006532: 685b ldr r3, [r3, #4] 8006534: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8006536: 687b ldr r3, [r7, #4] 8006538: 699b ldr r3, [r3, #24] 800653a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 800653c: 68fb ldr r3, [r7, #12] 800653e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8006542: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8006544: 68fb ldr r3, [r7, #12] 8006546: f423 7340 bic.w r3, r3, #768 @ 0x300 800654a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800654c: 683b ldr r3, [r7, #0] 800654e: 681b ldr r3, [r3, #0] 8006550: 021b lsls r3, r3, #8 8006552: 68fa ldr r2, [r7, #12] 8006554: 4313 orrs r3, r2 8006556: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8006558: 697b ldr r3, [r7, #20] 800655a: f023 0320 bic.w r3, r3, #32 800655e: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8006560: 683b ldr r3, [r7, #0] 8006562: 689b ldr r3, [r3, #8] 8006564: 011b lsls r3, r3, #4 8006566: 697a ldr r2, [r7, #20] 8006568: 4313 orrs r3, r2 800656a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800656c: 687b ldr r3, [r7, #4] 800656e: 4a22 ldr r2, [pc, #136] @ (80065f8 ) 8006570: 4293 cmp r3, r2 8006572: d003 beq.n 800657c 8006574: 687b ldr r3, [r7, #4] 8006576: 4a21 ldr r2, [pc, #132] @ (80065fc ) 8006578: 4293 cmp r3, r2 800657a: d10d bne.n 8006598 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 800657c: 697b ldr r3, [r7, #20] 800657e: f023 0380 bic.w r3, r3, #128 @ 0x80 8006582: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8006584: 683b ldr r3, [r7, #0] 8006586: 68db ldr r3, [r3, #12] 8006588: 011b lsls r3, r3, #4 800658a: 697a ldr r2, [r7, #20] 800658c: 4313 orrs r3, r2 800658e: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8006590: 697b ldr r3, [r7, #20] 8006592: f023 0340 bic.w r3, r3, #64 @ 0x40 8006596: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006598: 687b ldr r3, [r7, #4] 800659a: 4a17 ldr r2, [pc, #92] @ (80065f8 ) 800659c: 4293 cmp r3, r2 800659e: d003 beq.n 80065a8 80065a0: 687b ldr r3, [r7, #4] 80065a2: 4a16 ldr r2, [pc, #88] @ (80065fc ) 80065a4: 4293 cmp r3, r2 80065a6: d113 bne.n 80065d0 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 80065a8: 693b ldr r3, [r7, #16] 80065aa: f423 6380 bic.w r3, r3, #1024 @ 0x400 80065ae: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 80065b0: 693b ldr r3, [r7, #16] 80065b2: f423 6300 bic.w r3, r3, #2048 @ 0x800 80065b6: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 80065b8: 683b ldr r3, [r7, #0] 80065ba: 695b ldr r3, [r3, #20] 80065bc: 009b lsls r3, r3, #2 80065be: 693a ldr r2, [r7, #16] 80065c0: 4313 orrs r3, r2 80065c2: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 80065c4: 683b ldr r3, [r7, #0] 80065c6: 699b ldr r3, [r3, #24] 80065c8: 009b lsls r3, r3, #2 80065ca: 693a ldr r2, [r7, #16] 80065cc: 4313 orrs r3, r2 80065ce: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80065d0: 687b ldr r3, [r7, #4] 80065d2: 693a ldr r2, [r7, #16] 80065d4: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80065d6: 687b ldr r3, [r7, #4] 80065d8: 68fa ldr r2, [r7, #12] 80065da: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 80065dc: 683b ldr r3, [r7, #0] 80065de: 685a ldr r2, [r3, #4] 80065e0: 687b ldr r3, [r7, #4] 80065e2: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80065e4: 687b ldr r3, [r7, #4] 80065e6: 697a ldr r2, [r7, #20] 80065e8: 621a str r2, [r3, #32] } 80065ea: bf00 nop 80065ec: 371c adds r7, #28 80065ee: 46bd mov sp, r7 80065f0: f85d 7b04 ldr.w r7, [sp], #4 80065f4: 4770 bx lr 80065f6: bf00 nop 80065f8: 40010000 .word 0x40010000 80065fc: 40010400 .word 0x40010400 08006600 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006600: b480 push {r7} 8006602: b087 sub sp, #28 8006604: af00 add r7, sp, #0 8006606: 6078 str r0, [r7, #4] 8006608: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800660a: 687b ldr r3, [r7, #4] 800660c: 6a1b ldr r3, [r3, #32] 800660e: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8006610: 687b ldr r3, [r7, #4] 8006612: 6a1b ldr r3, [r3, #32] 8006614: f423 7280 bic.w r2, r3, #256 @ 0x100 8006618: 687b ldr r3, [r7, #4] 800661a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800661c: 687b ldr r3, [r7, #4] 800661e: 685b ldr r3, [r3, #4] 8006620: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8006622: 687b ldr r3, [r7, #4] 8006624: 69db ldr r3, [r3, #28] 8006626: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8006628: 68fb ldr r3, [r7, #12] 800662a: f023 0370 bic.w r3, r3, #112 @ 0x70 800662e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8006630: 68fb ldr r3, [r7, #12] 8006632: f023 0303 bic.w r3, r3, #3 8006636: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8006638: 683b ldr r3, [r7, #0] 800663a: 681b ldr r3, [r3, #0] 800663c: 68fa ldr r2, [r7, #12] 800663e: 4313 orrs r3, r2 8006640: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8006642: 697b ldr r3, [r7, #20] 8006644: f423 7300 bic.w r3, r3, #512 @ 0x200 8006648: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800664a: 683b ldr r3, [r7, #0] 800664c: 689b ldr r3, [r3, #8] 800664e: 021b lsls r3, r3, #8 8006650: 697a ldr r2, [r7, #20] 8006652: 4313 orrs r3, r2 8006654: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8006656: 687b ldr r3, [r7, #4] 8006658: 4a21 ldr r2, [pc, #132] @ (80066e0 ) 800665a: 4293 cmp r3, r2 800665c: d003 beq.n 8006666 800665e: 687b ldr r3, [r7, #4] 8006660: 4a20 ldr r2, [pc, #128] @ (80066e4 ) 8006662: 4293 cmp r3, r2 8006664: d10d bne.n 8006682 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8006666: 697b ldr r3, [r7, #20] 8006668: f423 6300 bic.w r3, r3, #2048 @ 0x800 800666c: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 800666e: 683b ldr r3, [r7, #0] 8006670: 68db ldr r3, [r3, #12] 8006672: 021b lsls r3, r3, #8 8006674: 697a ldr r2, [r7, #20] 8006676: 4313 orrs r3, r2 8006678: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 800667a: 697b ldr r3, [r7, #20] 800667c: f423 6380 bic.w r3, r3, #1024 @ 0x400 8006680: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006682: 687b ldr r3, [r7, #4] 8006684: 4a16 ldr r2, [pc, #88] @ (80066e0 ) 8006686: 4293 cmp r3, r2 8006688: d003 beq.n 8006692 800668a: 687b ldr r3, [r7, #4] 800668c: 4a15 ldr r2, [pc, #84] @ (80066e4 ) 800668e: 4293 cmp r3, r2 8006690: d113 bne.n 80066ba /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8006692: 693b ldr r3, [r7, #16] 8006694: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8006698: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800669a: 693b ldr r3, [r7, #16] 800669c: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80066a0: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 80066a2: 683b ldr r3, [r7, #0] 80066a4: 695b ldr r3, [r3, #20] 80066a6: 011b lsls r3, r3, #4 80066a8: 693a ldr r2, [r7, #16] 80066aa: 4313 orrs r3, r2 80066ac: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80066ae: 683b ldr r3, [r7, #0] 80066b0: 699b ldr r3, [r3, #24] 80066b2: 011b lsls r3, r3, #4 80066b4: 693a ldr r2, [r7, #16] 80066b6: 4313 orrs r3, r2 80066b8: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80066ba: 687b ldr r3, [r7, #4] 80066bc: 693a ldr r2, [r7, #16] 80066be: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80066c0: 687b ldr r3, [r7, #4] 80066c2: 68fa ldr r2, [r7, #12] 80066c4: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 80066c6: 683b ldr r3, [r7, #0] 80066c8: 685a ldr r2, [r3, #4] 80066ca: 687b ldr r3, [r7, #4] 80066cc: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80066ce: 687b ldr r3, [r7, #4] 80066d0: 697a ldr r2, [r7, #20] 80066d2: 621a str r2, [r3, #32] } 80066d4: bf00 nop 80066d6: 371c adds r7, #28 80066d8: 46bd mov sp, r7 80066da: f85d 7b04 ldr.w r7, [sp], #4 80066de: 4770 bx lr 80066e0: 40010000 .word 0x40010000 80066e4: 40010400 .word 0x40010400 080066e8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80066e8: b480 push {r7} 80066ea: b087 sub sp, #28 80066ec: af00 add r7, sp, #0 80066ee: 6078 str r0, [r7, #4] 80066f0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80066f2: 687b ldr r3, [r7, #4] 80066f4: 6a1b ldr r3, [r3, #32] 80066f6: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 80066f8: 687b ldr r3, [r7, #4] 80066fa: 6a1b ldr r3, [r3, #32] 80066fc: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8006700: 687b ldr r3, [r7, #4] 8006702: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006704: 687b ldr r3, [r7, #4] 8006706: 685b ldr r3, [r3, #4] 8006708: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800670a: 687b ldr r3, [r7, #4] 800670c: 69db ldr r3, [r3, #28] 800670e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8006710: 68fb ldr r3, [r7, #12] 8006712: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8006716: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8006718: 68fb ldr r3, [r7, #12] 800671a: f423 7340 bic.w r3, r3, #768 @ 0x300 800671e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8006720: 683b ldr r3, [r7, #0] 8006722: 681b ldr r3, [r3, #0] 8006724: 021b lsls r3, r3, #8 8006726: 68fa ldr r2, [r7, #12] 8006728: 4313 orrs r3, r2 800672a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 800672c: 693b ldr r3, [r7, #16] 800672e: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8006732: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8006734: 683b ldr r3, [r7, #0] 8006736: 689b ldr r3, [r3, #8] 8006738: 031b lsls r3, r3, #12 800673a: 693a ldr r2, [r7, #16] 800673c: 4313 orrs r3, r2 800673e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006740: 687b ldr r3, [r7, #4] 8006742: 4a12 ldr r2, [pc, #72] @ (800678c ) 8006744: 4293 cmp r3, r2 8006746: d003 beq.n 8006750 8006748: 687b ldr r3, [r7, #4] 800674a: 4a11 ldr r2, [pc, #68] @ (8006790 ) 800674c: 4293 cmp r3, r2 800674e: d109 bne.n 8006764 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8006750: 697b ldr r3, [r7, #20] 8006752: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8006756: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8006758: 683b ldr r3, [r7, #0] 800675a: 695b ldr r3, [r3, #20] 800675c: 019b lsls r3, r3, #6 800675e: 697a ldr r2, [r7, #20] 8006760: 4313 orrs r3, r2 8006762: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006764: 687b ldr r3, [r7, #4] 8006766: 697a ldr r2, [r7, #20] 8006768: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800676a: 687b ldr r3, [r7, #4] 800676c: 68fa ldr r2, [r7, #12] 800676e: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8006770: 683b ldr r3, [r7, #0] 8006772: 685a ldr r2, [r3, #4] 8006774: 687b ldr r3, [r7, #4] 8006776: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8006778: 687b ldr r3, [r7, #4] 800677a: 693a ldr r2, [r7, #16] 800677c: 621a str r2, [r3, #32] } 800677e: bf00 nop 8006780: 371c adds r7, #28 8006782: 46bd mov sp, r7 8006784: f85d 7b04 ldr.w r7, [sp], #4 8006788: 4770 bx lr 800678a: bf00 nop 800678c: 40010000 .word 0x40010000 8006790: 40010400 .word 0x40010400 08006794 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8006794: b480 push {r7} 8006796: b087 sub sp, #28 8006798: af00 add r7, sp, #0 800679a: 60f8 str r0, [r7, #12] 800679c: 60b9 str r1, [r7, #8] 800679e: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 80067a0: 68bb ldr r3, [r7, #8] 80067a2: f003 031f and.w r3, r3, #31 80067a6: 2201 movs r2, #1 80067a8: fa02 f303 lsl.w r3, r2, r3 80067ac: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 80067ae: 68fb ldr r3, [r7, #12] 80067b0: 6a1a ldr r2, [r3, #32] 80067b2: 697b ldr r3, [r7, #20] 80067b4: 43db mvns r3, r3 80067b6: 401a ands r2, r3 80067b8: 68fb ldr r3, [r7, #12] 80067ba: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 80067bc: 68fb ldr r3, [r7, #12] 80067be: 6a1a ldr r2, [r3, #32] 80067c0: 68bb ldr r3, [r7, #8] 80067c2: f003 031f and.w r3, r3, #31 80067c6: 6879 ldr r1, [r7, #4] 80067c8: fa01 f303 lsl.w r3, r1, r3 80067cc: 431a orrs r2, r3 80067ce: 68fb ldr r3, [r7, #12] 80067d0: 621a str r2, [r3, #32] } 80067d2: bf00 nop 80067d4: 371c adds r7, #28 80067d6: 46bd mov sp, r7 80067d8: f85d 7b04 ldr.w r7, [sp], #4 80067dc: 4770 bx lr ... 080067e0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 80067e0: b480 push {r7} 80067e2: b085 sub sp, #20 80067e4: af00 add r7, sp, #0 80067e6: 6078 str r0, [r7, #4] 80067e8: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 80067ea: 687b ldr r3, [r7, #4] 80067ec: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80067f0: 2b01 cmp r3, #1 80067f2: d101 bne.n 80067f8 80067f4: 2302 movs r3, #2 80067f6: e05a b.n 80068ae 80067f8: 687b ldr r3, [r7, #4] 80067fa: 2201 movs r2, #1 80067fc: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8006800: 687b ldr r3, [r7, #4] 8006802: 2202 movs r2, #2 8006804: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8006808: 687b ldr r3, [r7, #4] 800680a: 681b ldr r3, [r3, #0] 800680c: 685b ldr r3, [r3, #4] 800680e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8006810: 687b ldr r3, [r7, #4] 8006812: 681b ldr r3, [r3, #0] 8006814: 689b ldr r3, [r3, #8] 8006816: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8006818: 68fb ldr r3, [r7, #12] 800681a: f023 0370 bic.w r3, r3, #112 @ 0x70 800681e: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8006820: 683b ldr r3, [r7, #0] 8006822: 681b ldr r3, [r3, #0] 8006824: 68fa ldr r2, [r7, #12] 8006826: 4313 orrs r3, r2 8006828: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800682a: 687b ldr r3, [r7, #4] 800682c: 681b ldr r3, [r3, #0] 800682e: 68fa ldr r2, [r7, #12] 8006830: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8006832: 687b ldr r3, [r7, #4] 8006834: 681b ldr r3, [r3, #0] 8006836: 4a21 ldr r2, [pc, #132] @ (80068bc ) 8006838: 4293 cmp r3, r2 800683a: d022 beq.n 8006882 800683c: 687b ldr r3, [r7, #4] 800683e: 681b ldr r3, [r3, #0] 8006840: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006844: d01d beq.n 8006882 8006846: 687b ldr r3, [r7, #4] 8006848: 681b ldr r3, [r3, #0] 800684a: 4a1d ldr r2, [pc, #116] @ (80068c0 ) 800684c: 4293 cmp r3, r2 800684e: d018 beq.n 8006882 8006850: 687b ldr r3, [r7, #4] 8006852: 681b ldr r3, [r3, #0] 8006854: 4a1b ldr r2, [pc, #108] @ (80068c4 ) 8006856: 4293 cmp r3, r2 8006858: d013 beq.n 8006882 800685a: 687b ldr r3, [r7, #4] 800685c: 681b ldr r3, [r3, #0] 800685e: 4a1a ldr r2, [pc, #104] @ (80068c8 ) 8006860: 4293 cmp r3, r2 8006862: d00e beq.n 8006882 8006864: 687b ldr r3, [r7, #4] 8006866: 681b ldr r3, [r3, #0] 8006868: 4a18 ldr r2, [pc, #96] @ (80068cc ) 800686a: 4293 cmp r3, r2 800686c: d009 beq.n 8006882 800686e: 687b ldr r3, [r7, #4] 8006870: 681b ldr r3, [r3, #0] 8006872: 4a17 ldr r2, [pc, #92] @ (80068d0 ) 8006874: 4293 cmp r3, r2 8006876: d004 beq.n 8006882 8006878: 687b ldr r3, [r7, #4] 800687a: 681b ldr r3, [r3, #0] 800687c: 4a15 ldr r2, [pc, #84] @ (80068d4 ) 800687e: 4293 cmp r3, r2 8006880: d10c bne.n 800689c { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8006882: 68bb ldr r3, [r7, #8] 8006884: f023 0380 bic.w r3, r3, #128 @ 0x80 8006888: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800688a: 683b ldr r3, [r7, #0] 800688c: 685b ldr r3, [r3, #4] 800688e: 68ba ldr r2, [r7, #8] 8006890: 4313 orrs r3, r2 8006892: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8006894: 687b ldr r3, [r7, #4] 8006896: 681b ldr r3, [r3, #0] 8006898: 68ba ldr r2, [r7, #8] 800689a: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 800689c: 687b ldr r3, [r7, #4] 800689e: 2201 movs r2, #1 80068a0: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80068a4: 687b ldr r3, [r7, #4] 80068a6: 2200 movs r2, #0 80068a8: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80068ac: 2300 movs r3, #0 } 80068ae: 4618 mov r0, r3 80068b0: 3714 adds r7, #20 80068b2: 46bd mov sp, r7 80068b4: f85d 7b04 ldr.w r7, [sp], #4 80068b8: 4770 bx lr 80068ba: bf00 nop 80068bc: 40010000 .word 0x40010000 80068c0: 40000400 .word 0x40000400 80068c4: 40000800 .word 0x40000800 80068c8: 40000c00 .word 0x40000c00 80068cc: 40010400 .word 0x40010400 80068d0: 40014000 .word 0x40014000 80068d4: 40001800 .word 0x40001800 080068d8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80068d8: b580 push {r7, lr} 80068da: b082 sub sp, #8 80068dc: af00 add r7, sp, #0 80068de: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80068e0: 687b ldr r3, [r7, #4] 80068e2: 2b00 cmp r3, #0 80068e4: d101 bne.n 80068ea { return HAL_ERROR; 80068e6: 2301 movs r3, #1 80068e8: e042 b.n 8006970 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 80068ea: 687b ldr r3, [r7, #4] 80068ec: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80068f0: b2db uxtb r3, r3 80068f2: 2b00 cmp r3, #0 80068f4: d106 bne.n 8006904 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80068f6: 687b ldr r3, [r7, #4] 80068f8: 2200 movs r2, #0 80068fa: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80068fe: 6878 ldr r0, [r7, #4] 8006900: f7fa ffea bl 80018d8 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8006904: 687b ldr r3, [r7, #4] 8006906: 2224 movs r2, #36 @ 0x24 8006908: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 800690c: 687b ldr r3, [r7, #4] 800690e: 681b ldr r3, [r3, #0] 8006910: 68da ldr r2, [r3, #12] 8006912: 687b ldr r3, [r7, #4] 8006914: 681b ldr r3, [r3, #0] 8006916: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800691a: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 800691c: 6878 ldr r0, [r7, #4] 800691e: f000 ff63 bl 80077e8 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8006922: 687b ldr r3, [r7, #4] 8006924: 681b ldr r3, [r3, #0] 8006926: 691a ldr r2, [r3, #16] 8006928: 687b ldr r3, [r7, #4] 800692a: 681b ldr r3, [r3, #0] 800692c: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8006930: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8006932: 687b ldr r3, [r7, #4] 8006934: 681b ldr r3, [r3, #0] 8006936: 695a ldr r2, [r3, #20] 8006938: 687b ldr r3, [r7, #4] 800693a: 681b ldr r3, [r3, #0] 800693c: f022 022a bic.w r2, r2, #42 @ 0x2a 8006940: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8006942: 687b ldr r3, [r7, #4] 8006944: 681b ldr r3, [r3, #0] 8006946: 68da ldr r2, [r3, #12] 8006948: 687b ldr r3, [r7, #4] 800694a: 681b ldr r3, [r3, #0] 800694c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8006950: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006952: 687b ldr r3, [r7, #4] 8006954: 2200 movs r2, #0 8006956: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8006958: 687b ldr r3, [r7, #4] 800695a: 2220 movs r2, #32 800695c: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8006960: 687b ldr r3, [r7, #4] 8006962: 2220 movs r2, #32 8006964: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8006968: 687b ldr r3, [r7, #4] 800696a: 2200 movs r2, #0 800696c: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 800696e: 2300 movs r3, #0 } 8006970: 4618 mov r0, r3 8006972: 3708 adds r7, #8 8006974: 46bd mov sp, r7 8006976: bd80 pop {r7, pc} 08006978 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8006978: b580 push {r7, lr} 800697a: b08c sub sp, #48 @ 0x30 800697c: af00 add r7, sp, #0 800697e: 60f8 str r0, [r7, #12] 8006980: 60b9 str r1, [r7, #8] 8006982: 4613 mov r3, r2 8006984: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8006986: 68fb ldr r3, [r7, #12] 8006988: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800698c: b2db uxtb r3, r3 800698e: 2b20 cmp r3, #32 8006990: d162 bne.n 8006a58 { if ((pData == NULL) || (Size == 0U)) 8006992: 68bb ldr r3, [r7, #8] 8006994: 2b00 cmp r3, #0 8006996: d002 beq.n 800699e 8006998: 88fb ldrh r3, [r7, #6] 800699a: 2b00 cmp r3, #0 800699c: d101 bne.n 80069a2 { return HAL_ERROR; 800699e: 2301 movs r3, #1 80069a0: e05b b.n 8006a5a } huart->pTxBuffPtr = pData; 80069a2: 68ba ldr r2, [r7, #8] 80069a4: 68fb ldr r3, [r7, #12] 80069a6: 621a str r2, [r3, #32] huart->TxXferSize = Size; 80069a8: 68fb ldr r3, [r7, #12] 80069aa: 88fa ldrh r2, [r7, #6] 80069ac: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 80069ae: 68fb ldr r3, [r7, #12] 80069b0: 88fa ldrh r2, [r7, #6] 80069b2: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 80069b4: 68fb ldr r3, [r7, #12] 80069b6: 2200 movs r2, #0 80069b8: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 80069ba: 68fb ldr r3, [r7, #12] 80069bc: 2221 movs r2, #33 @ 0x21 80069be: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 80069c2: 68fb ldr r3, [r7, #12] 80069c4: 6b9b ldr r3, [r3, #56] @ 0x38 80069c6: 4a27 ldr r2, [pc, #156] @ (8006a64 ) 80069c8: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 80069ca: 68fb ldr r3, [r7, #12] 80069cc: 6b9b ldr r3, [r3, #56] @ 0x38 80069ce: 4a26 ldr r2, [pc, #152] @ (8006a68 ) 80069d0: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 80069d2: 68fb ldr r3, [r7, #12] 80069d4: 6b9b ldr r3, [r3, #56] @ 0x38 80069d6: 4a25 ldr r2, [pc, #148] @ (8006a6c ) 80069d8: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 80069da: 68fb ldr r3, [r7, #12] 80069dc: 6b9b ldr r3, [r3, #56] @ 0x38 80069de: 2200 movs r2, #0 80069e0: 651a str r2, [r3, #80] @ 0x50 /* Enable the UART transmit DMA stream */ tmp = (const uint32_t *)&pData; 80069e2: f107 0308 add.w r3, r7, #8 80069e6: 62fb str r3, [r7, #44] @ 0x2c if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) 80069e8: 68fb ldr r3, [r7, #12] 80069ea: 6b98 ldr r0, [r3, #56] @ 0x38 80069ec: 6afb ldr r3, [r7, #44] @ 0x2c 80069ee: 6819 ldr r1, [r3, #0] 80069f0: 68fb ldr r3, [r7, #12] 80069f2: 681b ldr r3, [r3, #0] 80069f4: 3304 adds r3, #4 80069f6: 461a mov r2, r3 80069f8: 88fb ldrh r3, [r7, #6] 80069fa: f7fb fcaf bl 800235c 80069fe: 4603 mov r3, r0 8006a00: 2b00 cmp r3, #0 8006a02: d008 beq.n 8006a16 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8006a04: 68fb ldr r3, [r7, #12] 8006a06: 2210 movs r2, #16 8006a08: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 8006a0a: 68fb ldr r3, [r7, #12] 8006a0c: 2220 movs r2, #32 8006a0e: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_ERROR; 8006a12: 2301 movs r3, #1 8006a14: e021 b.n 8006a5a } /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8006a16: 68fb ldr r3, [r7, #12] 8006a18: 681b ldr r3, [r3, #0] 8006a1a: f06f 0240 mvn.w r2, #64 @ 0x40 8006a1e: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8006a20: 68fb ldr r3, [r7, #12] 8006a22: 681b ldr r3, [r3, #0] 8006a24: 3314 adds r3, #20 8006a26: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006a28: 69bb ldr r3, [r7, #24] 8006a2a: e853 3f00 ldrex r3, [r3] 8006a2e: 617b str r3, [r7, #20] return(result); 8006a30: 697b ldr r3, [r7, #20] 8006a32: f043 0380 orr.w r3, r3, #128 @ 0x80 8006a36: 62bb str r3, [r7, #40] @ 0x28 8006a38: 68fb ldr r3, [r7, #12] 8006a3a: 681b ldr r3, [r3, #0] 8006a3c: 3314 adds r3, #20 8006a3e: 6aba ldr r2, [r7, #40] @ 0x28 8006a40: 627a str r2, [r7, #36] @ 0x24 8006a42: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006a44: 6a39 ldr r1, [r7, #32] 8006a46: 6a7a ldr r2, [r7, #36] @ 0x24 8006a48: e841 2300 strex r3, r2, [r1] 8006a4c: 61fb str r3, [r7, #28] return(result); 8006a4e: 69fb ldr r3, [r7, #28] 8006a50: 2b00 cmp r3, #0 8006a52: d1e5 bne.n 8006a20 return HAL_OK; 8006a54: 2300 movs r3, #0 8006a56: e000 b.n 8006a5a } else { return HAL_BUSY; 8006a58: 2302 movs r3, #2 } } 8006a5a: 4618 mov r0, r3 8006a5c: 3730 adds r7, #48 @ 0x30 8006a5e: 46bd mov sp, r7 8006a60: bd80 pop {r7, pc} 8006a62: bf00 nop 8006a64: 08007065 .word 0x08007065 8006a68: 080070ff .word 0x080070ff 8006a6c: 08007283 .word 0x08007283 08006a70 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8006a70: b580 push {r7, lr} 8006a72: b084 sub sp, #16 8006a74: af00 add r7, sp, #0 8006a76: 60f8 str r0, [r7, #12] 8006a78: 60b9 str r1, [r7, #8] 8006a7a: 4613 mov r3, r2 8006a7c: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8006a7e: 68fb ldr r3, [r7, #12] 8006a80: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8006a84: b2db uxtb r3, r3 8006a86: 2b20 cmp r3, #32 8006a88: d112 bne.n 8006ab0 { if ((pData == NULL) || (Size == 0U)) 8006a8a: 68bb ldr r3, [r7, #8] 8006a8c: 2b00 cmp r3, #0 8006a8e: d002 beq.n 8006a96 8006a90: 88fb ldrh r3, [r7, #6] 8006a92: 2b00 cmp r3, #0 8006a94: d101 bne.n 8006a9a { return HAL_ERROR; 8006a96: 2301 movs r3, #1 8006a98: e00b b.n 8006ab2 } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006a9a: 68fb ldr r3, [r7, #12] 8006a9c: 2200 movs r2, #0 8006a9e: 631a str r2, [r3, #48] @ 0x30 return (UART_Start_Receive_DMA(huart, pData, Size)); 8006aa0: 88fb ldrh r3, [r7, #6] 8006aa2: 461a mov r2, r3 8006aa4: 68b9 ldr r1, [r7, #8] 8006aa6: 68f8 ldr r0, [r7, #12] 8006aa8: f000 fc36 bl 8007318 8006aac: 4603 mov r3, r0 8006aae: e000 b.n 8006ab2 } else { return HAL_BUSY; 8006ab0: 2302 movs r3, #2 } } 8006ab2: 4618 mov r0, r3 8006ab4: 3710 adds r7, #16 8006ab6: 46bd mov sp, r7 8006ab8: bd80 pop {r7, pc} ... 08006abc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8006abc: b580 push {r7, lr} 8006abe: b0ba sub sp, #232 @ 0xe8 8006ac0: af00 add r7, sp, #0 8006ac2: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8006ac4: 687b ldr r3, [r7, #4] 8006ac6: 681b ldr r3, [r3, #0] 8006ac8: 681b ldr r3, [r3, #0] 8006aca: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8006ace: 687b ldr r3, [r7, #4] 8006ad0: 681b ldr r3, [r3, #0] 8006ad2: 68db ldr r3, [r3, #12] 8006ad4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8006ad8: 687b ldr r3, [r7, #4] 8006ada: 681b ldr r3, [r3, #0] 8006adc: 695b ldr r3, [r3, #20] 8006ade: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8006ae2: 2300 movs r3, #0 8006ae4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8006ae8: 2300 movs r3, #0 8006aea: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8006aee: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006af2: f003 030f and.w r3, r3, #15 8006af6: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8006afa: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8006afe: 2b00 cmp r3, #0 8006b00: d10f bne.n 8006b22 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8006b02: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006b06: f003 0320 and.w r3, r3, #32 8006b0a: 2b00 cmp r3, #0 8006b0c: d009 beq.n 8006b22 8006b0e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006b12: f003 0320 and.w r3, r3, #32 8006b16: 2b00 cmp r3, #0 8006b18: d003 beq.n 8006b22 { UART_Receive_IT(huart); 8006b1a: 6878 ldr r0, [r7, #4] 8006b1c: f000 fda6 bl 800766c return; 8006b20: e273 b.n 800700a } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8006b22: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8006b26: 2b00 cmp r3, #0 8006b28: f000 80de beq.w 8006ce8 8006b2c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8006b30: f003 0301 and.w r3, r3, #1 8006b34: 2b00 cmp r3, #0 8006b36: d106 bne.n 8006b46 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8006b38: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006b3c: f403 7390 and.w r3, r3, #288 @ 0x120 8006b40: 2b00 cmp r3, #0 8006b42: f000 80d1 beq.w 8006ce8 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8006b46: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006b4a: f003 0301 and.w r3, r3, #1 8006b4e: 2b00 cmp r3, #0 8006b50: d00b beq.n 8006b6a 8006b52: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006b56: f403 7380 and.w r3, r3, #256 @ 0x100 8006b5a: 2b00 cmp r3, #0 8006b5c: d005 beq.n 8006b6a { huart->ErrorCode |= HAL_UART_ERROR_PE; 8006b5e: 687b ldr r3, [r7, #4] 8006b60: 6c5b ldr r3, [r3, #68] @ 0x44 8006b62: f043 0201 orr.w r2, r3, #1 8006b66: 687b ldr r3, [r7, #4] 8006b68: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8006b6a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006b6e: f003 0304 and.w r3, r3, #4 8006b72: 2b00 cmp r3, #0 8006b74: d00b beq.n 8006b8e 8006b76: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8006b7a: f003 0301 and.w r3, r3, #1 8006b7e: 2b00 cmp r3, #0 8006b80: d005 beq.n 8006b8e { huart->ErrorCode |= HAL_UART_ERROR_NE; 8006b82: 687b ldr r3, [r7, #4] 8006b84: 6c5b ldr r3, [r3, #68] @ 0x44 8006b86: f043 0202 orr.w r2, r3, #2 8006b8a: 687b ldr r3, [r7, #4] 8006b8c: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8006b8e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006b92: f003 0302 and.w r3, r3, #2 8006b96: 2b00 cmp r3, #0 8006b98: d00b beq.n 8006bb2 8006b9a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8006b9e: f003 0301 and.w r3, r3, #1 8006ba2: 2b00 cmp r3, #0 8006ba4: d005 beq.n 8006bb2 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8006ba6: 687b ldr r3, [r7, #4] 8006ba8: 6c5b ldr r3, [r3, #68] @ 0x44 8006baa: f043 0204 orr.w r2, r3, #4 8006bae: 687b ldr r3, [r7, #4] 8006bb0: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8006bb2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006bb6: f003 0308 and.w r3, r3, #8 8006bba: 2b00 cmp r3, #0 8006bbc: d011 beq.n 8006be2 8006bbe: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006bc2: f003 0320 and.w r3, r3, #32 8006bc6: 2b00 cmp r3, #0 8006bc8: d105 bne.n 8006bd6 || ((cr3its & USART_CR3_EIE) != RESET))) 8006bca: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8006bce: f003 0301 and.w r3, r3, #1 8006bd2: 2b00 cmp r3, #0 8006bd4: d005 beq.n 8006be2 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8006bd6: 687b ldr r3, [r7, #4] 8006bd8: 6c5b ldr r3, [r3, #68] @ 0x44 8006bda: f043 0208 orr.w r2, r3, #8 8006bde: 687b ldr r3, [r7, #4] 8006be0: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8006be2: 687b ldr r3, [r7, #4] 8006be4: 6c5b ldr r3, [r3, #68] @ 0x44 8006be6: 2b00 cmp r3, #0 8006be8: f000 820a beq.w 8007000 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8006bec: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006bf0: f003 0320 and.w r3, r3, #32 8006bf4: 2b00 cmp r3, #0 8006bf6: d008 beq.n 8006c0a 8006bf8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006bfc: f003 0320 and.w r3, r3, #32 8006c00: 2b00 cmp r3, #0 8006c02: d002 beq.n 8006c0a { UART_Receive_IT(huart); 8006c04: 6878 ldr r0, [r7, #4] 8006c06: f000 fd31 bl 800766c } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8006c0a: 687b ldr r3, [r7, #4] 8006c0c: 681b ldr r3, [r3, #0] 8006c0e: 695b ldr r3, [r3, #20] 8006c10: f003 0340 and.w r3, r3, #64 @ 0x40 8006c14: 2b40 cmp r3, #64 @ 0x40 8006c16: bf0c ite eq 8006c18: 2301 moveq r3, #1 8006c1a: 2300 movne r3, #0 8006c1c: b2db uxtb r3, r3 8006c1e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8006c22: 687b ldr r3, [r7, #4] 8006c24: 6c5b ldr r3, [r3, #68] @ 0x44 8006c26: f003 0308 and.w r3, r3, #8 8006c2a: 2b00 cmp r3, #0 8006c2c: d103 bne.n 8006c36 8006c2e: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8006c32: 2b00 cmp r3, #0 8006c34: d04f beq.n 8006cd6 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8006c36: 6878 ldr r0, [r7, #4] 8006c38: f000 fc3c bl 80074b4 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006c3c: 687b ldr r3, [r7, #4] 8006c3e: 681b ldr r3, [r3, #0] 8006c40: 695b ldr r3, [r3, #20] 8006c42: f003 0340 and.w r3, r3, #64 @ 0x40 8006c46: 2b40 cmp r3, #64 @ 0x40 8006c48: d141 bne.n 8006cce { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006c4a: 687b ldr r3, [r7, #4] 8006c4c: 681b ldr r3, [r3, #0] 8006c4e: 3314 adds r3, #20 8006c50: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006c54: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8006c58: e853 3f00 ldrex r3, [r3] 8006c5c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8006c60: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8006c64: f023 0340 bic.w r3, r3, #64 @ 0x40 8006c68: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8006c6c: 687b ldr r3, [r7, #4] 8006c6e: 681b ldr r3, [r3, #0] 8006c70: 3314 adds r3, #20 8006c72: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8006c76: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8006c7a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006c7e: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8006c82: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8006c86: e841 2300 strex r3, r2, [r1] 8006c8a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8006c8e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8006c92: 2b00 cmp r3, #0 8006c94: d1d9 bne.n 8006c4a /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) 8006c96: 687b ldr r3, [r7, #4] 8006c98: 6bdb ldr r3, [r3, #60] @ 0x3c 8006c9a: 2b00 cmp r3, #0 8006c9c: d013 beq.n 8006cc6 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8006c9e: 687b ldr r3, [r7, #4] 8006ca0: 6bdb ldr r3, [r3, #60] @ 0x3c 8006ca2: 4a8a ldr r2, [pc, #552] @ (8006ecc ) 8006ca4: 651a str r2, [r3, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8006ca6: 687b ldr r3, [r7, #4] 8006ca8: 6bdb ldr r3, [r3, #60] @ 0x3c 8006caa: 4618 mov r0, r3 8006cac: f7fb fc1e bl 80024ec 8006cb0: 4603 mov r3, r0 8006cb2: 2b00 cmp r3, #0 8006cb4: d016 beq.n 8006ce4 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8006cb6: 687b ldr r3, [r7, #4] 8006cb8: 6bdb ldr r3, [r3, #60] @ 0x3c 8006cba: 6d1b ldr r3, [r3, #80] @ 0x50 8006cbc: 687a ldr r2, [r7, #4] 8006cbe: 6bd2 ldr r2, [r2, #60] @ 0x3c 8006cc0: 4610 mov r0, r2 8006cc2: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006cc4: e00e b.n 8006ce4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006cc6: 6878 ldr r0, [r7, #4] 8006cc8: f7fa f900 bl 8000ecc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006ccc: e00a b.n 8006ce4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006cce: 6878 ldr r0, [r7, #4] 8006cd0: f7fa f8fc bl 8000ecc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006cd4: e006 b.n 8006ce4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006cd6: 6878 ldr r0, [r7, #4] 8006cd8: f7fa f8f8 bl 8000ecc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006cdc: 687b ldr r3, [r7, #4] 8006cde: 2200 movs r2, #0 8006ce0: 645a str r2, [r3, #68] @ 0x44 } } return; 8006ce2: e18d b.n 8007000 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006ce4: bf00 nop return; 8006ce6: e18b b.n 8007000 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006ce8: 687b ldr r3, [r7, #4] 8006cea: 6b1b ldr r3, [r3, #48] @ 0x30 8006cec: 2b01 cmp r3, #1 8006cee: f040 8167 bne.w 8006fc0 && ((isrflags & USART_SR_IDLE) != 0U) 8006cf2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006cf6: f003 0310 and.w r3, r3, #16 8006cfa: 2b00 cmp r3, #0 8006cfc: f000 8160 beq.w 8006fc0 && ((cr1its & USART_CR1_IDLEIE) != 0U)) 8006d00: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006d04: f003 0310 and.w r3, r3, #16 8006d08: 2b00 cmp r3, #0 8006d0a: f000 8159 beq.w 8006fc0 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8006d0e: 2300 movs r3, #0 8006d10: 60bb str r3, [r7, #8] 8006d12: 687b ldr r3, [r7, #4] 8006d14: 681b ldr r3, [r3, #0] 8006d16: 681b ldr r3, [r3, #0] 8006d18: 60bb str r3, [r7, #8] 8006d1a: 687b ldr r3, [r7, #4] 8006d1c: 681b ldr r3, [r3, #0] 8006d1e: 685b ldr r3, [r3, #4] 8006d20: 60bb str r3, [r7, #8] 8006d22: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006d24: 687b ldr r3, [r7, #4] 8006d26: 681b ldr r3, [r3, #0] 8006d28: 695b ldr r3, [r3, #20] 8006d2a: f003 0340 and.w r3, r3, #64 @ 0x40 8006d2e: 2b40 cmp r3, #64 @ 0x40 8006d30: f040 80ce bne.w 8006ed0 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8006d34: 687b ldr r3, [r7, #4] 8006d36: 6bdb ldr r3, [r3, #60] @ 0x3c 8006d38: 681b ldr r3, [r3, #0] 8006d3a: 685b ldr r3, [r3, #4] 8006d3c: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8006d40: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8006d44: 2b00 cmp r3, #0 8006d46: f000 80a9 beq.w 8006e9c && (nb_remaining_rx_data < huart->RxXferSize)) 8006d4a: 687b ldr r3, [r7, #4] 8006d4c: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006d4e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006d52: 429a cmp r2, r3 8006d54: f080 80a2 bcs.w 8006e9c { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8006d58: 687b ldr r3, [r7, #4] 8006d5a: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006d5e: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8006d60: 687b ldr r3, [r7, #4] 8006d62: 6bdb ldr r3, [r3, #60] @ 0x3c 8006d64: 69db ldr r3, [r3, #28] 8006d66: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006d6a: f000 8088 beq.w 8006e7e { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006d6e: 687b ldr r3, [r7, #4] 8006d70: 681b ldr r3, [r3, #0] 8006d72: 330c adds r3, #12 8006d74: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006d78: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8006d7c: e853 3f00 ldrex r3, [r3] 8006d80: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8006d84: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8006d88: f423 7380 bic.w r3, r3, #256 @ 0x100 8006d8c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006d90: 687b ldr r3, [r7, #4] 8006d92: 681b ldr r3, [r3, #0] 8006d94: 330c adds r3, #12 8006d96: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8006d9a: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8006d9e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006da2: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8006da6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8006daa: e841 2300 strex r3, r2, [r1] 8006dae: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8006db2: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8006db6: 2b00 cmp r3, #0 8006db8: d1d9 bne.n 8006d6e ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006dba: 687b ldr r3, [r7, #4] 8006dbc: 681b ldr r3, [r3, #0] 8006dbe: 3314 adds r3, #20 8006dc0: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006dc2: 6f7b ldr r3, [r7, #116] @ 0x74 8006dc4: e853 3f00 ldrex r3, [r3] 8006dc8: 673b str r3, [r7, #112] @ 0x70 return(result); 8006dca: 6f3b ldr r3, [r7, #112] @ 0x70 8006dcc: f023 0301 bic.w r3, r3, #1 8006dd0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006dd4: 687b ldr r3, [r7, #4] 8006dd6: 681b ldr r3, [r3, #0] 8006dd8: 3314 adds r3, #20 8006dda: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8006dde: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8006de2: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006de4: 6ff9 ldr r1, [r7, #124] @ 0x7c 8006de6: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8006dea: e841 2300 strex r3, r2, [r1] 8006dee: 67bb str r3, [r7, #120] @ 0x78 return(result); 8006df0: 6fbb ldr r3, [r7, #120] @ 0x78 8006df2: 2b00 cmp r3, #0 8006df4: d1e1 bne.n 8006dba /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006df6: 687b ldr r3, [r7, #4] 8006df8: 681b ldr r3, [r3, #0] 8006dfa: 3314 adds r3, #20 8006dfc: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006dfe: 6e3b ldr r3, [r7, #96] @ 0x60 8006e00: e853 3f00 ldrex r3, [r3] 8006e04: 65fb str r3, [r7, #92] @ 0x5c return(result); 8006e06: 6dfb ldr r3, [r7, #92] @ 0x5c 8006e08: f023 0340 bic.w r3, r3, #64 @ 0x40 8006e0c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8006e10: 687b ldr r3, [r7, #4] 8006e12: 681b ldr r3, [r3, #0] 8006e14: 3314 adds r3, #20 8006e16: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8006e1a: 66fa str r2, [r7, #108] @ 0x6c 8006e1c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006e1e: 6eb9 ldr r1, [r7, #104] @ 0x68 8006e20: 6efa ldr r2, [r7, #108] @ 0x6c 8006e22: e841 2300 strex r3, r2, [r1] 8006e26: 667b str r3, [r7, #100] @ 0x64 return(result); 8006e28: 6e7b ldr r3, [r7, #100] @ 0x64 8006e2a: 2b00 cmp r3, #0 8006e2c: d1e3 bne.n 8006df6 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006e2e: 687b ldr r3, [r7, #4] 8006e30: 2220 movs r2, #32 8006e32: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006e36: 687b ldr r3, [r7, #4] 8006e38: 2200 movs r2, #0 8006e3a: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006e3c: 687b ldr r3, [r7, #4] 8006e3e: 681b ldr r3, [r3, #0] 8006e40: 330c adds r3, #12 8006e42: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006e44: 6cfb ldr r3, [r7, #76] @ 0x4c 8006e46: e853 3f00 ldrex r3, [r3] 8006e4a: 64bb str r3, [r7, #72] @ 0x48 return(result); 8006e4c: 6cbb ldr r3, [r7, #72] @ 0x48 8006e4e: f023 0310 bic.w r3, r3, #16 8006e52: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8006e56: 687b ldr r3, [r7, #4] 8006e58: 681b ldr r3, [r3, #0] 8006e5a: 330c adds r3, #12 8006e5c: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8006e60: 65ba str r2, [r7, #88] @ 0x58 8006e62: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006e64: 6d79 ldr r1, [r7, #84] @ 0x54 8006e66: 6dba ldr r2, [r7, #88] @ 0x58 8006e68: e841 2300 strex r3, r2, [r1] 8006e6c: 653b str r3, [r7, #80] @ 0x50 return(result); 8006e6e: 6d3b ldr r3, [r7, #80] @ 0x50 8006e70: 2b00 cmp r3, #0 8006e72: d1e3 bne.n 8006e3c /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8006e74: 687b ldr r3, [r7, #4] 8006e76: 6bdb ldr r3, [r3, #60] @ 0x3c 8006e78: 4618 mov r0, r3 8006e7a: f7fb fac7 bl 800240c } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006e7e: 687b ldr r3, [r7, #4] 8006e80: 2202 movs r2, #2 8006e82: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8006e84: 687b ldr r3, [r7, #4] 8006e86: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006e88: 687b ldr r3, [r7, #4] 8006e8a: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006e8c: b29b uxth r3, r3 8006e8e: 1ad3 subs r3, r2, r3 8006e90: b29b uxth r3, r3 8006e92: 4619 mov r1, r3 8006e94: 6878 ldr r0, [r7, #4] 8006e96: f000 f8d9 bl 800704c HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 8006e9a: e0b3 b.n 8007004 if (nb_remaining_rx_data == huart->RxXferSize) 8006e9c: 687b ldr r3, [r7, #4] 8006e9e: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006ea0: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006ea4: 429a cmp r2, r3 8006ea6: f040 80ad bne.w 8007004 if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 8006eaa: 687b ldr r3, [r7, #4] 8006eac: 6bdb ldr r3, [r3, #60] @ 0x3c 8006eae: 69db ldr r3, [r3, #28] 8006eb0: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006eb4: f040 80a6 bne.w 8007004 huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006eb8: 687b ldr r3, [r7, #4] 8006eba: 2202 movs r2, #2 8006ebc: 635a str r2, [r3, #52] @ 0x34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006ebe: 687b ldr r3, [r7, #4] 8006ec0: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006ec2: 4619 mov r1, r3 8006ec4: 6878 ldr r0, [r7, #4] 8006ec6: f000 f8c1 bl 800704c return; 8006eca: e09b b.n 8007004 8006ecc: 0800757b .word 0x0800757b else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8006ed0: 687b ldr r3, [r7, #4] 8006ed2: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006ed4: 687b ldr r3, [r7, #4] 8006ed6: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006ed8: b29b uxth r3, r3 8006eda: 1ad3 subs r3, r2, r3 8006edc: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8006ee0: 687b ldr r3, [r7, #4] 8006ee2: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006ee4: b29b uxth r3, r3 8006ee6: 2b00 cmp r3, #0 8006ee8: f000 808e beq.w 8007008 && (nb_rx_data > 0U)) 8006eec: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006ef0: 2b00 cmp r3, #0 8006ef2: f000 8089 beq.w 8007008 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006ef6: 687b ldr r3, [r7, #4] 8006ef8: 681b ldr r3, [r3, #0] 8006efa: 330c adds r3, #12 8006efc: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006efe: 6bbb ldr r3, [r7, #56] @ 0x38 8006f00: e853 3f00 ldrex r3, [r3] 8006f04: 637b str r3, [r7, #52] @ 0x34 return(result); 8006f06: 6b7b ldr r3, [r7, #52] @ 0x34 8006f08: f423 7390 bic.w r3, r3, #288 @ 0x120 8006f0c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006f10: 687b ldr r3, [r7, #4] 8006f12: 681b ldr r3, [r3, #0] 8006f14: 330c adds r3, #12 8006f16: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8006f1a: 647a str r2, [r7, #68] @ 0x44 8006f1c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006f1e: 6c39 ldr r1, [r7, #64] @ 0x40 8006f20: 6c7a ldr r2, [r7, #68] @ 0x44 8006f22: e841 2300 strex r3, r2, [r1] 8006f26: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006f28: 6bfb ldr r3, [r7, #60] @ 0x3c 8006f2a: 2b00 cmp r3, #0 8006f2c: d1e3 bne.n 8006ef6 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006f2e: 687b ldr r3, [r7, #4] 8006f30: 681b ldr r3, [r3, #0] 8006f32: 3314 adds r3, #20 8006f34: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006f36: 6a7b ldr r3, [r7, #36] @ 0x24 8006f38: e853 3f00 ldrex r3, [r3] 8006f3c: 623b str r3, [r7, #32] return(result); 8006f3e: 6a3b ldr r3, [r7, #32] 8006f40: f023 0301 bic.w r3, r3, #1 8006f44: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8006f48: 687b ldr r3, [r7, #4] 8006f4a: 681b ldr r3, [r3, #0] 8006f4c: 3314 adds r3, #20 8006f4e: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8006f52: 633a str r2, [r7, #48] @ 0x30 8006f54: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006f56: 6af9 ldr r1, [r7, #44] @ 0x2c 8006f58: 6b3a ldr r2, [r7, #48] @ 0x30 8006f5a: e841 2300 strex r3, r2, [r1] 8006f5e: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006f60: 6abb ldr r3, [r7, #40] @ 0x28 8006f62: 2b00 cmp r3, #0 8006f64: d1e3 bne.n 8006f2e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006f66: 687b ldr r3, [r7, #4] 8006f68: 2220 movs r2, #32 8006f6a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006f6e: 687b ldr r3, [r7, #4] 8006f70: 2200 movs r2, #0 8006f72: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006f74: 687b ldr r3, [r7, #4] 8006f76: 681b ldr r3, [r3, #0] 8006f78: 330c adds r3, #12 8006f7a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006f7c: 693b ldr r3, [r7, #16] 8006f7e: e853 3f00 ldrex r3, [r3] 8006f82: 60fb str r3, [r7, #12] return(result); 8006f84: 68fb ldr r3, [r7, #12] 8006f86: f023 0310 bic.w r3, r3, #16 8006f8a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006f8e: 687b ldr r3, [r7, #4] 8006f90: 681b ldr r3, [r3, #0] 8006f92: 330c adds r3, #12 8006f94: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8006f98: 61fa str r2, [r7, #28] 8006f9a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006f9c: 69b9 ldr r1, [r7, #24] 8006f9e: 69fa ldr r2, [r7, #28] 8006fa0: e841 2300 strex r3, r2, [r1] 8006fa4: 617b str r3, [r7, #20] return(result); 8006fa6: 697b ldr r3, [r7, #20] 8006fa8: 2b00 cmp r3, #0 8006faa: d1e3 bne.n 8006f74 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006fac: 687b ldr r3, [r7, #4] 8006fae: 2202 movs r2, #2 8006fb0: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8006fb2: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006fb6: 4619 mov r1, r3 8006fb8: 6878 ldr r0, [r7, #4] 8006fba: f000 f847 bl 800704c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8006fbe: e023 b.n 8007008 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8006fc0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006fc4: f003 0380 and.w r3, r3, #128 @ 0x80 8006fc8: 2b00 cmp r3, #0 8006fca: d009 beq.n 8006fe0 8006fcc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006fd0: f003 0380 and.w r3, r3, #128 @ 0x80 8006fd4: 2b00 cmp r3, #0 8006fd6: d003 beq.n 8006fe0 { UART_Transmit_IT(huart); 8006fd8: 6878 ldr r0, [r7, #4] 8006fda: f000 fadf bl 800759c return; 8006fde: e014 b.n 800700a } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8006fe0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006fe4: f003 0340 and.w r3, r3, #64 @ 0x40 8006fe8: 2b00 cmp r3, #0 8006fea: d00e beq.n 800700a 8006fec: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006ff0: f003 0340 and.w r3, r3, #64 @ 0x40 8006ff4: 2b00 cmp r3, #0 8006ff6: d008 beq.n 800700a { UART_EndTransmit_IT(huart); 8006ff8: 6878 ldr r0, [r7, #4] 8006ffa: f000 fb1f bl 800763c return; 8006ffe: e004 b.n 800700a return; 8007000: bf00 nop 8007002: e002 b.n 800700a return; 8007004: bf00 nop 8007006: e000 b.n 800700a return; 8007008: bf00 nop } } 800700a: 37e8 adds r7, #232 @ 0xe8 800700c: 46bd mov sp, r7 800700e: bd80 pop {r7, pc} 08007010 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8007010: b480 push {r7} 8007012: b083 sub sp, #12 8007014: af00 add r7, sp, #0 8007016: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8007018: bf00 nop 800701a: 370c adds r7, #12 800701c: 46bd mov sp, r7 800701e: f85d 7b04 ldr.w r7, [sp], #4 8007022: 4770 bx lr 08007024 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8007024: b480 push {r7} 8007026: b083 sub sp, #12 8007028: af00 add r7, sp, #0 800702a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 800702c: bf00 nop 800702e: 370c adds r7, #12 8007030: 46bd mov sp, r7 8007032: f85d 7b04 ldr.w r7, [sp], #4 8007036: 4770 bx lr 08007038 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8007038: b480 push {r7} 800703a: b083 sub sp, #12 800703c: af00 add r7, sp, #0 800703e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 8007040: bf00 nop 8007042: 370c adds r7, #12 8007044: 46bd mov sp, r7 8007046: f85d 7b04 ldr.w r7, [sp], #4 800704a: 4770 bx lr 0800704c : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800704c: b480 push {r7} 800704e: b083 sub sp, #12 8007050: af00 add r7, sp, #0 8007052: 6078 str r0, [r7, #4] 8007054: 460b mov r3, r1 8007056: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8007058: bf00 nop 800705a: 370c adds r7, #12 800705c: 46bd mov sp, r7 800705e: f85d 7b04 ldr.w r7, [sp], #4 8007062: 4770 bx lr 08007064 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8007064: b580 push {r7, lr} 8007066: b090 sub sp, #64 @ 0x40 8007068: af00 add r7, sp, #0 800706a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800706c: 687b ldr r3, [r7, #4] 800706e: 6b9b ldr r3, [r3, #56] @ 0x38 8007070: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8007072: 687b ldr r3, [r7, #4] 8007074: 681b ldr r3, [r3, #0] 8007076: 681b ldr r3, [r3, #0] 8007078: f403 7380 and.w r3, r3, #256 @ 0x100 800707c: 2b00 cmp r3, #0 800707e: d137 bne.n 80070f0 { huart->TxXferCount = 0x00U; 8007080: 6bfb ldr r3, [r7, #60] @ 0x3c 8007082: 2200 movs r2, #0 8007084: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8007086: 6bfb ldr r3, [r7, #60] @ 0x3c 8007088: 681b ldr r3, [r3, #0] 800708a: 3314 adds r3, #20 800708c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800708e: 6a7b ldr r3, [r7, #36] @ 0x24 8007090: e853 3f00 ldrex r3, [r3] 8007094: 623b str r3, [r7, #32] return(result); 8007096: 6a3b ldr r3, [r7, #32] 8007098: f023 0380 bic.w r3, r3, #128 @ 0x80 800709c: 63bb str r3, [r7, #56] @ 0x38 800709e: 6bfb ldr r3, [r7, #60] @ 0x3c 80070a0: 681b ldr r3, [r3, #0] 80070a2: 3314 adds r3, #20 80070a4: 6bba ldr r2, [r7, #56] @ 0x38 80070a6: 633a str r2, [r7, #48] @ 0x30 80070a8: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80070aa: 6af9 ldr r1, [r7, #44] @ 0x2c 80070ac: 6b3a ldr r2, [r7, #48] @ 0x30 80070ae: e841 2300 strex r3, r2, [r1] 80070b2: 62bb str r3, [r7, #40] @ 0x28 return(result); 80070b4: 6abb ldr r3, [r7, #40] @ 0x28 80070b6: 2b00 cmp r3, #0 80070b8: d1e5 bne.n 8007086 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80070ba: 6bfb ldr r3, [r7, #60] @ 0x3c 80070bc: 681b ldr r3, [r3, #0] 80070be: 330c adds r3, #12 80070c0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80070c2: 693b ldr r3, [r7, #16] 80070c4: e853 3f00 ldrex r3, [r3] 80070c8: 60fb str r3, [r7, #12] return(result); 80070ca: 68fb ldr r3, [r7, #12] 80070cc: f043 0340 orr.w r3, r3, #64 @ 0x40 80070d0: 637b str r3, [r7, #52] @ 0x34 80070d2: 6bfb ldr r3, [r7, #60] @ 0x3c 80070d4: 681b ldr r3, [r3, #0] 80070d6: 330c adds r3, #12 80070d8: 6b7a ldr r2, [r7, #52] @ 0x34 80070da: 61fa str r2, [r7, #28] 80070dc: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80070de: 69b9 ldr r1, [r7, #24] 80070e0: 69fa ldr r2, [r7, #28] 80070e2: e841 2300 strex r3, r2, [r1] 80070e6: 617b str r3, [r7, #20] return(result); 80070e8: 697b ldr r3, [r7, #20] 80070ea: 2b00 cmp r3, #0 80070ec: d1e5 bne.n 80070ba #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80070ee: e002 b.n 80070f6 HAL_UART_TxCpltCallback(huart); 80070f0: 6bf8 ldr r0, [r7, #60] @ 0x3c 80070f2: f7ff ff8d bl 8007010 } 80070f6: bf00 nop 80070f8: 3740 adds r7, #64 @ 0x40 80070fa: 46bd mov sp, r7 80070fc: bd80 pop {r7, pc} 080070fe : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 80070fe: b580 push {r7, lr} 8007100: b084 sub sp, #16 8007102: af00 add r7, sp, #0 8007104: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007106: 687b ldr r3, [r7, #4] 8007108: 6b9b ldr r3, [r3, #56] @ 0x38 800710a: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 800710c: 68f8 ldr r0, [r7, #12] 800710e: f7ff ff89 bl 8007024 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8007112: bf00 nop 8007114: 3710 adds r7, #16 8007116: 46bd mov sp, r7 8007118: bd80 pop {r7, pc} 0800711a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 800711a: b580 push {r7, lr} 800711c: b09c sub sp, #112 @ 0x70 800711e: af00 add r7, sp, #0 8007120: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007122: 687b ldr r3, [r7, #4] 8007124: 6b9b ldr r3, [r3, #56] @ 0x38 8007126: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8007128: 687b ldr r3, [r7, #4] 800712a: 681b ldr r3, [r3, #0] 800712c: 681b ldr r3, [r3, #0] 800712e: f403 7380 and.w r3, r3, #256 @ 0x100 8007132: 2b00 cmp r3, #0 8007134: d172 bne.n 800721c { huart->RxXferCount = 0U; 8007136: 6efb ldr r3, [r7, #108] @ 0x6c 8007138: 2200 movs r2, #0 800713a: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800713c: 6efb ldr r3, [r7, #108] @ 0x6c 800713e: 681b ldr r3, [r3, #0] 8007140: 330c adds r3, #12 8007142: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007144: 6cfb ldr r3, [r7, #76] @ 0x4c 8007146: e853 3f00 ldrex r3, [r3] 800714a: 64bb str r3, [r7, #72] @ 0x48 return(result); 800714c: 6cbb ldr r3, [r7, #72] @ 0x48 800714e: f423 7380 bic.w r3, r3, #256 @ 0x100 8007152: 66bb str r3, [r7, #104] @ 0x68 8007154: 6efb ldr r3, [r7, #108] @ 0x6c 8007156: 681b ldr r3, [r3, #0] 8007158: 330c adds r3, #12 800715a: 6eba ldr r2, [r7, #104] @ 0x68 800715c: 65ba str r2, [r7, #88] @ 0x58 800715e: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007160: 6d79 ldr r1, [r7, #84] @ 0x54 8007162: 6dba ldr r2, [r7, #88] @ 0x58 8007164: e841 2300 strex r3, r2, [r1] 8007168: 653b str r3, [r7, #80] @ 0x50 return(result); 800716a: 6d3b ldr r3, [r7, #80] @ 0x50 800716c: 2b00 cmp r3, #0 800716e: d1e5 bne.n 800713c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8007170: 6efb ldr r3, [r7, #108] @ 0x6c 8007172: 681b ldr r3, [r3, #0] 8007174: 3314 adds r3, #20 8007176: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007178: 6bbb ldr r3, [r7, #56] @ 0x38 800717a: e853 3f00 ldrex r3, [r3] 800717e: 637b str r3, [r7, #52] @ 0x34 return(result); 8007180: 6b7b ldr r3, [r7, #52] @ 0x34 8007182: f023 0301 bic.w r3, r3, #1 8007186: 667b str r3, [r7, #100] @ 0x64 8007188: 6efb ldr r3, [r7, #108] @ 0x6c 800718a: 681b ldr r3, [r3, #0] 800718c: 3314 adds r3, #20 800718e: 6e7a ldr r2, [r7, #100] @ 0x64 8007190: 647a str r2, [r7, #68] @ 0x44 8007192: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007194: 6c39 ldr r1, [r7, #64] @ 0x40 8007196: 6c7a ldr r2, [r7, #68] @ 0x44 8007198: e841 2300 strex r3, r2, [r1] 800719c: 63fb str r3, [r7, #60] @ 0x3c return(result); 800719e: 6bfb ldr r3, [r7, #60] @ 0x3c 80071a0: 2b00 cmp r3, #0 80071a2: d1e5 bne.n 8007170 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80071a4: 6efb ldr r3, [r7, #108] @ 0x6c 80071a6: 681b ldr r3, [r3, #0] 80071a8: 3314 adds r3, #20 80071aa: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80071ac: 6a7b ldr r3, [r7, #36] @ 0x24 80071ae: e853 3f00 ldrex r3, [r3] 80071b2: 623b str r3, [r7, #32] return(result); 80071b4: 6a3b ldr r3, [r7, #32] 80071b6: f023 0340 bic.w r3, r3, #64 @ 0x40 80071ba: 663b str r3, [r7, #96] @ 0x60 80071bc: 6efb ldr r3, [r7, #108] @ 0x6c 80071be: 681b ldr r3, [r3, #0] 80071c0: 3314 adds r3, #20 80071c2: 6e3a ldr r2, [r7, #96] @ 0x60 80071c4: 633a str r2, [r7, #48] @ 0x30 80071c6: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80071c8: 6af9 ldr r1, [r7, #44] @ 0x2c 80071ca: 6b3a ldr r2, [r7, #48] @ 0x30 80071cc: e841 2300 strex r3, r2, [r1] 80071d0: 62bb str r3, [r7, #40] @ 0x28 return(result); 80071d2: 6abb ldr r3, [r7, #40] @ 0x28 80071d4: 2b00 cmp r3, #0 80071d6: d1e5 bne.n 80071a4 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80071d8: 6efb ldr r3, [r7, #108] @ 0x6c 80071da: 2220 movs r2, #32 80071dc: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80071e0: 6efb ldr r3, [r7, #108] @ 0x6c 80071e2: 6b1b ldr r3, [r3, #48] @ 0x30 80071e4: 2b01 cmp r3, #1 80071e6: d119 bne.n 800721c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80071e8: 6efb ldr r3, [r7, #108] @ 0x6c 80071ea: 681b ldr r3, [r3, #0] 80071ec: 330c adds r3, #12 80071ee: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80071f0: 693b ldr r3, [r7, #16] 80071f2: e853 3f00 ldrex r3, [r3] 80071f6: 60fb str r3, [r7, #12] return(result); 80071f8: 68fb ldr r3, [r7, #12] 80071fa: f023 0310 bic.w r3, r3, #16 80071fe: 65fb str r3, [r7, #92] @ 0x5c 8007200: 6efb ldr r3, [r7, #108] @ 0x6c 8007202: 681b ldr r3, [r3, #0] 8007204: 330c adds r3, #12 8007206: 6dfa ldr r2, [r7, #92] @ 0x5c 8007208: 61fa str r2, [r7, #28] 800720a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800720c: 69b9 ldr r1, [r7, #24] 800720e: 69fa ldr r2, [r7, #28] 8007210: e841 2300 strex r3, r2, [r1] 8007214: 617b str r3, [r7, #20] return(result); 8007216: 697b ldr r3, [r7, #20] 8007218: 2b00 cmp r3, #0 800721a: d1e5 bne.n 80071e8 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800721c: 6efb ldr r3, [r7, #108] @ 0x6c 800721e: 2200 movs r2, #0 8007220: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8007222: 6efb ldr r3, [r7, #108] @ 0x6c 8007224: 6b1b ldr r3, [r3, #48] @ 0x30 8007226: 2b01 cmp r3, #1 8007228: d106 bne.n 8007238 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800722a: 6efb ldr r3, [r7, #108] @ 0x6c 800722c: 8d9b ldrh r3, [r3, #44] @ 0x2c 800722e: 4619 mov r1, r3 8007230: 6ef8 ldr r0, [r7, #108] @ 0x6c 8007232: f7ff ff0b bl 800704c #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8007236: e002 b.n 800723e HAL_UART_RxCpltCallback(huart); 8007238: 6ef8 ldr r0, [r7, #108] @ 0x6c 800723a: f7f9 fdeb bl 8000e14 } 800723e: bf00 nop 8007240: 3770 adds r7, #112 @ 0x70 8007242: 46bd mov sp, r7 8007244: bd80 pop {r7, pc} 08007246 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8007246: b580 push {r7, lr} 8007248: b084 sub sp, #16 800724a: af00 add r7, sp, #0 800724c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800724e: 687b ldr r3, [r7, #4] 8007250: 6b9b ldr r3, [r3, #56] @ 0x38 8007252: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 8007254: 68fb ldr r3, [r7, #12] 8007256: 2201 movs r2, #1 8007258: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800725a: 68fb ldr r3, [r7, #12] 800725c: 6b1b ldr r3, [r3, #48] @ 0x30 800725e: 2b01 cmp r3, #1 8007260: d108 bne.n 8007274 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 8007262: 68fb ldr r3, [r7, #12] 8007264: 8d9b ldrh r3, [r3, #44] @ 0x2c 8007266: 085b lsrs r3, r3, #1 8007268: b29b uxth r3, r3 800726a: 4619 mov r1, r3 800726c: 68f8 ldr r0, [r7, #12] 800726e: f7ff feed bl 800704c #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8007272: e002 b.n 800727a HAL_UART_RxHalfCpltCallback(huart); 8007274: 68f8 ldr r0, [r7, #12] 8007276: f7ff fedf bl 8007038 } 800727a: bf00 nop 800727c: 3710 adds r7, #16 800727e: 46bd mov sp, r7 8007280: bd80 pop {r7, pc} 08007282 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8007282: b580 push {r7, lr} 8007284: b084 sub sp, #16 8007286: af00 add r7, sp, #0 8007288: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 800728a: 2300 movs r3, #0 800728c: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800728e: 687b ldr r3, [r7, #4] 8007290: 6b9b ldr r3, [r3, #56] @ 0x38 8007292: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8007294: 68bb ldr r3, [r7, #8] 8007296: 681b ldr r3, [r3, #0] 8007298: 695b ldr r3, [r3, #20] 800729a: f003 0380 and.w r3, r3, #128 @ 0x80 800729e: 2b80 cmp r3, #128 @ 0x80 80072a0: bf0c ite eq 80072a2: 2301 moveq r3, #1 80072a4: 2300 movne r3, #0 80072a6: b2db uxtb r3, r3 80072a8: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 80072aa: 68bb ldr r3, [r7, #8] 80072ac: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80072b0: b2db uxtb r3, r3 80072b2: 2b21 cmp r3, #33 @ 0x21 80072b4: d108 bne.n 80072c8 80072b6: 68fb ldr r3, [r7, #12] 80072b8: 2b00 cmp r3, #0 80072ba: d005 beq.n 80072c8 { huart->TxXferCount = 0x00U; 80072bc: 68bb ldr r3, [r7, #8] 80072be: 2200 movs r2, #0 80072c0: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 80072c2: 68b8 ldr r0, [r7, #8] 80072c4: f000 f8ce bl 8007464 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80072c8: 68bb ldr r3, [r7, #8] 80072ca: 681b ldr r3, [r3, #0] 80072cc: 695b ldr r3, [r3, #20] 80072ce: f003 0340 and.w r3, r3, #64 @ 0x40 80072d2: 2b40 cmp r3, #64 @ 0x40 80072d4: bf0c ite eq 80072d6: 2301 moveq r3, #1 80072d8: 2300 movne r3, #0 80072da: b2db uxtb r3, r3 80072dc: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 80072de: 68bb ldr r3, [r7, #8] 80072e0: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80072e4: b2db uxtb r3, r3 80072e6: 2b22 cmp r3, #34 @ 0x22 80072e8: d108 bne.n 80072fc 80072ea: 68fb ldr r3, [r7, #12] 80072ec: 2b00 cmp r3, #0 80072ee: d005 beq.n 80072fc { huart->RxXferCount = 0x00U; 80072f0: 68bb ldr r3, [r7, #8] 80072f2: 2200 movs r2, #0 80072f4: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 80072f6: 68b8 ldr r0, [r7, #8] 80072f8: f000 f8dc bl 80074b4 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 80072fc: 68bb ldr r3, [r7, #8] 80072fe: 6c5b ldr r3, [r3, #68] @ 0x44 8007300: f043 0210 orr.w r2, r3, #16 8007304: 68bb ldr r3, [r7, #8] 8007306: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8007308: 68b8 ldr r0, [r7, #8] 800730a: f7f9 fddf bl 8000ecc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800730e: bf00 nop 8007310: 3710 adds r7, #16 8007312: 46bd mov sp, r7 8007314: bd80 pop {r7, pc} ... 08007318 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8007318: b580 push {r7, lr} 800731a: b098 sub sp, #96 @ 0x60 800731c: af00 add r7, sp, #0 800731e: 60f8 str r0, [r7, #12] 8007320: 60b9 str r1, [r7, #8] 8007322: 4613 mov r3, r2 8007324: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 8007326: 68ba ldr r2, [r7, #8] 8007328: 68fb ldr r3, [r7, #12] 800732a: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 800732c: 68fb ldr r3, [r7, #12] 800732e: 88fa ldrh r2, [r7, #6] 8007330: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 8007332: 68fb ldr r3, [r7, #12] 8007334: 2200 movs r2, #0 8007336: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8007338: 68fb ldr r3, [r7, #12] 800733a: 2222 movs r2, #34 @ 0x22 800733c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8007340: 68fb ldr r3, [r7, #12] 8007342: 6bdb ldr r3, [r3, #60] @ 0x3c 8007344: 4a44 ldr r2, [pc, #272] @ (8007458 ) 8007346: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8007348: 68fb ldr r3, [r7, #12] 800734a: 6bdb ldr r3, [r3, #60] @ 0x3c 800734c: 4a43 ldr r2, [pc, #268] @ (800745c ) 800734e: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 8007350: 68fb ldr r3, [r7, #12] 8007352: 6bdb ldr r3, [r3, #60] @ 0x3c 8007354: 4a42 ldr r2, [pc, #264] @ (8007460 ) 8007356: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 8007358: 68fb ldr r3, [r7, #12] 800735a: 6bdb ldr r3, [r3, #60] @ 0x3c 800735c: 2200 movs r2, #0 800735e: 651a str r2, [r3, #80] @ 0x50 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 8007360: f107 0308 add.w r3, r7, #8 8007364: 65fb str r3, [r7, #92] @ 0x5c if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) 8007366: 68fb ldr r3, [r7, #12] 8007368: 6bd8 ldr r0, [r3, #60] @ 0x3c 800736a: 68fb ldr r3, [r7, #12] 800736c: 681b ldr r3, [r3, #0] 800736e: 3304 adds r3, #4 8007370: 4619 mov r1, r3 8007372: 6dfb ldr r3, [r7, #92] @ 0x5c 8007374: 681a ldr r2, [r3, #0] 8007376: 88fb ldrh r3, [r7, #6] 8007378: f7fa fff0 bl 800235c 800737c: 4603 mov r3, r0 800737e: 2b00 cmp r3, #0 8007380: d008 beq.n 8007394 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8007382: 68fb ldr r3, [r7, #12] 8007384: 2210 movs r2, #16 8007386: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 8007388: 68fb ldr r3, [r7, #12] 800738a: 2220 movs r2, #32 800738c: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_ERROR; 8007390: 2301 movs r3, #1 8007392: e05d b.n 8007450 } /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 8007394: 2300 movs r3, #0 8007396: 613b str r3, [r7, #16] 8007398: 68fb ldr r3, [r7, #12] 800739a: 681b ldr r3, [r3, #0] 800739c: 681b ldr r3, [r3, #0] 800739e: 613b str r3, [r7, #16] 80073a0: 68fb ldr r3, [r7, #12] 80073a2: 681b ldr r3, [r3, #0] 80073a4: 685b ldr r3, [r3, #4] 80073a6: 613b str r3, [r7, #16] 80073a8: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 80073aa: 68fb ldr r3, [r7, #12] 80073ac: 691b ldr r3, [r3, #16] 80073ae: 2b00 cmp r3, #0 80073b0: d019 beq.n 80073e6 { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80073b2: 68fb ldr r3, [r7, #12] 80073b4: 681b ldr r3, [r3, #0] 80073b6: 330c adds r3, #12 80073b8: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80073ba: 6c3b ldr r3, [r7, #64] @ 0x40 80073bc: e853 3f00 ldrex r3, [r3] 80073c0: 63fb str r3, [r7, #60] @ 0x3c return(result); 80073c2: 6bfb ldr r3, [r7, #60] @ 0x3c 80073c4: f443 7380 orr.w r3, r3, #256 @ 0x100 80073c8: 65bb str r3, [r7, #88] @ 0x58 80073ca: 68fb ldr r3, [r7, #12] 80073cc: 681b ldr r3, [r3, #0] 80073ce: 330c adds r3, #12 80073d0: 6dba ldr r2, [r7, #88] @ 0x58 80073d2: 64fa str r2, [r7, #76] @ 0x4c 80073d4: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80073d6: 6cb9 ldr r1, [r7, #72] @ 0x48 80073d8: 6cfa ldr r2, [r7, #76] @ 0x4c 80073da: e841 2300 strex r3, r2, [r1] 80073de: 647b str r3, [r7, #68] @ 0x44 return(result); 80073e0: 6c7b ldr r3, [r7, #68] @ 0x44 80073e2: 2b00 cmp r3, #0 80073e4: d1e5 bne.n 80073b2 } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 80073e6: 68fb ldr r3, [r7, #12] 80073e8: 681b ldr r3, [r3, #0] 80073ea: 3314 adds r3, #20 80073ec: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80073ee: 6afb ldr r3, [r7, #44] @ 0x2c 80073f0: e853 3f00 ldrex r3, [r3] 80073f4: 62bb str r3, [r7, #40] @ 0x28 return(result); 80073f6: 6abb ldr r3, [r7, #40] @ 0x28 80073f8: f043 0301 orr.w r3, r3, #1 80073fc: 657b str r3, [r7, #84] @ 0x54 80073fe: 68fb ldr r3, [r7, #12] 8007400: 681b ldr r3, [r3, #0] 8007402: 3314 adds r3, #20 8007404: 6d7a ldr r2, [r7, #84] @ 0x54 8007406: 63ba str r2, [r7, #56] @ 0x38 8007408: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800740a: 6b79 ldr r1, [r7, #52] @ 0x34 800740c: 6bba ldr r2, [r7, #56] @ 0x38 800740e: e841 2300 strex r3, r2, [r1] 8007412: 633b str r3, [r7, #48] @ 0x30 return(result); 8007414: 6b3b ldr r3, [r7, #48] @ 0x30 8007416: 2b00 cmp r3, #0 8007418: d1e5 bne.n 80073e6 /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800741a: 68fb ldr r3, [r7, #12] 800741c: 681b ldr r3, [r3, #0] 800741e: 3314 adds r3, #20 8007420: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007422: 69bb ldr r3, [r7, #24] 8007424: e853 3f00 ldrex r3, [r3] 8007428: 617b str r3, [r7, #20] return(result); 800742a: 697b ldr r3, [r7, #20] 800742c: f043 0340 orr.w r3, r3, #64 @ 0x40 8007430: 653b str r3, [r7, #80] @ 0x50 8007432: 68fb ldr r3, [r7, #12] 8007434: 681b ldr r3, [r3, #0] 8007436: 3314 adds r3, #20 8007438: 6d3a ldr r2, [r7, #80] @ 0x50 800743a: 627a str r2, [r7, #36] @ 0x24 800743c: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800743e: 6a39 ldr r1, [r7, #32] 8007440: 6a7a ldr r2, [r7, #36] @ 0x24 8007442: e841 2300 strex r3, r2, [r1] 8007446: 61fb str r3, [r7, #28] return(result); 8007448: 69fb ldr r3, [r7, #28] 800744a: 2b00 cmp r3, #0 800744c: d1e5 bne.n 800741a return HAL_OK; 800744e: 2300 movs r3, #0 } 8007450: 4618 mov r0, r3 8007452: 3760 adds r7, #96 @ 0x60 8007454: 46bd mov sp, r7 8007456: bd80 pop {r7, pc} 8007458: 0800711b .word 0x0800711b 800745c: 08007247 .word 0x08007247 8007460: 08007283 .word 0x08007283 08007464 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8007464: b480 push {r7} 8007466: b089 sub sp, #36 @ 0x24 8007468: af00 add r7, sp, #0 800746a: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 800746c: 687b ldr r3, [r7, #4] 800746e: 681b ldr r3, [r3, #0] 8007470: 330c adds r3, #12 8007472: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007474: 68fb ldr r3, [r7, #12] 8007476: e853 3f00 ldrex r3, [r3] 800747a: 60bb str r3, [r7, #8] return(result); 800747c: 68bb ldr r3, [r7, #8] 800747e: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8007482: 61fb str r3, [r7, #28] 8007484: 687b ldr r3, [r7, #4] 8007486: 681b ldr r3, [r3, #0] 8007488: 330c adds r3, #12 800748a: 69fa ldr r2, [r7, #28] 800748c: 61ba str r2, [r7, #24] 800748e: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007490: 6979 ldr r1, [r7, #20] 8007492: 69ba ldr r2, [r7, #24] 8007494: e841 2300 strex r3, r2, [r1] 8007498: 613b str r3, [r7, #16] return(result); 800749a: 693b ldr r3, [r7, #16] 800749c: 2b00 cmp r3, #0 800749e: d1e5 bne.n 800746c /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80074a0: 687b ldr r3, [r7, #4] 80074a2: 2220 movs r2, #32 80074a4: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 80074a8: bf00 nop 80074aa: 3724 adds r7, #36 @ 0x24 80074ac: 46bd mov sp, r7 80074ae: f85d 7b04 ldr.w r7, [sp], #4 80074b2: 4770 bx lr 080074b4 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 80074b4: b480 push {r7} 80074b6: b095 sub sp, #84 @ 0x54 80074b8: af00 add r7, sp, #0 80074ba: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80074bc: 687b ldr r3, [r7, #4] 80074be: 681b ldr r3, [r3, #0] 80074c0: 330c adds r3, #12 80074c2: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80074c4: 6b7b ldr r3, [r7, #52] @ 0x34 80074c6: e853 3f00 ldrex r3, [r3] 80074ca: 633b str r3, [r7, #48] @ 0x30 return(result); 80074cc: 6b3b ldr r3, [r7, #48] @ 0x30 80074ce: f423 7390 bic.w r3, r3, #288 @ 0x120 80074d2: 64fb str r3, [r7, #76] @ 0x4c 80074d4: 687b ldr r3, [r7, #4] 80074d6: 681b ldr r3, [r3, #0] 80074d8: 330c adds r3, #12 80074da: 6cfa ldr r2, [r7, #76] @ 0x4c 80074dc: 643a str r2, [r7, #64] @ 0x40 80074de: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80074e0: 6bf9 ldr r1, [r7, #60] @ 0x3c 80074e2: 6c3a ldr r2, [r7, #64] @ 0x40 80074e4: e841 2300 strex r3, r2, [r1] 80074e8: 63bb str r3, [r7, #56] @ 0x38 return(result); 80074ea: 6bbb ldr r3, [r7, #56] @ 0x38 80074ec: 2b00 cmp r3, #0 80074ee: d1e5 bne.n 80074bc ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80074f0: 687b ldr r3, [r7, #4] 80074f2: 681b ldr r3, [r3, #0] 80074f4: 3314 adds r3, #20 80074f6: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80074f8: 6a3b ldr r3, [r7, #32] 80074fa: e853 3f00 ldrex r3, [r3] 80074fe: 61fb str r3, [r7, #28] return(result); 8007500: 69fb ldr r3, [r7, #28] 8007502: f023 0301 bic.w r3, r3, #1 8007506: 64bb str r3, [r7, #72] @ 0x48 8007508: 687b ldr r3, [r7, #4] 800750a: 681b ldr r3, [r3, #0] 800750c: 3314 adds r3, #20 800750e: 6cba ldr r2, [r7, #72] @ 0x48 8007510: 62fa str r2, [r7, #44] @ 0x2c 8007512: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007514: 6ab9 ldr r1, [r7, #40] @ 0x28 8007516: 6afa ldr r2, [r7, #44] @ 0x2c 8007518: e841 2300 strex r3, r2, [r1] 800751c: 627b str r3, [r7, #36] @ 0x24 return(result); 800751e: 6a7b ldr r3, [r7, #36] @ 0x24 8007520: 2b00 cmp r3, #0 8007522: d1e5 bne.n 80074f0 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8007524: 687b ldr r3, [r7, #4] 8007526: 6b1b ldr r3, [r3, #48] @ 0x30 8007528: 2b01 cmp r3, #1 800752a: d119 bne.n 8007560 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800752c: 687b ldr r3, [r7, #4] 800752e: 681b ldr r3, [r3, #0] 8007530: 330c adds r3, #12 8007532: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007534: 68fb ldr r3, [r7, #12] 8007536: e853 3f00 ldrex r3, [r3] 800753a: 60bb str r3, [r7, #8] return(result); 800753c: 68bb ldr r3, [r7, #8] 800753e: f023 0310 bic.w r3, r3, #16 8007542: 647b str r3, [r7, #68] @ 0x44 8007544: 687b ldr r3, [r7, #4] 8007546: 681b ldr r3, [r3, #0] 8007548: 330c adds r3, #12 800754a: 6c7a ldr r2, [r7, #68] @ 0x44 800754c: 61ba str r2, [r7, #24] 800754e: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007550: 6979 ldr r1, [r7, #20] 8007552: 69ba ldr r2, [r7, #24] 8007554: e841 2300 strex r3, r2, [r1] 8007558: 613b str r3, [r7, #16] return(result); 800755a: 693b ldr r3, [r7, #16] 800755c: 2b00 cmp r3, #0 800755e: d1e5 bne.n 800752c } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8007560: 687b ldr r3, [r7, #4] 8007562: 2220 movs r2, #32 8007564: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8007568: 687b ldr r3, [r7, #4] 800756a: 2200 movs r2, #0 800756c: 631a str r2, [r3, #48] @ 0x30 } 800756e: bf00 nop 8007570: 3754 adds r7, #84 @ 0x54 8007572: 46bd mov sp, r7 8007574: f85d 7b04 ldr.w r7, [sp], #4 8007578: 4770 bx lr 0800757a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 800757a: b580 push {r7, lr} 800757c: b084 sub sp, #16 800757e: af00 add r7, sp, #0 8007580: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007582: 687b ldr r3, [r7, #4] 8007584: 6b9b ldr r3, [r3, #56] @ 0x38 8007586: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8007588: 68fb ldr r3, [r7, #12] 800758a: 2200 movs r2, #0 800758c: 85da strh r2, [r3, #46] @ 0x2e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800758e: 68f8 ldr r0, [r7, #12] 8007590: f7f9 fc9c bl 8000ecc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8007594: bf00 nop 8007596: 3710 adds r7, #16 8007598: 46bd mov sp, r7 800759a: bd80 pop {r7, pc} 0800759c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 800759c: b480 push {r7} 800759e: b085 sub sp, #20 80075a0: af00 add r7, sp, #0 80075a2: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80075a4: 687b ldr r3, [r7, #4] 80075a6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80075aa: b2db uxtb r3, r3 80075ac: 2b21 cmp r3, #33 @ 0x21 80075ae: d13e bne.n 800762e { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80075b0: 687b ldr r3, [r7, #4] 80075b2: 689b ldr r3, [r3, #8] 80075b4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80075b8: d114 bne.n 80075e4 80075ba: 687b ldr r3, [r7, #4] 80075bc: 691b ldr r3, [r3, #16] 80075be: 2b00 cmp r3, #0 80075c0: d110 bne.n 80075e4 { tmp = (const uint16_t *) huart->pTxBuffPtr; 80075c2: 687b ldr r3, [r7, #4] 80075c4: 6a1b ldr r3, [r3, #32] 80075c6: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 80075c8: 68fb ldr r3, [r7, #12] 80075ca: 881b ldrh r3, [r3, #0] 80075cc: 461a mov r2, r3 80075ce: 687b ldr r3, [r7, #4] 80075d0: 681b ldr r3, [r3, #0] 80075d2: f3c2 0208 ubfx r2, r2, #0, #9 80075d6: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 80075d8: 687b ldr r3, [r7, #4] 80075da: 6a1b ldr r3, [r3, #32] 80075dc: 1c9a adds r2, r3, #2 80075de: 687b ldr r3, [r7, #4] 80075e0: 621a str r2, [r3, #32] 80075e2: e008 b.n 80075f6 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 80075e4: 687b ldr r3, [r7, #4] 80075e6: 6a1b ldr r3, [r3, #32] 80075e8: 1c59 adds r1, r3, #1 80075ea: 687a ldr r2, [r7, #4] 80075ec: 6211 str r1, [r2, #32] 80075ee: 781a ldrb r2, [r3, #0] 80075f0: 687b ldr r3, [r7, #4] 80075f2: 681b ldr r3, [r3, #0] 80075f4: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 80075f6: 687b ldr r3, [r7, #4] 80075f8: 8cdb ldrh r3, [r3, #38] @ 0x26 80075fa: b29b uxth r3, r3 80075fc: 3b01 subs r3, #1 80075fe: b29b uxth r3, r3 8007600: 687a ldr r2, [r7, #4] 8007602: 4619 mov r1, r3 8007604: 84d1 strh r1, [r2, #38] @ 0x26 8007606: 2b00 cmp r3, #0 8007608: d10f bne.n 800762a { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 800760a: 687b ldr r3, [r7, #4] 800760c: 681b ldr r3, [r3, #0] 800760e: 68da ldr r2, [r3, #12] 8007610: 687b ldr r3, [r7, #4] 8007612: 681b ldr r3, [r3, #0] 8007614: f022 0280 bic.w r2, r2, #128 @ 0x80 8007618: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 800761a: 687b ldr r3, [r7, #4] 800761c: 681b ldr r3, [r3, #0] 800761e: 68da ldr r2, [r3, #12] 8007620: 687b ldr r3, [r7, #4] 8007622: 681b ldr r3, [r3, #0] 8007624: f042 0240 orr.w r2, r2, #64 @ 0x40 8007628: 60da str r2, [r3, #12] } return HAL_OK; 800762a: 2300 movs r3, #0 800762c: e000 b.n 8007630 } else { return HAL_BUSY; 800762e: 2302 movs r3, #2 } } 8007630: 4618 mov r0, r3 8007632: 3714 adds r7, #20 8007634: 46bd mov sp, r7 8007636: f85d 7b04 ldr.w r7, [sp], #4 800763a: 4770 bx lr 0800763c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 800763c: b580 push {r7, lr} 800763e: b082 sub sp, #8 8007640: af00 add r7, sp, #0 8007642: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8007644: 687b ldr r3, [r7, #4] 8007646: 681b ldr r3, [r3, #0] 8007648: 68da ldr r2, [r3, #12] 800764a: 687b ldr r3, [r7, #4] 800764c: 681b ldr r3, [r3, #0] 800764e: f022 0240 bic.w r2, r2, #64 @ 0x40 8007652: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8007654: 687b ldr r3, [r7, #4] 8007656: 2220 movs r2, #32 8007658: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 800765c: 6878 ldr r0, [r7, #4] 800765e: f7ff fcd7 bl 8007010 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8007662: 2300 movs r3, #0 } 8007664: 4618 mov r0, r3 8007666: 3708 adds r7, #8 8007668: 46bd mov sp, r7 800766a: bd80 pop {r7, pc} 0800766c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 800766c: b580 push {r7, lr} 800766e: b08c sub sp, #48 @ 0x30 8007670: af00 add r7, sp, #0 8007672: 6078 str r0, [r7, #4] uint8_t *pdata8bits = NULL; 8007674: 2300 movs r3, #0 8007676: 62fb str r3, [r7, #44] @ 0x2c uint16_t *pdata16bits = NULL; 8007678: 2300 movs r3, #0 800767a: 62bb str r3, [r7, #40] @ 0x28 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800767c: 687b ldr r3, [r7, #4] 800767e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8007682: b2db uxtb r3, r3 8007684: 2b22 cmp r3, #34 @ 0x22 8007686: f040 80aa bne.w 80077de { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800768a: 687b ldr r3, [r7, #4] 800768c: 689b ldr r3, [r3, #8] 800768e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8007692: d115 bne.n 80076c0 8007694: 687b ldr r3, [r7, #4] 8007696: 691b ldr r3, [r3, #16] 8007698: 2b00 cmp r3, #0 800769a: d111 bne.n 80076c0 { /* Unused pdata8bits */ UNUSED(pdata8bits); pdata16bits = (uint16_t *) huart->pRxBuffPtr; 800769c: 687b ldr r3, [r7, #4] 800769e: 6a9b ldr r3, [r3, #40] @ 0x28 80076a0: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 80076a2: 687b ldr r3, [r7, #4] 80076a4: 681b ldr r3, [r3, #0] 80076a6: 685b ldr r3, [r3, #4] 80076a8: b29b uxth r3, r3 80076aa: f3c3 0308 ubfx r3, r3, #0, #9 80076ae: b29a uxth r2, r3 80076b0: 6abb ldr r3, [r7, #40] @ 0x28 80076b2: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80076b4: 687b ldr r3, [r7, #4] 80076b6: 6a9b ldr r3, [r3, #40] @ 0x28 80076b8: 1c9a adds r2, r3, #2 80076ba: 687b ldr r3, [r7, #4] 80076bc: 629a str r2, [r3, #40] @ 0x28 80076be: e024 b.n 800770a } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 80076c0: 687b ldr r3, [r7, #4] 80076c2: 6a9b ldr r3, [r3, #40] @ 0x28 80076c4: 62fb str r3, [r7, #44] @ 0x2c /* Unused pdata16bits */ UNUSED(pdata16bits); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 80076c6: 687b ldr r3, [r7, #4] 80076c8: 689b ldr r3, [r3, #8] 80076ca: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80076ce: d007 beq.n 80076e0 80076d0: 687b ldr r3, [r7, #4] 80076d2: 689b ldr r3, [r3, #8] 80076d4: 2b00 cmp r3, #0 80076d6: d10a bne.n 80076ee 80076d8: 687b ldr r3, [r7, #4] 80076da: 691b ldr r3, [r3, #16] 80076dc: 2b00 cmp r3, #0 80076de: d106 bne.n 80076ee { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 80076e0: 687b ldr r3, [r7, #4] 80076e2: 681b ldr r3, [r3, #0] 80076e4: 685b ldr r3, [r3, #4] 80076e6: b2da uxtb r2, r3 80076e8: 6afb ldr r3, [r7, #44] @ 0x2c 80076ea: 701a strb r2, [r3, #0] 80076ec: e008 b.n 8007700 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 80076ee: 687b ldr r3, [r7, #4] 80076f0: 681b ldr r3, [r3, #0] 80076f2: 685b ldr r3, [r3, #4] 80076f4: b2db uxtb r3, r3 80076f6: f003 037f and.w r3, r3, #127 @ 0x7f 80076fa: b2da uxtb r2, r3 80076fc: 6afb ldr r3, [r7, #44] @ 0x2c 80076fe: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8007700: 687b ldr r3, [r7, #4] 8007702: 6a9b ldr r3, [r3, #40] @ 0x28 8007704: 1c5a adds r2, r3, #1 8007706: 687b ldr r3, [r7, #4] 8007708: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 800770a: 687b ldr r3, [r7, #4] 800770c: 8ddb ldrh r3, [r3, #46] @ 0x2e 800770e: b29b uxth r3, r3 8007710: 3b01 subs r3, #1 8007712: b29b uxth r3, r3 8007714: 687a ldr r2, [r7, #4] 8007716: 4619 mov r1, r3 8007718: 85d1 strh r1, [r2, #46] @ 0x2e 800771a: 2b00 cmp r3, #0 800771c: d15d bne.n 80077da { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 800771e: 687b ldr r3, [r7, #4] 8007720: 681b ldr r3, [r3, #0] 8007722: 68da ldr r2, [r3, #12] 8007724: 687b ldr r3, [r7, #4] 8007726: 681b ldr r3, [r3, #0] 8007728: f022 0220 bic.w r2, r2, #32 800772c: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 800772e: 687b ldr r3, [r7, #4] 8007730: 681b ldr r3, [r3, #0] 8007732: 68da ldr r2, [r3, #12] 8007734: 687b ldr r3, [r7, #4] 8007736: 681b ldr r3, [r3, #0] 8007738: f422 7280 bic.w r2, r2, #256 @ 0x100 800773c: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 800773e: 687b ldr r3, [r7, #4] 8007740: 681b ldr r3, [r3, #0] 8007742: 695a ldr r2, [r3, #20] 8007744: 687b ldr r3, [r7, #4] 8007746: 681b ldr r3, [r3, #0] 8007748: f022 0201 bic.w r2, r2, #1 800774c: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800774e: 687b ldr r3, [r7, #4] 8007750: 2220 movs r2, #32 8007752: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8007756: 687b ldr r3, [r7, #4] 8007758: 2200 movs r2, #0 800775a: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800775c: 687b ldr r3, [r7, #4] 800775e: 6b1b ldr r3, [r3, #48] @ 0x30 8007760: 2b01 cmp r3, #1 8007762: d135 bne.n 80077d0 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8007764: 687b ldr r3, [r7, #4] 8007766: 2200 movs r2, #0 8007768: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800776a: 687b ldr r3, [r7, #4] 800776c: 681b ldr r3, [r3, #0] 800776e: 330c adds r3, #12 8007770: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007772: 697b ldr r3, [r7, #20] 8007774: e853 3f00 ldrex r3, [r3] 8007778: 613b str r3, [r7, #16] return(result); 800777a: 693b ldr r3, [r7, #16] 800777c: f023 0310 bic.w r3, r3, #16 8007780: 627b str r3, [r7, #36] @ 0x24 8007782: 687b ldr r3, [r7, #4] 8007784: 681b ldr r3, [r3, #0] 8007786: 330c adds r3, #12 8007788: 6a7a ldr r2, [r7, #36] @ 0x24 800778a: 623a str r2, [r7, #32] 800778c: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800778e: 69f9 ldr r1, [r7, #28] 8007790: 6a3a ldr r2, [r7, #32] 8007792: e841 2300 strex r3, r2, [r1] 8007796: 61bb str r3, [r7, #24] return(result); 8007798: 69bb ldr r3, [r7, #24] 800779a: 2b00 cmp r3, #0 800779c: d1e5 bne.n 800776a /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 800779e: 687b ldr r3, [r7, #4] 80077a0: 681b ldr r3, [r3, #0] 80077a2: 681b ldr r3, [r3, #0] 80077a4: f003 0310 and.w r3, r3, #16 80077a8: 2b10 cmp r3, #16 80077aa: d10a bne.n 80077c2 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 80077ac: 2300 movs r3, #0 80077ae: 60fb str r3, [r7, #12] 80077b0: 687b ldr r3, [r7, #4] 80077b2: 681b ldr r3, [r3, #0] 80077b4: 681b ldr r3, [r3, #0] 80077b6: 60fb str r3, [r7, #12] 80077b8: 687b ldr r3, [r7, #4] 80077ba: 681b ldr r3, [r3, #0] 80077bc: 685b ldr r3, [r3, #4] 80077be: 60fb str r3, [r7, #12] 80077c0: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80077c2: 687b ldr r3, [r7, #4] 80077c4: 8d9b ldrh r3, [r3, #44] @ 0x2c 80077c6: 4619 mov r1, r3 80077c8: 6878 ldr r0, [r7, #4] 80077ca: f7ff fc3f bl 800704c 80077ce: e002 b.n 80077d6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 80077d0: 6878 ldr r0, [r7, #4] 80077d2: f7f9 fb1f bl 8000e14 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 80077d6: 2300 movs r3, #0 80077d8: e002 b.n 80077e0 } return HAL_OK; 80077da: 2300 movs r3, #0 80077dc: e000 b.n 80077e0 } else { return HAL_BUSY; 80077de: 2302 movs r3, #2 } } 80077e0: 4618 mov r0, r3 80077e2: 3730 adds r7, #48 @ 0x30 80077e4: 46bd mov sp, r7 80077e6: bd80 pop {r7, pc} 080077e8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 80077e8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80077ec: b0c0 sub sp, #256 @ 0x100 80077ee: af00 add r7, sp, #0 80077f0: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80077f4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80077f8: 681b ldr r3, [r3, #0] 80077fa: 691b ldr r3, [r3, #16] 80077fc: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8007800: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007804: 68d9 ldr r1, [r3, #12] 8007806: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800780a: 681a ldr r2, [r3, #0] 800780c: ea40 0301 orr.w r3, r0, r1 8007810: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8007812: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007816: 689a ldr r2, [r3, #8] 8007818: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800781c: 691b ldr r3, [r3, #16] 800781e: 431a orrs r2, r3 8007820: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007824: 695b ldr r3, [r3, #20] 8007826: 431a orrs r2, r3 8007828: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800782c: 69db ldr r3, [r3, #28] 800782e: 4313 orrs r3, r2 8007830: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 8007834: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007838: 681b ldr r3, [r3, #0] 800783a: 68db ldr r3, [r3, #12] 800783c: f423 4116 bic.w r1, r3, #38400 @ 0x9600 8007840: f021 010c bic.w r1, r1, #12 8007844: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007848: 681a ldr r2, [r3, #0] 800784a: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 800784e: 430b orrs r3, r1 8007850: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8007852: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007856: 681b ldr r3, [r3, #0] 8007858: 695b ldr r3, [r3, #20] 800785a: f423 7040 bic.w r0, r3, #768 @ 0x300 800785e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007862: 6999 ldr r1, [r3, #24] 8007864: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007868: 681a ldr r2, [r3, #0] 800786a: ea40 0301 orr.w r3, r0, r1 800786e: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 8007870: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007874: 681a ldr r2, [r3, #0] 8007876: 4b8f ldr r3, [pc, #572] @ (8007ab4 ) 8007878: 429a cmp r2, r3 800787a: d005 beq.n 8007888 800787c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007880: 681a ldr r2, [r3, #0] 8007882: 4b8d ldr r3, [pc, #564] @ (8007ab8 ) 8007884: 429a cmp r2, r3 8007886: d104 bne.n 8007892 { pclk = HAL_RCC_GetPCLK2Freq(); 8007888: f7fc ff52 bl 8004730 800788c: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8007890: e003 b.n 800789a pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8007892: f7fc ff39 bl 8004708 8007896: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800789a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800789e: 69db ldr r3, [r3, #28] 80078a0: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80078a4: f040 810c bne.w 8007ac0 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 80078a8: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80078ac: 2200 movs r2, #0 80078ae: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 80078b2: f8c7 20ec str.w r2, [r7, #236] @ 0xec 80078b6: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 80078ba: 4622 mov r2, r4 80078bc: 462b mov r3, r5 80078be: 1891 adds r1, r2, r2 80078c0: 65b9 str r1, [r7, #88] @ 0x58 80078c2: 415b adcs r3, r3 80078c4: 65fb str r3, [r7, #92] @ 0x5c 80078c6: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 80078ca: 4621 mov r1, r4 80078cc: eb12 0801 adds.w r8, r2, r1 80078d0: 4629 mov r1, r5 80078d2: eb43 0901 adc.w r9, r3, r1 80078d6: f04f 0200 mov.w r2, #0 80078da: f04f 0300 mov.w r3, #0 80078de: ea4f 03c9 mov.w r3, r9, lsl #3 80078e2: ea43 7358 orr.w r3, r3, r8, lsr #29 80078e6: ea4f 02c8 mov.w r2, r8, lsl #3 80078ea: 4690 mov r8, r2 80078ec: 4699 mov r9, r3 80078ee: 4623 mov r3, r4 80078f0: eb18 0303 adds.w r3, r8, r3 80078f4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 80078f8: 462b mov r3, r5 80078fa: eb49 0303 adc.w r3, r9, r3 80078fe: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8007902: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007906: 685b ldr r3, [r3, #4] 8007908: 2200 movs r2, #0 800790a: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800790e: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 8007912: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 8007916: 460b mov r3, r1 8007918: 18db adds r3, r3, r3 800791a: 653b str r3, [r7, #80] @ 0x50 800791c: 4613 mov r3, r2 800791e: eb42 0303 adc.w r3, r2, r3 8007922: 657b str r3, [r7, #84] @ 0x54 8007924: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 8007928: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 800792c: f7f8 fc6a bl 8000204 <__aeabi_uldivmod> 8007930: 4602 mov r2, r0 8007932: 460b mov r3, r1 8007934: 4b61 ldr r3, [pc, #388] @ (8007abc ) 8007936: fba3 2302 umull r2, r3, r3, r2 800793a: 095b lsrs r3, r3, #5 800793c: 011c lsls r4, r3, #4 800793e: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8007942: 2200 movs r2, #0 8007944: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8007948: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 800794c: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8007950: 4642 mov r2, r8 8007952: 464b mov r3, r9 8007954: 1891 adds r1, r2, r2 8007956: 64b9 str r1, [r7, #72] @ 0x48 8007958: 415b adcs r3, r3 800795a: 64fb str r3, [r7, #76] @ 0x4c 800795c: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8007960: 4641 mov r1, r8 8007962: eb12 0a01 adds.w sl, r2, r1 8007966: 4649 mov r1, r9 8007968: eb43 0b01 adc.w fp, r3, r1 800796c: f04f 0200 mov.w r2, #0 8007970: f04f 0300 mov.w r3, #0 8007974: ea4f 03cb mov.w r3, fp, lsl #3 8007978: ea43 735a orr.w r3, r3, sl, lsr #29 800797c: ea4f 02ca mov.w r2, sl, lsl #3 8007980: 4692 mov sl, r2 8007982: 469b mov fp, r3 8007984: 4643 mov r3, r8 8007986: eb1a 0303 adds.w r3, sl, r3 800798a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800798e: 464b mov r3, r9 8007990: eb4b 0303 adc.w r3, fp, r3 8007994: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8007998: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800799c: 685b ldr r3, [r3, #4] 800799e: 2200 movs r2, #0 80079a0: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 80079a4: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 80079a8: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 80079ac: 460b mov r3, r1 80079ae: 18db adds r3, r3, r3 80079b0: 643b str r3, [r7, #64] @ 0x40 80079b2: 4613 mov r3, r2 80079b4: eb42 0303 adc.w r3, r2, r3 80079b8: 647b str r3, [r7, #68] @ 0x44 80079ba: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 80079be: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 80079c2: f7f8 fc1f bl 8000204 <__aeabi_uldivmod> 80079c6: 4602 mov r2, r0 80079c8: 460b mov r3, r1 80079ca: 4611 mov r1, r2 80079cc: 4b3b ldr r3, [pc, #236] @ (8007abc ) 80079ce: fba3 2301 umull r2, r3, r3, r1 80079d2: 095b lsrs r3, r3, #5 80079d4: 2264 movs r2, #100 @ 0x64 80079d6: fb02 f303 mul.w r3, r2, r3 80079da: 1acb subs r3, r1, r3 80079dc: 00db lsls r3, r3, #3 80079de: f103 0232 add.w r2, r3, #50 @ 0x32 80079e2: 4b36 ldr r3, [pc, #216] @ (8007abc ) 80079e4: fba3 2302 umull r2, r3, r3, r2 80079e8: 095b lsrs r3, r3, #5 80079ea: 005b lsls r3, r3, #1 80079ec: f403 73f8 and.w r3, r3, #496 @ 0x1f0 80079f0: 441c add r4, r3 80079f2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80079f6: 2200 movs r2, #0 80079f8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80079fc: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8007a00: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 8007a04: 4642 mov r2, r8 8007a06: 464b mov r3, r9 8007a08: 1891 adds r1, r2, r2 8007a0a: 63b9 str r1, [r7, #56] @ 0x38 8007a0c: 415b adcs r3, r3 8007a0e: 63fb str r3, [r7, #60] @ 0x3c 8007a10: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 8007a14: 4641 mov r1, r8 8007a16: 1851 adds r1, r2, r1 8007a18: 6339 str r1, [r7, #48] @ 0x30 8007a1a: 4649 mov r1, r9 8007a1c: 414b adcs r3, r1 8007a1e: 637b str r3, [r7, #52] @ 0x34 8007a20: f04f 0200 mov.w r2, #0 8007a24: f04f 0300 mov.w r3, #0 8007a28: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 8007a2c: 4659 mov r1, fp 8007a2e: 00cb lsls r3, r1, #3 8007a30: 4651 mov r1, sl 8007a32: ea43 7351 orr.w r3, r3, r1, lsr #29 8007a36: 4651 mov r1, sl 8007a38: 00ca lsls r2, r1, #3 8007a3a: 4610 mov r0, r2 8007a3c: 4619 mov r1, r3 8007a3e: 4603 mov r3, r0 8007a40: 4642 mov r2, r8 8007a42: 189b adds r3, r3, r2 8007a44: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8007a48: 464b mov r3, r9 8007a4a: 460a mov r2, r1 8007a4c: eb42 0303 adc.w r3, r2, r3 8007a50: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8007a54: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007a58: 685b ldr r3, [r3, #4] 8007a5a: 2200 movs r2, #0 8007a5c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8007a60: f8c7 20ac str.w r2, [r7, #172] @ 0xac 8007a64: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8007a68: 460b mov r3, r1 8007a6a: 18db adds r3, r3, r3 8007a6c: 62bb str r3, [r7, #40] @ 0x28 8007a6e: 4613 mov r3, r2 8007a70: eb42 0303 adc.w r3, r2, r3 8007a74: 62fb str r3, [r7, #44] @ 0x2c 8007a76: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 8007a7a: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 8007a7e: f7f8 fbc1 bl 8000204 <__aeabi_uldivmod> 8007a82: 4602 mov r2, r0 8007a84: 460b mov r3, r1 8007a86: 4b0d ldr r3, [pc, #52] @ (8007abc ) 8007a88: fba3 1302 umull r1, r3, r3, r2 8007a8c: 095b lsrs r3, r3, #5 8007a8e: 2164 movs r1, #100 @ 0x64 8007a90: fb01 f303 mul.w r3, r1, r3 8007a94: 1ad3 subs r3, r2, r3 8007a96: 00db lsls r3, r3, #3 8007a98: 3332 adds r3, #50 @ 0x32 8007a9a: 4a08 ldr r2, [pc, #32] @ (8007abc ) 8007a9c: fba2 2303 umull r2, r3, r2, r3 8007aa0: 095b lsrs r3, r3, #5 8007aa2: f003 0207 and.w r2, r3, #7 8007aa6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007aaa: 681b ldr r3, [r3, #0] 8007aac: 4422 add r2, r4 8007aae: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8007ab0: e106 b.n 8007cc0 8007ab2: bf00 nop 8007ab4: 40011000 .word 0x40011000 8007ab8: 40011400 .word 0x40011400 8007abc: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8007ac0: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8007ac4: 2200 movs r2, #0 8007ac6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8007aca: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 8007ace: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8007ad2: 4642 mov r2, r8 8007ad4: 464b mov r3, r9 8007ad6: 1891 adds r1, r2, r2 8007ad8: 6239 str r1, [r7, #32] 8007ada: 415b adcs r3, r3 8007adc: 627b str r3, [r7, #36] @ 0x24 8007ade: e9d7 2308 ldrd r2, r3, [r7, #32] 8007ae2: 4641 mov r1, r8 8007ae4: 1854 adds r4, r2, r1 8007ae6: 4649 mov r1, r9 8007ae8: eb43 0501 adc.w r5, r3, r1 8007aec: f04f 0200 mov.w r2, #0 8007af0: f04f 0300 mov.w r3, #0 8007af4: 00eb lsls r3, r5, #3 8007af6: ea43 7354 orr.w r3, r3, r4, lsr #29 8007afa: 00e2 lsls r2, r4, #3 8007afc: 4614 mov r4, r2 8007afe: 461d mov r5, r3 8007b00: 4643 mov r3, r8 8007b02: 18e3 adds r3, r4, r3 8007b04: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8007b08: 464b mov r3, r9 8007b0a: eb45 0303 adc.w r3, r5, r3 8007b0e: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8007b12: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007b16: 685b ldr r3, [r3, #4] 8007b18: 2200 movs r2, #0 8007b1a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8007b1e: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8007b22: f04f 0200 mov.w r2, #0 8007b26: f04f 0300 mov.w r3, #0 8007b2a: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8007b2e: 4629 mov r1, r5 8007b30: 008b lsls r3, r1, #2 8007b32: 4621 mov r1, r4 8007b34: ea43 7391 orr.w r3, r3, r1, lsr #30 8007b38: 4621 mov r1, r4 8007b3a: 008a lsls r2, r1, #2 8007b3c: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 8007b40: f7f8 fb60 bl 8000204 <__aeabi_uldivmod> 8007b44: 4602 mov r2, r0 8007b46: 460b mov r3, r1 8007b48: 4b60 ldr r3, [pc, #384] @ (8007ccc ) 8007b4a: fba3 2302 umull r2, r3, r3, r2 8007b4e: 095b lsrs r3, r3, #5 8007b50: 011c lsls r4, r3, #4 8007b52: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8007b56: 2200 movs r2, #0 8007b58: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8007b5c: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8007b60: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 8007b64: 4642 mov r2, r8 8007b66: 464b mov r3, r9 8007b68: 1891 adds r1, r2, r2 8007b6a: 61b9 str r1, [r7, #24] 8007b6c: 415b adcs r3, r3 8007b6e: 61fb str r3, [r7, #28] 8007b70: e9d7 2306 ldrd r2, r3, [r7, #24] 8007b74: 4641 mov r1, r8 8007b76: 1851 adds r1, r2, r1 8007b78: 6139 str r1, [r7, #16] 8007b7a: 4649 mov r1, r9 8007b7c: 414b adcs r3, r1 8007b7e: 617b str r3, [r7, #20] 8007b80: f04f 0200 mov.w r2, #0 8007b84: f04f 0300 mov.w r3, #0 8007b88: e9d7 ab04 ldrd sl, fp, [r7, #16] 8007b8c: 4659 mov r1, fp 8007b8e: 00cb lsls r3, r1, #3 8007b90: 4651 mov r1, sl 8007b92: ea43 7351 orr.w r3, r3, r1, lsr #29 8007b96: 4651 mov r1, sl 8007b98: 00ca lsls r2, r1, #3 8007b9a: 4610 mov r0, r2 8007b9c: 4619 mov r1, r3 8007b9e: 4603 mov r3, r0 8007ba0: 4642 mov r2, r8 8007ba2: 189b adds r3, r3, r2 8007ba4: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8007ba8: 464b mov r3, r9 8007baa: 460a mov r2, r1 8007bac: eb42 0303 adc.w r3, r2, r3 8007bb0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8007bb4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007bb8: 685b ldr r3, [r3, #4] 8007bba: 2200 movs r2, #0 8007bbc: 67bb str r3, [r7, #120] @ 0x78 8007bbe: 67fa str r2, [r7, #124] @ 0x7c 8007bc0: f04f 0200 mov.w r2, #0 8007bc4: f04f 0300 mov.w r3, #0 8007bc8: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 8007bcc: 4649 mov r1, r9 8007bce: 008b lsls r3, r1, #2 8007bd0: 4641 mov r1, r8 8007bd2: ea43 7391 orr.w r3, r3, r1, lsr #30 8007bd6: 4641 mov r1, r8 8007bd8: 008a lsls r2, r1, #2 8007bda: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 8007bde: f7f8 fb11 bl 8000204 <__aeabi_uldivmod> 8007be2: 4602 mov r2, r0 8007be4: 460b mov r3, r1 8007be6: 4611 mov r1, r2 8007be8: 4b38 ldr r3, [pc, #224] @ (8007ccc ) 8007bea: fba3 2301 umull r2, r3, r3, r1 8007bee: 095b lsrs r3, r3, #5 8007bf0: 2264 movs r2, #100 @ 0x64 8007bf2: fb02 f303 mul.w r3, r2, r3 8007bf6: 1acb subs r3, r1, r3 8007bf8: 011b lsls r3, r3, #4 8007bfa: 3332 adds r3, #50 @ 0x32 8007bfc: 4a33 ldr r2, [pc, #204] @ (8007ccc ) 8007bfe: fba2 2303 umull r2, r3, r2, r3 8007c02: 095b lsrs r3, r3, #5 8007c04: f003 03f0 and.w r3, r3, #240 @ 0xf0 8007c08: 441c add r4, r3 8007c0a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8007c0e: 2200 movs r2, #0 8007c10: 673b str r3, [r7, #112] @ 0x70 8007c12: 677a str r2, [r7, #116] @ 0x74 8007c14: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 8007c18: 4642 mov r2, r8 8007c1a: 464b mov r3, r9 8007c1c: 1891 adds r1, r2, r2 8007c1e: 60b9 str r1, [r7, #8] 8007c20: 415b adcs r3, r3 8007c22: 60fb str r3, [r7, #12] 8007c24: e9d7 2302 ldrd r2, r3, [r7, #8] 8007c28: 4641 mov r1, r8 8007c2a: 1851 adds r1, r2, r1 8007c2c: 6039 str r1, [r7, #0] 8007c2e: 4649 mov r1, r9 8007c30: 414b adcs r3, r1 8007c32: 607b str r3, [r7, #4] 8007c34: f04f 0200 mov.w r2, #0 8007c38: f04f 0300 mov.w r3, #0 8007c3c: e9d7 ab00 ldrd sl, fp, [r7] 8007c40: 4659 mov r1, fp 8007c42: 00cb lsls r3, r1, #3 8007c44: 4651 mov r1, sl 8007c46: ea43 7351 orr.w r3, r3, r1, lsr #29 8007c4a: 4651 mov r1, sl 8007c4c: 00ca lsls r2, r1, #3 8007c4e: 4610 mov r0, r2 8007c50: 4619 mov r1, r3 8007c52: 4603 mov r3, r0 8007c54: 4642 mov r2, r8 8007c56: 189b adds r3, r3, r2 8007c58: 66bb str r3, [r7, #104] @ 0x68 8007c5a: 464b mov r3, r9 8007c5c: 460a mov r2, r1 8007c5e: eb42 0303 adc.w r3, r2, r3 8007c62: 66fb str r3, [r7, #108] @ 0x6c 8007c64: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007c68: 685b ldr r3, [r3, #4] 8007c6a: 2200 movs r2, #0 8007c6c: 663b str r3, [r7, #96] @ 0x60 8007c6e: 667a str r2, [r7, #100] @ 0x64 8007c70: f04f 0200 mov.w r2, #0 8007c74: f04f 0300 mov.w r3, #0 8007c78: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 8007c7c: 4649 mov r1, r9 8007c7e: 008b lsls r3, r1, #2 8007c80: 4641 mov r1, r8 8007c82: ea43 7391 orr.w r3, r3, r1, lsr #30 8007c86: 4641 mov r1, r8 8007c88: 008a lsls r2, r1, #2 8007c8a: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 8007c8e: f7f8 fab9 bl 8000204 <__aeabi_uldivmod> 8007c92: 4602 mov r2, r0 8007c94: 460b mov r3, r1 8007c96: 4b0d ldr r3, [pc, #52] @ (8007ccc ) 8007c98: fba3 1302 umull r1, r3, r3, r2 8007c9c: 095b lsrs r3, r3, #5 8007c9e: 2164 movs r1, #100 @ 0x64 8007ca0: fb01 f303 mul.w r3, r1, r3 8007ca4: 1ad3 subs r3, r2, r3 8007ca6: 011b lsls r3, r3, #4 8007ca8: 3332 adds r3, #50 @ 0x32 8007caa: 4a08 ldr r2, [pc, #32] @ (8007ccc ) 8007cac: fba2 2303 umull r2, r3, r2, r3 8007cb0: 095b lsrs r3, r3, #5 8007cb2: f003 020f and.w r2, r3, #15 8007cb6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007cba: 681b ldr r3, [r3, #0] 8007cbc: 4422 add r2, r4 8007cbe: 609a str r2, [r3, #8] } 8007cc0: bf00 nop 8007cc2: f507 7780 add.w r7, r7, #256 @ 0x100 8007cc6: 46bd mov sp, r7 8007cc8: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8007ccc: 51eb851f .word 0x51eb851f 08007cd0 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007cd0: b084 sub sp, #16 8007cd2: b580 push {r7, lr} 8007cd4: b084 sub sp, #16 8007cd6: af00 add r7, sp, #0 8007cd8: 6078 str r0, [r7, #4] 8007cda: f107 001c add.w r0, r7, #28 8007cde: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8007ce2: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 8007ce6: 2b01 cmp r3, #1 8007ce8: d123 bne.n 8007d32 { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8007cea: 687b ldr r3, [r7, #4] 8007cec: 6b9b ldr r3, [r3, #56] @ 0x38 8007cee: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8007cf2: 687b ldr r3, [r7, #4] 8007cf4: 639a str r2, [r3, #56] @ 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 8007cf6: 687b ldr r3, [r7, #4] 8007cf8: 68db ldr r3, [r3, #12] 8007cfa: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 8007cfe: f023 0340 bic.w r3, r3, #64 @ 0x40 8007d02: 687a ldr r2, [r7, #4] 8007d04: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 8007d06: 687b ldr r3, [r7, #4] 8007d08: 68db ldr r3, [r3, #12] 8007d0a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8007d0e: 687b ldr r3, [r7, #4] 8007d10: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8007d12: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8007d16: 2b01 cmp r3, #1 8007d18: d105 bne.n 8007d26 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 8007d1a: 687b ldr r3, [r7, #4] 8007d1c: 68db ldr r3, [r3, #12] 8007d1e: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8007d22: 687b ldr r3, [r7, #4] 8007d24: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8007d26: 6878 ldr r0, [r7, #4] 8007d28: f001 fae2 bl 80092f0 8007d2c: 4603 mov r3, r0 8007d2e: 73fb strb r3, [r7, #15] 8007d30: e01b b.n 8007d6a } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8007d32: 687b ldr r3, [r7, #4] 8007d34: 68db ldr r3, [r3, #12] 8007d36: f043 0240 orr.w r2, r3, #64 @ 0x40 8007d3a: 687b ldr r3, [r7, #4] 8007d3c: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8007d3e: 6878 ldr r0, [r7, #4] 8007d40: f001 fad6 bl 80092f0 8007d44: 4603 mov r3, r0 8007d46: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 8007d48: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 8007d4c: 2b00 cmp r3, #0 8007d4e: d106 bne.n 8007d5e { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8007d50: 687b ldr r3, [r7, #4] 8007d52: 6b9b ldr r3, [r3, #56] @ 0x38 8007d54: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8007d58: 687b ldr r3, [r7, #4] 8007d5a: 639a str r2, [r3, #56] @ 0x38 8007d5c: e005 b.n 8007d6a } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8007d5e: 687b ldr r3, [r7, #4] 8007d60: 6b9b ldr r3, [r3, #56] @ 0x38 8007d62: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8007d66: 687b ldr r3, [r7, #4] 8007d68: 639a str r2, [r3, #56] @ 0x38 } } if (cfg.dma_enable == 1U) 8007d6a: 7fbb ldrb r3, [r7, #30] 8007d6c: 2b01 cmp r3, #1 8007d6e: d10b bne.n 8007d88 { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8007d70: 687b ldr r3, [r7, #4] 8007d72: 689b ldr r3, [r3, #8] 8007d74: f043 0206 orr.w r2, r3, #6 8007d78: 687b ldr r3, [r7, #4] 8007d7a: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 8007d7c: 687b ldr r3, [r7, #4] 8007d7e: 689b ldr r3, [r3, #8] 8007d80: f043 0220 orr.w r2, r3, #32 8007d84: 687b ldr r3, [r7, #4] 8007d86: 609a str r2, [r3, #8] } return ret; 8007d88: 7bfb ldrb r3, [r7, #15] } 8007d8a: 4618 mov r0, r3 8007d8c: 3710 adds r7, #16 8007d8e: 46bd mov sp, r7 8007d90: e8bd 4080 ldmia.w sp!, {r7, lr} 8007d94: b004 add sp, #16 8007d96: 4770 bx lr 08007d98 : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8007d98: b480 push {r7} 8007d9a: b087 sub sp, #28 8007d9c: af00 add r7, sp, #0 8007d9e: 60f8 str r0, [r7, #12] 8007da0: 60b9 str r1, [r7, #8] 8007da2: 4613 mov r3, r2 8007da4: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 8007da6: 79fb ldrb r3, [r7, #7] 8007da8: 2b02 cmp r3, #2 8007daa: d165 bne.n 8007e78 { if ((hclk >= 14200000U) && (hclk < 15000000U)) 8007dac: 68bb ldr r3, [r7, #8] 8007dae: 4a41 ldr r2, [pc, #260] @ (8007eb4 ) 8007db0: 4293 cmp r3, r2 8007db2: d906 bls.n 8007dc2 8007db4: 68bb ldr r3, [r7, #8] 8007db6: 4a40 ldr r2, [pc, #256] @ (8007eb8 ) 8007db8: 4293 cmp r3, r2 8007dba: d202 bcs.n 8007dc2 { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 8007dbc: 230f movs r3, #15 8007dbe: 617b str r3, [r7, #20] 8007dc0: e062 b.n 8007e88 } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 8007dc2: 68bb ldr r3, [r7, #8] 8007dc4: 4a3c ldr r2, [pc, #240] @ (8007eb8 ) 8007dc6: 4293 cmp r3, r2 8007dc8: d306 bcc.n 8007dd8 8007dca: 68bb ldr r3, [r7, #8] 8007dcc: 4a3b ldr r2, [pc, #236] @ (8007ebc ) 8007dce: 4293 cmp r3, r2 8007dd0: d202 bcs.n 8007dd8 { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8007dd2: 230e movs r3, #14 8007dd4: 617b str r3, [r7, #20] 8007dd6: e057 b.n 8007e88 } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 8007dd8: 68bb ldr r3, [r7, #8] 8007dda: 4a38 ldr r2, [pc, #224] @ (8007ebc ) 8007ddc: 4293 cmp r3, r2 8007dde: d306 bcc.n 8007dee 8007de0: 68bb ldr r3, [r7, #8] 8007de2: 4a37 ldr r2, [pc, #220] @ (8007ec0 ) 8007de4: 4293 cmp r3, r2 8007de6: d202 bcs.n 8007dee { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 8007de8: 230d movs r3, #13 8007dea: 617b str r3, [r7, #20] 8007dec: e04c b.n 8007e88 } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 8007dee: 68bb ldr r3, [r7, #8] 8007df0: 4a33 ldr r2, [pc, #204] @ (8007ec0 ) 8007df2: 4293 cmp r3, r2 8007df4: d306 bcc.n 8007e04 8007df6: 68bb ldr r3, [r7, #8] 8007df8: 4a32 ldr r2, [pc, #200] @ (8007ec4 ) 8007dfa: 4293 cmp r3, r2 8007dfc: d802 bhi.n 8007e04 { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 8007dfe: 230c movs r3, #12 8007e00: 617b str r3, [r7, #20] 8007e02: e041 b.n 8007e88 } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 8007e04: 68bb ldr r3, [r7, #8] 8007e06: 4a2f ldr r2, [pc, #188] @ (8007ec4 ) 8007e08: 4293 cmp r3, r2 8007e0a: d906 bls.n 8007e1a 8007e0c: 68bb ldr r3, [r7, #8] 8007e0e: 4a2e ldr r2, [pc, #184] @ (8007ec8 ) 8007e10: 4293 cmp r3, r2 8007e12: d802 bhi.n 8007e1a { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 8007e14: 230b movs r3, #11 8007e16: 617b str r3, [r7, #20] 8007e18: e036 b.n 8007e88 } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 8007e1a: 68bb ldr r3, [r7, #8] 8007e1c: 4a2a ldr r2, [pc, #168] @ (8007ec8 ) 8007e1e: 4293 cmp r3, r2 8007e20: d906 bls.n 8007e30 8007e22: 68bb ldr r3, [r7, #8] 8007e24: 4a29 ldr r2, [pc, #164] @ (8007ecc ) 8007e26: 4293 cmp r3, r2 8007e28: d802 bhi.n 8007e30 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 8007e2a: 230a movs r3, #10 8007e2c: 617b str r3, [r7, #20] 8007e2e: e02b b.n 8007e88 } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 8007e30: 68bb ldr r3, [r7, #8] 8007e32: 4a26 ldr r2, [pc, #152] @ (8007ecc ) 8007e34: 4293 cmp r3, r2 8007e36: d906 bls.n 8007e46 8007e38: 68bb ldr r3, [r7, #8] 8007e3a: 4a25 ldr r2, [pc, #148] @ (8007ed0 ) 8007e3c: 4293 cmp r3, r2 8007e3e: d202 bcs.n 8007e46 { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 8007e40: 2309 movs r3, #9 8007e42: 617b str r3, [r7, #20] 8007e44: e020 b.n 8007e88 } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 8007e46: 68bb ldr r3, [r7, #8] 8007e48: 4a21 ldr r2, [pc, #132] @ (8007ed0 ) 8007e4a: 4293 cmp r3, r2 8007e4c: d306 bcc.n 8007e5c 8007e4e: 68bb ldr r3, [r7, #8] 8007e50: 4a20 ldr r2, [pc, #128] @ (8007ed4 ) 8007e52: 4293 cmp r3, r2 8007e54: d802 bhi.n 8007e5c { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 8007e56: 2308 movs r3, #8 8007e58: 617b str r3, [r7, #20] 8007e5a: e015 b.n 8007e88 } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8007e5c: 68bb ldr r3, [r7, #8] 8007e5e: 4a1d ldr r2, [pc, #116] @ (8007ed4 ) 8007e60: 4293 cmp r3, r2 8007e62: d906 bls.n 8007e72 8007e64: 68bb ldr r3, [r7, #8] 8007e66: 4a1c ldr r2, [pc, #112] @ (8007ed8 ) 8007e68: 4293 cmp r3, r2 8007e6a: d202 bcs.n 8007e72 { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 8007e6c: 2307 movs r3, #7 8007e6e: 617b str r3, [r7, #20] 8007e70: e00a b.n 8007e88 } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 8007e72: 2306 movs r3, #6 8007e74: 617b str r3, [r7, #20] 8007e76: e007 b.n 8007e88 } } else if (speed == USBD_HS_SPEED) 8007e78: 79fb ldrb r3, [r7, #7] 8007e7a: 2b00 cmp r3, #0 8007e7c: d102 bne.n 8007e84 { UsbTrd = USBD_HS_TRDT_VALUE; 8007e7e: 2309 movs r3, #9 8007e80: 617b str r3, [r7, #20] 8007e82: e001 b.n 8007e88 } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 8007e84: 2309 movs r3, #9 8007e86: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 8007e88: 68fb ldr r3, [r7, #12] 8007e8a: 68db ldr r3, [r3, #12] 8007e8c: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 8007e90: 68fb ldr r3, [r7, #12] 8007e92: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 8007e94: 68fb ldr r3, [r7, #12] 8007e96: 68da ldr r2, [r3, #12] 8007e98: 697b ldr r3, [r7, #20] 8007e9a: 029b lsls r3, r3, #10 8007e9c: f403 5370 and.w r3, r3, #15360 @ 0x3c00 8007ea0: 431a orrs r2, r3 8007ea2: 68fb ldr r3, [r7, #12] 8007ea4: 60da str r2, [r3, #12] return HAL_OK; 8007ea6: 2300 movs r3, #0 } 8007ea8: 4618 mov r0, r3 8007eaa: 371c adds r7, #28 8007eac: 46bd mov sp, r7 8007eae: f85d 7b04 ldr.w r7, [sp], #4 8007eb2: 4770 bx lr 8007eb4: 00d8acbf .word 0x00d8acbf 8007eb8: 00e4e1c0 .word 0x00e4e1c0 8007ebc: 00f42400 .word 0x00f42400 8007ec0: 01067380 .word 0x01067380 8007ec4: 011a499f .word 0x011a499f 8007ec8: 01312cff .word 0x01312cff 8007ecc: 014ca43f .word 0x014ca43f 8007ed0: 016e3600 .word 0x016e3600 8007ed4: 01a6ab1f .word 0x01a6ab1f 8007ed8: 01e84800 .word 0x01e84800 08007edc : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007edc: b480 push {r7} 8007ede: b083 sub sp, #12 8007ee0: af00 add r7, sp, #0 8007ee2: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8007ee4: 687b ldr r3, [r7, #4] 8007ee6: 689b ldr r3, [r3, #8] 8007ee8: f043 0201 orr.w r2, r3, #1 8007eec: 687b ldr r3, [r7, #4] 8007eee: 609a str r2, [r3, #8] return HAL_OK; 8007ef0: 2300 movs r3, #0 } 8007ef2: 4618 mov r0, r3 8007ef4: 370c adds r7, #12 8007ef6: 46bd mov sp, r7 8007ef8: f85d 7b04 ldr.w r7, [sp], #4 8007efc: 4770 bx lr 08007efe : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007efe: b480 push {r7} 8007f00: b083 sub sp, #12 8007f02: af00 add r7, sp, #0 8007f04: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 8007f06: 687b ldr r3, [r7, #4] 8007f08: 689b ldr r3, [r3, #8] 8007f0a: f023 0201 bic.w r2, r3, #1 8007f0e: 687b ldr r3, [r7, #4] 8007f10: 609a str r2, [r3, #8] return HAL_OK; 8007f12: 2300 movs r3, #0 } 8007f14: 4618 mov r0, r3 8007f16: 370c adds r7, #12 8007f18: 46bd mov sp, r7 8007f1a: f85d 7b04 ldr.w r7, [sp], #4 8007f1e: 4770 bx lr 08007f20 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8007f20: b580 push {r7, lr} 8007f22: b084 sub sp, #16 8007f24: af00 add r7, sp, #0 8007f26: 6078 str r0, [r7, #4] 8007f28: 460b mov r3, r1 8007f2a: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 8007f2c: 2300 movs r3, #0 8007f2e: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8007f30: 687b ldr r3, [r7, #4] 8007f32: 68db ldr r3, [r3, #12] 8007f34: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 8007f38: 687b ldr r3, [r7, #4] 8007f3a: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 8007f3c: 78fb ldrb r3, [r7, #3] 8007f3e: 2b01 cmp r3, #1 8007f40: d115 bne.n 8007f6e { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8007f42: 687b ldr r3, [r7, #4] 8007f44: 68db ldr r3, [r3, #12] 8007f46: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 8007f4a: 687b ldr r3, [r7, #4] 8007f4c: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8007f4e: 200a movs r0, #10 8007f50: f7fa f820 bl 8001f94 ms += 10U; 8007f54: 68fb ldr r3, [r7, #12] 8007f56: 330a adds r3, #10 8007f58: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007f5a: 6878 ldr r0, [r7, #4] 8007f5c: f001 f939 bl 80091d2 8007f60: 4603 mov r3, r0 8007f62: 2b01 cmp r3, #1 8007f64: d01e beq.n 8007fa4 8007f66: 68fb ldr r3, [r7, #12] 8007f68: 2bc7 cmp r3, #199 @ 0xc7 8007f6a: d9f0 bls.n 8007f4e 8007f6c: e01a b.n 8007fa4 } else if (mode == USB_DEVICE_MODE) 8007f6e: 78fb ldrb r3, [r7, #3] 8007f70: 2b00 cmp r3, #0 8007f72: d115 bne.n 8007fa0 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 8007f74: 687b ldr r3, [r7, #4] 8007f76: 68db ldr r3, [r3, #12] 8007f78: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 8007f7c: 687b ldr r3, [r7, #4] 8007f7e: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8007f80: 200a movs r0, #10 8007f82: f7fa f807 bl 8001f94 ms += 10U; 8007f86: 68fb ldr r3, [r7, #12] 8007f88: 330a adds r3, #10 8007f8a: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007f8c: 6878 ldr r0, [r7, #4] 8007f8e: f001 f920 bl 80091d2 8007f92: 4603 mov r3, r0 8007f94: 2b00 cmp r3, #0 8007f96: d005 beq.n 8007fa4 8007f98: 68fb ldr r3, [r7, #12] 8007f9a: 2bc7 cmp r3, #199 @ 0xc7 8007f9c: d9f0 bls.n 8007f80 8007f9e: e001 b.n 8007fa4 } else { return HAL_ERROR; 8007fa0: 2301 movs r3, #1 8007fa2: e005 b.n 8007fb0 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 8007fa4: 68fb ldr r3, [r7, #12] 8007fa6: 2bc8 cmp r3, #200 @ 0xc8 8007fa8: d101 bne.n 8007fae { return HAL_ERROR; 8007faa: 2301 movs r3, #1 8007fac: e000 b.n 8007fb0 } return HAL_OK; 8007fae: 2300 movs r3, #0 } 8007fb0: 4618 mov r0, r3 8007fb2: 3710 adds r7, #16 8007fb4: 46bd mov sp, r7 8007fb6: bd80 pop {r7, pc} 08007fb8 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007fb8: b084 sub sp, #16 8007fba: b580 push {r7, lr} 8007fbc: b086 sub sp, #24 8007fbe: af00 add r7, sp, #0 8007fc0: 6078 str r0, [r7, #4] 8007fc2: f107 0024 add.w r0, r7, #36 @ 0x24 8007fc6: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 8007fca: 2300 movs r3, #0 8007fcc: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007fce: 687b ldr r3, [r7, #4] 8007fd0: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 8007fd2: 2300 movs r3, #0 8007fd4: 613b str r3, [r7, #16] 8007fd6: e009 b.n 8007fec { USBx->DIEPTXF[i] = 0U; 8007fd8: 687a ldr r2, [r7, #4] 8007fda: 693b ldr r3, [r7, #16] 8007fdc: 3340 adds r3, #64 @ 0x40 8007fde: 009b lsls r3, r3, #2 8007fe0: 4413 add r3, r2 8007fe2: 2200 movs r2, #0 8007fe4: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 8007fe6: 693b ldr r3, [r7, #16] 8007fe8: 3301 adds r3, #1 8007fea: 613b str r3, [r7, #16] 8007fec: 693b ldr r3, [r7, #16] 8007fee: 2b0e cmp r3, #14 8007ff0: d9f2 bls.n 8007fd8 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 8007ff2: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8007ff6: 2b00 cmp r3, #0 8007ff8: d11c bne.n 8008034 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8007ffa: 68fb ldr r3, [r7, #12] 8007ffc: f503 6300 add.w r3, r3, #2048 @ 0x800 8008000: 685b ldr r3, [r3, #4] 8008002: 68fa ldr r2, [r7, #12] 8008004: f502 6200 add.w r2, r2, #2048 @ 0x800 8008008: f043 0302 orr.w r3, r3, #2 800800c: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 800800e: 687b ldr r3, [r7, #4] 8008010: 6b9b ldr r3, [r3, #56] @ 0x38 8008012: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 8008016: 687b ldr r3, [r7, #4] 8008018: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 800801a: 687b ldr r3, [r7, #4] 800801c: 681b ldr r3, [r3, #0] 800801e: f043 0240 orr.w r2, r3, #64 @ 0x40 8008022: 687b ldr r3, [r7, #4] 8008024: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8008026: 687b ldr r3, [r7, #4] 8008028: 681b ldr r3, [r3, #0] 800802a: f043 0280 orr.w r2, r3, #128 @ 0x80 800802e: 687b ldr r3, [r7, #4] 8008030: 601a str r2, [r3, #0] 8008032: e005 b.n 8008040 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 8008034: 687b ldr r3, [r7, #4] 8008036: 6b9b ldr r3, [r3, #56] @ 0x38 8008038: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800803c: 687b ldr r3, [r7, #4] 800803e: 639a str r2, [r3, #56] @ 0x38 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 8008040: 68fb ldr r3, [r7, #12] 8008042: f503 6360 add.w r3, r3, #3584 @ 0xe00 8008046: 461a mov r2, r3 8008048: 2300 movs r3, #0 800804a: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 800804c: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 8008050: 2b01 cmp r3, #1 8008052: d10d bne.n 8008070 { if (cfg.speed == USBD_HS_SPEED) 8008054: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8008058: 2b00 cmp r3, #0 800805a: d104 bne.n 8008066 { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 800805c: 2100 movs r1, #0 800805e: 6878 ldr r0, [r7, #4] 8008060: f000 f968 bl 8008334 8008064: e008 b.n 8008078 } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 8008066: 2101 movs r1, #1 8008068: 6878 ldr r0, [r7, #4] 800806a: f000 f963 bl 8008334 800806e: e003 b.n 8008078 } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 8008070: 2103 movs r1, #3 8008072: 6878 ldr r0, [r7, #4] 8008074: f000 f95e bl 8008334 } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 8008078: 2110 movs r1, #16 800807a: 6878 ldr r0, [r7, #4] 800807c: f000 f8fa bl 8008274 8008080: 4603 mov r3, r0 8008082: 2b00 cmp r3, #0 8008084: d001 beq.n 800808a { ret = HAL_ERROR; 8008086: 2301 movs r3, #1 8008088: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 800808a: 6878 ldr r0, [r7, #4] 800808c: f000 f924 bl 80082d8 8008090: 4603 mov r3, r0 8008092: 2b00 cmp r3, #0 8008094: d001 beq.n 800809a { ret = HAL_ERROR; 8008096: 2301 movs r3, #1 8008098: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 800809a: 68fb ldr r3, [r7, #12] 800809c: f503 6300 add.w r3, r3, #2048 @ 0x800 80080a0: 461a mov r2, r3 80080a2: 2300 movs r3, #0 80080a4: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 80080a6: 68fb ldr r3, [r7, #12] 80080a8: f503 6300 add.w r3, r3, #2048 @ 0x800 80080ac: 461a mov r2, r3 80080ae: 2300 movs r3, #0 80080b0: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 80080b2: 68fb ldr r3, [r7, #12] 80080b4: f503 6300 add.w r3, r3, #2048 @ 0x800 80080b8: 461a mov r2, r3 80080ba: 2300 movs r3, #0 80080bc: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 80080be: 2300 movs r3, #0 80080c0: 613b str r3, [r7, #16] 80080c2: e043 b.n 800814c { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 80080c4: 693b ldr r3, [r7, #16] 80080c6: 015a lsls r2, r3, #5 80080c8: 68fb ldr r3, [r7, #12] 80080ca: 4413 add r3, r2 80080cc: f503 6310 add.w r3, r3, #2304 @ 0x900 80080d0: 681b ldr r3, [r3, #0] 80080d2: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80080d6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80080da: d118 bne.n 800810e { if (i == 0U) 80080dc: 693b ldr r3, [r7, #16] 80080de: 2b00 cmp r3, #0 80080e0: d10a bne.n 80080f8 { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 80080e2: 693b ldr r3, [r7, #16] 80080e4: 015a lsls r2, r3, #5 80080e6: 68fb ldr r3, [r7, #12] 80080e8: 4413 add r3, r2 80080ea: f503 6310 add.w r3, r3, #2304 @ 0x900 80080ee: 461a mov r2, r3 80080f0: f04f 6300 mov.w r3, #134217728 @ 0x8000000 80080f4: 6013 str r3, [r2, #0] 80080f6: e013 b.n 8008120 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 80080f8: 693b ldr r3, [r7, #16] 80080fa: 015a lsls r2, r3, #5 80080fc: 68fb ldr r3, [r7, #12] 80080fe: 4413 add r3, r2 8008100: f503 6310 add.w r3, r3, #2304 @ 0x900 8008104: 461a mov r2, r3 8008106: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 800810a: 6013 str r3, [r2, #0] 800810c: e008 b.n 8008120 } } else { USBx_INEP(i)->DIEPCTL = 0U; 800810e: 693b ldr r3, [r7, #16] 8008110: 015a lsls r2, r3, #5 8008112: 68fb ldr r3, [r7, #12] 8008114: 4413 add r3, r2 8008116: f503 6310 add.w r3, r3, #2304 @ 0x900 800811a: 461a mov r2, r3 800811c: 2300 movs r3, #0 800811e: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8008120: 693b ldr r3, [r7, #16] 8008122: 015a lsls r2, r3, #5 8008124: 68fb ldr r3, [r7, #12] 8008126: 4413 add r3, r2 8008128: f503 6310 add.w r3, r3, #2304 @ 0x900 800812c: 461a mov r2, r3 800812e: 2300 movs r3, #0 8008130: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 8008132: 693b ldr r3, [r7, #16] 8008134: 015a lsls r2, r3, #5 8008136: 68fb ldr r3, [r7, #12] 8008138: 4413 add r3, r2 800813a: f503 6310 add.w r3, r3, #2304 @ 0x900 800813e: 461a mov r2, r3 8008140: f64f 337f movw r3, #64383 @ 0xfb7f 8008144: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8008146: 693b ldr r3, [r7, #16] 8008148: 3301 adds r3, #1 800814a: 613b str r3, [r7, #16] 800814c: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8008150: 461a mov r2, r3 8008152: 693b ldr r3, [r7, #16] 8008154: 4293 cmp r3, r2 8008156: d3b5 bcc.n 80080c4 } for (i = 0U; i < cfg.dev_endpoints; i++) 8008158: 2300 movs r3, #0 800815a: 613b str r3, [r7, #16] 800815c: e043 b.n 80081e6 { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 800815e: 693b ldr r3, [r7, #16] 8008160: 015a lsls r2, r3, #5 8008162: 68fb ldr r3, [r7, #12] 8008164: 4413 add r3, r2 8008166: f503 6330 add.w r3, r3, #2816 @ 0xb00 800816a: 681b ldr r3, [r3, #0] 800816c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008170: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008174: d118 bne.n 80081a8 { if (i == 0U) 8008176: 693b ldr r3, [r7, #16] 8008178: 2b00 cmp r3, #0 800817a: d10a bne.n 8008192 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 800817c: 693b ldr r3, [r7, #16] 800817e: 015a lsls r2, r3, #5 8008180: 68fb ldr r3, [r7, #12] 8008182: 4413 add r3, r2 8008184: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008188: 461a mov r2, r3 800818a: f04f 6300 mov.w r3, #134217728 @ 0x8000000 800818e: 6013 str r3, [r2, #0] 8008190: e013 b.n 80081ba } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 8008192: 693b ldr r3, [r7, #16] 8008194: 015a lsls r2, r3, #5 8008196: 68fb ldr r3, [r7, #12] 8008198: 4413 add r3, r2 800819a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800819e: 461a mov r2, r3 80081a0: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 80081a4: 6013 str r3, [r2, #0] 80081a6: e008 b.n 80081ba } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 80081a8: 693b ldr r3, [r7, #16] 80081aa: 015a lsls r2, r3, #5 80081ac: 68fb ldr r3, [r7, #12] 80081ae: 4413 add r3, r2 80081b0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80081b4: 461a mov r2, r3 80081b6: 2300 movs r3, #0 80081b8: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 80081ba: 693b ldr r3, [r7, #16] 80081bc: 015a lsls r2, r3, #5 80081be: 68fb ldr r3, [r7, #12] 80081c0: 4413 add r3, r2 80081c2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80081c6: 461a mov r2, r3 80081c8: 2300 movs r3, #0 80081ca: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 80081cc: 693b ldr r3, [r7, #16] 80081ce: 015a lsls r2, r3, #5 80081d0: 68fb ldr r3, [r7, #12] 80081d2: 4413 add r3, r2 80081d4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80081d8: 461a mov r2, r3 80081da: f64f 337f movw r3, #64383 @ 0xfb7f 80081de: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 80081e0: 693b ldr r3, [r7, #16] 80081e2: 3301 adds r3, #1 80081e4: 613b str r3, [r7, #16] 80081e6: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 80081ea: 461a mov r2, r3 80081ec: 693b ldr r3, [r7, #16] 80081ee: 4293 cmp r3, r2 80081f0: d3b5 bcc.n 800815e } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 80081f2: 68fb ldr r3, [r7, #12] 80081f4: f503 6300 add.w r3, r3, #2048 @ 0x800 80081f8: 691b ldr r3, [r3, #16] 80081fa: 68fa ldr r2, [r7, #12] 80081fc: f502 6200 add.w r2, r2, #2048 @ 0x800 8008200: f423 7380 bic.w r3, r3, #256 @ 0x100 8008204: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 8008206: 687b ldr r3, [r7, #4] 8008208: 2200 movs r2, #0 800820a: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 800820c: 687b ldr r3, [r7, #4] 800820e: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 8008212: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 8008214: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8008218: 2b00 cmp r3, #0 800821a: d105 bne.n 8008228 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 800821c: 687b ldr r3, [r7, #4] 800821e: 699b ldr r3, [r3, #24] 8008220: f043 0210 orr.w r2, r3, #16 8008224: 687b ldr r3, [r7, #4] 8008226: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8008228: 687b ldr r3, [r7, #4] 800822a: 699a ldr r2, [r3, #24] 800822c: 4b10 ldr r3, [pc, #64] @ (8008270 ) 800822e: 4313 orrs r3, r2 8008230: 687a ldr r2, [r7, #4] 8008232: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 8008234: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 8008238: 2b00 cmp r3, #0 800823a: d005 beq.n 8008248 { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 800823c: 687b ldr r3, [r7, #4] 800823e: 699b ldr r3, [r3, #24] 8008240: f043 0208 orr.w r2, r3, #8 8008244: 687b ldr r3, [r7, #4] 8008246: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 8008248: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800824c: 2b01 cmp r3, #1 800824e: d107 bne.n 8008260 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 8008250: 687b ldr r3, [r7, #4] 8008252: 699b ldr r3, [r3, #24] 8008254: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8008258: f043 0304 orr.w r3, r3, #4 800825c: 687a ldr r2, [r7, #4] 800825e: 6193 str r3, [r2, #24] } return ret; 8008260: 7dfb ldrb r3, [r7, #23] } 8008262: 4618 mov r0, r3 8008264: 3718 adds r7, #24 8008266: 46bd mov sp, r7 8008268: e8bd 4080 ldmia.w sp!, {r7, lr} 800826c: b004 add sp, #16 800826e: 4770 bx lr 8008270: 803c3800 .word 0x803c3800 08008274 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 8008274: b480 push {r7} 8008276: b085 sub sp, #20 8008278: af00 add r7, sp, #0 800827a: 6078 str r0, [r7, #4] 800827c: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 800827e: 2300 movs r3, #0 8008280: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8008282: 68fb ldr r3, [r7, #12] 8008284: 3301 adds r3, #1 8008286: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8008288: 68fb ldr r3, [r7, #12] 800828a: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 800828e: d901 bls.n 8008294 { return HAL_TIMEOUT; 8008290: 2303 movs r3, #3 8008292: e01b b.n 80082cc } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8008294: 687b ldr r3, [r7, #4] 8008296: 691b ldr r3, [r3, #16] 8008298: 2b00 cmp r3, #0 800829a: daf2 bge.n 8008282 /* Flush TX Fifo */ count = 0U; 800829c: 2300 movs r3, #0 800829e: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 80082a0: 683b ldr r3, [r7, #0] 80082a2: 019b lsls r3, r3, #6 80082a4: f043 0220 orr.w r2, r3, #32 80082a8: 687b ldr r3, [r7, #4] 80082aa: 611a str r2, [r3, #16] do { count++; 80082ac: 68fb ldr r3, [r7, #12] 80082ae: 3301 adds r3, #1 80082b0: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80082b2: 68fb ldr r3, [r7, #12] 80082b4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80082b8: d901 bls.n 80082be { return HAL_TIMEOUT; 80082ba: 2303 movs r3, #3 80082bc: e006 b.n 80082cc } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 80082be: 687b ldr r3, [r7, #4] 80082c0: 691b ldr r3, [r3, #16] 80082c2: f003 0320 and.w r3, r3, #32 80082c6: 2b20 cmp r3, #32 80082c8: d0f0 beq.n 80082ac return HAL_OK; 80082ca: 2300 movs r3, #0 } 80082cc: 4618 mov r0, r3 80082ce: 3714 adds r7, #20 80082d0: 46bd mov sp, r7 80082d2: f85d 7b04 ldr.w r7, [sp], #4 80082d6: 4770 bx lr 080082d8 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 80082d8: b480 push {r7} 80082da: b085 sub sp, #20 80082dc: af00 add r7, sp, #0 80082de: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80082e0: 2300 movs r3, #0 80082e2: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80082e4: 68fb ldr r3, [r7, #12] 80082e6: 3301 adds r3, #1 80082e8: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80082ea: 68fb ldr r3, [r7, #12] 80082ec: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80082f0: d901 bls.n 80082f6 { return HAL_TIMEOUT; 80082f2: 2303 movs r3, #3 80082f4: e018 b.n 8008328 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80082f6: 687b ldr r3, [r7, #4] 80082f8: 691b ldr r3, [r3, #16] 80082fa: 2b00 cmp r3, #0 80082fc: daf2 bge.n 80082e4 /* Flush RX Fifo */ count = 0U; 80082fe: 2300 movs r3, #0 8008300: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 8008302: 687b ldr r3, [r7, #4] 8008304: 2210 movs r2, #16 8008306: 611a str r2, [r3, #16] do { count++; 8008308: 68fb ldr r3, [r7, #12] 800830a: 3301 adds r3, #1 800830c: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800830e: 68fb ldr r3, [r7, #12] 8008310: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8008314: d901 bls.n 800831a { return HAL_TIMEOUT; 8008316: 2303 movs r3, #3 8008318: e006 b.n 8008328 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 800831a: 687b ldr r3, [r7, #4] 800831c: 691b ldr r3, [r3, #16] 800831e: f003 0310 and.w r3, r3, #16 8008322: 2b10 cmp r3, #16 8008324: d0f0 beq.n 8008308 return HAL_OK; 8008326: 2300 movs r3, #0 } 8008328: 4618 mov r0, r3 800832a: 3714 adds r7, #20 800832c: 46bd mov sp, r7 800832e: f85d 7b04 ldr.w r7, [sp], #4 8008332: 4770 bx lr 08008334 : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 8008334: b480 push {r7} 8008336: b085 sub sp, #20 8008338: af00 add r7, sp, #0 800833a: 6078 str r0, [r7, #4] 800833c: 460b mov r3, r1 800833e: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008340: 687b ldr r3, [r7, #4] 8008342: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 8008344: 68fb ldr r3, [r7, #12] 8008346: f503 6300 add.w r3, r3, #2048 @ 0x800 800834a: 681a ldr r2, [r3, #0] 800834c: 78fb ldrb r3, [r7, #3] 800834e: 68f9 ldr r1, [r7, #12] 8008350: f501 6100 add.w r1, r1, #2048 @ 0x800 8008354: 4313 orrs r3, r2 8008356: 600b str r3, [r1, #0] return HAL_OK; 8008358: 2300 movs r3, #0 } 800835a: 4618 mov r0, r3 800835c: 3714 adds r7, #20 800835e: 46bd mov sp, r7 8008360: f85d 7b04 ldr.w r7, [sp], #4 8008364: 4770 bx lr 08008366 : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { 8008366: b480 push {r7} 8008368: b087 sub sp, #28 800836a: af00 add r7, sp, #0 800836c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800836e: 687b ldr r3, [r7, #4] 8008370: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 8008372: 693b ldr r3, [r7, #16] 8008374: f503 6300 add.w r3, r3, #2048 @ 0x800 8008378: 689b ldr r3, [r3, #8] 800837a: f003 0306 and.w r3, r3, #6 800837e: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 8008380: 68fb ldr r3, [r7, #12] 8008382: 2b00 cmp r3, #0 8008384: d102 bne.n 800838c { speed = USBD_HS_SPEED; 8008386: 2300 movs r3, #0 8008388: 75fb strb r3, [r7, #23] 800838a: e00a b.n 80083a2 } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 800838c: 68fb ldr r3, [r7, #12] 800838e: 2b02 cmp r3, #2 8008390: d002 beq.n 8008398 8008392: 68fb ldr r3, [r7, #12] 8008394: 2b06 cmp r3, #6 8008396: d102 bne.n 800839e (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 8008398: 2302 movs r3, #2 800839a: 75fb strb r3, [r7, #23] 800839c: e001 b.n 80083a2 } else { speed = 0xFU; 800839e: 230f movs r3, #15 80083a0: 75fb strb r3, [r7, #23] } return speed; 80083a2: 7dfb ldrb r3, [r7, #23] } 80083a4: 4618 mov r0, r3 80083a6: 371c adds r7, #28 80083a8: 46bd mov sp, r7 80083aa: f85d 7b04 ldr.w r7, [sp], #4 80083ae: 4770 bx lr 080083b0 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80083b0: b480 push {r7} 80083b2: b085 sub sp, #20 80083b4: af00 add r7, sp, #0 80083b6: 6078 str r0, [r7, #4] 80083b8: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80083ba: 687b ldr r3, [r7, #4] 80083bc: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80083be: 683b ldr r3, [r7, #0] 80083c0: 781b ldrb r3, [r3, #0] 80083c2: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80083c4: 683b ldr r3, [r7, #0] 80083c6: 785b ldrb r3, [r3, #1] 80083c8: 2b01 cmp r3, #1 80083ca: d13a bne.n 8008442 { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 80083cc: 68fb ldr r3, [r7, #12] 80083ce: f503 6300 add.w r3, r3, #2048 @ 0x800 80083d2: 69da ldr r2, [r3, #28] 80083d4: 683b ldr r3, [r7, #0] 80083d6: 781b ldrb r3, [r3, #0] 80083d8: f003 030f and.w r3, r3, #15 80083dc: 2101 movs r1, #1 80083de: fa01 f303 lsl.w r3, r1, r3 80083e2: b29b uxth r3, r3 80083e4: 68f9 ldr r1, [r7, #12] 80083e6: f501 6100 add.w r1, r1, #2048 @ 0x800 80083ea: 4313 orrs r3, r2 80083ec: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 80083ee: 68bb ldr r3, [r7, #8] 80083f0: 015a lsls r2, r3, #5 80083f2: 68fb ldr r3, [r7, #12] 80083f4: 4413 add r3, r2 80083f6: f503 6310 add.w r3, r3, #2304 @ 0x900 80083fa: 681b ldr r3, [r3, #0] 80083fc: f403 4300 and.w r3, r3, #32768 @ 0x8000 8008400: 2b00 cmp r3, #0 8008402: d155 bne.n 80084b0 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8008404: 68bb ldr r3, [r7, #8] 8008406: 015a lsls r2, r3, #5 8008408: 68fb ldr r3, [r7, #12] 800840a: 4413 add r3, r2 800840c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008410: 681a ldr r2, [r3, #0] 8008412: 683b ldr r3, [r7, #0] 8008414: 689b ldr r3, [r3, #8] 8008416: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 800841a: 683b ldr r3, [r7, #0] 800841c: 791b ldrb r3, [r3, #4] 800841e: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8008420: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 8008422: 68bb ldr r3, [r7, #8] 8008424: 059b lsls r3, r3, #22 8008426: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8008428: 4313 orrs r3, r2 800842a: 68ba ldr r2, [r7, #8] 800842c: 0151 lsls r1, r2, #5 800842e: 68fa ldr r2, [r7, #12] 8008430: 440a add r2, r1 8008432: f502 6210 add.w r2, r2, #2304 @ 0x900 8008436: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800843a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800843e: 6013 str r3, [r2, #0] 8008440: e036 b.n 80084b0 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 8008442: 68fb ldr r3, [r7, #12] 8008444: f503 6300 add.w r3, r3, #2048 @ 0x800 8008448: 69da ldr r2, [r3, #28] 800844a: 683b ldr r3, [r7, #0] 800844c: 781b ldrb r3, [r3, #0] 800844e: f003 030f and.w r3, r3, #15 8008452: 2101 movs r1, #1 8008454: fa01 f303 lsl.w r3, r1, r3 8008458: 041b lsls r3, r3, #16 800845a: 68f9 ldr r1, [r7, #12] 800845c: f501 6100 add.w r1, r1, #2048 @ 0x800 8008460: 4313 orrs r3, r2 8008462: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 8008464: 68bb ldr r3, [r7, #8] 8008466: 015a lsls r2, r3, #5 8008468: 68fb ldr r3, [r7, #12] 800846a: 4413 add r3, r2 800846c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008470: 681b ldr r3, [r3, #0] 8008472: f403 4300 and.w r3, r3, #32768 @ 0x8000 8008476: 2b00 cmp r3, #0 8008478: d11a bne.n 80084b0 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 800847a: 68bb ldr r3, [r7, #8] 800847c: 015a lsls r2, r3, #5 800847e: 68fb ldr r3, [r7, #12] 8008480: 4413 add r3, r2 8008482: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008486: 681a ldr r2, [r3, #0] 8008488: 683b ldr r3, [r7, #0] 800848a: 689b ldr r3, [r3, #8] 800848c: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 8008490: 683b ldr r3, [r7, #0] 8008492: 791b ldrb r3, [r3, #4] 8008494: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 8008496: 430b orrs r3, r1 8008498: 4313 orrs r3, r2 800849a: 68ba ldr r2, [r7, #8] 800849c: 0151 lsls r1, r2, #5 800849e: 68fa ldr r2, [r7, #12] 80084a0: 440a add r2, r1 80084a2: f502 6230 add.w r2, r2, #2816 @ 0xb00 80084a6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80084aa: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80084ae: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 80084b0: 2300 movs r3, #0 } 80084b2: 4618 mov r0, r3 80084b4: 3714 adds r7, #20 80084b6: 46bd mov sp, r7 80084b8: f85d 7b04 ldr.w r7, [sp], #4 80084bc: 4770 bx lr ... 080084c0 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80084c0: b480 push {r7} 80084c2: b085 sub sp, #20 80084c4: af00 add r7, sp, #0 80084c6: 6078 str r0, [r7, #4] 80084c8: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80084ca: 687b ldr r3, [r7, #4] 80084cc: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80084ce: 683b ldr r3, [r7, #0] 80084d0: 781b ldrb r3, [r3, #0] 80084d2: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 80084d4: 683b ldr r3, [r7, #0] 80084d6: 785b ldrb r3, [r3, #1] 80084d8: 2b01 cmp r3, #1 80084da: d161 bne.n 80085a0 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 80084dc: 68bb ldr r3, [r7, #8] 80084de: 015a lsls r2, r3, #5 80084e0: 68fb ldr r3, [r7, #12] 80084e2: 4413 add r3, r2 80084e4: f503 6310 add.w r3, r3, #2304 @ 0x900 80084e8: 681b ldr r3, [r3, #0] 80084ea: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80084ee: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80084f2: d11f bne.n 8008534 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 80084f4: 68bb ldr r3, [r7, #8] 80084f6: 015a lsls r2, r3, #5 80084f8: 68fb ldr r3, [r7, #12] 80084fa: 4413 add r3, r2 80084fc: f503 6310 add.w r3, r3, #2304 @ 0x900 8008500: 681b ldr r3, [r3, #0] 8008502: 68ba ldr r2, [r7, #8] 8008504: 0151 lsls r1, r2, #5 8008506: 68fa ldr r2, [r7, #12] 8008508: 440a add r2, r1 800850a: f502 6210 add.w r2, r2, #2304 @ 0x900 800850e: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8008512: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 8008514: 68bb ldr r3, [r7, #8] 8008516: 015a lsls r2, r3, #5 8008518: 68fb ldr r3, [r7, #12] 800851a: 4413 add r3, r2 800851c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008520: 681b ldr r3, [r3, #0] 8008522: 68ba ldr r2, [r7, #8] 8008524: 0151 lsls r1, r2, #5 8008526: 68fa ldr r2, [r7, #12] 8008528: 440a add r2, r1 800852a: f502 6210 add.w r2, r2, #2304 @ 0x900 800852e: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8008532: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8008534: 68fb ldr r3, [r7, #12] 8008536: f503 6300 add.w r3, r3, #2048 @ 0x800 800853a: 6bda ldr r2, [r3, #60] @ 0x3c 800853c: 683b ldr r3, [r7, #0] 800853e: 781b ldrb r3, [r3, #0] 8008540: f003 030f and.w r3, r3, #15 8008544: 2101 movs r1, #1 8008546: fa01 f303 lsl.w r3, r1, r3 800854a: b29b uxth r3, r3 800854c: 43db mvns r3, r3 800854e: 68f9 ldr r1, [r7, #12] 8008550: f501 6100 add.w r1, r1, #2048 @ 0x800 8008554: 4013 ands r3, r2 8008556: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8008558: 68fb ldr r3, [r7, #12] 800855a: f503 6300 add.w r3, r3, #2048 @ 0x800 800855e: 69da ldr r2, [r3, #28] 8008560: 683b ldr r3, [r7, #0] 8008562: 781b ldrb r3, [r3, #0] 8008564: f003 030f and.w r3, r3, #15 8008568: 2101 movs r1, #1 800856a: fa01 f303 lsl.w r3, r1, r3 800856e: b29b uxth r3, r3 8008570: 43db mvns r3, r3 8008572: 68f9 ldr r1, [r7, #12] 8008574: f501 6100 add.w r1, r1, #2048 @ 0x800 8008578: 4013 ands r3, r2 800857a: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 800857c: 68bb ldr r3, [r7, #8] 800857e: 015a lsls r2, r3, #5 8008580: 68fb ldr r3, [r7, #12] 8008582: 4413 add r3, r2 8008584: f503 6310 add.w r3, r3, #2304 @ 0x900 8008588: 681a ldr r2, [r3, #0] 800858a: 68bb ldr r3, [r7, #8] 800858c: 0159 lsls r1, r3, #5 800858e: 68fb ldr r3, [r7, #12] 8008590: 440b add r3, r1 8008592: f503 6310 add.w r3, r3, #2304 @ 0x900 8008596: 4619 mov r1, r3 8008598: 4b35 ldr r3, [pc, #212] @ (8008670 ) 800859a: 4013 ands r3, r2 800859c: 600b str r3, [r1, #0] 800859e: e060 b.n 8008662 USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80085a0: 68bb ldr r3, [r7, #8] 80085a2: 015a lsls r2, r3, #5 80085a4: 68fb ldr r3, [r7, #12] 80085a6: 4413 add r3, r2 80085a8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80085ac: 681b ldr r3, [r3, #0] 80085ae: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80085b2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80085b6: d11f bne.n 80085f8 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 80085b8: 68bb ldr r3, [r7, #8] 80085ba: 015a lsls r2, r3, #5 80085bc: 68fb ldr r3, [r7, #12] 80085be: 4413 add r3, r2 80085c0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80085c4: 681b ldr r3, [r3, #0] 80085c6: 68ba ldr r2, [r7, #8] 80085c8: 0151 lsls r1, r2, #5 80085ca: 68fa ldr r2, [r7, #12] 80085cc: 440a add r2, r1 80085ce: f502 6230 add.w r2, r2, #2816 @ 0xb00 80085d2: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80085d6: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 80085d8: 68bb ldr r3, [r7, #8] 80085da: 015a lsls r2, r3, #5 80085dc: 68fb ldr r3, [r7, #12] 80085de: 4413 add r3, r2 80085e0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80085e4: 681b ldr r3, [r3, #0] 80085e6: 68ba ldr r2, [r7, #8] 80085e8: 0151 lsls r1, r2, #5 80085ea: 68fa ldr r2, [r7, #12] 80085ec: 440a add r2, r1 80085ee: f502 6230 add.w r2, r2, #2816 @ 0xb00 80085f2: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80085f6: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 80085f8: 68fb ldr r3, [r7, #12] 80085fa: f503 6300 add.w r3, r3, #2048 @ 0x800 80085fe: 6bda ldr r2, [r3, #60] @ 0x3c 8008600: 683b ldr r3, [r7, #0] 8008602: 781b ldrb r3, [r3, #0] 8008604: f003 030f and.w r3, r3, #15 8008608: 2101 movs r1, #1 800860a: fa01 f303 lsl.w r3, r1, r3 800860e: 041b lsls r3, r3, #16 8008610: 43db mvns r3, r3 8008612: 68f9 ldr r1, [r7, #12] 8008614: f501 6100 add.w r1, r1, #2048 @ 0x800 8008618: 4013 ands r3, r2 800861a: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 800861c: 68fb ldr r3, [r7, #12] 800861e: f503 6300 add.w r3, r3, #2048 @ 0x800 8008622: 69da ldr r2, [r3, #28] 8008624: 683b ldr r3, [r7, #0] 8008626: 781b ldrb r3, [r3, #0] 8008628: f003 030f and.w r3, r3, #15 800862c: 2101 movs r1, #1 800862e: fa01 f303 lsl.w r3, r1, r3 8008632: 041b lsls r3, r3, #16 8008634: 43db mvns r3, r3 8008636: 68f9 ldr r1, [r7, #12] 8008638: f501 6100 add.w r1, r1, #2048 @ 0x800 800863c: 4013 ands r3, r2 800863e: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 8008640: 68bb ldr r3, [r7, #8] 8008642: 015a lsls r2, r3, #5 8008644: 68fb ldr r3, [r7, #12] 8008646: 4413 add r3, r2 8008648: f503 6330 add.w r3, r3, #2816 @ 0xb00 800864c: 681a ldr r2, [r3, #0] 800864e: 68bb ldr r3, [r7, #8] 8008650: 0159 lsls r1, r3, #5 8008652: 68fb ldr r3, [r7, #12] 8008654: 440b add r3, r1 8008656: f503 6330 add.w r3, r3, #2816 @ 0xb00 800865a: 4619 mov r1, r3 800865c: 4b05 ldr r3, [pc, #20] @ (8008674 ) 800865e: 4013 ands r3, r2 8008660: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 8008662: 2300 movs r3, #0 } 8008664: 4618 mov r0, r3 8008666: 3714 adds r7, #20 8008668: 46bd mov sp, r7 800866a: f85d 7b04 ldr.w r7, [sp], #4 800866e: 4770 bx lr 8008670: ec337800 .word 0xec337800 8008674: eff37800 .word 0xeff37800 08008678 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 8008678: b580 push {r7, lr} 800867a: b08a sub sp, #40 @ 0x28 800867c: af02 add r7, sp, #8 800867e: 60f8 str r0, [r7, #12] 8008680: 60b9 str r1, [r7, #8] 8008682: 4613 mov r3, r2 8008684: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 8008686: 68fb ldr r3, [r7, #12] 8008688: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 800868a: 68bb ldr r3, [r7, #8] 800868c: 781b ldrb r3, [r3, #0] 800868e: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 8008690: 68bb ldr r3, [r7, #8] 8008692: 785b ldrb r3, [r3, #1] 8008694: 2b01 cmp r3, #1 8008696: f040 817f bne.w 8008998 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 800869a: 68bb ldr r3, [r7, #8] 800869c: 691b ldr r3, [r3, #16] 800869e: 2b00 cmp r3, #0 80086a0: d132 bne.n 8008708 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 80086a2: 69bb ldr r3, [r7, #24] 80086a4: 015a lsls r2, r3, #5 80086a6: 69fb ldr r3, [r7, #28] 80086a8: 4413 add r3, r2 80086aa: f503 6310 add.w r3, r3, #2304 @ 0x900 80086ae: 691b ldr r3, [r3, #16] 80086b0: 69ba ldr r2, [r7, #24] 80086b2: 0151 lsls r1, r2, #5 80086b4: 69fa ldr r2, [r7, #28] 80086b6: 440a add r2, r1 80086b8: f502 6210 add.w r2, r2, #2304 @ 0x900 80086bc: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 80086c0: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 80086c4: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 80086c6: 69bb ldr r3, [r7, #24] 80086c8: 015a lsls r2, r3, #5 80086ca: 69fb ldr r3, [r7, #28] 80086cc: 4413 add r3, r2 80086ce: f503 6310 add.w r3, r3, #2304 @ 0x900 80086d2: 691b ldr r3, [r3, #16] 80086d4: 69ba ldr r2, [r7, #24] 80086d6: 0151 lsls r1, r2, #5 80086d8: 69fa ldr r2, [r7, #28] 80086da: 440a add r2, r1 80086dc: f502 6210 add.w r2, r2, #2304 @ 0x900 80086e0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80086e4: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 80086e6: 69bb ldr r3, [r7, #24] 80086e8: 015a lsls r2, r3, #5 80086ea: 69fb ldr r3, [r7, #28] 80086ec: 4413 add r3, r2 80086ee: f503 6310 add.w r3, r3, #2304 @ 0x900 80086f2: 691b ldr r3, [r3, #16] 80086f4: 69ba ldr r2, [r7, #24] 80086f6: 0151 lsls r1, r2, #5 80086f8: 69fa ldr r2, [r7, #28] 80086fa: 440a add r2, r1 80086fc: f502 6210 add.w r2, r2, #2304 @ 0x900 8008700: 0cdb lsrs r3, r3, #19 8008702: 04db lsls r3, r3, #19 8008704: 6113 str r3, [r2, #16] 8008706: e097 b.n 8008838 /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8008708: 69bb ldr r3, [r7, #24] 800870a: 015a lsls r2, r3, #5 800870c: 69fb ldr r3, [r7, #28] 800870e: 4413 add r3, r2 8008710: f503 6310 add.w r3, r3, #2304 @ 0x900 8008714: 691b ldr r3, [r3, #16] 8008716: 69ba ldr r2, [r7, #24] 8008718: 0151 lsls r1, r2, #5 800871a: 69fa ldr r2, [r7, #28] 800871c: 440a add r2, r1 800871e: f502 6210 add.w r2, r2, #2304 @ 0x900 8008722: 0cdb lsrs r3, r3, #19 8008724: 04db lsls r3, r3, #19 8008726: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8008728: 69bb ldr r3, [r7, #24] 800872a: 015a lsls r2, r3, #5 800872c: 69fb ldr r3, [r7, #28] 800872e: 4413 add r3, r2 8008730: f503 6310 add.w r3, r3, #2304 @ 0x900 8008734: 691b ldr r3, [r3, #16] 8008736: 69ba ldr r2, [r7, #24] 8008738: 0151 lsls r1, r2, #5 800873a: 69fa ldr r2, [r7, #28] 800873c: 440a add r2, r1 800873e: f502 6210 add.w r2, r2, #2304 @ 0x900 8008742: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8008746: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 800874a: 6113 str r3, [r2, #16] if (epnum == 0U) 800874c: 69bb ldr r3, [r7, #24] 800874e: 2b00 cmp r3, #0 8008750: d11a bne.n 8008788 { if (ep->xfer_len > ep->maxpacket) 8008752: 68bb ldr r3, [r7, #8] 8008754: 691a ldr r2, [r3, #16] 8008756: 68bb ldr r3, [r7, #8] 8008758: 689b ldr r3, [r3, #8] 800875a: 429a cmp r2, r3 800875c: d903 bls.n 8008766 { ep->xfer_len = ep->maxpacket; 800875e: 68bb ldr r3, [r7, #8] 8008760: 689a ldr r2, [r3, #8] 8008762: 68bb ldr r3, [r7, #8] 8008764: 611a str r2, [r3, #16] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8008766: 69bb ldr r3, [r7, #24] 8008768: 015a lsls r2, r3, #5 800876a: 69fb ldr r3, [r7, #28] 800876c: 4413 add r3, r2 800876e: f503 6310 add.w r3, r3, #2304 @ 0x900 8008772: 691b ldr r3, [r3, #16] 8008774: 69ba ldr r2, [r7, #24] 8008776: 0151 lsls r1, r2, #5 8008778: 69fa ldr r2, [r7, #28] 800877a: 440a add r2, r1 800877c: f502 6210 add.w r2, r2, #2304 @ 0x900 8008780: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008784: 6113 str r3, [r2, #16] 8008786: e044 b.n 8008812 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8008788: 68bb ldr r3, [r7, #8] 800878a: 691a ldr r2, [r3, #16] 800878c: 68bb ldr r3, [r7, #8] 800878e: 689b ldr r3, [r3, #8] 8008790: 4413 add r3, r2 8008792: 1e5a subs r2, r3, #1 8008794: 68bb ldr r3, [r7, #8] 8008796: 689b ldr r3, [r3, #8] 8008798: fbb2 f3f3 udiv r3, r2, r3 800879c: 82fb strh r3, [r7, #22] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); 800879e: 69bb ldr r3, [r7, #24] 80087a0: 015a lsls r2, r3, #5 80087a2: 69fb ldr r3, [r7, #28] 80087a4: 4413 add r3, r2 80087a6: f503 6310 add.w r3, r3, #2304 @ 0x900 80087aa: 691a ldr r2, [r3, #16] 80087ac: 8afb ldrh r3, [r7, #22] 80087ae: 04d9 lsls r1, r3, #19 80087b0: 4ba4 ldr r3, [pc, #656] @ (8008a44 ) 80087b2: 400b ands r3, r1 80087b4: 69b9 ldr r1, [r7, #24] 80087b6: 0148 lsls r0, r1, #5 80087b8: 69f9 ldr r1, [r7, #28] 80087ba: 4401 add r1, r0 80087bc: f501 6110 add.w r1, r1, #2304 @ 0x900 80087c0: 4313 orrs r3, r2 80087c2: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 80087c4: 68bb ldr r3, [r7, #8] 80087c6: 791b ldrb r3, [r3, #4] 80087c8: 2b01 cmp r3, #1 80087ca: d122 bne.n 8008812 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 80087cc: 69bb ldr r3, [r7, #24] 80087ce: 015a lsls r2, r3, #5 80087d0: 69fb ldr r3, [r7, #28] 80087d2: 4413 add r3, r2 80087d4: f503 6310 add.w r3, r3, #2304 @ 0x900 80087d8: 691b ldr r3, [r3, #16] 80087da: 69ba ldr r2, [r7, #24] 80087dc: 0151 lsls r1, r2, #5 80087de: 69fa ldr r2, [r7, #28] 80087e0: 440a add r2, r1 80087e2: f502 6210 add.w r2, r2, #2304 @ 0x900 80087e6: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 80087ea: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); 80087ec: 69bb ldr r3, [r7, #24] 80087ee: 015a lsls r2, r3, #5 80087f0: 69fb ldr r3, [r7, #28] 80087f2: 4413 add r3, r2 80087f4: f503 6310 add.w r3, r3, #2304 @ 0x900 80087f8: 691a ldr r2, [r3, #16] 80087fa: 8afb ldrh r3, [r7, #22] 80087fc: 075b lsls r3, r3, #29 80087fe: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 8008802: 69b9 ldr r1, [r7, #24] 8008804: 0148 lsls r0, r1, #5 8008806: 69f9 ldr r1, [r7, #28] 8008808: 4401 add r1, r0 800880a: f501 6110 add.w r1, r1, #2304 @ 0x900 800880e: 4313 orrs r3, r2 8008810: 610b str r3, [r1, #16] } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8008812: 69bb ldr r3, [r7, #24] 8008814: 015a lsls r2, r3, #5 8008816: 69fb ldr r3, [r7, #28] 8008818: 4413 add r3, r2 800881a: f503 6310 add.w r3, r3, #2304 @ 0x900 800881e: 691a ldr r2, [r3, #16] 8008820: 68bb ldr r3, [r7, #8] 8008822: 691b ldr r3, [r3, #16] 8008824: f3c3 0312 ubfx r3, r3, #0, #19 8008828: 69b9 ldr r1, [r7, #24] 800882a: 0148 lsls r0, r1, #5 800882c: 69f9 ldr r1, [r7, #28] 800882e: 4401 add r1, r0 8008830: f501 6110 add.w r1, r1, #2304 @ 0x900 8008834: 4313 orrs r3, r2 8008836: 610b str r3, [r1, #16] } if (dma == 1U) 8008838: 79fb ldrb r3, [r7, #7] 800883a: 2b01 cmp r3, #1 800883c: d14b bne.n 80088d6 { if ((uint32_t)ep->dma_addr != 0U) 800883e: 68bb ldr r3, [r7, #8] 8008840: 69db ldr r3, [r3, #28] 8008842: 2b00 cmp r3, #0 8008844: d009 beq.n 800885a { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8008846: 69bb ldr r3, [r7, #24] 8008848: 015a lsls r2, r3, #5 800884a: 69fb ldr r3, [r7, #28] 800884c: 4413 add r3, r2 800884e: f503 6310 add.w r3, r3, #2304 @ 0x900 8008852: 461a mov r2, r3 8008854: 68bb ldr r3, [r7, #8] 8008856: 69db ldr r3, [r3, #28] 8008858: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 800885a: 68bb ldr r3, [r7, #8] 800885c: 791b ldrb r3, [r3, #4] 800885e: 2b01 cmp r3, #1 8008860: d128 bne.n 80088b4 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8008862: 69fb ldr r3, [r7, #28] 8008864: f503 6300 add.w r3, r3, #2048 @ 0x800 8008868: 689b ldr r3, [r3, #8] 800886a: f403 7380 and.w r3, r3, #256 @ 0x100 800886e: 2b00 cmp r3, #0 8008870: d110 bne.n 8008894 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8008872: 69bb ldr r3, [r7, #24] 8008874: 015a lsls r2, r3, #5 8008876: 69fb ldr r3, [r7, #28] 8008878: 4413 add r3, r2 800887a: f503 6310 add.w r3, r3, #2304 @ 0x900 800887e: 681b ldr r3, [r3, #0] 8008880: 69ba ldr r2, [r7, #24] 8008882: 0151 lsls r1, r2, #5 8008884: 69fa ldr r2, [r7, #28] 8008886: 440a add r2, r1 8008888: f502 6210 add.w r2, r2, #2304 @ 0x900 800888c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8008890: 6013 str r3, [r2, #0] 8008892: e00f b.n 80088b4 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8008894: 69bb ldr r3, [r7, #24] 8008896: 015a lsls r2, r3, #5 8008898: 69fb ldr r3, [r7, #28] 800889a: 4413 add r3, r2 800889c: f503 6310 add.w r3, r3, #2304 @ 0x900 80088a0: 681b ldr r3, [r3, #0] 80088a2: 69ba ldr r2, [r7, #24] 80088a4: 0151 lsls r1, r2, #5 80088a6: 69fa ldr r2, [r7, #28] 80088a8: 440a add r2, r1 80088aa: f502 6210 add.w r2, r2, #2304 @ 0x900 80088ae: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80088b2: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 80088b4: 69bb ldr r3, [r7, #24] 80088b6: 015a lsls r2, r3, #5 80088b8: 69fb ldr r3, [r7, #28] 80088ba: 4413 add r3, r2 80088bc: f503 6310 add.w r3, r3, #2304 @ 0x900 80088c0: 681b ldr r3, [r3, #0] 80088c2: 69ba ldr r2, [r7, #24] 80088c4: 0151 lsls r1, r2, #5 80088c6: 69fa ldr r2, [r7, #28] 80088c8: 440a add r2, r1 80088ca: f502 6210 add.w r2, r2, #2304 @ 0x900 80088ce: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 80088d2: 6013 str r3, [r2, #0] 80088d4: e166 b.n 8008ba4 } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 80088d6: 69bb ldr r3, [r7, #24] 80088d8: 015a lsls r2, r3, #5 80088da: 69fb ldr r3, [r7, #28] 80088dc: 4413 add r3, r2 80088de: f503 6310 add.w r3, r3, #2304 @ 0x900 80088e2: 681b ldr r3, [r3, #0] 80088e4: 69ba ldr r2, [r7, #24] 80088e6: 0151 lsls r1, r2, #5 80088e8: 69fa ldr r2, [r7, #28] 80088ea: 440a add r2, r1 80088ec: f502 6210 add.w r2, r2, #2304 @ 0x900 80088f0: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 80088f4: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 80088f6: 68bb ldr r3, [r7, #8] 80088f8: 791b ldrb r3, [r3, #4] 80088fa: 2b01 cmp r3, #1 80088fc: d015 beq.n 800892a { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 80088fe: 68bb ldr r3, [r7, #8] 8008900: 691b ldr r3, [r3, #16] 8008902: 2b00 cmp r3, #0 8008904: f000 814e beq.w 8008ba4 { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8008908: 69fb ldr r3, [r7, #28] 800890a: f503 6300 add.w r3, r3, #2048 @ 0x800 800890e: 6b5a ldr r2, [r3, #52] @ 0x34 8008910: 68bb ldr r3, [r7, #8] 8008912: 781b ldrb r3, [r3, #0] 8008914: f003 030f and.w r3, r3, #15 8008918: 2101 movs r1, #1 800891a: fa01 f303 lsl.w r3, r1, r3 800891e: 69f9 ldr r1, [r7, #28] 8008920: f501 6100 add.w r1, r1, #2048 @ 0x800 8008924: 4313 orrs r3, r2 8008926: 634b str r3, [r1, #52] @ 0x34 8008928: e13c b.n 8008ba4 } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 800892a: 69fb ldr r3, [r7, #28] 800892c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008930: 689b ldr r3, [r3, #8] 8008932: f403 7380 and.w r3, r3, #256 @ 0x100 8008936: 2b00 cmp r3, #0 8008938: d110 bne.n 800895c { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 800893a: 69bb ldr r3, [r7, #24] 800893c: 015a lsls r2, r3, #5 800893e: 69fb ldr r3, [r7, #28] 8008940: 4413 add r3, r2 8008942: f503 6310 add.w r3, r3, #2304 @ 0x900 8008946: 681b ldr r3, [r3, #0] 8008948: 69ba ldr r2, [r7, #24] 800894a: 0151 lsls r1, r2, #5 800894c: 69fa ldr r2, [r7, #28] 800894e: 440a add r2, r1 8008950: f502 6210 add.w r2, r2, #2304 @ 0x900 8008954: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8008958: 6013 str r3, [r2, #0] 800895a: e00f b.n 800897c } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 800895c: 69bb ldr r3, [r7, #24] 800895e: 015a lsls r2, r3, #5 8008960: 69fb ldr r3, [r7, #28] 8008962: 4413 add r3, r2 8008964: f503 6310 add.w r3, r3, #2304 @ 0x900 8008968: 681b ldr r3, [r3, #0] 800896a: 69ba ldr r2, [r7, #24] 800896c: 0151 lsls r1, r2, #5 800896e: 69fa ldr r2, [r7, #28] 8008970: 440a add r2, r1 8008972: f502 6210 add.w r2, r2, #2304 @ 0x900 8008976: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800897a: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 800897c: 68bb ldr r3, [r7, #8] 800897e: 68d9 ldr r1, [r3, #12] 8008980: 68bb ldr r3, [r7, #8] 8008982: 781a ldrb r2, [r3, #0] 8008984: 68bb ldr r3, [r7, #8] 8008986: 691b ldr r3, [r3, #16] 8008988: b298 uxth r0, r3 800898a: 79fb ldrb r3, [r7, #7] 800898c: 9300 str r3, [sp, #0] 800898e: 4603 mov r3, r0 8008990: 68f8 ldr r0, [r7, #12] 8008992: f000 f9b9 bl 8008d08 8008996: e105 b.n 8008ba4 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8008998: 69bb ldr r3, [r7, #24] 800899a: 015a lsls r2, r3, #5 800899c: 69fb ldr r3, [r7, #28] 800899e: 4413 add r3, r2 80089a0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80089a4: 691b ldr r3, [r3, #16] 80089a6: 69ba ldr r2, [r7, #24] 80089a8: 0151 lsls r1, r2, #5 80089aa: 69fa ldr r2, [r7, #28] 80089ac: 440a add r2, r1 80089ae: f502 6230 add.w r2, r2, #2816 @ 0xb00 80089b2: 0cdb lsrs r3, r3, #19 80089b4: 04db lsls r3, r3, #19 80089b6: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 80089b8: 69bb ldr r3, [r7, #24] 80089ba: 015a lsls r2, r3, #5 80089bc: 69fb ldr r3, [r7, #28] 80089be: 4413 add r3, r2 80089c0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80089c4: 691b ldr r3, [r3, #16] 80089c6: 69ba ldr r2, [r7, #24] 80089c8: 0151 lsls r1, r2, #5 80089ca: 69fa ldr r2, [r7, #28] 80089cc: 440a add r2, r1 80089ce: f502 6230 add.w r2, r2, #2816 @ 0xb00 80089d2: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 80089d6: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 80089da: 6113 str r3, [r2, #16] if (epnum == 0U) 80089dc: 69bb ldr r3, [r7, #24] 80089de: 2b00 cmp r3, #0 80089e0: d132 bne.n 8008a48 { if (ep->xfer_len > 0U) 80089e2: 68bb ldr r3, [r7, #8] 80089e4: 691b ldr r3, [r3, #16] 80089e6: 2b00 cmp r3, #0 80089e8: d003 beq.n 80089f2 { ep->xfer_len = ep->maxpacket; 80089ea: 68bb ldr r3, [r7, #8] 80089ec: 689a ldr r2, [r3, #8] 80089ee: 68bb ldr r3, [r7, #8] 80089f0: 611a str r2, [r3, #16] } /* Store transfer size, for EP0 this is equal to endpoint max packet size */ ep->xfer_size = ep->maxpacket; 80089f2: 68bb ldr r3, [r7, #8] 80089f4: 689a ldr r2, [r3, #8] 80089f6: 68bb ldr r3, [r7, #8] 80089f8: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); 80089fa: 69bb ldr r3, [r7, #24] 80089fc: 015a lsls r2, r3, #5 80089fe: 69fb ldr r3, [r7, #28] 8008a00: 4413 add r3, r2 8008a02: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a06: 691a ldr r2, [r3, #16] 8008a08: 68bb ldr r3, [r7, #8] 8008a0a: 6a1b ldr r3, [r3, #32] 8008a0c: f3c3 0312 ubfx r3, r3, #0, #19 8008a10: 69b9 ldr r1, [r7, #24] 8008a12: 0148 lsls r0, r1, #5 8008a14: 69f9 ldr r1, [r7, #28] 8008a16: 4401 add r1, r0 8008a18: f501 6130 add.w r1, r1, #2816 @ 0xb00 8008a1c: 4313 orrs r3, r2 8008a1e: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8008a20: 69bb ldr r3, [r7, #24] 8008a22: 015a lsls r2, r3, #5 8008a24: 69fb ldr r3, [r7, #28] 8008a26: 4413 add r3, r2 8008a28: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a2c: 691b ldr r3, [r3, #16] 8008a2e: 69ba ldr r2, [r7, #24] 8008a30: 0151 lsls r1, r2, #5 8008a32: 69fa ldr r2, [r7, #28] 8008a34: 440a add r2, r1 8008a36: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008a3a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008a3e: 6113 str r3, [r2, #16] 8008a40: e062 b.n 8008b08 8008a42: bf00 nop 8008a44: 1ff80000 .word 0x1ff80000 } else { if (ep->xfer_len == 0U) 8008a48: 68bb ldr r3, [r7, #8] 8008a4a: 691b ldr r3, [r3, #16] 8008a4c: 2b00 cmp r3, #0 8008a4e: d123 bne.n 8008a98 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8008a50: 69bb ldr r3, [r7, #24] 8008a52: 015a lsls r2, r3, #5 8008a54: 69fb ldr r3, [r7, #28] 8008a56: 4413 add r3, r2 8008a58: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a5c: 691a ldr r2, [r3, #16] 8008a5e: 68bb ldr r3, [r7, #8] 8008a60: 689b ldr r3, [r3, #8] 8008a62: f3c3 0312 ubfx r3, r3, #0, #19 8008a66: 69b9 ldr r1, [r7, #24] 8008a68: 0148 lsls r0, r1, #5 8008a6a: 69f9 ldr r1, [r7, #28] 8008a6c: 4401 add r1, r0 8008a6e: f501 6130 add.w r1, r1, #2816 @ 0xb00 8008a72: 4313 orrs r3, r2 8008a74: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8008a76: 69bb ldr r3, [r7, #24] 8008a78: 015a lsls r2, r3, #5 8008a7a: 69fb ldr r3, [r7, #28] 8008a7c: 4413 add r3, r2 8008a7e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a82: 691b ldr r3, [r3, #16] 8008a84: 69ba ldr r2, [r7, #24] 8008a86: 0151 lsls r1, r2, #5 8008a88: 69fa ldr r2, [r7, #28] 8008a8a: 440a add r2, r1 8008a8c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008a90: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008a94: 6113 str r3, [r2, #16] 8008a96: e037 b.n 8008b08 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8008a98: 68bb ldr r3, [r7, #8] 8008a9a: 691a ldr r2, [r3, #16] 8008a9c: 68bb ldr r3, [r7, #8] 8008a9e: 689b ldr r3, [r3, #8] 8008aa0: 4413 add r3, r2 8008aa2: 1e5a subs r2, r3, #1 8008aa4: 68bb ldr r3, [r7, #8] 8008aa6: 689b ldr r3, [r3, #8] 8008aa8: fbb2 f3f3 udiv r3, r2, r3 8008aac: 82fb strh r3, [r7, #22] ep->xfer_size = ep->maxpacket * pktcnt; 8008aae: 68bb ldr r3, [r7, #8] 8008ab0: 689b ldr r3, [r3, #8] 8008ab2: 8afa ldrh r2, [r7, #22] 8008ab4: fb03 f202 mul.w r2, r3, r2 8008ab8: 68bb ldr r3, [r7, #8] 8008aba: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8008abc: 69bb ldr r3, [r7, #24] 8008abe: 015a lsls r2, r3, #5 8008ac0: 69fb ldr r3, [r7, #28] 8008ac2: 4413 add r3, r2 8008ac4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008ac8: 691a ldr r2, [r3, #16] 8008aca: 8afb ldrh r3, [r7, #22] 8008acc: 04d9 lsls r1, r3, #19 8008ace: 4b38 ldr r3, [pc, #224] @ (8008bb0 ) 8008ad0: 400b ands r3, r1 8008ad2: 69b9 ldr r1, [r7, #24] 8008ad4: 0148 lsls r0, r1, #5 8008ad6: 69f9 ldr r1, [r7, #28] 8008ad8: 4401 add r1, r0 8008ada: f501 6130 add.w r1, r1, #2816 @ 0xb00 8008ade: 4313 orrs r3, r2 8008ae0: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; 8008ae2: 69bb ldr r3, [r7, #24] 8008ae4: 015a lsls r2, r3, #5 8008ae6: 69fb ldr r3, [r7, #28] 8008ae8: 4413 add r3, r2 8008aea: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008aee: 691a ldr r2, [r3, #16] 8008af0: 68bb ldr r3, [r7, #8] 8008af2: 6a1b ldr r3, [r3, #32] 8008af4: f3c3 0312 ubfx r3, r3, #0, #19 8008af8: 69b9 ldr r1, [r7, #24] 8008afa: 0148 lsls r0, r1, #5 8008afc: 69f9 ldr r1, [r7, #28] 8008afe: 4401 add r1, r0 8008b00: f501 6130 add.w r1, r1, #2816 @ 0xb00 8008b04: 4313 orrs r3, r2 8008b06: 610b str r3, [r1, #16] } } if (dma == 1U) 8008b08: 79fb ldrb r3, [r7, #7] 8008b0a: 2b01 cmp r3, #1 8008b0c: d10d bne.n 8008b2a { if ((uint32_t)ep->xfer_buff != 0U) 8008b0e: 68bb ldr r3, [r7, #8] 8008b10: 68db ldr r3, [r3, #12] 8008b12: 2b00 cmp r3, #0 8008b14: d009 beq.n 8008b2a { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8008b16: 68bb ldr r3, [r7, #8] 8008b18: 68d9 ldr r1, [r3, #12] 8008b1a: 69bb ldr r3, [r7, #24] 8008b1c: 015a lsls r2, r3, #5 8008b1e: 69fb ldr r3, [r7, #28] 8008b20: 4413 add r3, r2 8008b22: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008b26: 460a mov r2, r1 8008b28: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8008b2a: 68bb ldr r3, [r7, #8] 8008b2c: 791b ldrb r3, [r3, #4] 8008b2e: 2b01 cmp r3, #1 8008b30: d128 bne.n 8008b84 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8008b32: 69fb ldr r3, [r7, #28] 8008b34: f503 6300 add.w r3, r3, #2048 @ 0x800 8008b38: 689b ldr r3, [r3, #8] 8008b3a: f403 7380 and.w r3, r3, #256 @ 0x100 8008b3e: 2b00 cmp r3, #0 8008b40: d110 bne.n 8008b64 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 8008b42: 69bb ldr r3, [r7, #24] 8008b44: 015a lsls r2, r3, #5 8008b46: 69fb ldr r3, [r7, #28] 8008b48: 4413 add r3, r2 8008b4a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008b4e: 681b ldr r3, [r3, #0] 8008b50: 69ba ldr r2, [r7, #24] 8008b52: 0151 lsls r1, r2, #5 8008b54: 69fa ldr r2, [r7, #28] 8008b56: 440a add r2, r1 8008b58: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008b5c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8008b60: 6013 str r3, [r2, #0] 8008b62: e00f b.n 8008b84 } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8008b64: 69bb ldr r3, [r7, #24] 8008b66: 015a lsls r2, r3, #5 8008b68: 69fb ldr r3, [r7, #28] 8008b6a: 4413 add r3, r2 8008b6c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008b70: 681b ldr r3, [r3, #0] 8008b72: 69ba ldr r2, [r7, #24] 8008b74: 0151 lsls r1, r2, #5 8008b76: 69fa ldr r2, [r7, #28] 8008b78: 440a add r2, r1 8008b7a: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008b7e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008b82: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8008b84: 69bb ldr r3, [r7, #24] 8008b86: 015a lsls r2, r3, #5 8008b88: 69fb ldr r3, [r7, #28] 8008b8a: 4413 add r3, r2 8008b8c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008b90: 681b ldr r3, [r3, #0] 8008b92: 69ba ldr r2, [r7, #24] 8008b94: 0151 lsls r1, r2, #5 8008b96: 69fa ldr r2, [r7, #28] 8008b98: 440a add r2, r1 8008b9a: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008b9e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8008ba2: 6013 str r3, [r2, #0] } return HAL_OK; 8008ba4: 2300 movs r3, #0 } 8008ba6: 4618 mov r0, r3 8008ba8: 3720 adds r7, #32 8008baa: 46bd mov sp, r7 8008bac: bd80 pop {r7, pc} 8008bae: bf00 nop 8008bb0: 1ff80000 .word 0x1ff80000 08008bb4 : * @param USBx usb device instance * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8008bb4: b480 push {r7} 8008bb6: b087 sub sp, #28 8008bb8: af00 add r7, sp, #0 8008bba: 6078 str r0, [r7, #4] 8008bbc: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8008bbe: 2300 movs r3, #0 8008bc0: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; 8008bc2: 2300 movs r3, #0 8008bc4: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8008bc6: 687b ldr r3, [r7, #4] 8008bc8: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8008bca: 683b ldr r3, [r7, #0] 8008bcc: 785b ldrb r3, [r3, #1] 8008bce: 2b01 cmp r3, #1 8008bd0: d14a bne.n 8008c68 { /* EP enable, IN data in FIFO */ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8008bd2: 683b ldr r3, [r7, #0] 8008bd4: 781b ldrb r3, [r3, #0] 8008bd6: 015a lsls r2, r3, #5 8008bd8: 693b ldr r3, [r7, #16] 8008bda: 4413 add r3, r2 8008bdc: f503 6310 add.w r3, r3, #2304 @ 0x900 8008be0: 681b ldr r3, [r3, #0] 8008be2: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008be6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008bea: f040 8086 bne.w 8008cfa { USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); 8008bee: 683b ldr r3, [r7, #0] 8008bf0: 781b ldrb r3, [r3, #0] 8008bf2: 015a lsls r2, r3, #5 8008bf4: 693b ldr r3, [r7, #16] 8008bf6: 4413 add r3, r2 8008bf8: f503 6310 add.w r3, r3, #2304 @ 0x900 8008bfc: 681b ldr r3, [r3, #0] 8008bfe: 683a ldr r2, [r7, #0] 8008c00: 7812 ldrb r2, [r2, #0] 8008c02: 0151 lsls r1, r2, #5 8008c04: 693a ldr r2, [r7, #16] 8008c06: 440a add r2, r1 8008c08: f502 6210 add.w r2, r2, #2304 @ 0x900 8008c0c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8008c10: 6013 str r3, [r2, #0] USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); 8008c12: 683b ldr r3, [r7, #0] 8008c14: 781b ldrb r3, [r3, #0] 8008c16: 015a lsls r2, r3, #5 8008c18: 693b ldr r3, [r7, #16] 8008c1a: 4413 add r3, r2 8008c1c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008c20: 681b ldr r3, [r3, #0] 8008c22: 683a ldr r2, [r7, #0] 8008c24: 7812 ldrb r2, [r2, #0] 8008c26: 0151 lsls r1, r2, #5 8008c28: 693a ldr r2, [r7, #16] 8008c2a: 440a add r2, r1 8008c2c: f502 6210 add.w r2, r2, #2304 @ 0x900 8008c30: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8008c34: 6013 str r3, [r2, #0] do { count++; 8008c36: 68fb ldr r3, [r7, #12] 8008c38: 3301 adds r3, #1 8008c3a: 60fb str r3, [r7, #12] if (count > 10000U) 8008c3c: 68fb ldr r3, [r7, #12] 8008c3e: f242 7210 movw r2, #10000 @ 0x2710 8008c42: 4293 cmp r3, r2 8008c44: d902 bls.n 8008c4c { ret = HAL_ERROR; 8008c46: 2301 movs r3, #1 8008c48: 75fb strb r3, [r7, #23] break; 8008c4a: e056 b.n 8008cfa } } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); 8008c4c: 683b ldr r3, [r7, #0] 8008c4e: 781b ldrb r3, [r3, #0] 8008c50: 015a lsls r2, r3, #5 8008c52: 693b ldr r3, [r7, #16] 8008c54: 4413 add r3, r2 8008c56: f503 6310 add.w r3, r3, #2304 @ 0x900 8008c5a: 681b ldr r3, [r3, #0] 8008c5c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008c60: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008c64: d0e7 beq.n 8008c36 8008c66: e048 b.n 8008cfa } } else /* OUT endpoint */ { if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8008c68: 683b ldr r3, [r7, #0] 8008c6a: 781b ldrb r3, [r3, #0] 8008c6c: 015a lsls r2, r3, #5 8008c6e: 693b ldr r3, [r7, #16] 8008c70: 4413 add r3, r2 8008c72: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008c76: 681b ldr r3, [r3, #0] 8008c78: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008c7c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008c80: d13b bne.n 8008cfa { USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); 8008c82: 683b ldr r3, [r7, #0] 8008c84: 781b ldrb r3, [r3, #0] 8008c86: 015a lsls r2, r3, #5 8008c88: 693b ldr r3, [r7, #16] 8008c8a: 4413 add r3, r2 8008c8c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008c90: 681b ldr r3, [r3, #0] 8008c92: 683a ldr r2, [r7, #0] 8008c94: 7812 ldrb r2, [r2, #0] 8008c96: 0151 lsls r1, r2, #5 8008c98: 693a ldr r2, [r7, #16] 8008c9a: 440a add r2, r1 8008c9c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008ca0: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8008ca4: 6013 str r3, [r2, #0] USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); 8008ca6: 683b ldr r3, [r7, #0] 8008ca8: 781b ldrb r3, [r3, #0] 8008caa: 015a lsls r2, r3, #5 8008cac: 693b ldr r3, [r7, #16] 8008cae: 4413 add r3, r2 8008cb0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008cb4: 681b ldr r3, [r3, #0] 8008cb6: 683a ldr r2, [r7, #0] 8008cb8: 7812 ldrb r2, [r2, #0] 8008cba: 0151 lsls r1, r2, #5 8008cbc: 693a ldr r2, [r7, #16] 8008cbe: 440a add r2, r1 8008cc0: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008cc4: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8008cc8: 6013 str r3, [r2, #0] do { count++; 8008cca: 68fb ldr r3, [r7, #12] 8008ccc: 3301 adds r3, #1 8008cce: 60fb str r3, [r7, #12] if (count > 10000U) 8008cd0: 68fb ldr r3, [r7, #12] 8008cd2: f242 7210 movw r2, #10000 @ 0x2710 8008cd6: 4293 cmp r3, r2 8008cd8: d902 bls.n 8008ce0 { ret = HAL_ERROR; 8008cda: 2301 movs r3, #1 8008cdc: 75fb strb r3, [r7, #23] break; 8008cde: e00c b.n 8008cfa } } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); 8008ce0: 683b ldr r3, [r7, #0] 8008ce2: 781b ldrb r3, [r3, #0] 8008ce4: 015a lsls r2, r3, #5 8008ce6: 693b ldr r3, [r7, #16] 8008ce8: 4413 add r3, r2 8008cea: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008cee: 681b ldr r3, [r3, #0] 8008cf0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008cf4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008cf8: d0e7 beq.n 8008cca } } return ret; 8008cfa: 7dfb ldrb r3, [r7, #23] } 8008cfc: 4618 mov r0, r3 8008cfe: 371c adds r7, #28 8008d00: 46bd mov sp, r7 8008d02: f85d 7b04 ldr.w r7, [sp], #4 8008d06: 4770 bx lr 08008d08 : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 8008d08: b480 push {r7} 8008d0a: b089 sub sp, #36 @ 0x24 8008d0c: af00 add r7, sp, #0 8008d0e: 60f8 str r0, [r7, #12] 8008d10: 60b9 str r1, [r7, #8] 8008d12: 4611 mov r1, r2 8008d14: 461a mov r2, r3 8008d16: 460b mov r3, r1 8008d18: 71fb strb r3, [r7, #7] 8008d1a: 4613 mov r3, r2 8008d1c: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008d1e: 68fb ldr r3, [r7, #12] 8008d20: 617b str r3, [r7, #20] uint8_t *pSrc = src; 8008d22: 68bb ldr r3, [r7, #8] 8008d24: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 8008d26: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8008d2a: 2b00 cmp r3, #0 8008d2c: d123 bne.n 8008d76 { count32b = ((uint32_t)len + 3U) / 4U; 8008d2e: 88bb ldrh r3, [r7, #4] 8008d30: 3303 adds r3, #3 8008d32: 089b lsrs r3, r3, #2 8008d34: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 8008d36: 2300 movs r3, #0 8008d38: 61bb str r3, [r7, #24] 8008d3a: e018 b.n 8008d6e { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 8008d3c: 79fb ldrb r3, [r7, #7] 8008d3e: 031a lsls r2, r3, #12 8008d40: 697b ldr r3, [r7, #20] 8008d42: 4413 add r3, r2 8008d44: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008d48: 461a mov r2, r3 8008d4a: 69fb ldr r3, [r7, #28] 8008d4c: 681b ldr r3, [r3, #0] 8008d4e: 6013 str r3, [r2, #0] pSrc++; 8008d50: 69fb ldr r3, [r7, #28] 8008d52: 3301 adds r3, #1 8008d54: 61fb str r3, [r7, #28] pSrc++; 8008d56: 69fb ldr r3, [r7, #28] 8008d58: 3301 adds r3, #1 8008d5a: 61fb str r3, [r7, #28] pSrc++; 8008d5c: 69fb ldr r3, [r7, #28] 8008d5e: 3301 adds r3, #1 8008d60: 61fb str r3, [r7, #28] pSrc++; 8008d62: 69fb ldr r3, [r7, #28] 8008d64: 3301 adds r3, #1 8008d66: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8008d68: 69bb ldr r3, [r7, #24] 8008d6a: 3301 adds r3, #1 8008d6c: 61bb str r3, [r7, #24] 8008d6e: 69ba ldr r2, [r7, #24] 8008d70: 693b ldr r3, [r7, #16] 8008d72: 429a cmp r2, r3 8008d74: d3e2 bcc.n 8008d3c } } return HAL_OK; 8008d76: 2300 movs r3, #0 } 8008d78: 4618 mov r0, r3 8008d7a: 3724 adds r7, #36 @ 0x24 8008d7c: 46bd mov sp, r7 8008d7e: f85d 7b04 ldr.w r7, [sp], #4 8008d82: 4770 bx lr 08008d84 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8008d84: b480 push {r7} 8008d86: b08b sub sp, #44 @ 0x2c 8008d88: af00 add r7, sp, #0 8008d8a: 60f8 str r0, [r7, #12] 8008d8c: 60b9 str r1, [r7, #8] 8008d8e: 4613 mov r3, r2 8008d90: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8008d92: 68fb ldr r3, [r7, #12] 8008d94: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8008d96: 68bb ldr r3, [r7, #8] 8008d98: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8008d9a: 88fb ldrh r3, [r7, #6] 8008d9c: 089b lsrs r3, r3, #2 8008d9e: b29b uxth r3, r3 8008da0: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8008da2: 88fb ldrh r3, [r7, #6] 8008da4: f003 0303 and.w r3, r3, #3 8008da8: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8008daa: 2300 movs r3, #0 8008dac: 623b str r3, [r7, #32] 8008dae: e014 b.n 8008dda { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8008db0: 69bb ldr r3, [r7, #24] 8008db2: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008db6: 681a ldr r2, [r3, #0] 8008db8: 6a7b ldr r3, [r7, #36] @ 0x24 8008dba: 601a str r2, [r3, #0] pDest++; 8008dbc: 6a7b ldr r3, [r7, #36] @ 0x24 8008dbe: 3301 adds r3, #1 8008dc0: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008dc2: 6a7b ldr r3, [r7, #36] @ 0x24 8008dc4: 3301 adds r3, #1 8008dc6: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008dc8: 6a7b ldr r3, [r7, #36] @ 0x24 8008dca: 3301 adds r3, #1 8008dcc: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008dce: 6a7b ldr r3, [r7, #36] @ 0x24 8008dd0: 3301 adds r3, #1 8008dd2: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 8008dd4: 6a3b ldr r3, [r7, #32] 8008dd6: 3301 adds r3, #1 8008dd8: 623b str r3, [r7, #32] 8008dda: 6a3a ldr r2, [r7, #32] 8008ddc: 697b ldr r3, [r7, #20] 8008dde: 429a cmp r2, r3 8008de0: d3e6 bcc.n 8008db0 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8008de2: 8bfb ldrh r3, [r7, #30] 8008de4: 2b00 cmp r3, #0 8008de6: d01e beq.n 8008e26 { i = 0U; 8008de8: 2300 movs r3, #0 8008dea: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8008dec: 69bb ldr r3, [r7, #24] 8008dee: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008df2: 461a mov r2, r3 8008df4: f107 0310 add.w r3, r7, #16 8008df8: 6812 ldr r2, [r2, #0] 8008dfa: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 8008dfc: 693a ldr r2, [r7, #16] 8008dfe: 6a3b ldr r3, [r7, #32] 8008e00: b2db uxtb r3, r3 8008e02: 00db lsls r3, r3, #3 8008e04: fa22 f303 lsr.w r3, r2, r3 8008e08: b2da uxtb r2, r3 8008e0a: 6a7b ldr r3, [r7, #36] @ 0x24 8008e0c: 701a strb r2, [r3, #0] i++; 8008e0e: 6a3b ldr r3, [r7, #32] 8008e10: 3301 adds r3, #1 8008e12: 623b str r3, [r7, #32] pDest++; 8008e14: 6a7b ldr r3, [r7, #36] @ 0x24 8008e16: 3301 adds r3, #1 8008e18: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 8008e1a: 8bfb ldrh r3, [r7, #30] 8008e1c: 3b01 subs r3, #1 8008e1e: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 8008e20: 8bfb ldrh r3, [r7, #30] 8008e22: 2b00 cmp r3, #0 8008e24: d1ea bne.n 8008dfc } return ((void *)pDest); 8008e26: 6a7b ldr r3, [r7, #36] @ 0x24 } 8008e28: 4618 mov r0, r3 8008e2a: 372c adds r7, #44 @ 0x2c 8008e2c: 46bd mov sp, r7 8008e2e: f85d 7b04 ldr.w r7, [sp], #4 8008e32: 4770 bx lr 08008e34 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008e34: b480 push {r7} 8008e36: b085 sub sp, #20 8008e38: af00 add r7, sp, #0 8008e3a: 6078 str r0, [r7, #4] 8008e3c: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8008e3e: 687b ldr r3, [r7, #4] 8008e40: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008e42: 683b ldr r3, [r7, #0] 8008e44: 781b ldrb r3, [r3, #0] 8008e46: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8008e48: 683b ldr r3, [r7, #0] 8008e4a: 785b ldrb r3, [r3, #1] 8008e4c: 2b01 cmp r3, #1 8008e4e: d12c bne.n 8008eaa { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 8008e50: 68bb ldr r3, [r7, #8] 8008e52: 015a lsls r2, r3, #5 8008e54: 68fb ldr r3, [r7, #12] 8008e56: 4413 add r3, r2 8008e58: f503 6310 add.w r3, r3, #2304 @ 0x900 8008e5c: 681b ldr r3, [r3, #0] 8008e5e: 2b00 cmp r3, #0 8008e60: db12 blt.n 8008e88 8008e62: 68bb ldr r3, [r7, #8] 8008e64: 2b00 cmp r3, #0 8008e66: d00f beq.n 8008e88 { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8008e68: 68bb ldr r3, [r7, #8] 8008e6a: 015a lsls r2, r3, #5 8008e6c: 68fb ldr r3, [r7, #12] 8008e6e: 4413 add r3, r2 8008e70: f503 6310 add.w r3, r3, #2304 @ 0x900 8008e74: 681b ldr r3, [r3, #0] 8008e76: 68ba ldr r2, [r7, #8] 8008e78: 0151 lsls r1, r2, #5 8008e7a: 68fa ldr r2, [r7, #12] 8008e7c: 440a add r2, r1 8008e7e: f502 6210 add.w r2, r2, #2304 @ 0x900 8008e82: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008e86: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8008e88: 68bb ldr r3, [r7, #8] 8008e8a: 015a lsls r2, r3, #5 8008e8c: 68fb ldr r3, [r7, #12] 8008e8e: 4413 add r3, r2 8008e90: f503 6310 add.w r3, r3, #2304 @ 0x900 8008e94: 681b ldr r3, [r3, #0] 8008e96: 68ba ldr r2, [r7, #8] 8008e98: 0151 lsls r1, r2, #5 8008e9a: 68fa ldr r2, [r7, #12] 8008e9c: 440a add r2, r1 8008e9e: f502 6210 add.w r2, r2, #2304 @ 0x900 8008ea2: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008ea6: 6013 str r3, [r2, #0] 8008ea8: e02b b.n 8008f02 } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 8008eaa: 68bb ldr r3, [r7, #8] 8008eac: 015a lsls r2, r3, #5 8008eae: 68fb ldr r3, [r7, #12] 8008eb0: 4413 add r3, r2 8008eb2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008eb6: 681b ldr r3, [r3, #0] 8008eb8: 2b00 cmp r3, #0 8008eba: db12 blt.n 8008ee2 8008ebc: 68bb ldr r3, [r7, #8] 8008ebe: 2b00 cmp r3, #0 8008ec0: d00f beq.n 8008ee2 { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 8008ec2: 68bb ldr r3, [r7, #8] 8008ec4: 015a lsls r2, r3, #5 8008ec6: 68fb ldr r3, [r7, #12] 8008ec8: 4413 add r3, r2 8008eca: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008ece: 681b ldr r3, [r3, #0] 8008ed0: 68ba ldr r2, [r7, #8] 8008ed2: 0151 lsls r1, r2, #5 8008ed4: 68fa ldr r2, [r7, #12] 8008ed6: 440a add r2, r1 8008ed8: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008edc: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008ee0: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 8008ee2: 68bb ldr r3, [r7, #8] 8008ee4: 015a lsls r2, r3, #5 8008ee6: 68fb ldr r3, [r7, #12] 8008ee8: 4413 add r3, r2 8008eea: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008eee: 681b ldr r3, [r3, #0] 8008ef0: 68ba ldr r2, [r7, #8] 8008ef2: 0151 lsls r1, r2, #5 8008ef4: 68fa ldr r2, [r7, #12] 8008ef6: 440a add r2, r1 8008ef8: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008efc: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008f00: 6013 str r3, [r2, #0] } return HAL_OK; 8008f02: 2300 movs r3, #0 } 8008f04: 4618 mov r0, r3 8008f06: 3714 adds r7, #20 8008f08: 46bd mov sp, r7 8008f0a: f85d 7b04 ldr.w r7, [sp], #4 8008f0e: 4770 bx lr 08008f10 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008f10: b480 push {r7} 8008f12: b085 sub sp, #20 8008f14: af00 add r7, sp, #0 8008f16: 6078 str r0, [r7, #4] 8008f18: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8008f1a: 687b ldr r3, [r7, #4] 8008f1c: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008f1e: 683b ldr r3, [r7, #0] 8008f20: 781b ldrb r3, [r3, #0] 8008f22: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8008f24: 683b ldr r3, [r7, #0] 8008f26: 785b ldrb r3, [r3, #1] 8008f28: 2b01 cmp r3, #1 8008f2a: d128 bne.n 8008f7e { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8008f2c: 68bb ldr r3, [r7, #8] 8008f2e: 015a lsls r2, r3, #5 8008f30: 68fb ldr r3, [r7, #12] 8008f32: 4413 add r3, r2 8008f34: f503 6310 add.w r3, r3, #2304 @ 0x900 8008f38: 681b ldr r3, [r3, #0] 8008f3a: 68ba ldr r2, [r7, #8] 8008f3c: 0151 lsls r1, r2, #5 8008f3e: 68fa ldr r2, [r7, #12] 8008f40: 440a add r2, r1 8008f42: f502 6210 add.w r2, r2, #2304 @ 0x900 8008f46: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8008f4a: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8008f4c: 683b ldr r3, [r7, #0] 8008f4e: 791b ldrb r3, [r3, #4] 8008f50: 2b03 cmp r3, #3 8008f52: d003 beq.n 8008f5c 8008f54: 683b ldr r3, [r7, #0] 8008f56: 791b ldrb r3, [r3, #4] 8008f58: 2b02 cmp r3, #2 8008f5a: d138 bne.n 8008fce { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008f5c: 68bb ldr r3, [r7, #8] 8008f5e: 015a lsls r2, r3, #5 8008f60: 68fb ldr r3, [r7, #12] 8008f62: 4413 add r3, r2 8008f64: f503 6310 add.w r3, r3, #2304 @ 0x900 8008f68: 681b ldr r3, [r3, #0] 8008f6a: 68ba ldr r2, [r7, #8] 8008f6c: 0151 lsls r1, r2, #5 8008f6e: 68fa ldr r2, [r7, #12] 8008f70: 440a add r2, r1 8008f72: f502 6210 add.w r2, r2, #2304 @ 0x900 8008f76: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008f7a: 6013 str r3, [r2, #0] 8008f7c: e027 b.n 8008fce } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8008f7e: 68bb ldr r3, [r7, #8] 8008f80: 015a lsls r2, r3, #5 8008f82: 68fb ldr r3, [r7, #12] 8008f84: 4413 add r3, r2 8008f86: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008f8a: 681b ldr r3, [r3, #0] 8008f8c: 68ba ldr r2, [r7, #8] 8008f8e: 0151 lsls r1, r2, #5 8008f90: 68fa ldr r2, [r7, #12] 8008f92: 440a add r2, r1 8008f94: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008f98: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8008f9c: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8008f9e: 683b ldr r3, [r7, #0] 8008fa0: 791b ldrb r3, [r3, #4] 8008fa2: 2b03 cmp r3, #3 8008fa4: d003 beq.n 8008fae 8008fa6: 683b ldr r3, [r7, #0] 8008fa8: 791b ldrb r3, [r3, #4] 8008faa: 2b02 cmp r3, #2 8008fac: d10f bne.n 8008fce { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008fae: 68bb ldr r3, [r7, #8] 8008fb0: 015a lsls r2, r3, #5 8008fb2: 68fb ldr r3, [r7, #12] 8008fb4: 4413 add r3, r2 8008fb6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008fba: 681b ldr r3, [r3, #0] 8008fbc: 68ba ldr r2, [r7, #8] 8008fbe: 0151 lsls r1, r2, #5 8008fc0: 68fa ldr r2, [r7, #12] 8008fc2: 440a add r2, r1 8008fc4: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008fc8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008fcc: 6013 str r3, [r2, #0] } } return HAL_OK; 8008fce: 2300 movs r3, #0 } 8008fd0: 4618 mov r0, r3 8008fd2: 3714 adds r7, #20 8008fd4: 46bd mov sp, r7 8008fd6: f85d 7b04 ldr.w r7, [sp], #4 8008fda: 4770 bx lr 08008fdc : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 8008fdc: b480 push {r7} 8008fde: b085 sub sp, #20 8008fe0: af00 add r7, sp, #0 8008fe2: 6078 str r0, [r7, #4] 8008fe4: 460b mov r3, r1 8008fe6: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008fe8: 687b ldr r3, [r7, #4] 8008fea: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 8008fec: 68fb ldr r3, [r7, #12] 8008fee: f503 6300 add.w r3, r3, #2048 @ 0x800 8008ff2: 681b ldr r3, [r3, #0] 8008ff4: 68fa ldr r2, [r7, #12] 8008ff6: f502 6200 add.w r2, r2, #2048 @ 0x800 8008ffa: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8008ffe: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 8009000: 68fb ldr r3, [r7, #12] 8009002: f503 6300 add.w r3, r3, #2048 @ 0x800 8009006: 681a ldr r2, [r3, #0] 8009008: 78fb ldrb r3, [r7, #3] 800900a: 011b lsls r3, r3, #4 800900c: f403 63fe and.w r3, r3, #2032 @ 0x7f0 8009010: 68f9 ldr r1, [r7, #12] 8009012: f501 6100 add.w r1, r1, #2048 @ 0x800 8009016: 4313 orrs r3, r2 8009018: 600b str r3, [r1, #0] return HAL_OK; 800901a: 2300 movs r3, #0 } 800901c: 4618 mov r0, r3 800901e: 3714 adds r7, #20 8009020: 46bd mov sp, r7 8009022: f85d 7b04 ldr.w r7, [sp], #4 8009026: 4770 bx lr 08009028 : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { 8009028: b480 push {r7} 800902a: b085 sub sp, #20 800902c: af00 add r7, sp, #0 800902e: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8009030: 687b ldr r3, [r7, #4] 8009032: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8009034: 68fb ldr r3, [r7, #12] 8009036: f503 6360 add.w r3, r3, #3584 @ 0xe00 800903a: 681b ldr r3, [r3, #0] 800903c: 68fa ldr r2, [r7, #12] 800903e: f502 6260 add.w r2, r2, #3584 @ 0xe00 8009042: f023 0303 bic.w r3, r3, #3 8009046: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 8009048: 68fb ldr r3, [r7, #12] 800904a: f503 6300 add.w r3, r3, #2048 @ 0x800 800904e: 685b ldr r3, [r3, #4] 8009050: 68fa ldr r2, [r7, #12] 8009052: f502 6200 add.w r2, r2, #2048 @ 0x800 8009056: f023 0302 bic.w r3, r3, #2 800905a: 6053 str r3, [r2, #4] return HAL_OK; 800905c: 2300 movs r3, #0 } 800905e: 4618 mov r0, r3 8009060: 3714 adds r7, #20 8009062: 46bd mov sp, r7 8009064: f85d 7b04 ldr.w r7, [sp], #4 8009068: 4770 bx lr 0800906a : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 800906a: b480 push {r7} 800906c: b085 sub sp, #20 800906e: af00 add r7, sp, #0 8009070: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8009072: 687b ldr r3, [r7, #4] 8009074: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8009076: 68fb ldr r3, [r7, #12] 8009078: f503 6360 add.w r3, r3, #3584 @ 0xe00 800907c: 681b ldr r3, [r3, #0] 800907e: 68fa ldr r2, [r7, #12] 8009080: f502 6260 add.w r2, r2, #3584 @ 0xe00 8009084: f023 0303 bic.w r3, r3, #3 8009088: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 800908a: 68fb ldr r3, [r7, #12] 800908c: f503 6300 add.w r3, r3, #2048 @ 0x800 8009090: 685b ldr r3, [r3, #4] 8009092: 68fa ldr r2, [r7, #12] 8009094: f502 6200 add.w r2, r2, #2048 @ 0x800 8009098: f043 0302 orr.w r3, r3, #2 800909c: 6053 str r3, [r2, #4] return HAL_OK; 800909e: 2300 movs r3, #0 } 80090a0: 4618 mov r0, r3 80090a2: 3714 adds r7, #20 80090a4: 46bd mov sp, r7 80090a6: f85d 7b04 ldr.w r7, [sp], #4 80090aa: 4770 bx lr 080090ac : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 80090ac: b480 push {r7} 80090ae: b085 sub sp, #20 80090b0: af00 add r7, sp, #0 80090b2: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 80090b4: 687b ldr r3, [r7, #4] 80090b6: 695b ldr r3, [r3, #20] 80090b8: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 80090ba: 687b ldr r3, [r7, #4] 80090bc: 699b ldr r3, [r3, #24] 80090be: 68fa ldr r2, [r7, #12] 80090c0: 4013 ands r3, r2 80090c2: 60fb str r3, [r7, #12] return tmpreg; 80090c4: 68fb ldr r3, [r7, #12] } 80090c6: 4618 mov r0, r3 80090c8: 3714 adds r7, #20 80090ca: 46bd mov sp, r7 80090cc: f85d 7b04 ldr.w r7, [sp], #4 80090d0: 4770 bx lr 080090d2 : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 80090d2: b480 push {r7} 80090d4: b085 sub sp, #20 80090d6: af00 add r7, sp, #0 80090d8: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80090da: 687b ldr r3, [r7, #4] 80090dc: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 80090de: 68fb ldr r3, [r7, #12] 80090e0: f503 6300 add.w r3, r3, #2048 @ 0x800 80090e4: 699b ldr r3, [r3, #24] 80090e6: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 80090e8: 68fb ldr r3, [r7, #12] 80090ea: f503 6300 add.w r3, r3, #2048 @ 0x800 80090ee: 69db ldr r3, [r3, #28] 80090f0: 68ba ldr r2, [r7, #8] 80090f2: 4013 ands r3, r2 80090f4: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 80090f6: 68bb ldr r3, [r7, #8] 80090f8: 0c1b lsrs r3, r3, #16 } 80090fa: 4618 mov r0, r3 80090fc: 3714 adds r7, #20 80090fe: 46bd mov sp, r7 8009100: f85d 7b04 ldr.w r7, [sp], #4 8009104: 4770 bx lr 08009106 : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 8009106: b480 push {r7} 8009108: b085 sub sp, #20 800910a: af00 add r7, sp, #0 800910c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800910e: 687b ldr r3, [r7, #4] 8009110: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8009112: 68fb ldr r3, [r7, #12] 8009114: f503 6300 add.w r3, r3, #2048 @ 0x800 8009118: 699b ldr r3, [r3, #24] 800911a: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 800911c: 68fb ldr r3, [r7, #12] 800911e: f503 6300 add.w r3, r3, #2048 @ 0x800 8009122: 69db ldr r3, [r3, #28] 8009124: 68ba ldr r2, [r7, #8] 8009126: 4013 ands r3, r2 8009128: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 800912a: 68bb ldr r3, [r7, #8] 800912c: b29b uxth r3, r3 } 800912e: 4618 mov r0, r3 8009130: 3714 adds r7, #20 8009132: 46bd mov sp, r7 8009134: f85d 7b04 ldr.w r7, [sp], #4 8009138: 4770 bx lr 0800913a : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 800913a: b480 push {r7} 800913c: b085 sub sp, #20 800913e: af00 add r7, sp, #0 8009140: 6078 str r0, [r7, #4] 8009142: 460b mov r3, r1 8009144: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8009146: 687b ldr r3, [r7, #4] 8009148: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 800914a: 78fb ldrb r3, [r7, #3] 800914c: 015a lsls r2, r3, #5 800914e: 68fb ldr r3, [r7, #12] 8009150: 4413 add r3, r2 8009152: f503 6330 add.w r3, r3, #2816 @ 0xb00 8009156: 689b ldr r3, [r3, #8] 8009158: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 800915a: 68fb ldr r3, [r7, #12] 800915c: f503 6300 add.w r3, r3, #2048 @ 0x800 8009160: 695b ldr r3, [r3, #20] 8009162: 68ba ldr r2, [r7, #8] 8009164: 4013 ands r3, r2 8009166: 60bb str r3, [r7, #8] return tmpreg; 8009168: 68bb ldr r3, [r7, #8] } 800916a: 4618 mov r0, r3 800916c: 3714 adds r7, #20 800916e: 46bd mov sp, r7 8009170: f85d 7b04 ldr.w r7, [sp], #4 8009174: 4770 bx lr 08009176 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8009176: b480 push {r7} 8009178: b087 sub sp, #28 800917a: af00 add r7, sp, #0 800917c: 6078 str r0, [r7, #4] 800917e: 460b mov r3, r1 8009180: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8009182: 687b ldr r3, [r7, #4] 8009184: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 8009186: 697b ldr r3, [r7, #20] 8009188: f503 6300 add.w r3, r3, #2048 @ 0x800 800918c: 691b ldr r3, [r3, #16] 800918e: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 8009190: 697b ldr r3, [r7, #20] 8009192: f503 6300 add.w r3, r3, #2048 @ 0x800 8009196: 6b5b ldr r3, [r3, #52] @ 0x34 8009198: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 800919a: 78fb ldrb r3, [r7, #3] 800919c: f003 030f and.w r3, r3, #15 80091a0: 68fa ldr r2, [r7, #12] 80091a2: fa22 f303 lsr.w r3, r2, r3 80091a6: 01db lsls r3, r3, #7 80091a8: b2db uxtb r3, r3 80091aa: 693a ldr r2, [r7, #16] 80091ac: 4313 orrs r3, r2 80091ae: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 80091b0: 78fb ldrb r3, [r7, #3] 80091b2: 015a lsls r2, r3, #5 80091b4: 697b ldr r3, [r7, #20] 80091b6: 4413 add r3, r2 80091b8: f503 6310 add.w r3, r3, #2304 @ 0x900 80091bc: 689b ldr r3, [r3, #8] 80091be: 693a ldr r2, [r7, #16] 80091c0: 4013 ands r3, r2 80091c2: 60bb str r3, [r7, #8] return tmpreg; 80091c4: 68bb ldr r3, [r7, #8] } 80091c6: 4618 mov r0, r3 80091c8: 371c adds r7, #28 80091ca: 46bd mov sp, r7 80091cc: f85d 7b04 ldr.w r7, [sp], #4 80091d0: 4770 bx lr 080091d2 : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 80091d2: b480 push {r7} 80091d4: b083 sub sp, #12 80091d6: af00 add r7, sp, #0 80091d8: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 80091da: 687b ldr r3, [r7, #4] 80091dc: 695b ldr r3, [r3, #20] 80091de: f003 0301 and.w r3, r3, #1 } 80091e2: 4618 mov r0, r3 80091e4: 370c adds r7, #12 80091e6: 46bd mov sp, r7 80091e8: f85d 7b04 ldr.w r7, [sp], #4 80091ec: 4770 bx lr 080091ee : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { 80091ee: b480 push {r7} 80091f0: b085 sub sp, #20 80091f2: af00 add r7, sp, #0 80091f4: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80091f6: 687b ldr r3, [r7, #4] 80091f8: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 80091fa: 68fb ldr r3, [r7, #12] 80091fc: f503 6310 add.w r3, r3, #2304 @ 0x900 8009200: 681b ldr r3, [r3, #0] 8009202: 68fa ldr r2, [r7, #12] 8009204: f502 6210 add.w r2, r2, #2304 @ 0x900 8009208: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 800920c: f023 0307 bic.w r3, r3, #7 8009210: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 8009212: 68fb ldr r3, [r7, #12] 8009214: f503 6300 add.w r3, r3, #2048 @ 0x800 8009218: 685b ldr r3, [r3, #4] 800921a: 68fa ldr r2, [r7, #12] 800921c: f502 6200 add.w r2, r2, #2048 @ 0x800 8009220: f443 7380 orr.w r3, r3, #256 @ 0x100 8009224: 6053 str r3, [r2, #4] return HAL_OK; 8009226: 2300 movs r3, #0 } 8009228: 4618 mov r0, r3 800922a: 3714 adds r7, #20 800922c: 46bd mov sp, r7 800922e: f85d 7b04 ldr.w r7, [sp], #4 8009232: 4770 bx lr 08009234 : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { 8009234: b480 push {r7} 8009236: b087 sub sp, #28 8009238: af00 add r7, sp, #0 800923a: 60f8 str r0, [r7, #12] 800923c: 460b mov r3, r1 800923e: 607a str r2, [r7, #4] 8009240: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 8009242: 68fb ldr r3, [r7, #12] 8009244: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8009246: 68fb ldr r3, [r7, #12] 8009248: 333c adds r3, #60 @ 0x3c 800924a: 3304 adds r3, #4 800924c: 681b ldr r3, [r3, #0] 800924e: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 8009250: 693b ldr r3, [r7, #16] 8009252: 4a26 ldr r2, [pc, #152] @ (80092ec ) 8009254: 4293 cmp r3, r2 8009256: d90a bls.n 800926e { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8009258: 697b ldr r3, [r7, #20] 800925a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800925e: 681b ldr r3, [r3, #0] 8009260: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8009264: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8009268: d101 bne.n 800926e { return HAL_OK; 800926a: 2300 movs r3, #0 800926c: e037 b.n 80092de } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 800926e: 697b ldr r3, [r7, #20] 8009270: f503 6330 add.w r3, r3, #2816 @ 0xb00 8009274: 461a mov r2, r3 8009276: 2300 movs r3, #0 8009278: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 800927a: 697b ldr r3, [r7, #20] 800927c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8009280: 691b ldr r3, [r3, #16] 8009282: 697a ldr r2, [r7, #20] 8009284: f502 6230 add.w r2, r2, #2816 @ 0xb00 8009288: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800928c: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 800928e: 697b ldr r3, [r7, #20] 8009290: f503 6330 add.w r3, r3, #2816 @ 0xb00 8009294: 691b ldr r3, [r3, #16] 8009296: 697a ldr r2, [r7, #20] 8009298: f502 6230 add.w r2, r2, #2816 @ 0xb00 800929c: f043 0318 orr.w r3, r3, #24 80092a0: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 80092a2: 697b ldr r3, [r7, #20] 80092a4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80092a8: 691b ldr r3, [r3, #16] 80092aa: 697a ldr r2, [r7, #20] 80092ac: f502 6230 add.w r2, r2, #2816 @ 0xb00 80092b0: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 80092b4: 6113 str r3, [r2, #16] if (dma == 1U) 80092b6: 7afb ldrb r3, [r7, #11] 80092b8: 2b01 cmp r3, #1 80092ba: d10f bne.n 80092dc { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 80092bc: 697b ldr r3, [r7, #20] 80092be: f503 6330 add.w r3, r3, #2816 @ 0xb00 80092c2: 461a mov r2, r3 80092c4: 687b ldr r3, [r7, #4] 80092c6: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 80092c8: 697b ldr r3, [r7, #20] 80092ca: f503 6330 add.w r3, r3, #2816 @ 0xb00 80092ce: 681b ldr r3, [r3, #0] 80092d0: 697a ldr r2, [r7, #20] 80092d2: f502 6230 add.w r2, r2, #2816 @ 0xb00 80092d6: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 80092da: 6013 str r3, [r2, #0] } return HAL_OK; 80092dc: 2300 movs r3, #0 } 80092de: 4618 mov r0, r3 80092e0: 371c adds r7, #28 80092e2: 46bd mov sp, r7 80092e4: f85d 7b04 ldr.w r7, [sp], #4 80092e8: 4770 bx lr 80092ea: bf00 nop 80092ec: 4f54300a .word 0x4f54300a 080092f0 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 80092f0: b480 push {r7} 80092f2: b085 sub sp, #20 80092f4: af00 add r7, sp, #0 80092f6: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80092f8: 2300 movs r3, #0 80092fa: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80092fc: 68fb ldr r3, [r7, #12] 80092fe: 3301 adds r3, #1 8009300: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8009302: 68fb ldr r3, [r7, #12] 8009304: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8009308: d901 bls.n 800930e { return HAL_TIMEOUT; 800930a: 2303 movs r3, #3 800930c: e022 b.n 8009354 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 800930e: 687b ldr r3, [r7, #4] 8009310: 691b ldr r3, [r3, #16] 8009312: 2b00 cmp r3, #0 8009314: daf2 bge.n 80092fc count = 10U; 8009316: 230a movs r3, #10 8009318: 60fb str r3, [r7, #12] /* few cycles before setting core reset */ while (count > 0U) 800931a: e002 b.n 8009322 { count--; 800931c: 68fb ldr r3, [r7, #12] 800931e: 3b01 subs r3, #1 8009320: 60fb str r3, [r7, #12] while (count > 0U) 8009322: 68fb ldr r3, [r7, #12] 8009324: 2b00 cmp r3, #0 8009326: d1f9 bne.n 800931c } /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 8009328: 687b ldr r3, [r7, #4] 800932a: 691b ldr r3, [r3, #16] 800932c: f043 0201 orr.w r2, r3, #1 8009330: 687b ldr r3, [r7, #4] 8009332: 611a str r2, [r3, #16] do { count++; 8009334: 68fb ldr r3, [r7, #12] 8009336: 3301 adds r3, #1 8009338: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800933a: 68fb ldr r3, [r7, #12] 800933c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8009340: d901 bls.n 8009346 { return HAL_TIMEOUT; 8009342: 2303 movs r3, #3 8009344: e006 b.n 8009354 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 8009346: 687b ldr r3, [r7, #4] 8009348: 691b ldr r3, [r3, #16] 800934a: f003 0301 and.w r3, r3, #1 800934e: 2b01 cmp r3, #1 8009350: d0f0 beq.n 8009334 return HAL_OK; 8009352: 2300 movs r3, #0 } 8009354: 4618 mov r0, r3 8009356: 3714 adds r7, #20 8009358: 46bd mov sp, r7 800935a: f85d 7b04 ldr.w r7, [sp], #4 800935e: 4770 bx lr 08009360 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8009360: b580 push {r7, lr} 8009362: b084 sub sp, #16 8009364: af00 add r7, sp, #0 8009366: 6078 str r0, [r7, #4] 8009368: 460b mov r3, r1 800936a: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_HID_HandleTypeDef *hhid; hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); 800936c: 2010 movs r0, #16 800936e: f002 f9e3 bl 800b738 8009372: 60f8 str r0, [r7, #12] if (hhid == NULL) 8009374: 68fb ldr r3, [r7, #12] 8009376: 2b00 cmp r3, #0 8009378: d109 bne.n 800938e { pdev->pClassDataCmsit[pdev->classId] = NULL; 800937a: 687b ldr r3, [r7, #4] 800937c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009380: 687b ldr r3, [r7, #4] 8009382: 32b0 adds r2, #176 @ 0xb0 8009384: 2100 movs r1, #0 8009386: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 800938a: 2302 movs r3, #2 800938c: e048 b.n 8009420 } pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; 800938e: 687b ldr r3, [r7, #4] 8009390: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009394: 687b ldr r3, [r7, #4] 8009396: 32b0 adds r2, #176 @ 0xb0 8009398: 68f9 ldr r1, [r7, #12] 800939a: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 800939e: 687b ldr r3, [r7, #4] 80093a0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80093a4: 687b ldr r3, [r7, #4] 80093a6: 32b0 adds r2, #176 @ 0xb0 80093a8: f853 2022 ldr.w r2, [r3, r2, lsl #2] 80093ac: 687b ldr r3, [r7, #4] 80093ae: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 80093b2: 687b ldr r3, [r7, #4] 80093b4: 7c1b ldrb r3, [r3, #16] 80093b6: 2b00 cmp r3, #0 80093b8: d10d bne.n 80093d6 { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; 80093ba: 4b1b ldr r3, [pc, #108] @ (8009428 ) 80093bc: 781b ldrb r3, [r3, #0] 80093be: f003 020f and.w r2, r3, #15 80093c2: 6879 ldr r1, [r7, #4] 80093c4: 4613 mov r3, r2 80093c6: 009b lsls r3, r3, #2 80093c8: 4413 add r3, r2 80093ca: 009b lsls r3, r3, #2 80093cc: 440b add r3, r1 80093ce: 331c adds r3, #28 80093d0: 2207 movs r2, #7 80093d2: 601a str r2, [r3, #0] 80093d4: e00c b.n 80093f0 } else /* LOW and FULL-speed endpoints */ { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; 80093d6: 4b14 ldr r3, [pc, #80] @ (8009428 ) 80093d8: 781b ldrb r3, [r3, #0] 80093da: f003 020f and.w r2, r3, #15 80093de: 6879 ldr r1, [r7, #4] 80093e0: 4613 mov r3, r2 80093e2: 009b lsls r3, r3, #2 80093e4: 4413 add r3, r2 80093e6: 009b lsls r3, r3, #2 80093e8: 440b add r3, r1 80093ea: 331c adds r3, #28 80093ec: 220a movs r2, #10 80093ee: 601a str r2, [r3, #0] } /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); 80093f0: 4b0d ldr r3, [pc, #52] @ (8009428 ) 80093f2: 7819 ldrb r1, [r3, #0] 80093f4: 230e movs r3, #14 80093f6: 2203 movs r2, #3 80093f8: 6878 ldr r0, [r7, #4] 80093fa: f002 f83e bl 800b47a pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; 80093fe: 4b0a ldr r3, [pc, #40] @ (8009428 ) 8009400: 781b ldrb r3, [r3, #0] 8009402: f003 020f and.w r2, r3, #15 8009406: 6879 ldr r1, [r7, #4] 8009408: 4613 mov r3, r2 800940a: 009b lsls r3, r3, #2 800940c: 4413 add r3, r2 800940e: 009b lsls r3, r3, #2 8009410: 440b add r3, r1 8009412: 3323 adds r3, #35 @ 0x23 8009414: 2201 movs r2, #1 8009416: 701a strb r2, [r3, #0] hhid->state = USBD_HID_IDLE; 8009418: 68fb ldr r3, [r7, #12] 800941a: 2200 movs r2, #0 800941c: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 800941e: 2300 movs r3, #0 } 8009420: 4618 mov r0, r3 8009422: 3710 adds r7, #16 8009424: 46bd mov sp, r7 8009426: bd80 pop {r7, pc} 8009428: 2000013d .word 0x2000013d 0800942c : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800942c: b580 push {r7, lr} 800942e: b082 sub sp, #8 8009430: af00 add r7, sp, #0 8009432: 6078 str r0, [r7, #4] 8009434: 460b mov r3, r1 8009436: 70fb strb r3, [r7, #3] /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close HID EPs */ (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); 8009438: 4b1f ldr r3, [pc, #124] @ (80094b8 ) 800943a: 781b ldrb r3, [r3, #0] 800943c: 4619 mov r1, r3 800943e: 6878 ldr r0, [r7, #4] 8009440: f002 f841 bl 800b4c6 pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; 8009444: 4b1c ldr r3, [pc, #112] @ (80094b8 ) 8009446: 781b ldrb r3, [r3, #0] 8009448: f003 020f and.w r2, r3, #15 800944c: 6879 ldr r1, [r7, #4] 800944e: 4613 mov r3, r2 8009450: 009b lsls r3, r3, #2 8009452: 4413 add r3, r2 8009454: 009b lsls r3, r3, #2 8009456: 440b add r3, r1 8009458: 3323 adds r3, #35 @ 0x23 800945a: 2200 movs r2, #0 800945c: 701a strb r2, [r3, #0] pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; 800945e: 4b16 ldr r3, [pc, #88] @ (80094b8 ) 8009460: 781b ldrb r3, [r3, #0] 8009462: f003 020f and.w r2, r3, #15 8009466: 6879 ldr r1, [r7, #4] 8009468: 4613 mov r3, r2 800946a: 009b lsls r3, r3, #2 800946c: 4413 add r3, r2 800946e: 009b lsls r3, r3, #2 8009470: 440b add r3, r1 8009472: 331c adds r3, #28 8009474: 2200 movs r2, #0 8009476: 601a str r2, [r3, #0] /* Free allocated memory */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 8009478: 687b ldr r3, [r7, #4] 800947a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800947e: 687b ldr r3, [r7, #4] 8009480: 32b0 adds r2, #176 @ 0xb0 8009482: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009486: 2b00 cmp r3, #0 8009488: d011 beq.n 80094ae { (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 800948a: 687b ldr r3, [r7, #4] 800948c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009490: 687b ldr r3, [r7, #4] 8009492: 32b0 adds r2, #176 @ 0xb0 8009494: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009498: 4618 mov r0, r3 800949a: f002 f95b bl 800b754 pdev->pClassDataCmsit[pdev->classId] = NULL; 800949e: 687b ldr r3, [r7, #4] 80094a0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80094a4: 687b ldr r3, [r7, #4] 80094a6: 32b0 adds r2, #176 @ 0xb0 80094a8: 2100 movs r1, #0 80094aa: f843 1022 str.w r1, [r3, r2, lsl #2] } return (uint8_t)USBD_OK; 80094ae: 2300 movs r3, #0 } 80094b0: 4618 mov r0, r3 80094b2: 3708 adds r7, #8 80094b4: 46bd mov sp, r7 80094b6: bd80 pop {r7, pc} 80094b8: 2000013d .word 0x2000013d 080094bc : * @param pdev: instance * @param req: usb requests * @retval status */ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80094bc: b580 push {r7, lr} 80094be: b086 sub sp, #24 80094c0: af00 add r7, sp, #0 80094c2: 6078 str r0, [r7, #4] 80094c4: 6039 str r1, [r7, #0] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 80094c6: 687b ldr r3, [r7, #4] 80094c8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80094cc: 687b ldr r3, [r7, #4] 80094ce: 32b0 adds r2, #176 @ 0xb0 80094d0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80094d4: 60fb str r3, [r7, #12] USBD_StatusTypeDef ret = USBD_OK; 80094d6: 2300 movs r3, #0 80094d8: 75fb strb r3, [r7, #23] uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; 80094da: 2300 movs r3, #0 80094dc: 817b strh r3, [r7, #10] if (hhid == NULL) 80094de: 68fb ldr r3, [r7, #12] 80094e0: 2b00 cmp r3, #0 80094e2: d101 bne.n 80094e8 { return (uint8_t)USBD_FAIL; 80094e4: 2303 movs r3, #3 80094e6: e0e8 b.n 80096ba } switch (req->bmRequest & USB_REQ_TYPE_MASK) 80094e8: 683b ldr r3, [r7, #0] 80094ea: 781b ldrb r3, [r3, #0] 80094ec: f003 0360 and.w r3, r3, #96 @ 0x60 80094f0: 2b00 cmp r3, #0 80094f2: d046 beq.n 8009582 80094f4: 2b20 cmp r3, #32 80094f6: f040 80d8 bne.w 80096aa { case USB_REQ_TYPE_CLASS : switch (req->bRequest) 80094fa: 683b ldr r3, [r7, #0] 80094fc: 785b ldrb r3, [r3, #1] 80094fe: 3b02 subs r3, #2 8009500: 2b09 cmp r3, #9 8009502: d836 bhi.n 8009572 8009504: a201 add r2, pc, #4 @ (adr r2, 800950c ) 8009506: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800950a: bf00 nop 800950c: 08009563 .word 0x08009563 8009510: 08009543 .word 0x08009543 8009514: 08009573 .word 0x08009573 8009518: 08009573 .word 0x08009573 800951c: 08009573 .word 0x08009573 8009520: 08009573 .word 0x08009573 8009524: 08009573 .word 0x08009573 8009528: 08009573 .word 0x08009573 800952c: 08009551 .word 0x08009551 8009530: 08009535 .word 0x08009535 { case USBD_HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); 8009534: 683b ldr r3, [r7, #0] 8009536: 885b ldrh r3, [r3, #2] 8009538: b2db uxtb r3, r3 800953a: 461a mov r2, r3 800953c: 68fb ldr r3, [r7, #12] 800953e: 601a str r2, [r3, #0] break; 8009540: e01e b.n 8009580 case USBD_HID_REQ_GET_PROTOCOL: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); 8009542: 68fb ldr r3, [r7, #12] 8009544: 2201 movs r2, #1 8009546: 4619 mov r1, r3 8009548: 6878 ldr r0, [r7, #4] 800954a: f001 fc25 bl 800ad98 break; 800954e: e017 b.n 8009580 case USBD_HID_REQ_SET_IDLE: hhid->IdleState = (uint8_t)(req->wValue >> 8); 8009550: 683b ldr r3, [r7, #0] 8009552: 885b ldrh r3, [r3, #2] 8009554: 0a1b lsrs r3, r3, #8 8009556: b29b uxth r3, r3 8009558: b2db uxtb r3, r3 800955a: 461a mov r2, r3 800955c: 68fb ldr r3, [r7, #12] 800955e: 605a str r2, [r3, #4] break; 8009560: e00e b.n 8009580 case USBD_HID_REQ_GET_IDLE: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); 8009562: 68fb ldr r3, [r7, #12] 8009564: 3304 adds r3, #4 8009566: 2201 movs r2, #1 8009568: 4619 mov r1, r3 800956a: 6878 ldr r0, [r7, #4] 800956c: f001 fc14 bl 800ad98 break; 8009570: e006 b.n 8009580 default: USBD_CtlError(pdev, req); 8009572: 6839 ldr r1, [r7, #0] 8009574: 6878 ldr r0, [r7, #4] 8009576: f001 fb92 bl 800ac9e ret = USBD_FAIL; 800957a: 2303 movs r3, #3 800957c: 75fb strb r3, [r7, #23] break; 800957e: bf00 nop } break; 8009580: e09a b.n 80096b8 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8009582: 683b ldr r3, [r7, #0] 8009584: 785b ldrb r3, [r3, #1] 8009586: 2b0b cmp r3, #11 8009588: f200 8086 bhi.w 8009698 800958c: a201 add r2, pc, #4 @ (adr r2, 8009594 ) 800958e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009592: bf00 nop 8009594: 080095c5 .word 0x080095c5 8009598: 080096a7 .word 0x080096a7 800959c: 08009699 .word 0x08009699 80095a0: 08009699 .word 0x08009699 80095a4: 08009699 .word 0x08009699 80095a8: 08009699 .word 0x08009699 80095ac: 080095ef .word 0x080095ef 80095b0: 08009699 .word 0x08009699 80095b4: 08009699 .word 0x08009699 80095b8: 08009699 .word 0x08009699 80095bc: 08009647 .word 0x08009647 80095c0: 08009671 .word 0x08009671 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 80095c4: 687b ldr r3, [r7, #4] 80095c6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80095ca: b2db uxtb r3, r3 80095cc: 2b03 cmp r3, #3 80095ce: d107 bne.n 80095e0 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 80095d0: f107 030a add.w r3, r7, #10 80095d4: 2202 movs r2, #2 80095d6: 4619 mov r1, r3 80095d8: 6878 ldr r0, [r7, #4] 80095da: f001 fbdd bl 800ad98 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80095de: e063 b.n 80096a8 USBD_CtlError(pdev, req); 80095e0: 6839 ldr r1, [r7, #0] 80095e2: 6878 ldr r0, [r7, #4] 80095e4: f001 fb5b bl 800ac9e ret = USBD_FAIL; 80095e8: 2303 movs r3, #3 80095ea: 75fb strb r3, [r7, #23] break; 80095ec: e05c b.n 80096a8 case USB_REQ_GET_DESCRIPTOR: if ((req->wValue >> 8) == HID_REPORT_DESC) 80095ee: 683b ldr r3, [r7, #0] 80095f0: 885b ldrh r3, [r3, #2] 80095f2: 0a1b lsrs r3, r3, #8 80095f4: b29b uxth r3, r3 80095f6: 2b22 cmp r3, #34 @ 0x22 80095f8: d108 bne.n 800960c { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); 80095fa: 683b ldr r3, [r7, #0] 80095fc: 88db ldrh r3, [r3, #6] 80095fe: 2b2d cmp r3, #45 @ 0x2d 8009600: bf28 it cs 8009602: 232d movcs r3, #45 @ 0x2d 8009604: 82bb strh r3, [r7, #20] pbuf = HID_MOUSE_ReportDesc; 8009606: 4b2f ldr r3, [pc, #188] @ (80096c4 ) 8009608: 613b str r3, [r7, #16] 800960a: e015 b.n 8009638 } else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) 800960c: 683b ldr r3, [r7, #0] 800960e: 885b ldrh r3, [r3, #2] 8009610: 0a1b lsrs r3, r3, #8 8009612: b29b uxth r3, r3 8009614: 2b21 cmp r3, #33 @ 0x21 8009616: d108 bne.n 800962a { pbuf = USBD_HID_Desc; 8009618: 4b2b ldr r3, [pc, #172] @ (80096c8 ) 800961a: 613b str r3, [r7, #16] len = MIN(USB_HID_DESC_SIZ, req->wLength); 800961c: 683b ldr r3, [r7, #0] 800961e: 88db ldrh r3, [r3, #6] 8009620: 2b09 cmp r3, #9 8009622: bf28 it cs 8009624: 2309 movcs r3, #9 8009626: 82bb strh r3, [r7, #20] 8009628: e006 b.n 8009638 } else { USBD_CtlError(pdev, req); 800962a: 6839 ldr r1, [r7, #0] 800962c: 6878 ldr r0, [r7, #4] 800962e: f001 fb36 bl 800ac9e ret = USBD_FAIL; 8009632: 2303 movs r3, #3 8009634: 75fb strb r3, [r7, #23] break; 8009636: e037 b.n 80096a8 } (void)USBD_CtlSendData(pdev, pbuf, len); 8009638: 8abb ldrh r3, [r7, #20] 800963a: 461a mov r2, r3 800963c: 6939 ldr r1, [r7, #16] 800963e: 6878 ldr r0, [r7, #4] 8009640: f001 fbaa bl 800ad98 break; 8009644: e030 b.n 80096a8 case USB_REQ_GET_INTERFACE : if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009646: 687b ldr r3, [r7, #4] 8009648: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800964c: b2db uxtb r3, r3 800964e: 2b03 cmp r3, #3 8009650: d107 bne.n 8009662 { (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); 8009652: 68fb ldr r3, [r7, #12] 8009654: 3308 adds r3, #8 8009656: 2201 movs r2, #1 8009658: 4619 mov r1, r3 800965a: 6878 ldr r0, [r7, #4] 800965c: f001 fb9c bl 800ad98 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8009660: e022 b.n 80096a8 USBD_CtlError(pdev, req); 8009662: 6839 ldr r1, [r7, #0] 8009664: 6878 ldr r0, [r7, #4] 8009666: f001 fb1a bl 800ac9e ret = USBD_FAIL; 800966a: 2303 movs r3, #3 800966c: 75fb strb r3, [r7, #23] break; 800966e: e01b b.n 80096a8 case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009670: 687b ldr r3, [r7, #4] 8009672: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009676: b2db uxtb r3, r3 8009678: 2b03 cmp r3, #3 800967a: d106 bne.n 800968a { hhid->AltSetting = (uint8_t)(req->wValue); 800967c: 683b ldr r3, [r7, #0] 800967e: 885b ldrh r3, [r3, #2] 8009680: b2db uxtb r3, r3 8009682: 461a mov r2, r3 8009684: 68fb ldr r3, [r7, #12] 8009686: 609a str r2, [r3, #8] else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8009688: e00e b.n 80096a8 USBD_CtlError(pdev, req); 800968a: 6839 ldr r1, [r7, #0] 800968c: 6878 ldr r0, [r7, #4] 800968e: f001 fb06 bl 800ac9e ret = USBD_FAIL; 8009692: 2303 movs r3, #3 8009694: 75fb strb r3, [r7, #23] break; 8009696: e007 b.n 80096a8 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 8009698: 6839 ldr r1, [r7, #0] 800969a: 6878 ldr r0, [r7, #4] 800969c: f001 faff bl 800ac9e ret = USBD_FAIL; 80096a0: 2303 movs r3, #3 80096a2: 75fb strb r3, [r7, #23] break; 80096a4: e000 b.n 80096a8 break; 80096a6: bf00 nop } break; 80096a8: e006 b.n 80096b8 default: USBD_CtlError(pdev, req); 80096aa: 6839 ldr r1, [r7, #0] 80096ac: 6878 ldr r0, [r7, #4] 80096ae: f001 faf6 bl 800ac9e ret = USBD_FAIL; 80096b2: 2303 movs r3, #3 80096b4: 75fb strb r3, [r7, #23] break; 80096b6: bf00 nop } return (uint8_t)ret; 80096b8: 7dfb ldrb r3, [r7, #23] } 80096ba: 4618 mov r0, r3 80096bc: 3718 adds r7, #24 80096be: 46bd mov sp, r7 80096c0: bd80 pop {r7, pc} 80096c2: bf00 nop 80096c4: 20000110 .word 0x20000110 80096c8: 200000f8 .word 0x200000f8 080096cc : uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) { USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { 80096cc: b580 push {r7, lr} 80096ce: b086 sub sp, #24 80096d0: af00 add r7, sp, #0 80096d2: 60f8 str r0, [r7, #12] 80096d4: 60b9 str r1, [r7, #8] 80096d6: 4613 mov r3, r2 80096d8: 80fb strh r3, [r7, #6] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 80096da: 68fb ldr r3, [r7, #12] 80096dc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80096e0: 68fb ldr r3, [r7, #12] 80096e2: 32b0 adds r2, #176 @ 0xb0 80096e4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80096e8: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hhid == NULL) 80096ea: 697b ldr r3, [r7, #20] 80096ec: 2b00 cmp r3, #0 80096ee: d101 bne.n 80096f4 { return (uint8_t)USBD_FAIL; 80096f0: 2303 movs r3, #3 80096f2: e014 b.n 800971e #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80096f4: 68fb ldr r3, [r7, #12] 80096f6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80096fa: b2db uxtb r3, r3 80096fc: 2b03 cmp r3, #3 80096fe: d10d bne.n 800971c { if (hhid->state == USBD_HID_IDLE) 8009700: 697b ldr r3, [r7, #20] 8009702: 7b1b ldrb r3, [r3, #12] 8009704: 2b00 cmp r3, #0 8009706: d109 bne.n 800971c { hhid->state = USBD_HID_BUSY; 8009708: 697b ldr r3, [r7, #20] 800970a: 2201 movs r2, #1 800970c: 731a strb r2, [r3, #12] (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); 800970e: 4b06 ldr r3, [pc, #24] @ (8009728 ) 8009710: 7819 ldrb r1, [r3, #0] 8009712: 88fb ldrh r3, [r7, #6] 8009714: 68ba ldr r2, [r7, #8] 8009716: 68f8 ldr r0, [r7, #12] 8009718: f001 ff7d bl 800b616 } } return (uint8_t)USBD_OK; 800971c: 2300 movs r3, #0 } 800971e: 4618 mov r0, r3 8009720: 3718 adds r7, #24 8009722: 46bd mov sp, r7 8009724: bd80 pop {r7, pc} 8009726: bf00 nop 8009728: 2000013d .word 0x2000013d 0800972c : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { 800972c: b580 push {r7, lr} 800972e: b084 sub sp, #16 8009730: af00 add r7, sp, #0 8009732: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8009734: 2181 movs r1, #129 @ 0x81 8009736: 4809 ldr r0, [pc, #36] @ (800975c ) 8009738: f000 fc4e bl 8009fd8 800973c: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 800973e: 68fb ldr r3, [r7, #12] 8009740: 2b00 cmp r3, #0 8009742: d002 beq.n 800974a { pEpDesc->bInterval = HID_FS_BINTERVAL; 8009744: 68fb ldr r3, [r7, #12] 8009746: 220a movs r2, #10 8009748: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 800974a: 687b ldr r3, [r7, #4] 800974c: 2222 movs r2, #34 @ 0x22 800974e: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8009750: 4b02 ldr r3, [pc, #8] @ (800975c ) } 8009752: 4618 mov r0, r3 8009754: 3710 adds r7, #16 8009756: 46bd mov sp, r7 8009758: bd80 pop {r7, pc} 800975a: bf00 nop 800975c: 200000d4 .word 0x200000d4 08009760 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { 8009760: b580 push {r7, lr} 8009762: b084 sub sp, #16 8009764: af00 add r7, sp, #0 8009766: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8009768: 2181 movs r1, #129 @ 0x81 800976a: 4809 ldr r0, [pc, #36] @ (8009790 ) 800976c: f000 fc34 bl 8009fd8 8009770: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8009772: 68fb ldr r3, [r7, #12] 8009774: 2b00 cmp r3, #0 8009776: d002 beq.n 800977e { pEpDesc->bInterval = HID_HS_BINTERVAL; 8009778: 68fb ldr r3, [r7, #12] 800977a: 2207 movs r2, #7 800977c: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 800977e: 687b ldr r3, [r7, #4] 8009780: 2222 movs r2, #34 @ 0x22 8009782: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8009784: 4b02 ldr r3, [pc, #8] @ (8009790 ) } 8009786: 4618 mov r0, r3 8009788: 3710 adds r7, #16 800978a: 46bd mov sp, r7 800978c: bd80 pop {r7, pc} 800978e: bf00 nop 8009790: 200000d4 .word 0x200000d4 08009794 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { 8009794: b580 push {r7, lr} 8009796: b084 sub sp, #16 8009798: af00 add r7, sp, #0 800979a: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 800979c: 2181 movs r1, #129 @ 0x81 800979e: 4809 ldr r0, [pc, #36] @ (80097c4 ) 80097a0: f000 fc1a bl 8009fd8 80097a4: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80097a6: 68fb ldr r3, [r7, #12] 80097a8: 2b00 cmp r3, #0 80097aa: d002 beq.n 80097b2 { pEpDesc->bInterval = HID_FS_BINTERVAL; 80097ac: 68fb ldr r3, [r7, #12] 80097ae: 220a movs r2, #10 80097b0: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80097b2: 687b ldr r3, [r7, #4] 80097b4: 2222 movs r2, #34 @ 0x22 80097b6: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 80097b8: 4b02 ldr r3, [pc, #8] @ (80097c4 ) } 80097ba: 4618 mov r0, r3 80097bc: 3710 adds r7, #16 80097be: 46bd mov sp, r7 80097c0: bd80 pop {r7, pc} 80097c2: bf00 nop 80097c4: 200000d4 .word 0x200000d4 080097c8 : * @param pdev: device instance * @param epnum: endpoint index * @retval status */ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 80097c8: b480 push {r7} 80097ca: b083 sub sp, #12 80097cc: af00 add r7, sp, #0 80097ce: 6078 str r0, [r7, #4] 80097d0: 460b mov r3, r1 80097d2: 70fb strb r3, [r7, #3] UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; 80097d4: 687b ldr r3, [r7, #4] 80097d6: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80097da: 687b ldr r3, [r7, #4] 80097dc: 32b0 adds r2, #176 @ 0xb0 80097de: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80097e2: 2200 movs r2, #0 80097e4: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 80097e6: 2300 movs r3, #0 } 80097e8: 4618 mov r0, r3 80097ea: 370c adds r7, #12 80097ec: 46bd mov sp, r7 80097ee: f85d 7b04 ldr.w r7, [sp], #4 80097f2: 4770 bx lr 080097f4 : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { 80097f4: b480 push {r7} 80097f6: b083 sub sp, #12 80097f8: af00 add r7, sp, #0 80097fa: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); 80097fc: 687b ldr r3, [r7, #4] 80097fe: 220a movs r2, #10 8009800: 801a strh r2, [r3, #0] return USBD_HID_DeviceQualifierDesc; 8009802: 4b03 ldr r3, [pc, #12] @ (8009810 ) } 8009804: 4618 mov r0, r3 8009806: 370c adds r7, #12 8009808: 46bd mov sp, r7 800980a: f85d 7b04 ldr.w r7, [sp], #4 800980e: 4770 bx lr 8009810: 20000104 .word 0x20000104 08009814 : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 8009814: b580 push {r7, lr} 8009816: b086 sub sp, #24 8009818: af00 add r7, sp, #0 800981a: 60f8 str r0, [r7, #12] 800981c: 60b9 str r1, [r7, #8] 800981e: 4613 mov r3, r2 8009820: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 8009822: 68fb ldr r3, [r7, #12] 8009824: 2b00 cmp r3, #0 8009826: d101 bne.n 800982c { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8009828: 2303 movs r3, #3 800982a: e01f b.n 800986c pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 800982c: 68fb ldr r3, [r7, #12] 800982e: 2200 movs r2, #0 8009830: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 8009834: 68fb ldr r3, [r7, #12] 8009836: 2200 movs r2, #0 8009838: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 800983c: 68fb ldr r3, [r7, #12] 800983e: 2200 movs r2, #0 8009840: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 8009844: 68bb ldr r3, [r7, #8] 8009846: 2b00 cmp r3, #0 8009848: d003 beq.n 8009852 { pdev->pDesc = pdesc; 800984a: 68fb ldr r3, [r7, #12] 800984c: 68ba ldr r2, [r7, #8] 800984e: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 8009852: 68fb ldr r3, [r7, #12] 8009854: 2201 movs r2, #1 8009856: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 800985a: 68fb ldr r3, [r7, #12] 800985c: 79fa ldrb r2, [r7, #7] 800985e: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8009860: 68f8 ldr r0, [r7, #12] 8009862: f001 fda3 bl 800b3ac 8009866: 4603 mov r3, r0 8009868: 75fb strb r3, [r7, #23] return ret; 800986a: 7dfb ldrb r3, [r7, #23] } 800986c: 4618 mov r0, r3 800986e: 3718 adds r7, #24 8009870: 46bd mov sp, r7 8009872: bd80 pop {r7, pc} 08009874 : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 8009874: b580 push {r7, lr} 8009876: b084 sub sp, #16 8009878: af00 add r7, sp, #0 800987a: 6078 str r0, [r7, #4] 800987c: 6039 str r1, [r7, #0] uint16_t len = 0U; 800987e: 2300 movs r3, #0 8009880: 81fb strh r3, [r7, #14] if (pclass == NULL) 8009882: 683b ldr r3, [r7, #0] 8009884: 2b00 cmp r3, #0 8009886: d101 bne.n 800988c { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8009888: 2303 movs r3, #3 800988a: e025 b.n 80098d8 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 800988c: 687b ldr r3, [r7, #4] 800988e: 683a ldr r2, [r7, #0] 8009890: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 8009894: 687b ldr r3, [r7, #4] 8009896: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800989a: 687b ldr r3, [r7, #4] 800989c: 32ae adds r2, #174 @ 0xae 800989e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80098a2: 6adb ldr r3, [r3, #44] @ 0x2c 80098a4: 2b00 cmp r3, #0 80098a6: d00f beq.n 80098c8 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 80098a8: 687b ldr r3, [r7, #4] 80098aa: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80098ae: 687b ldr r3, [r7, #4] 80098b0: 32ae adds r2, #174 @ 0xae 80098b2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80098b6: 6adb ldr r3, [r3, #44] @ 0x2c 80098b8: f107 020e add.w r2, r7, #14 80098bc: 4610 mov r0, r2 80098be: 4798 blx r3 80098c0: 4602 mov r2, r0 80098c2: 687b ldr r3, [r7, #4] 80098c4: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 80098c8: 687b ldr r3, [r7, #4] 80098ca: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 80098ce: 1c5a adds r2, r3, #1 80098d0: 687b ldr r3, [r7, #4] 80098d2: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 80098d6: 2300 movs r3, #0 } 80098d8: 4618 mov r0, r3 80098da: 3710 adds r7, #16 80098dc: 46bd mov sp, r7 80098de: bd80 pop {r7, pc} 080098e0 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 80098e0: b580 push {r7, lr} 80098e2: b082 sub sp, #8 80098e4: af00 add r7, sp, #0 80098e6: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 80098e8: 6878 ldr r0, [r7, #4] 80098ea: f001 fdab bl 800b444 80098ee: 4603 mov r3, r0 } 80098f0: 4618 mov r0, r3 80098f2: 3708 adds r7, #8 80098f4: 46bd mov sp, r7 80098f6: bd80 pop {r7, pc} 080098f8 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 80098f8: b480 push {r7} 80098fa: b083 sub sp, #12 80098fc: af00 add r7, sp, #0 80098fe: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8009900: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 8009902: 4618 mov r0, r3 8009904: 370c adds r7, #12 8009906: 46bd mov sp, r7 8009908: f85d 7b04 ldr.w r7, [sp], #4 800990c: 4770 bx lr 0800990e : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800990e: b580 push {r7, lr} 8009910: b084 sub sp, #16 8009912: af00 add r7, sp, #0 8009914: 6078 str r0, [r7, #4] 8009916: 460b mov r3, r1 8009918: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 800991a: 2300 movs r3, #0 800991c: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 800991e: 687b ldr r3, [r7, #4] 8009920: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009924: 2b00 cmp r3, #0 8009926: d009 beq.n 800993c { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 8009928: 687b ldr r3, [r7, #4] 800992a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800992e: 681b ldr r3, [r3, #0] 8009930: 78fa ldrb r2, [r7, #3] 8009932: 4611 mov r1, r2 8009934: 6878 ldr r0, [r7, #4] 8009936: 4798 blx r3 8009938: 4603 mov r3, r0 800993a: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 800993c: 7bfb ldrb r3, [r7, #15] } 800993e: 4618 mov r0, r3 8009940: 3710 adds r7, #16 8009942: 46bd mov sp, r7 8009944: bd80 pop {r7, pc} 08009946 : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8009946: b580 push {r7, lr} 8009948: b084 sub sp, #16 800994a: af00 add r7, sp, #0 800994c: 6078 str r0, [r7, #4] 800994e: 460b mov r3, r1 8009950: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8009952: 2300 movs r3, #0 8009954: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 8009956: 687b ldr r3, [r7, #4] 8009958: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800995c: 685b ldr r3, [r3, #4] 800995e: 78fa ldrb r2, [r7, #3] 8009960: 4611 mov r1, r2 8009962: 6878 ldr r0, [r7, #4] 8009964: 4798 blx r3 8009966: 4603 mov r3, r0 8009968: 2b00 cmp r3, #0 800996a: d001 beq.n 8009970 { ret = USBD_FAIL; 800996c: 2303 movs r3, #3 800996e: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8009970: 7bfb ldrb r3, [r7, #15] } 8009972: 4618 mov r0, r3 8009974: 3710 adds r7, #16 8009976: 46bd mov sp, r7 8009978: bd80 pop {r7, pc} 0800997a : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 800997a: b580 push {r7, lr} 800997c: b084 sub sp, #16 800997e: af00 add r7, sp, #0 8009980: 6078 str r0, [r7, #4] 8009982: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 8009984: 687b ldr r3, [r7, #4] 8009986: f203 23aa addw r3, r3, #682 @ 0x2aa 800998a: 6839 ldr r1, [r7, #0] 800998c: 4618 mov r0, r3 800998e: f001 f94c bl 800ac2a pdev->ep0_state = USBD_EP0_SETUP; 8009992: 687b ldr r3, [r7, #4] 8009994: 2201 movs r2, #1 8009996: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 800999a: 687b ldr r3, [r7, #4] 800999c: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 80099a0: 461a mov r2, r3 80099a2: 687b ldr r3, [r7, #4] 80099a4: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 80099a8: 687b ldr r3, [r7, #4] 80099aa: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 80099ae: f003 031f and.w r3, r3, #31 80099b2: 2b02 cmp r3, #2 80099b4: d01a beq.n 80099ec 80099b6: 2b02 cmp r3, #2 80099b8: d822 bhi.n 8009a00 80099ba: 2b00 cmp r3, #0 80099bc: d002 beq.n 80099c4 80099be: 2b01 cmp r3, #1 80099c0: d00a beq.n 80099d8 80099c2: e01d b.n 8009a00 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 80099c4: 687b ldr r3, [r7, #4] 80099c6: f203 23aa addw r3, r3, #682 @ 0x2aa 80099ca: 4619 mov r1, r3 80099cc: 6878 ldr r0, [r7, #4] 80099ce: f000 fb77 bl 800a0c0 80099d2: 4603 mov r3, r0 80099d4: 73fb strb r3, [r7, #15] break; 80099d6: e020 b.n 8009a1a case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 80099d8: 687b ldr r3, [r7, #4] 80099da: f203 23aa addw r3, r3, #682 @ 0x2aa 80099de: 4619 mov r1, r3 80099e0: 6878 ldr r0, [r7, #4] 80099e2: f000 fbdf bl 800a1a4 80099e6: 4603 mov r3, r0 80099e8: 73fb strb r3, [r7, #15] break; 80099ea: e016 b.n 8009a1a case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 80099ec: 687b ldr r3, [r7, #4] 80099ee: f203 23aa addw r3, r3, #682 @ 0x2aa 80099f2: 4619 mov r1, r3 80099f4: 6878 ldr r0, [r7, #4] 80099f6: f000 fc41 bl 800a27c 80099fa: 4603 mov r3, r0 80099fc: 73fb strb r3, [r7, #15] break; 80099fe: e00c b.n 8009a1a default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8009a00: 687b ldr r3, [r7, #4] 8009a02: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8009a06: f023 037f bic.w r3, r3, #127 @ 0x7f 8009a0a: b2db uxtb r3, r3 8009a0c: 4619 mov r1, r3 8009a0e: 6878 ldr r0, [r7, #4] 8009a10: f001 fd78 bl 800b504 8009a14: 4603 mov r3, r0 8009a16: 73fb strb r3, [r7, #15] break; 8009a18: bf00 nop } return ret; 8009a1a: 7bfb ldrb r3, [r7, #15] } 8009a1c: 4618 mov r0, r3 8009a1e: 3710 adds r7, #16 8009a20: 46bd mov sp, r7 8009a22: bd80 pop {r7, pc} 08009a24 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8009a24: b580 push {r7, lr} 8009a26: b086 sub sp, #24 8009a28: af00 add r7, sp, #0 8009a2a: 60f8 str r0, [r7, #12] 8009a2c: 460b mov r3, r1 8009a2e: 607a str r2, [r7, #4] 8009a30: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 8009a32: 2300 movs r3, #0 8009a34: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8009a36: 7afb ldrb r3, [r7, #11] 8009a38: 2b00 cmp r3, #0 8009a3a: d177 bne.n 8009b2c { pep = &pdev->ep_out[0]; 8009a3c: 68fb ldr r3, [r7, #12] 8009a3e: f503 73aa add.w r3, r3, #340 @ 0x154 8009a42: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 8009a44: 68fb ldr r3, [r7, #12] 8009a46: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8009a4a: 2b03 cmp r3, #3 8009a4c: f040 80a1 bne.w 8009b92 { if (pep->rem_length > pep->maxpacket) 8009a50: 693b ldr r3, [r7, #16] 8009a52: 685b ldr r3, [r3, #4] 8009a54: 693a ldr r2, [r7, #16] 8009a56: 8992 ldrh r2, [r2, #12] 8009a58: 4293 cmp r3, r2 8009a5a: d91c bls.n 8009a96 { pep->rem_length -= pep->maxpacket; 8009a5c: 693b ldr r3, [r7, #16] 8009a5e: 685b ldr r3, [r3, #4] 8009a60: 693a ldr r2, [r7, #16] 8009a62: 8992 ldrh r2, [r2, #12] 8009a64: 1a9a subs r2, r3, r2 8009a66: 693b ldr r3, [r7, #16] 8009a68: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8009a6a: 693b ldr r3, [r7, #16] 8009a6c: 691b ldr r3, [r3, #16] 8009a6e: 693a ldr r2, [r7, #16] 8009a70: 8992 ldrh r2, [r2, #12] 8009a72: 441a add r2, r3 8009a74: 693b ldr r3, [r7, #16] 8009a76: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 8009a78: 693b ldr r3, [r7, #16] 8009a7a: 6919 ldr r1, [r3, #16] 8009a7c: 693b ldr r3, [r7, #16] 8009a7e: 899b ldrh r3, [r3, #12] 8009a80: 461a mov r2, r3 8009a82: 693b ldr r3, [r7, #16] 8009a84: 685b ldr r3, [r3, #4] 8009a86: 4293 cmp r3, r2 8009a88: bf38 it cc 8009a8a: 4613 movcc r3, r2 8009a8c: 461a mov r2, r3 8009a8e: 68f8 ldr r0, [r7, #12] 8009a90: f001 f9b1 bl 800adf6 8009a94: e07d b.n 8009b92 } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 8009a96: 68fb ldr r3, [r7, #12] 8009a98: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8009a9c: f003 031f and.w r3, r3, #31 8009aa0: 2b02 cmp r3, #2 8009aa2: d014 beq.n 8009ace 8009aa4: 2b02 cmp r3, #2 8009aa6: d81d bhi.n 8009ae4 8009aa8: 2b00 cmp r3, #0 8009aaa: d002 beq.n 8009ab2 8009aac: 2b01 cmp r3, #1 8009aae: d003 beq.n 8009ab8 8009ab0: e018 b.n 8009ae4 { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 8009ab2: 2300 movs r3, #0 8009ab4: 75bb strb r3, [r7, #22] break; 8009ab6: e018 b.n 8009aea case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8009ab8: 68fb ldr r3, [r7, #12] 8009aba: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8009abe: b2db uxtb r3, r3 8009ac0: 4619 mov r1, r3 8009ac2: 68f8 ldr r0, [r7, #12] 8009ac4: f000 fa6e bl 8009fa4 8009ac8: 4603 mov r3, r0 8009aca: 75bb strb r3, [r7, #22] break; 8009acc: e00d b.n 8009aea case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8009ace: 68fb ldr r3, [r7, #12] 8009ad0: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8009ad4: b2db uxtb r3, r3 8009ad6: 4619 mov r1, r3 8009ad8: 68f8 ldr r0, [r7, #12] 8009ada: f000 fa70 bl 8009fbe 8009ade: 4603 mov r3, r0 8009ae0: 75bb strb r3, [r7, #22] break; 8009ae2: e002 b.n 8009aea default: /* Back to the first class in case of doubt */ idx = 0U; 8009ae4: 2300 movs r3, #0 8009ae6: 75bb strb r3, [r7, #22] break; 8009ae8: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 8009aea: 7dbb ldrb r3, [r7, #22] 8009aec: 2b00 cmp r3, #0 8009aee: d119 bne.n 8009b24 { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009af0: 68fb ldr r3, [r7, #12] 8009af2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009af6: b2db uxtb r3, r3 8009af8: 2b03 cmp r3, #3 8009afa: d113 bne.n 8009b24 { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8009afc: 7dba ldrb r2, [r7, #22] 8009afe: 68fb ldr r3, [r7, #12] 8009b00: 32ae adds r2, #174 @ 0xae 8009b02: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009b06: 691b ldr r3, [r3, #16] 8009b08: 2b00 cmp r3, #0 8009b0a: d00b beq.n 8009b24 { pdev->classId = idx; 8009b0c: 7dba ldrb r2, [r7, #22] 8009b0e: 68fb ldr r3, [r7, #12] 8009b10: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 8009b14: 7dba ldrb r2, [r7, #22] 8009b16: 68fb ldr r3, [r7, #12] 8009b18: 32ae adds r2, #174 @ 0xae 8009b1a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009b1e: 691b ldr r3, [r3, #16] 8009b20: 68f8 ldr r0, [r7, #12] 8009b22: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 8009b24: 68f8 ldr r0, [r7, #12] 8009b26: f001 f977 bl 800ae18 8009b2a: e032 b.n 8009b92 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 8009b2c: 7afb ldrb r3, [r7, #11] 8009b2e: f003 037f and.w r3, r3, #127 @ 0x7f 8009b32: b2db uxtb r3, r3 8009b34: 4619 mov r1, r3 8009b36: 68f8 ldr r0, [r7, #12] 8009b38: f000 fa41 bl 8009fbe 8009b3c: 4603 mov r3, r0 8009b3e: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009b40: 7dbb ldrb r3, [r7, #22] 8009b42: 2bff cmp r3, #255 @ 0xff 8009b44: d025 beq.n 8009b92 8009b46: 7dbb ldrb r3, [r7, #22] 8009b48: 2b00 cmp r3, #0 8009b4a: d122 bne.n 8009b92 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009b4c: 68fb ldr r3, [r7, #12] 8009b4e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009b52: b2db uxtb r3, r3 8009b54: 2b03 cmp r3, #3 8009b56: d117 bne.n 8009b88 { if (pdev->pClass[idx]->DataOut != NULL) 8009b58: 7dba ldrb r2, [r7, #22] 8009b5a: 68fb ldr r3, [r7, #12] 8009b5c: 32ae adds r2, #174 @ 0xae 8009b5e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009b62: 699b ldr r3, [r3, #24] 8009b64: 2b00 cmp r3, #0 8009b66: d00f beq.n 8009b88 { pdev->classId = idx; 8009b68: 7dba ldrb r2, [r7, #22] 8009b6a: 68fb ldr r3, [r7, #12] 8009b6c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 8009b70: 7dba ldrb r2, [r7, #22] 8009b72: 68fb ldr r3, [r7, #12] 8009b74: 32ae adds r2, #174 @ 0xae 8009b76: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009b7a: 699b ldr r3, [r3, #24] 8009b7c: 7afa ldrb r2, [r7, #11] 8009b7e: 4611 mov r1, r2 8009b80: 68f8 ldr r0, [r7, #12] 8009b82: 4798 blx r3 8009b84: 4603 mov r3, r0 8009b86: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8009b88: 7dfb ldrb r3, [r7, #23] 8009b8a: 2b00 cmp r3, #0 8009b8c: d001 beq.n 8009b92 { return ret; 8009b8e: 7dfb ldrb r3, [r7, #23] 8009b90: e000 b.n 8009b94 } } } return USBD_OK; 8009b92: 2300 movs r3, #0 } 8009b94: 4618 mov r0, r3 8009b96: 3718 adds r7, #24 8009b98: 46bd mov sp, r7 8009b9a: bd80 pop {r7, pc} 08009b9c : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8009b9c: b580 push {r7, lr} 8009b9e: b086 sub sp, #24 8009ba0: af00 add r7, sp, #0 8009ba2: 60f8 str r0, [r7, #12] 8009ba4: 460b mov r3, r1 8009ba6: 607a str r2, [r7, #4] 8009ba8: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8009baa: 7afb ldrb r3, [r7, #11] 8009bac: 2b00 cmp r3, #0 8009bae: d178 bne.n 8009ca2 { pep = &pdev->ep_in[0]; 8009bb0: 68fb ldr r3, [r7, #12] 8009bb2: 3314 adds r3, #20 8009bb4: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8009bb6: 68fb ldr r3, [r7, #12] 8009bb8: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8009bbc: 2b02 cmp r3, #2 8009bbe: d163 bne.n 8009c88 { if (pep->rem_length > pep->maxpacket) 8009bc0: 693b ldr r3, [r7, #16] 8009bc2: 685b ldr r3, [r3, #4] 8009bc4: 693a ldr r2, [r7, #16] 8009bc6: 8992 ldrh r2, [r2, #12] 8009bc8: 4293 cmp r3, r2 8009bca: d91c bls.n 8009c06 { pep->rem_length -= pep->maxpacket; 8009bcc: 693b ldr r3, [r7, #16] 8009bce: 685b ldr r3, [r3, #4] 8009bd0: 693a ldr r2, [r7, #16] 8009bd2: 8992 ldrh r2, [r2, #12] 8009bd4: 1a9a subs r2, r3, r2 8009bd6: 693b ldr r3, [r7, #16] 8009bd8: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8009bda: 693b ldr r3, [r7, #16] 8009bdc: 691b ldr r3, [r3, #16] 8009bde: 693a ldr r2, [r7, #16] 8009be0: 8992 ldrh r2, [r2, #12] 8009be2: 441a add r2, r3 8009be4: 693b ldr r3, [r7, #16] 8009be6: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8009be8: 693b ldr r3, [r7, #16] 8009bea: 6919 ldr r1, [r3, #16] 8009bec: 693b ldr r3, [r7, #16] 8009bee: 685b ldr r3, [r3, #4] 8009bf0: 461a mov r2, r3 8009bf2: 68f8 ldr r0, [r7, #12] 8009bf4: f001 f8ee bl 800add4 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8009bf8: 2300 movs r3, #0 8009bfa: 2200 movs r2, #0 8009bfc: 2100 movs r1, #0 8009bfe: 68f8 ldr r0, [r7, #12] 8009c00: f001 fd2a bl 800b658 8009c04: e040 b.n 8009c88 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8009c06: 693b ldr r3, [r7, #16] 8009c08: 899b ldrh r3, [r3, #12] 8009c0a: 461a mov r2, r3 8009c0c: 693b ldr r3, [r7, #16] 8009c0e: 685b ldr r3, [r3, #4] 8009c10: 429a cmp r2, r3 8009c12: d11c bne.n 8009c4e (pep->total_length >= pep->maxpacket) && 8009c14: 693b ldr r3, [r7, #16] 8009c16: 681b ldr r3, [r3, #0] 8009c18: 693a ldr r2, [r7, #16] 8009c1a: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 8009c1c: 4293 cmp r3, r2 8009c1e: d316 bcc.n 8009c4e (pep->total_length < pdev->ep0_data_len)) 8009c20: 693b ldr r3, [r7, #16] 8009c22: 681a ldr r2, [r3, #0] 8009c24: 68fb ldr r3, [r7, #12] 8009c26: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 8009c2a: 429a cmp r2, r3 8009c2c: d20f bcs.n 8009c4e { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8009c2e: 2200 movs r2, #0 8009c30: 2100 movs r1, #0 8009c32: 68f8 ldr r0, [r7, #12] 8009c34: f001 f8ce bl 800add4 pdev->ep0_data_len = 0U; 8009c38: 68fb ldr r3, [r7, #12] 8009c3a: 2200 movs r2, #0 8009c3c: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8009c40: 2300 movs r3, #0 8009c42: 2200 movs r2, #0 8009c44: 2100 movs r1, #0 8009c46: 68f8 ldr r0, [r7, #12] 8009c48: f001 fd06 bl 800b658 8009c4c: e01c b.n 8009c88 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009c4e: 68fb ldr r3, [r7, #12] 8009c50: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009c54: b2db uxtb r3, r3 8009c56: 2b03 cmp r3, #3 8009c58: d10f bne.n 8009c7a { if (pdev->pClass[0]->EP0_TxSent != NULL) 8009c5a: 68fb ldr r3, [r7, #12] 8009c5c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009c60: 68db ldr r3, [r3, #12] 8009c62: 2b00 cmp r3, #0 8009c64: d009 beq.n 8009c7a { pdev->classId = 0U; 8009c66: 68fb ldr r3, [r7, #12] 8009c68: 2200 movs r2, #0 8009c6a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 8009c6e: 68fb ldr r3, [r7, #12] 8009c70: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009c74: 68db ldr r3, [r3, #12] 8009c76: 68f8 ldr r0, [r7, #12] 8009c78: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8009c7a: 2180 movs r1, #128 @ 0x80 8009c7c: 68f8 ldr r0, [r7, #12] 8009c7e: f001 fc41 bl 800b504 (void)USBD_CtlReceiveStatus(pdev); 8009c82: 68f8 ldr r0, [r7, #12] 8009c84: f001 f8db bl 800ae3e } } } if (pdev->dev_test_mode != 0U) 8009c88: 68fb ldr r3, [r7, #12] 8009c8a: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8009c8e: 2b00 cmp r3, #0 8009c90: d03a beq.n 8009d08 { (void)USBD_RunTestMode(pdev); 8009c92: 68f8 ldr r0, [r7, #12] 8009c94: f7ff fe30 bl 80098f8 pdev->dev_test_mode = 0U; 8009c98: 68fb ldr r3, [r7, #12] 8009c9a: 2200 movs r2, #0 8009c9c: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8009ca0: e032 b.n 8009d08 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8009ca2: 7afb ldrb r3, [r7, #11] 8009ca4: f063 037f orn r3, r3, #127 @ 0x7f 8009ca8: b2db uxtb r3, r3 8009caa: 4619 mov r1, r3 8009cac: 68f8 ldr r0, [r7, #12] 8009cae: f000 f986 bl 8009fbe 8009cb2: 4603 mov r3, r0 8009cb4: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009cb6: 7dfb ldrb r3, [r7, #23] 8009cb8: 2bff cmp r3, #255 @ 0xff 8009cba: d025 beq.n 8009d08 8009cbc: 7dfb ldrb r3, [r7, #23] 8009cbe: 2b00 cmp r3, #0 8009cc0: d122 bne.n 8009d08 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009cc2: 68fb ldr r3, [r7, #12] 8009cc4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009cc8: b2db uxtb r3, r3 8009cca: 2b03 cmp r3, #3 8009ccc: d11c bne.n 8009d08 { if (pdev->pClass[idx]->DataIn != NULL) 8009cce: 7dfa ldrb r2, [r7, #23] 8009cd0: 68fb ldr r3, [r7, #12] 8009cd2: 32ae adds r2, #174 @ 0xae 8009cd4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009cd8: 695b ldr r3, [r3, #20] 8009cda: 2b00 cmp r3, #0 8009cdc: d014 beq.n 8009d08 { pdev->classId = idx; 8009cde: 7dfa ldrb r2, [r7, #23] 8009ce0: 68fb ldr r3, [r7, #12] 8009ce2: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 8009ce6: 7dfa ldrb r2, [r7, #23] 8009ce8: 68fb ldr r3, [r7, #12] 8009cea: 32ae adds r2, #174 @ 0xae 8009cec: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009cf0: 695b ldr r3, [r3, #20] 8009cf2: 7afa ldrb r2, [r7, #11] 8009cf4: 4611 mov r1, r2 8009cf6: 68f8 ldr r0, [r7, #12] 8009cf8: 4798 blx r3 8009cfa: 4603 mov r3, r0 8009cfc: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 8009cfe: 7dbb ldrb r3, [r7, #22] 8009d00: 2b00 cmp r3, #0 8009d02: d001 beq.n 8009d08 { return ret; 8009d04: 7dbb ldrb r3, [r7, #22] 8009d06: e000 b.n 8009d0a } } } } return USBD_OK; 8009d08: 2300 movs r3, #0 } 8009d0a: 4618 mov r0, r3 8009d0c: 3718 adds r7, #24 8009d0e: 46bd mov sp, r7 8009d10: bd80 pop {r7, pc} 08009d12 : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8009d12: b580 push {r7, lr} 8009d14: b084 sub sp, #16 8009d16: af00 add r7, sp, #0 8009d18: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8009d1a: 2300 movs r3, #0 8009d1c: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8009d1e: 687b ldr r3, [r7, #4] 8009d20: 2201 movs r2, #1 8009d22: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 8009d26: 687b ldr r3, [r7, #4] 8009d28: 2200 movs r2, #0 8009d2a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 8009d2e: 687b ldr r3, [r7, #4] 8009d30: 2200 movs r2, #0 8009d32: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 8009d34: 687b ldr r3, [r7, #4] 8009d36: 2200 movs r2, #0 8009d38: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 8009d3c: 687b ldr r3, [r7, #4] 8009d3e: 2200 movs r2, #0 8009d40: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 8009d44: 687b ldr r3, [r7, #4] 8009d46: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009d4a: 2b00 cmp r3, #0 8009d4c: d014 beq.n 8009d78 { if (pdev->pClass[0]->DeInit != NULL) 8009d4e: 687b ldr r3, [r7, #4] 8009d50: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009d54: 685b ldr r3, [r3, #4] 8009d56: 2b00 cmp r3, #0 8009d58: d00e beq.n 8009d78 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 8009d5a: 687b ldr r3, [r7, #4] 8009d5c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009d60: 685b ldr r3, [r3, #4] 8009d62: 687a ldr r2, [r7, #4] 8009d64: 6852 ldr r2, [r2, #4] 8009d66: b2d2 uxtb r2, r2 8009d68: 4611 mov r1, r2 8009d6a: 6878 ldr r0, [r7, #4] 8009d6c: 4798 blx r3 8009d6e: 4603 mov r3, r0 8009d70: 2b00 cmp r3, #0 8009d72: d001 beq.n 8009d78 { ret = USBD_FAIL; 8009d74: 2303 movs r3, #3 8009d76: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009d78: 2340 movs r3, #64 @ 0x40 8009d7a: 2200 movs r2, #0 8009d7c: 2100 movs r1, #0 8009d7e: 6878 ldr r0, [r7, #4] 8009d80: f001 fb7b bl 800b47a pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8009d84: 687b ldr r3, [r7, #4] 8009d86: 2201 movs r2, #1 8009d88: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8009d8c: 687b ldr r3, [r7, #4] 8009d8e: 2240 movs r2, #64 @ 0x40 8009d90: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009d94: 2340 movs r3, #64 @ 0x40 8009d96: 2200 movs r2, #0 8009d98: 2180 movs r1, #128 @ 0x80 8009d9a: 6878 ldr r0, [r7, #4] 8009d9c: f001 fb6d bl 800b47a pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8009da0: 687b ldr r3, [r7, #4] 8009da2: 2201 movs r2, #1 8009da4: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8009da8: 687b ldr r3, [r7, #4] 8009daa: 2240 movs r2, #64 @ 0x40 8009dac: 841a strh r2, [r3, #32] return ret; 8009dae: 7bfb ldrb r3, [r7, #15] } 8009db0: 4618 mov r0, r3 8009db2: 3710 adds r7, #16 8009db4: 46bd mov sp, r7 8009db6: bd80 pop {r7, pc} 08009db8 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8009db8: b480 push {r7} 8009dba: b083 sub sp, #12 8009dbc: af00 add r7, sp, #0 8009dbe: 6078 str r0, [r7, #4] 8009dc0: 460b mov r3, r1 8009dc2: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8009dc4: 687b ldr r3, [r7, #4] 8009dc6: 78fa ldrb r2, [r7, #3] 8009dc8: 741a strb r2, [r3, #16] return USBD_OK; 8009dca: 2300 movs r3, #0 } 8009dcc: 4618 mov r0, r3 8009dce: 370c adds r7, #12 8009dd0: 46bd mov sp, r7 8009dd2: f85d 7b04 ldr.w r7, [sp], #4 8009dd6: 4770 bx lr 08009dd8 : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8009dd8: b480 push {r7} 8009dda: b083 sub sp, #12 8009ddc: af00 add r7, sp, #0 8009dde: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8009de0: 687b ldr r3, [r7, #4] 8009de2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009de6: b2db uxtb r3, r3 8009de8: 2b04 cmp r3, #4 8009dea: d006 beq.n 8009dfa { pdev->dev_old_state = pdev->dev_state; 8009dec: 687b ldr r3, [r7, #4] 8009dee: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009df2: b2da uxtb r2, r3 8009df4: 687b ldr r3, [r7, #4] 8009df6: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 8009dfa: 687b ldr r3, [r7, #4] 8009dfc: 2204 movs r2, #4 8009dfe: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 8009e02: 2300 movs r3, #0 } 8009e04: 4618 mov r0, r3 8009e06: 370c adds r7, #12 8009e08: 46bd mov sp, r7 8009e0a: f85d 7b04 ldr.w r7, [sp], #4 8009e0e: 4770 bx lr 08009e10 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 8009e10: b480 push {r7} 8009e12: b083 sub sp, #12 8009e14: af00 add r7, sp, #0 8009e16: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 8009e18: 687b ldr r3, [r7, #4] 8009e1a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009e1e: b2db uxtb r3, r3 8009e20: 2b04 cmp r3, #4 8009e22: d106 bne.n 8009e32 { pdev->dev_state = pdev->dev_old_state; 8009e24: 687b ldr r3, [r7, #4] 8009e26: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 8009e2a: b2da uxtb r2, r3 8009e2c: 687b ldr r3, [r7, #4] 8009e2e: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 8009e32: 2300 movs r3, #0 } 8009e34: 4618 mov r0, r3 8009e36: 370c adds r7, #12 8009e38: 46bd mov sp, r7 8009e3a: f85d 7b04 ldr.w r7, [sp], #4 8009e3e: 4770 bx lr 08009e40 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 8009e40: b580 push {r7, lr} 8009e42: b082 sub sp, #8 8009e44: af00 add r7, sp, #0 8009e46: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009e48: 687b ldr r3, [r7, #4] 8009e4a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009e4e: b2db uxtb r3, r3 8009e50: 2b03 cmp r3, #3 8009e52: d110 bne.n 8009e76 } } } } #else if (pdev->pClass[0] != NULL) 8009e54: 687b ldr r3, [r7, #4] 8009e56: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009e5a: 2b00 cmp r3, #0 8009e5c: d00b beq.n 8009e76 { if (pdev->pClass[0]->SOF != NULL) 8009e5e: 687b ldr r3, [r7, #4] 8009e60: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009e64: 69db ldr r3, [r3, #28] 8009e66: 2b00 cmp r3, #0 8009e68: d005 beq.n 8009e76 { (void)pdev->pClass[0]->SOF(pdev); 8009e6a: 687b ldr r3, [r7, #4] 8009e6c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009e70: 69db ldr r3, [r3, #28] 8009e72: 6878 ldr r0, [r7, #4] 8009e74: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 8009e76: 2300 movs r3, #0 } 8009e78: 4618 mov r0, r3 8009e7a: 3708 adds r7, #8 8009e7c: 46bd mov sp, r7 8009e7e: bd80 pop {r7, pc} 08009e80 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009e80: b580 push {r7, lr} 8009e82: b082 sub sp, #8 8009e84: af00 add r7, sp, #0 8009e86: 6078 str r0, [r7, #4] 8009e88: 460b mov r3, r1 8009e8a: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009e8c: 687b ldr r3, [r7, #4] 8009e8e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009e92: 687b ldr r3, [r7, #4] 8009e94: 32ae adds r2, #174 @ 0xae 8009e96: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009e9a: 2b00 cmp r3, #0 8009e9c: d101 bne.n 8009ea2 { return USBD_FAIL; 8009e9e: 2303 movs r3, #3 8009ea0: e01c b.n 8009edc } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009ea2: 687b ldr r3, [r7, #4] 8009ea4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009ea8: b2db uxtb r3, r3 8009eaa: 2b03 cmp r3, #3 8009eac: d115 bne.n 8009eda { if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) 8009eae: 687b ldr r3, [r7, #4] 8009eb0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009eb4: 687b ldr r3, [r7, #4] 8009eb6: 32ae adds r2, #174 @ 0xae 8009eb8: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009ebc: 6a1b ldr r3, [r3, #32] 8009ebe: 2b00 cmp r3, #0 8009ec0: d00b beq.n 8009eda { (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); 8009ec2: 687b ldr r3, [r7, #4] 8009ec4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009ec8: 687b ldr r3, [r7, #4] 8009eca: 32ae adds r2, #174 @ 0xae 8009ecc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009ed0: 6a1b ldr r3, [r3, #32] 8009ed2: 78fa ldrb r2, [r7, #3] 8009ed4: 4611 mov r1, r2 8009ed6: 6878 ldr r0, [r7, #4] 8009ed8: 4798 blx r3 } } return USBD_OK; 8009eda: 2300 movs r3, #0 } 8009edc: 4618 mov r0, r3 8009ede: 3708 adds r7, #8 8009ee0: 46bd mov sp, r7 8009ee2: bd80 pop {r7, pc} 08009ee4 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009ee4: b580 push {r7, lr} 8009ee6: b082 sub sp, #8 8009ee8: af00 add r7, sp, #0 8009eea: 6078 str r0, [r7, #4] 8009eec: 460b mov r3, r1 8009eee: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009ef0: 687b ldr r3, [r7, #4] 8009ef2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009ef6: 687b ldr r3, [r7, #4] 8009ef8: 32ae adds r2, #174 @ 0xae 8009efa: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009efe: 2b00 cmp r3, #0 8009f00: d101 bne.n 8009f06 { return USBD_FAIL; 8009f02: 2303 movs r3, #3 8009f04: e01c b.n 8009f40 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009f06: 687b ldr r3, [r7, #4] 8009f08: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009f0c: b2db uxtb r3, r3 8009f0e: 2b03 cmp r3, #3 8009f10: d115 bne.n 8009f3e { if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) 8009f12: 687b ldr r3, [r7, #4] 8009f14: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009f18: 687b ldr r3, [r7, #4] 8009f1a: 32ae adds r2, #174 @ 0xae 8009f1c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009f20: 6a5b ldr r3, [r3, #36] @ 0x24 8009f22: 2b00 cmp r3, #0 8009f24: d00b beq.n 8009f3e { (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); 8009f26: 687b ldr r3, [r7, #4] 8009f28: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009f2c: 687b ldr r3, [r7, #4] 8009f2e: 32ae adds r2, #174 @ 0xae 8009f30: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009f34: 6a5b ldr r3, [r3, #36] @ 0x24 8009f36: 78fa ldrb r2, [r7, #3] 8009f38: 4611 mov r1, r2 8009f3a: 6878 ldr r0, [r7, #4] 8009f3c: 4798 blx r3 } } return USBD_OK; 8009f3e: 2300 movs r3, #0 } 8009f40: 4618 mov r0, r3 8009f42: 3708 adds r7, #8 8009f44: 46bd mov sp, r7 8009f46: bd80 pop {r7, pc} 08009f48 : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 8009f48: b480 push {r7} 8009f4a: b083 sub sp, #12 8009f4c: af00 add r7, sp, #0 8009f4e: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8009f50: 2300 movs r3, #0 } 8009f52: 4618 mov r0, r3 8009f54: 370c adds r7, #12 8009f56: 46bd mov sp, r7 8009f58: f85d 7b04 ldr.w r7, [sp], #4 8009f5c: 4770 bx lr 08009f5e : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 8009f5e: b580 push {r7, lr} 8009f60: b084 sub sp, #16 8009f62: af00 add r7, sp, #0 8009f64: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8009f66: 2300 movs r3, #0 8009f68: 73fb strb r3, [r7, #15] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 8009f6a: 687b ldr r3, [r7, #4] 8009f6c: 2201 movs r2, #1 8009f6e: f883 229c strb.w r2, [r3, #668] @ 0x29c } } } } #else if (pdev->pClass[0] != NULL) 8009f72: 687b ldr r3, [r7, #4] 8009f74: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009f78: 2b00 cmp r3, #0 8009f7a: d00e beq.n 8009f9a { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) 8009f7c: 687b ldr r3, [r7, #4] 8009f7e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009f82: 685b ldr r3, [r3, #4] 8009f84: 687a ldr r2, [r7, #4] 8009f86: 6852 ldr r2, [r2, #4] 8009f88: b2d2 uxtb r2, r2 8009f8a: 4611 mov r1, r2 8009f8c: 6878 ldr r0, [r7, #4] 8009f8e: 4798 blx r3 8009f90: 4603 mov r3, r0 8009f92: 2b00 cmp r3, #0 8009f94: d001 beq.n 8009f9a { ret = USBD_FAIL; 8009f96: 2303 movs r3, #3 8009f98: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ return ret; 8009f9a: 7bfb ldrb r3, [r7, #15] } 8009f9c: 4618 mov r0, r3 8009f9e: 3710 adds r7, #16 8009fa0: 46bd mov sp, r7 8009fa2: bd80 pop {r7, pc} 08009fa4 : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 8009fa4: b480 push {r7} 8009fa6: b083 sub sp, #12 8009fa8: af00 add r7, sp, #0 8009faa: 6078 str r0, [r7, #4] 8009fac: 460b mov r3, r1 8009fae: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009fb0: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009fb2: 4618 mov r0, r3 8009fb4: 370c adds r7, #12 8009fb6: 46bd mov sp, r7 8009fb8: f85d 7b04 ldr.w r7, [sp], #4 8009fbc: 4770 bx lr 08009fbe : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 8009fbe: b480 push {r7} 8009fc0: b083 sub sp, #12 8009fc2: af00 add r7, sp, #0 8009fc4: 6078 str r0, [r7, #4] 8009fc6: 460b mov r3, r1 8009fc8: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009fca: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009fcc: 4618 mov r0, r3 8009fce: 370c adds r7, #12 8009fd0: 46bd mov sp, r7 8009fd2: f85d 7b04 ldr.w r7, [sp], #4 8009fd6: 4770 bx lr 08009fd8 : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 8009fd8: b580 push {r7, lr} 8009fda: b086 sub sp, #24 8009fdc: af00 add r7, sp, #0 8009fde: 6078 str r0, [r7, #4] 8009fe0: 460b mov r3, r1 8009fe2: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 8009fe4: 687b ldr r3, [r7, #4] 8009fe6: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 8009fe8: 687b ldr r3, [r7, #4] 8009fea: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 8009fec: 2300 movs r3, #0 8009fee: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8009ff0: 68fb ldr r3, [r7, #12] 8009ff2: 885b ldrh r3, [r3, #2] 8009ff4: b29b uxth r3, r3 8009ff6: 68fa ldr r2, [r7, #12] 8009ff8: 7812 ldrb r2, [r2, #0] 8009ffa: 4293 cmp r3, r2 8009ffc: d91f bls.n 800a03e { ptr = desc->bLength; 8009ffe: 68fb ldr r3, [r7, #12] 800a000: 781b ldrb r3, [r3, #0] 800a002: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 800a004: e013 b.n 800a02e { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 800a006: f107 030a add.w r3, r7, #10 800a00a: 4619 mov r1, r3 800a00c: 6978 ldr r0, [r7, #20] 800a00e: f000 f81b bl 800a048 800a012: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 800a014: 697b ldr r3, [r7, #20] 800a016: 785b ldrb r3, [r3, #1] 800a018: 2b05 cmp r3, #5 800a01a: d108 bne.n 800a02e { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 800a01c: 697b ldr r3, [r7, #20] 800a01e: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 800a020: 693b ldr r3, [r7, #16] 800a022: 789b ldrb r3, [r3, #2] 800a024: 78fa ldrb r2, [r7, #3] 800a026: 429a cmp r2, r3 800a028: d008 beq.n 800a03c { break; } else { pEpDesc = NULL; 800a02a: 2300 movs r3, #0 800a02c: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 800a02e: 68fb ldr r3, [r7, #12] 800a030: 885b ldrh r3, [r3, #2] 800a032: b29a uxth r2, r3 800a034: 897b ldrh r3, [r7, #10] 800a036: 429a cmp r2, r3 800a038: d8e5 bhi.n 800a006 800a03a: e000 b.n 800a03e break; 800a03c: bf00 nop } } } } return (void *)pEpDesc; 800a03e: 693b ldr r3, [r7, #16] } 800a040: 4618 mov r0, r3 800a042: 3718 adds r7, #24 800a044: 46bd mov sp, r7 800a046: bd80 pop {r7, pc} 0800a048 : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 800a048: b480 push {r7} 800a04a: b085 sub sp, #20 800a04c: af00 add r7, sp, #0 800a04e: 6078 str r0, [r7, #4] 800a050: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 800a052: 687b ldr r3, [r7, #4] 800a054: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 800a056: 683b ldr r3, [r7, #0] 800a058: 881b ldrh r3, [r3, #0] 800a05a: 68fa ldr r2, [r7, #12] 800a05c: 7812 ldrb r2, [r2, #0] 800a05e: 4413 add r3, r2 800a060: b29a uxth r2, r3 800a062: 683b ldr r3, [r7, #0] 800a064: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 800a066: 68fb ldr r3, [r7, #12] 800a068: 781b ldrb r3, [r3, #0] 800a06a: 461a mov r2, r3 800a06c: 687b ldr r3, [r7, #4] 800a06e: 4413 add r3, r2 800a070: 60fb str r3, [r7, #12] return (pnext); 800a072: 68fb ldr r3, [r7, #12] } 800a074: 4618 mov r0, r3 800a076: 3714 adds r7, #20 800a078: 46bd mov sp, r7 800a07a: f85d 7b04 ldr.w r7, [sp], #4 800a07e: 4770 bx lr 0800a080 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 800a080: b480 push {r7} 800a082: b087 sub sp, #28 800a084: af00 add r7, sp, #0 800a086: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 800a088: 687b ldr r3, [r7, #4] 800a08a: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 800a08c: 697b ldr r3, [r7, #20] 800a08e: 781b ldrb r3, [r3, #0] 800a090: 827b strh r3, [r7, #18] _pbuff++; 800a092: 697b ldr r3, [r7, #20] 800a094: 3301 adds r3, #1 800a096: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 800a098: 697b ldr r3, [r7, #20] 800a09a: 781b ldrb r3, [r3, #0] 800a09c: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 800a09e: f9b7 3010 ldrsh.w r3, [r7, #16] 800a0a2: 021b lsls r3, r3, #8 800a0a4: b21a sxth r2, r3 800a0a6: f9b7 3012 ldrsh.w r3, [r7, #18] 800a0aa: 4313 orrs r3, r2 800a0ac: b21b sxth r3, r3 800a0ae: 81fb strh r3, [r7, #14] return _SwapVal; 800a0b0: 89fb ldrh r3, [r7, #14] } 800a0b2: 4618 mov r0, r3 800a0b4: 371c adds r7, #28 800a0b6: 46bd mov sp, r7 800a0b8: f85d 7b04 ldr.w r7, [sp], #4 800a0bc: 4770 bx lr ... 0800a0c0 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a0c0: b580 push {r7, lr} 800a0c2: b084 sub sp, #16 800a0c4: af00 add r7, sp, #0 800a0c6: 6078 str r0, [r7, #4] 800a0c8: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800a0ca: 2300 movs r3, #0 800a0cc: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800a0ce: 683b ldr r3, [r7, #0] 800a0d0: 781b ldrb r3, [r3, #0] 800a0d2: f003 0360 and.w r3, r3, #96 @ 0x60 800a0d6: 2b40 cmp r3, #64 @ 0x40 800a0d8: d005 beq.n 800a0e6 800a0da: 2b40 cmp r3, #64 @ 0x40 800a0dc: d857 bhi.n 800a18e 800a0de: 2b00 cmp r3, #0 800a0e0: d00f beq.n 800a102 800a0e2: 2b20 cmp r3, #32 800a0e4: d153 bne.n 800a18e { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 800a0e6: 687b ldr r3, [r7, #4] 800a0e8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800a0ec: 687b ldr r3, [r7, #4] 800a0ee: 32ae adds r2, #174 @ 0xae 800a0f0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a0f4: 689b ldr r3, [r3, #8] 800a0f6: 6839 ldr r1, [r7, #0] 800a0f8: 6878 ldr r0, [r7, #4] 800a0fa: 4798 blx r3 800a0fc: 4603 mov r3, r0 800a0fe: 73fb strb r3, [r7, #15] break; 800a100: e04a b.n 800a198 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800a102: 683b ldr r3, [r7, #0] 800a104: 785b ldrb r3, [r3, #1] 800a106: 2b09 cmp r3, #9 800a108: d83b bhi.n 800a182 800a10a: a201 add r2, pc, #4 @ (adr r2, 800a110 ) 800a10c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a110: 0800a165 .word 0x0800a165 800a114: 0800a179 .word 0x0800a179 800a118: 0800a183 .word 0x0800a183 800a11c: 0800a16f .word 0x0800a16f 800a120: 0800a183 .word 0x0800a183 800a124: 0800a143 .word 0x0800a143 800a128: 0800a139 .word 0x0800a139 800a12c: 0800a183 .word 0x0800a183 800a130: 0800a15b .word 0x0800a15b 800a134: 0800a14d .word 0x0800a14d { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 800a138: 6839 ldr r1, [r7, #0] 800a13a: 6878 ldr r0, [r7, #4] 800a13c: f000 fa3e bl 800a5bc break; 800a140: e024 b.n 800a18c case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 800a142: 6839 ldr r1, [r7, #0] 800a144: 6878 ldr r0, [r7, #4] 800a146: f000 fbcd bl 800a8e4 break; 800a14a: e01f b.n 800a18c case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 800a14c: 6839 ldr r1, [r7, #0] 800a14e: 6878 ldr r0, [r7, #4] 800a150: f000 fc0c bl 800a96c 800a154: 4603 mov r3, r0 800a156: 73fb strb r3, [r7, #15] break; 800a158: e018 b.n 800a18c case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 800a15a: 6839 ldr r1, [r7, #0] 800a15c: 6878 ldr r0, [r7, #4] 800a15e: f000 fcaf bl 800aac0 break; 800a162: e013 b.n 800a18c case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 800a164: 6839 ldr r1, [r7, #0] 800a166: 6878 ldr r0, [r7, #4] 800a168: f000 fce0 bl 800ab2c break; 800a16c: e00e b.n 800a18c case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 800a16e: 6839 ldr r1, [r7, #0] 800a170: 6878 ldr r0, [r7, #4] 800a172: f000 fd0f bl 800ab94 break; 800a176: e009 b.n 800a18c case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 800a178: 6839 ldr r1, [r7, #0] 800a17a: 6878 ldr r0, [r7, #4] 800a17c: f000 fd33 bl 800abe6 break; 800a180: e004 b.n 800a18c default: USBD_CtlError(pdev, req); 800a182: 6839 ldr r1, [r7, #0] 800a184: 6878 ldr r0, [r7, #4] 800a186: f000 fd8a bl 800ac9e break; 800a18a: bf00 nop } break; 800a18c: e004 b.n 800a198 default: USBD_CtlError(pdev, req); 800a18e: 6839 ldr r1, [r7, #0] 800a190: 6878 ldr r0, [r7, #4] 800a192: f000 fd84 bl 800ac9e break; 800a196: bf00 nop } return ret; 800a198: 7bfb ldrb r3, [r7, #15] } 800a19a: 4618 mov r0, r3 800a19c: 3710 adds r7, #16 800a19e: 46bd mov sp, r7 800a1a0: bd80 pop {r7, pc} 800a1a2: bf00 nop 0800a1a4 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a1a4: b580 push {r7, lr} 800a1a6: b084 sub sp, #16 800a1a8: af00 add r7, sp, #0 800a1aa: 6078 str r0, [r7, #4] 800a1ac: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800a1ae: 2300 movs r3, #0 800a1b0: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 800a1b2: 683b ldr r3, [r7, #0] 800a1b4: 781b ldrb r3, [r3, #0] 800a1b6: f003 0360 and.w r3, r3, #96 @ 0x60 800a1ba: 2b40 cmp r3, #64 @ 0x40 800a1bc: d005 beq.n 800a1ca 800a1be: 2b40 cmp r3, #64 @ 0x40 800a1c0: d852 bhi.n 800a268 800a1c2: 2b00 cmp r3, #0 800a1c4: d001 beq.n 800a1ca 800a1c6: 2b20 cmp r3, #32 800a1c8: d14e bne.n 800a268 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 800a1ca: 687b ldr r3, [r7, #4] 800a1cc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a1d0: b2db uxtb r3, r3 800a1d2: 3b01 subs r3, #1 800a1d4: 2b02 cmp r3, #2 800a1d6: d840 bhi.n 800a25a { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 800a1d8: 683b ldr r3, [r7, #0] 800a1da: 889b ldrh r3, [r3, #4] 800a1dc: b2db uxtb r3, r3 800a1de: 2b01 cmp r3, #1 800a1e0: d836 bhi.n 800a250 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 800a1e2: 683b ldr r3, [r7, #0] 800a1e4: 889b ldrh r3, [r3, #4] 800a1e6: b2db uxtb r3, r3 800a1e8: 4619 mov r1, r3 800a1ea: 6878 ldr r0, [r7, #4] 800a1ec: f7ff feda bl 8009fa4 800a1f0: 4603 mov r3, r0 800a1f2: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800a1f4: 7bbb ldrb r3, [r7, #14] 800a1f6: 2bff cmp r3, #255 @ 0xff 800a1f8: d01d beq.n 800a236 800a1fa: 7bbb ldrb r3, [r7, #14] 800a1fc: 2b00 cmp r3, #0 800a1fe: d11a bne.n 800a236 { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 800a200: 7bba ldrb r2, [r7, #14] 800a202: 687b ldr r3, [r7, #4] 800a204: 32ae adds r2, #174 @ 0xae 800a206: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a20a: 689b ldr r3, [r3, #8] 800a20c: 2b00 cmp r3, #0 800a20e: d00f beq.n 800a230 { pdev->classId = idx; 800a210: 7bba ldrb r2, [r7, #14] 800a212: 687b ldr r3, [r7, #4] 800a214: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 800a218: 7bba ldrb r2, [r7, #14] 800a21a: 687b ldr r3, [r7, #4] 800a21c: 32ae adds r2, #174 @ 0xae 800a21e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a222: 689b ldr r3, [r3, #8] 800a224: 6839 ldr r1, [r7, #0] 800a226: 6878 ldr r0, [r7, #4] 800a228: 4798 blx r3 800a22a: 4603 mov r3, r0 800a22c: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 800a22e: e004 b.n 800a23a } else { /* should never reach this condition */ ret = USBD_FAIL; 800a230: 2303 movs r3, #3 800a232: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 800a234: e001 b.n 800a23a } } else { /* No relative interface found */ ret = USBD_FAIL; 800a236: 2303 movs r3, #3 800a238: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 800a23a: 683b ldr r3, [r7, #0] 800a23c: 88db ldrh r3, [r3, #6] 800a23e: 2b00 cmp r3, #0 800a240: d110 bne.n 800a264 800a242: 7bfb ldrb r3, [r7, #15] 800a244: 2b00 cmp r3, #0 800a246: d10d bne.n 800a264 { (void)USBD_CtlSendStatus(pdev); 800a248: 6878 ldr r0, [r7, #4] 800a24a: f000 fde5 bl 800ae18 } else { USBD_CtlError(pdev, req); } break; 800a24e: e009 b.n 800a264 USBD_CtlError(pdev, req); 800a250: 6839 ldr r1, [r7, #0] 800a252: 6878 ldr r0, [r7, #4] 800a254: f000 fd23 bl 800ac9e break; 800a258: e004 b.n 800a264 default: USBD_CtlError(pdev, req); 800a25a: 6839 ldr r1, [r7, #0] 800a25c: 6878 ldr r0, [r7, #4] 800a25e: f000 fd1e bl 800ac9e break; 800a262: e000 b.n 800a266 break; 800a264: bf00 nop } break; 800a266: e004 b.n 800a272 default: USBD_CtlError(pdev, req); 800a268: 6839 ldr r1, [r7, #0] 800a26a: 6878 ldr r0, [r7, #4] 800a26c: f000 fd17 bl 800ac9e break; 800a270: bf00 nop } return ret; 800a272: 7bfb ldrb r3, [r7, #15] } 800a274: 4618 mov r0, r3 800a276: 3710 adds r7, #16 800a278: 46bd mov sp, r7 800a27a: bd80 pop {r7, pc} 0800a27c : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a27c: b580 push {r7, lr} 800a27e: b084 sub sp, #16 800a280: af00 add r7, sp, #0 800a282: 6078 str r0, [r7, #4] 800a284: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 800a286: 2300 movs r3, #0 800a288: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 800a28a: 683b ldr r3, [r7, #0] 800a28c: 889b ldrh r3, [r3, #4] 800a28e: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800a290: 683b ldr r3, [r7, #0] 800a292: 781b ldrb r3, [r3, #0] 800a294: f003 0360 and.w r3, r3, #96 @ 0x60 800a298: 2b40 cmp r3, #64 @ 0x40 800a29a: d007 beq.n 800a2ac 800a29c: 2b40 cmp r3, #64 @ 0x40 800a29e: f200 8181 bhi.w 800a5a4 800a2a2: 2b00 cmp r3, #0 800a2a4: d02a beq.n 800a2fc 800a2a6: 2b20 cmp r3, #32 800a2a8: f040 817c bne.w 800a5a4 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 800a2ac: 7bbb ldrb r3, [r7, #14] 800a2ae: 4619 mov r1, r3 800a2b0: 6878 ldr r0, [r7, #4] 800a2b2: f7ff fe84 bl 8009fbe 800a2b6: 4603 mov r3, r0 800a2b8: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800a2ba: 7b7b ldrb r3, [r7, #13] 800a2bc: 2bff cmp r3, #255 @ 0xff 800a2be: f000 8176 beq.w 800a5ae 800a2c2: 7b7b ldrb r3, [r7, #13] 800a2c4: 2b00 cmp r3, #0 800a2c6: f040 8172 bne.w 800a5ae { pdev->classId = idx; 800a2ca: 7b7a ldrb r2, [r7, #13] 800a2cc: 687b ldr r3, [r7, #4] 800a2ce: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 800a2d2: 7b7a ldrb r2, [r7, #13] 800a2d4: 687b ldr r3, [r7, #4] 800a2d6: 32ae adds r2, #174 @ 0xae 800a2d8: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a2dc: 689b ldr r3, [r3, #8] 800a2de: 2b00 cmp r3, #0 800a2e0: f000 8165 beq.w 800a5ae { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 800a2e4: 7b7a ldrb r2, [r7, #13] 800a2e6: 687b ldr r3, [r7, #4] 800a2e8: 32ae adds r2, #174 @ 0xae 800a2ea: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a2ee: 689b ldr r3, [r3, #8] 800a2f0: 6839 ldr r1, [r7, #0] 800a2f2: 6878 ldr r0, [r7, #4] 800a2f4: 4798 blx r3 800a2f6: 4603 mov r3, r0 800a2f8: 73fb strb r3, [r7, #15] } } break; 800a2fa: e158 b.n 800a5ae case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800a2fc: 683b ldr r3, [r7, #0] 800a2fe: 785b ldrb r3, [r3, #1] 800a300: 2b03 cmp r3, #3 800a302: d008 beq.n 800a316 800a304: 2b03 cmp r3, #3 800a306: f300 8147 bgt.w 800a598 800a30a: 2b00 cmp r3, #0 800a30c: f000 809b beq.w 800a446 800a310: 2b01 cmp r3, #1 800a312: d03c beq.n 800a38e 800a314: e140 b.n 800a598 { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 800a316: 687b ldr r3, [r7, #4] 800a318: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a31c: b2db uxtb r3, r3 800a31e: 2b02 cmp r3, #2 800a320: d002 beq.n 800a328 800a322: 2b03 cmp r3, #3 800a324: d016 beq.n 800a354 800a326: e02c b.n 800a382 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800a328: 7bbb ldrb r3, [r7, #14] 800a32a: 2b00 cmp r3, #0 800a32c: d00d beq.n 800a34a 800a32e: 7bbb ldrb r3, [r7, #14] 800a330: 2b80 cmp r3, #128 @ 0x80 800a332: d00a beq.n 800a34a { (void)USBD_LL_StallEP(pdev, ep_addr); 800a334: 7bbb ldrb r3, [r7, #14] 800a336: 4619 mov r1, r3 800a338: 6878 ldr r0, [r7, #4] 800a33a: f001 f8e3 bl 800b504 (void)USBD_LL_StallEP(pdev, 0x80U); 800a33e: 2180 movs r1, #128 @ 0x80 800a340: 6878 ldr r0, [r7, #4] 800a342: f001 f8df bl 800b504 800a346: bf00 nop } else { USBD_CtlError(pdev, req); } break; 800a348: e020 b.n 800a38c USBD_CtlError(pdev, req); 800a34a: 6839 ldr r1, [r7, #0] 800a34c: 6878 ldr r0, [r7, #4] 800a34e: f000 fca6 bl 800ac9e break; 800a352: e01b b.n 800a38c case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 800a354: 683b ldr r3, [r7, #0] 800a356: 885b ldrh r3, [r3, #2] 800a358: 2b00 cmp r3, #0 800a35a: d10e bne.n 800a37a { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 800a35c: 7bbb ldrb r3, [r7, #14] 800a35e: 2b00 cmp r3, #0 800a360: d00b beq.n 800a37a 800a362: 7bbb ldrb r3, [r7, #14] 800a364: 2b80 cmp r3, #128 @ 0x80 800a366: d008 beq.n 800a37a 800a368: 683b ldr r3, [r7, #0] 800a36a: 88db ldrh r3, [r3, #6] 800a36c: 2b00 cmp r3, #0 800a36e: d104 bne.n 800a37a { (void)USBD_LL_StallEP(pdev, ep_addr); 800a370: 7bbb ldrb r3, [r7, #14] 800a372: 4619 mov r1, r3 800a374: 6878 ldr r0, [r7, #4] 800a376: f001 f8c5 bl 800b504 } } (void)USBD_CtlSendStatus(pdev); 800a37a: 6878 ldr r0, [r7, #4] 800a37c: f000 fd4c bl 800ae18 break; 800a380: e004 b.n 800a38c default: USBD_CtlError(pdev, req); 800a382: 6839 ldr r1, [r7, #0] 800a384: 6878 ldr r0, [r7, #4] 800a386: f000 fc8a bl 800ac9e break; 800a38a: bf00 nop } break; 800a38c: e109 b.n 800a5a2 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 800a38e: 687b ldr r3, [r7, #4] 800a390: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a394: b2db uxtb r3, r3 800a396: 2b02 cmp r3, #2 800a398: d002 beq.n 800a3a0 800a39a: 2b03 cmp r3, #3 800a39c: d016 beq.n 800a3cc 800a39e: e04b b.n 800a438 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800a3a0: 7bbb ldrb r3, [r7, #14] 800a3a2: 2b00 cmp r3, #0 800a3a4: d00d beq.n 800a3c2 800a3a6: 7bbb ldrb r3, [r7, #14] 800a3a8: 2b80 cmp r3, #128 @ 0x80 800a3aa: d00a beq.n 800a3c2 { (void)USBD_LL_StallEP(pdev, ep_addr); 800a3ac: 7bbb ldrb r3, [r7, #14] 800a3ae: 4619 mov r1, r3 800a3b0: 6878 ldr r0, [r7, #4] 800a3b2: f001 f8a7 bl 800b504 (void)USBD_LL_StallEP(pdev, 0x80U); 800a3b6: 2180 movs r1, #128 @ 0x80 800a3b8: 6878 ldr r0, [r7, #4] 800a3ba: f001 f8a3 bl 800b504 800a3be: bf00 nop } else { USBD_CtlError(pdev, req); } break; 800a3c0: e040 b.n 800a444 USBD_CtlError(pdev, req); 800a3c2: 6839 ldr r1, [r7, #0] 800a3c4: 6878 ldr r0, [r7, #4] 800a3c6: f000 fc6a bl 800ac9e break; 800a3ca: e03b b.n 800a444 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 800a3cc: 683b ldr r3, [r7, #0] 800a3ce: 885b ldrh r3, [r3, #2] 800a3d0: 2b00 cmp r3, #0 800a3d2: d136 bne.n 800a442 { if ((ep_addr & 0x7FU) != 0x00U) 800a3d4: 7bbb ldrb r3, [r7, #14] 800a3d6: f003 037f and.w r3, r3, #127 @ 0x7f 800a3da: 2b00 cmp r3, #0 800a3dc: d004 beq.n 800a3e8 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 800a3de: 7bbb ldrb r3, [r7, #14] 800a3e0: 4619 mov r1, r3 800a3e2: 6878 ldr r0, [r7, #4] 800a3e4: f001 f8ad bl 800b542 } (void)USBD_CtlSendStatus(pdev); 800a3e8: 6878 ldr r0, [r7, #4] 800a3ea: f000 fd15 bl 800ae18 /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 800a3ee: 7bbb ldrb r3, [r7, #14] 800a3f0: 4619 mov r1, r3 800a3f2: 6878 ldr r0, [r7, #4] 800a3f4: f7ff fde3 bl 8009fbe 800a3f8: 4603 mov r3, r0 800a3fa: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800a3fc: 7b7b ldrb r3, [r7, #13] 800a3fe: 2bff cmp r3, #255 @ 0xff 800a400: d01f beq.n 800a442 800a402: 7b7b ldrb r3, [r7, #13] 800a404: 2b00 cmp r3, #0 800a406: d11c bne.n 800a442 { pdev->classId = idx; 800a408: 7b7a ldrb r2, [r7, #13] 800a40a: 687b ldr r3, [r7, #4] 800a40c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 800a410: 7b7a ldrb r2, [r7, #13] 800a412: 687b ldr r3, [r7, #4] 800a414: 32ae adds r2, #174 @ 0xae 800a416: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a41a: 689b ldr r3, [r3, #8] 800a41c: 2b00 cmp r3, #0 800a41e: d010 beq.n 800a442 { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 800a420: 7b7a ldrb r2, [r7, #13] 800a422: 687b ldr r3, [r7, #4] 800a424: 32ae adds r2, #174 @ 0xae 800a426: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a42a: 689b ldr r3, [r3, #8] 800a42c: 6839 ldr r1, [r7, #0] 800a42e: 6878 ldr r0, [r7, #4] 800a430: 4798 blx r3 800a432: 4603 mov r3, r0 800a434: 73fb strb r3, [r7, #15] } } } break; 800a436: e004 b.n 800a442 default: USBD_CtlError(pdev, req); 800a438: 6839 ldr r1, [r7, #0] 800a43a: 6878 ldr r0, [r7, #4] 800a43c: f000 fc2f bl 800ac9e break; 800a440: e000 b.n 800a444 break; 800a442: bf00 nop } break; 800a444: e0ad b.n 800a5a2 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 800a446: 687b ldr r3, [r7, #4] 800a448: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a44c: b2db uxtb r3, r3 800a44e: 2b02 cmp r3, #2 800a450: d002 beq.n 800a458 800a452: 2b03 cmp r3, #3 800a454: d033 beq.n 800a4be 800a456: e099 b.n 800a58c { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800a458: 7bbb ldrb r3, [r7, #14] 800a45a: 2b00 cmp r3, #0 800a45c: d007 beq.n 800a46e 800a45e: 7bbb ldrb r3, [r7, #14] 800a460: 2b80 cmp r3, #128 @ 0x80 800a462: d004 beq.n 800a46e { USBD_CtlError(pdev, req); 800a464: 6839 ldr r1, [r7, #0] 800a466: 6878 ldr r0, [r7, #4] 800a468: f000 fc19 bl 800ac9e break; 800a46c: e093 b.n 800a596 } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a46e: f997 300e ldrsb.w r3, [r7, #14] 800a472: 2b00 cmp r3, #0 800a474: da0b bge.n 800a48e 800a476: 7bbb ldrb r3, [r7, #14] 800a478: f003 027f and.w r2, r3, #127 @ 0x7f 800a47c: 4613 mov r3, r2 800a47e: 009b lsls r3, r3, #2 800a480: 4413 add r3, r2 800a482: 009b lsls r3, r3, #2 800a484: 3310 adds r3, #16 800a486: 687a ldr r2, [r7, #4] 800a488: 4413 add r3, r2 800a48a: 3304 adds r3, #4 800a48c: e00b b.n 800a4a6 &pdev->ep_out[ep_addr & 0x7FU]; 800a48e: 7bbb ldrb r3, [r7, #14] 800a490: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a494: 4613 mov r3, r2 800a496: 009b lsls r3, r3, #2 800a498: 4413 add r3, r2 800a49a: 009b lsls r3, r3, #2 800a49c: f503 73a8 add.w r3, r3, #336 @ 0x150 800a4a0: 687a ldr r2, [r7, #4] 800a4a2: 4413 add r3, r2 800a4a4: 3304 adds r3, #4 800a4a6: 60bb str r3, [r7, #8] pep->status = 0x0000U; 800a4a8: 68bb ldr r3, [r7, #8] 800a4aa: 2200 movs r2, #0 800a4ac: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 800a4ae: 68bb ldr r3, [r7, #8] 800a4b0: 330e adds r3, #14 800a4b2: 2202 movs r2, #2 800a4b4: 4619 mov r1, r3 800a4b6: 6878 ldr r0, [r7, #4] 800a4b8: f000 fc6e bl 800ad98 break; 800a4bc: e06b b.n 800a596 case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 800a4be: f997 300e ldrsb.w r3, [r7, #14] 800a4c2: 2b00 cmp r3, #0 800a4c4: da11 bge.n 800a4ea { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 800a4c6: 7bbb ldrb r3, [r7, #14] 800a4c8: f003 020f and.w r2, r3, #15 800a4cc: 6879 ldr r1, [r7, #4] 800a4ce: 4613 mov r3, r2 800a4d0: 009b lsls r3, r3, #2 800a4d2: 4413 add r3, r2 800a4d4: 009b lsls r3, r3, #2 800a4d6: 440b add r3, r1 800a4d8: 3323 adds r3, #35 @ 0x23 800a4da: 781b ldrb r3, [r3, #0] 800a4dc: 2b00 cmp r3, #0 800a4de: d117 bne.n 800a510 { USBD_CtlError(pdev, req); 800a4e0: 6839 ldr r1, [r7, #0] 800a4e2: 6878 ldr r0, [r7, #4] 800a4e4: f000 fbdb bl 800ac9e break; 800a4e8: e055 b.n 800a596 } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 800a4ea: 7bbb ldrb r3, [r7, #14] 800a4ec: f003 020f and.w r2, r3, #15 800a4f0: 6879 ldr r1, [r7, #4] 800a4f2: 4613 mov r3, r2 800a4f4: 009b lsls r3, r3, #2 800a4f6: 4413 add r3, r2 800a4f8: 009b lsls r3, r3, #2 800a4fa: 440b add r3, r1 800a4fc: f203 1363 addw r3, r3, #355 @ 0x163 800a500: 781b ldrb r3, [r3, #0] 800a502: 2b00 cmp r3, #0 800a504: d104 bne.n 800a510 { USBD_CtlError(pdev, req); 800a506: 6839 ldr r1, [r7, #0] 800a508: 6878 ldr r0, [r7, #4] 800a50a: f000 fbc8 bl 800ac9e break; 800a50e: e042 b.n 800a596 } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a510: f997 300e ldrsb.w r3, [r7, #14] 800a514: 2b00 cmp r3, #0 800a516: da0b bge.n 800a530 800a518: 7bbb ldrb r3, [r7, #14] 800a51a: f003 027f and.w r2, r3, #127 @ 0x7f 800a51e: 4613 mov r3, r2 800a520: 009b lsls r3, r3, #2 800a522: 4413 add r3, r2 800a524: 009b lsls r3, r3, #2 800a526: 3310 adds r3, #16 800a528: 687a ldr r2, [r7, #4] 800a52a: 4413 add r3, r2 800a52c: 3304 adds r3, #4 800a52e: e00b b.n 800a548 &pdev->ep_out[ep_addr & 0x7FU]; 800a530: 7bbb ldrb r3, [r7, #14] 800a532: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a536: 4613 mov r3, r2 800a538: 009b lsls r3, r3, #2 800a53a: 4413 add r3, r2 800a53c: 009b lsls r3, r3, #2 800a53e: f503 73a8 add.w r3, r3, #336 @ 0x150 800a542: 687a ldr r2, [r7, #4] 800a544: 4413 add r3, r2 800a546: 3304 adds r3, #4 800a548: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 800a54a: 7bbb ldrb r3, [r7, #14] 800a54c: 2b00 cmp r3, #0 800a54e: d002 beq.n 800a556 800a550: 7bbb ldrb r3, [r7, #14] 800a552: 2b80 cmp r3, #128 @ 0x80 800a554: d103 bne.n 800a55e { pep->status = 0x0000U; 800a556: 68bb ldr r3, [r7, #8] 800a558: 2200 movs r2, #0 800a55a: 739a strb r2, [r3, #14] 800a55c: e00e b.n 800a57c } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 800a55e: 7bbb ldrb r3, [r7, #14] 800a560: 4619 mov r1, r3 800a562: 6878 ldr r0, [r7, #4] 800a564: f001 f80c bl 800b580 800a568: 4603 mov r3, r0 800a56a: 2b00 cmp r3, #0 800a56c: d003 beq.n 800a576 { pep->status = 0x0001U; 800a56e: 68bb ldr r3, [r7, #8] 800a570: 2201 movs r2, #1 800a572: 739a strb r2, [r3, #14] 800a574: e002 b.n 800a57c } else { pep->status = 0x0000U; 800a576: 68bb ldr r3, [r7, #8] 800a578: 2200 movs r2, #0 800a57a: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 800a57c: 68bb ldr r3, [r7, #8] 800a57e: 330e adds r3, #14 800a580: 2202 movs r2, #2 800a582: 4619 mov r1, r3 800a584: 6878 ldr r0, [r7, #4] 800a586: f000 fc07 bl 800ad98 break; 800a58a: e004 b.n 800a596 default: USBD_CtlError(pdev, req); 800a58c: 6839 ldr r1, [r7, #0] 800a58e: 6878 ldr r0, [r7, #4] 800a590: f000 fb85 bl 800ac9e break; 800a594: bf00 nop } break; 800a596: e004 b.n 800a5a2 default: USBD_CtlError(pdev, req); 800a598: 6839 ldr r1, [r7, #0] 800a59a: 6878 ldr r0, [r7, #4] 800a59c: f000 fb7f bl 800ac9e break; 800a5a0: bf00 nop } break; 800a5a2: e005 b.n 800a5b0 default: USBD_CtlError(pdev, req); 800a5a4: 6839 ldr r1, [r7, #0] 800a5a6: 6878 ldr r0, [r7, #4] 800a5a8: f000 fb79 bl 800ac9e break; 800a5ac: e000 b.n 800a5b0 break; 800a5ae: bf00 nop } return ret; 800a5b0: 7bfb ldrb r3, [r7, #15] } 800a5b2: 4618 mov r0, r3 800a5b4: 3710 adds r7, #16 800a5b6: 46bd mov sp, r7 800a5b8: bd80 pop {r7, pc} ... 0800a5bc : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a5bc: b580 push {r7, lr} 800a5be: b084 sub sp, #16 800a5c0: af00 add r7, sp, #0 800a5c2: 6078 str r0, [r7, #4] 800a5c4: 6039 str r1, [r7, #0] uint16_t len = 0U; 800a5c6: 2300 movs r3, #0 800a5c8: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 800a5ca: 2300 movs r3, #0 800a5cc: 60fb str r3, [r7, #12] uint8_t err = 0U; 800a5ce: 2300 movs r3, #0 800a5d0: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 800a5d2: 683b ldr r3, [r7, #0] 800a5d4: 885b ldrh r3, [r3, #2] 800a5d6: 0a1b lsrs r3, r3, #8 800a5d8: b29b uxth r3, r3 800a5da: 3b01 subs r3, #1 800a5dc: 2b0e cmp r3, #14 800a5de: f200 8152 bhi.w 800a886 800a5e2: a201 add r2, pc, #4 @ (adr r2, 800a5e8 ) 800a5e4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a5e8: 0800a659 .word 0x0800a659 800a5ec: 0800a671 .word 0x0800a671 800a5f0: 0800a6b1 .word 0x0800a6b1 800a5f4: 0800a887 .word 0x0800a887 800a5f8: 0800a887 .word 0x0800a887 800a5fc: 0800a827 .word 0x0800a827 800a600: 0800a853 .word 0x0800a853 800a604: 0800a887 .word 0x0800a887 800a608: 0800a887 .word 0x0800a887 800a60c: 0800a887 .word 0x0800a887 800a610: 0800a887 .word 0x0800a887 800a614: 0800a887 .word 0x0800a887 800a618: 0800a887 .word 0x0800a887 800a61c: 0800a887 .word 0x0800a887 800a620: 0800a625 .word 0x0800a625 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 800a624: 687b ldr r3, [r7, #4] 800a626: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a62a: 69db ldr r3, [r3, #28] 800a62c: 2b00 cmp r3, #0 800a62e: d00b beq.n 800a648 { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 800a630: 687b ldr r3, [r7, #4] 800a632: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a636: 69db ldr r3, [r3, #28] 800a638: 687a ldr r2, [r7, #4] 800a63a: 7c12 ldrb r2, [r2, #16] 800a63c: f107 0108 add.w r1, r7, #8 800a640: 4610 mov r0, r2 800a642: 4798 blx r3 800a644: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a646: e126 b.n 800a896 USBD_CtlError(pdev, req); 800a648: 6839 ldr r1, [r7, #0] 800a64a: 6878 ldr r0, [r7, #4] 800a64c: f000 fb27 bl 800ac9e err++; 800a650: 7afb ldrb r3, [r7, #11] 800a652: 3301 adds r3, #1 800a654: 72fb strb r3, [r7, #11] break; 800a656: e11e b.n 800a896 #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 800a658: 687b ldr r3, [r7, #4] 800a65a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a65e: 681b ldr r3, [r3, #0] 800a660: 687a ldr r2, [r7, #4] 800a662: 7c12 ldrb r2, [r2, #16] 800a664: f107 0108 add.w r1, r7, #8 800a668: 4610 mov r0, r2 800a66a: 4798 blx r3 800a66c: 60f8 str r0, [r7, #12] break; 800a66e: e112 b.n 800a896 case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 800a670: 687b ldr r3, [r7, #4] 800a672: 7c1b ldrb r3, [r3, #16] 800a674: 2b00 cmp r3, #0 800a676: d10d bne.n 800a694 pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 800a678: 687b ldr r3, [r7, #4] 800a67a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a67e: 6a9b ldr r3, [r3, #40] @ 0x28 800a680: f107 0208 add.w r2, r7, #8 800a684: 4610 mov r0, r2 800a686: 4798 blx r3 800a688: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800a68a: 68fb ldr r3, [r7, #12] 800a68c: 3301 adds r3, #1 800a68e: 2202 movs r2, #2 800a690: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 800a692: e100 b.n 800a896 pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 800a694: 687b ldr r3, [r7, #4] 800a696: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a69a: 6adb ldr r3, [r3, #44] @ 0x2c 800a69c: f107 0208 add.w r2, r7, #8 800a6a0: 4610 mov r0, r2 800a6a2: 4798 blx r3 800a6a4: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800a6a6: 68fb ldr r3, [r7, #12] 800a6a8: 3301 adds r3, #1 800a6aa: 2202 movs r2, #2 800a6ac: 701a strb r2, [r3, #0] break; 800a6ae: e0f2 b.n 800a896 case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 800a6b0: 683b ldr r3, [r7, #0] 800a6b2: 885b ldrh r3, [r3, #2] 800a6b4: b2db uxtb r3, r3 800a6b6: 2b05 cmp r3, #5 800a6b8: f200 80ac bhi.w 800a814 800a6bc: a201 add r2, pc, #4 @ (adr r2, 800a6c4 ) 800a6be: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a6c2: bf00 nop 800a6c4: 0800a6dd .word 0x0800a6dd 800a6c8: 0800a711 .word 0x0800a711 800a6cc: 0800a745 .word 0x0800a745 800a6d0: 0800a779 .word 0x0800a779 800a6d4: 0800a7ad .word 0x0800a7ad 800a6d8: 0800a7e1 .word 0x0800a7e1 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 800a6dc: 687b ldr r3, [r7, #4] 800a6de: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a6e2: 685b ldr r3, [r3, #4] 800a6e4: 2b00 cmp r3, #0 800a6e6: d00b beq.n 800a700 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 800a6e8: 687b ldr r3, [r7, #4] 800a6ea: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a6ee: 685b ldr r3, [r3, #4] 800a6f0: 687a ldr r2, [r7, #4] 800a6f2: 7c12 ldrb r2, [r2, #16] 800a6f4: f107 0108 add.w r1, r7, #8 800a6f8: 4610 mov r0, r2 800a6fa: 4798 blx r3 800a6fc: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a6fe: e091 b.n 800a824 USBD_CtlError(pdev, req); 800a700: 6839 ldr r1, [r7, #0] 800a702: 6878 ldr r0, [r7, #4] 800a704: f000 facb bl 800ac9e err++; 800a708: 7afb ldrb r3, [r7, #11] 800a70a: 3301 adds r3, #1 800a70c: 72fb strb r3, [r7, #11] break; 800a70e: e089 b.n 800a824 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 800a710: 687b ldr r3, [r7, #4] 800a712: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a716: 689b ldr r3, [r3, #8] 800a718: 2b00 cmp r3, #0 800a71a: d00b beq.n 800a734 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 800a71c: 687b ldr r3, [r7, #4] 800a71e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a722: 689b ldr r3, [r3, #8] 800a724: 687a ldr r2, [r7, #4] 800a726: 7c12 ldrb r2, [r2, #16] 800a728: f107 0108 add.w r1, r7, #8 800a72c: 4610 mov r0, r2 800a72e: 4798 blx r3 800a730: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a732: e077 b.n 800a824 USBD_CtlError(pdev, req); 800a734: 6839 ldr r1, [r7, #0] 800a736: 6878 ldr r0, [r7, #4] 800a738: f000 fab1 bl 800ac9e err++; 800a73c: 7afb ldrb r3, [r7, #11] 800a73e: 3301 adds r3, #1 800a740: 72fb strb r3, [r7, #11] break; 800a742: e06f b.n 800a824 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 800a744: 687b ldr r3, [r7, #4] 800a746: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a74a: 68db ldr r3, [r3, #12] 800a74c: 2b00 cmp r3, #0 800a74e: d00b beq.n 800a768 { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 800a750: 687b ldr r3, [r7, #4] 800a752: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a756: 68db ldr r3, [r3, #12] 800a758: 687a ldr r2, [r7, #4] 800a75a: 7c12 ldrb r2, [r2, #16] 800a75c: f107 0108 add.w r1, r7, #8 800a760: 4610 mov r0, r2 800a762: 4798 blx r3 800a764: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a766: e05d b.n 800a824 USBD_CtlError(pdev, req); 800a768: 6839 ldr r1, [r7, #0] 800a76a: 6878 ldr r0, [r7, #4] 800a76c: f000 fa97 bl 800ac9e err++; 800a770: 7afb ldrb r3, [r7, #11] 800a772: 3301 adds r3, #1 800a774: 72fb strb r3, [r7, #11] break; 800a776: e055 b.n 800a824 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 800a778: 687b ldr r3, [r7, #4] 800a77a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a77e: 691b ldr r3, [r3, #16] 800a780: 2b00 cmp r3, #0 800a782: d00b beq.n 800a79c { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 800a784: 687b ldr r3, [r7, #4] 800a786: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a78a: 691b ldr r3, [r3, #16] 800a78c: 687a ldr r2, [r7, #4] 800a78e: 7c12 ldrb r2, [r2, #16] 800a790: f107 0108 add.w r1, r7, #8 800a794: 4610 mov r0, r2 800a796: 4798 blx r3 800a798: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a79a: e043 b.n 800a824 USBD_CtlError(pdev, req); 800a79c: 6839 ldr r1, [r7, #0] 800a79e: 6878 ldr r0, [r7, #4] 800a7a0: f000 fa7d bl 800ac9e err++; 800a7a4: 7afb ldrb r3, [r7, #11] 800a7a6: 3301 adds r3, #1 800a7a8: 72fb strb r3, [r7, #11] break; 800a7aa: e03b b.n 800a824 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 800a7ac: 687b ldr r3, [r7, #4] 800a7ae: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a7b2: 695b ldr r3, [r3, #20] 800a7b4: 2b00 cmp r3, #0 800a7b6: d00b beq.n 800a7d0 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 800a7b8: 687b ldr r3, [r7, #4] 800a7ba: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a7be: 695b ldr r3, [r3, #20] 800a7c0: 687a ldr r2, [r7, #4] 800a7c2: 7c12 ldrb r2, [r2, #16] 800a7c4: f107 0108 add.w r1, r7, #8 800a7c8: 4610 mov r0, r2 800a7ca: 4798 blx r3 800a7cc: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a7ce: e029 b.n 800a824 USBD_CtlError(pdev, req); 800a7d0: 6839 ldr r1, [r7, #0] 800a7d2: 6878 ldr r0, [r7, #4] 800a7d4: f000 fa63 bl 800ac9e err++; 800a7d8: 7afb ldrb r3, [r7, #11] 800a7da: 3301 adds r3, #1 800a7dc: 72fb strb r3, [r7, #11] break; 800a7de: e021 b.n 800a824 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 800a7e0: 687b ldr r3, [r7, #4] 800a7e2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a7e6: 699b ldr r3, [r3, #24] 800a7e8: 2b00 cmp r3, #0 800a7ea: d00b beq.n 800a804 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 800a7ec: 687b ldr r3, [r7, #4] 800a7ee: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a7f2: 699b ldr r3, [r3, #24] 800a7f4: 687a ldr r2, [r7, #4] 800a7f6: 7c12 ldrb r2, [r2, #16] 800a7f8: f107 0108 add.w r1, r7, #8 800a7fc: 4610 mov r0, r2 800a7fe: 4798 blx r3 800a800: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a802: e00f b.n 800a824 USBD_CtlError(pdev, req); 800a804: 6839 ldr r1, [r7, #0] 800a806: 6878 ldr r0, [r7, #4] 800a808: f000 fa49 bl 800ac9e err++; 800a80c: 7afb ldrb r3, [r7, #11] 800a80e: 3301 adds r3, #1 800a810: 72fb strb r3, [r7, #11] break; 800a812: e007 b.n 800a824 err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 800a814: 6839 ldr r1, [r7, #0] 800a816: 6878 ldr r0, [r7, #4] 800a818: f000 fa41 bl 800ac9e err++; 800a81c: 7afb ldrb r3, [r7, #11] 800a81e: 3301 adds r3, #1 800a820: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 800a822: bf00 nop } break; 800a824: e037 b.n 800a896 case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 800a826: 687b ldr r3, [r7, #4] 800a828: 7c1b ldrb r3, [r3, #16] 800a82a: 2b00 cmp r3, #0 800a82c: d109 bne.n 800a842 pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 800a82e: 687b ldr r3, [r7, #4] 800a830: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a834: 6b5b ldr r3, [r3, #52] @ 0x34 800a836: f107 0208 add.w r2, r7, #8 800a83a: 4610 mov r0, r2 800a83c: 4798 blx r3 800a83e: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a840: e029 b.n 800a896 USBD_CtlError(pdev, req); 800a842: 6839 ldr r1, [r7, #0] 800a844: 6878 ldr r0, [r7, #4] 800a846: f000 fa2a bl 800ac9e err++; 800a84a: 7afb ldrb r3, [r7, #11] 800a84c: 3301 adds r3, #1 800a84e: 72fb strb r3, [r7, #11] break; 800a850: e021 b.n 800a896 case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 800a852: 687b ldr r3, [r7, #4] 800a854: 7c1b ldrb r3, [r3, #16] 800a856: 2b00 cmp r3, #0 800a858: d10d bne.n 800a876 pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 800a85a: 687b ldr r3, [r7, #4] 800a85c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a860: 6b1b ldr r3, [r3, #48] @ 0x30 800a862: f107 0208 add.w r2, r7, #8 800a866: 4610 mov r0, r2 800a868: 4798 blx r3 800a86a: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 800a86c: 68fb ldr r3, [r7, #12] 800a86e: 3301 adds r3, #1 800a870: 2207 movs r2, #7 800a872: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 800a874: e00f b.n 800a896 USBD_CtlError(pdev, req); 800a876: 6839 ldr r1, [r7, #0] 800a878: 6878 ldr r0, [r7, #4] 800a87a: f000 fa10 bl 800ac9e err++; 800a87e: 7afb ldrb r3, [r7, #11] 800a880: 3301 adds r3, #1 800a882: 72fb strb r3, [r7, #11] break; 800a884: e007 b.n 800a896 default: USBD_CtlError(pdev, req); 800a886: 6839 ldr r1, [r7, #0] 800a888: 6878 ldr r0, [r7, #4] 800a88a: f000 fa08 bl 800ac9e err++; 800a88e: 7afb ldrb r3, [r7, #11] 800a890: 3301 adds r3, #1 800a892: 72fb strb r3, [r7, #11] break; 800a894: bf00 nop } if (err != 0U) 800a896: 7afb ldrb r3, [r7, #11] 800a898: 2b00 cmp r3, #0 800a89a: d11e bne.n 800a8da { return; } if (req->wLength != 0U) 800a89c: 683b ldr r3, [r7, #0] 800a89e: 88db ldrh r3, [r3, #6] 800a8a0: 2b00 cmp r3, #0 800a8a2: d016 beq.n 800a8d2 { if (len != 0U) 800a8a4: 893b ldrh r3, [r7, #8] 800a8a6: 2b00 cmp r3, #0 800a8a8: d00e beq.n 800a8c8 { len = MIN(len, req->wLength); 800a8aa: 683b ldr r3, [r7, #0] 800a8ac: 88da ldrh r2, [r3, #6] 800a8ae: 893b ldrh r3, [r7, #8] 800a8b0: 4293 cmp r3, r2 800a8b2: bf28 it cs 800a8b4: 4613 movcs r3, r2 800a8b6: b29b uxth r3, r3 800a8b8: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 800a8ba: 893b ldrh r3, [r7, #8] 800a8bc: 461a mov r2, r3 800a8be: 68f9 ldr r1, [r7, #12] 800a8c0: 6878 ldr r0, [r7, #4] 800a8c2: f000 fa69 bl 800ad98 800a8c6: e009 b.n 800a8dc } else { USBD_CtlError(pdev, req); 800a8c8: 6839 ldr r1, [r7, #0] 800a8ca: 6878 ldr r0, [r7, #4] 800a8cc: f000 f9e7 bl 800ac9e 800a8d0: e004 b.n 800a8dc } } else { (void)USBD_CtlSendStatus(pdev); 800a8d2: 6878 ldr r0, [r7, #4] 800a8d4: f000 faa0 bl 800ae18 800a8d8: e000 b.n 800a8dc return; 800a8da: bf00 nop } } 800a8dc: 3710 adds r7, #16 800a8de: 46bd mov sp, r7 800a8e0: bd80 pop {r7, pc} 800a8e2: bf00 nop 0800a8e4 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a8e4: b580 push {r7, lr} 800a8e6: b084 sub sp, #16 800a8e8: af00 add r7, sp, #0 800a8ea: 6078 str r0, [r7, #4] 800a8ec: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 800a8ee: 683b ldr r3, [r7, #0] 800a8f0: 889b ldrh r3, [r3, #4] 800a8f2: 2b00 cmp r3, #0 800a8f4: d131 bne.n 800a95a 800a8f6: 683b ldr r3, [r7, #0] 800a8f8: 88db ldrh r3, [r3, #6] 800a8fa: 2b00 cmp r3, #0 800a8fc: d12d bne.n 800a95a 800a8fe: 683b ldr r3, [r7, #0] 800a900: 885b ldrh r3, [r3, #2] 800a902: 2b7f cmp r3, #127 @ 0x7f 800a904: d829 bhi.n 800a95a { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 800a906: 683b ldr r3, [r7, #0] 800a908: 885b ldrh r3, [r3, #2] 800a90a: b2db uxtb r3, r3 800a90c: f003 037f and.w r3, r3, #127 @ 0x7f 800a910: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a912: 687b ldr r3, [r7, #4] 800a914: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a918: b2db uxtb r3, r3 800a91a: 2b03 cmp r3, #3 800a91c: d104 bne.n 800a928 { USBD_CtlError(pdev, req); 800a91e: 6839 ldr r1, [r7, #0] 800a920: 6878 ldr r0, [r7, #4] 800a922: f000 f9bc bl 800ac9e if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a926: e01d b.n 800a964 } else { pdev->dev_address = dev_addr; 800a928: 687b ldr r3, [r7, #4] 800a92a: 7bfa ldrb r2, [r7, #15] 800a92c: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 800a930: 7bfb ldrb r3, [r7, #15] 800a932: 4619 mov r1, r3 800a934: 6878 ldr r0, [r7, #4] 800a936: f000 fe4f bl 800b5d8 (void)USBD_CtlSendStatus(pdev); 800a93a: 6878 ldr r0, [r7, #4] 800a93c: f000 fa6c bl 800ae18 if (dev_addr != 0U) 800a940: 7bfb ldrb r3, [r7, #15] 800a942: 2b00 cmp r3, #0 800a944: d004 beq.n 800a950 { pdev->dev_state = USBD_STATE_ADDRESSED; 800a946: 687b ldr r3, [r7, #4] 800a948: 2202 movs r2, #2 800a94a: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a94e: e009 b.n 800a964 } else { pdev->dev_state = USBD_STATE_DEFAULT; 800a950: 687b ldr r3, [r7, #4] 800a952: 2201 movs r2, #1 800a954: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a958: e004 b.n 800a964 } } } else { USBD_CtlError(pdev, req); 800a95a: 6839 ldr r1, [r7, #0] 800a95c: 6878 ldr r0, [r7, #4] 800a95e: f000 f99e bl 800ac9e } } 800a962: bf00 nop 800a964: bf00 nop 800a966: 3710 adds r7, #16 800a968: 46bd mov sp, r7 800a96a: bd80 pop {r7, pc} 0800a96c : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a96c: b580 push {r7, lr} 800a96e: b084 sub sp, #16 800a970: af00 add r7, sp, #0 800a972: 6078 str r0, [r7, #4] 800a974: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800a976: 2300 movs r3, #0 800a978: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 800a97a: 683b ldr r3, [r7, #0] 800a97c: 885b ldrh r3, [r3, #2] 800a97e: b2da uxtb r2, r3 800a980: 4b4e ldr r3, [pc, #312] @ (800aabc ) 800a982: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 800a984: 4b4d ldr r3, [pc, #308] @ (800aabc ) 800a986: 781b ldrb r3, [r3, #0] 800a988: 2b01 cmp r3, #1 800a98a: d905 bls.n 800a998 { USBD_CtlError(pdev, req); 800a98c: 6839 ldr r1, [r7, #0] 800a98e: 6878 ldr r0, [r7, #4] 800a990: f000 f985 bl 800ac9e return USBD_FAIL; 800a994: 2303 movs r3, #3 800a996: e08c b.n 800aab2 } switch (pdev->dev_state) 800a998: 687b ldr r3, [r7, #4] 800a99a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a99e: b2db uxtb r3, r3 800a9a0: 2b02 cmp r3, #2 800a9a2: d002 beq.n 800a9aa 800a9a4: 2b03 cmp r3, #3 800a9a6: d029 beq.n 800a9fc 800a9a8: e075 b.n 800aa96 { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 800a9aa: 4b44 ldr r3, [pc, #272] @ (800aabc ) 800a9ac: 781b ldrb r3, [r3, #0] 800a9ae: 2b00 cmp r3, #0 800a9b0: d020 beq.n 800a9f4 { pdev->dev_config = cfgidx; 800a9b2: 4b42 ldr r3, [pc, #264] @ (800aabc ) 800a9b4: 781b ldrb r3, [r3, #0] 800a9b6: 461a mov r2, r3 800a9b8: 687b ldr r3, [r7, #4] 800a9ba: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 800a9bc: 4b3f ldr r3, [pc, #252] @ (800aabc ) 800a9be: 781b ldrb r3, [r3, #0] 800a9c0: 4619 mov r1, r3 800a9c2: 6878 ldr r0, [r7, #4] 800a9c4: f7fe ffa3 bl 800990e 800a9c8: 4603 mov r3, r0 800a9ca: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 800a9cc: 7bfb ldrb r3, [r7, #15] 800a9ce: 2b00 cmp r3, #0 800a9d0: d008 beq.n 800a9e4 { USBD_CtlError(pdev, req); 800a9d2: 6839 ldr r1, [r7, #0] 800a9d4: 6878 ldr r0, [r7, #4] 800a9d6: f000 f962 bl 800ac9e pdev->dev_state = USBD_STATE_ADDRESSED; 800a9da: 687b ldr r3, [r7, #4] 800a9dc: 2202 movs r2, #2 800a9de: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 800a9e2: e065 b.n 800aab0 (void)USBD_CtlSendStatus(pdev); 800a9e4: 6878 ldr r0, [r7, #4] 800a9e6: f000 fa17 bl 800ae18 pdev->dev_state = USBD_STATE_CONFIGURED; 800a9ea: 687b ldr r3, [r7, #4] 800a9ec: 2203 movs r2, #3 800a9ee: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 800a9f2: e05d b.n 800aab0 (void)USBD_CtlSendStatus(pdev); 800a9f4: 6878 ldr r0, [r7, #4] 800a9f6: f000 fa0f bl 800ae18 break; 800a9fa: e059 b.n 800aab0 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 800a9fc: 4b2f ldr r3, [pc, #188] @ (800aabc ) 800a9fe: 781b ldrb r3, [r3, #0] 800aa00: 2b00 cmp r3, #0 800aa02: d112 bne.n 800aa2a { pdev->dev_state = USBD_STATE_ADDRESSED; 800aa04: 687b ldr r3, [r7, #4] 800aa06: 2202 movs r2, #2 800aa08: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 800aa0c: 4b2b ldr r3, [pc, #172] @ (800aabc ) 800aa0e: 781b ldrb r3, [r3, #0] 800aa10: 461a mov r2, r3 800aa12: 687b ldr r3, [r7, #4] 800aa14: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 800aa16: 4b29 ldr r3, [pc, #164] @ (800aabc ) 800aa18: 781b ldrb r3, [r3, #0] 800aa1a: 4619 mov r1, r3 800aa1c: 6878 ldr r0, [r7, #4] 800aa1e: f7fe ff92 bl 8009946 (void)USBD_CtlSendStatus(pdev); 800aa22: 6878 ldr r0, [r7, #4] 800aa24: f000 f9f8 bl 800ae18 } else { (void)USBD_CtlSendStatus(pdev); } break; 800aa28: e042 b.n 800aab0 else if (cfgidx != pdev->dev_config) 800aa2a: 4b24 ldr r3, [pc, #144] @ (800aabc ) 800aa2c: 781b ldrb r3, [r3, #0] 800aa2e: 461a mov r2, r3 800aa30: 687b ldr r3, [r7, #4] 800aa32: 685b ldr r3, [r3, #4] 800aa34: 429a cmp r2, r3 800aa36: d02a beq.n 800aa8e (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 800aa38: 687b ldr r3, [r7, #4] 800aa3a: 685b ldr r3, [r3, #4] 800aa3c: b2db uxtb r3, r3 800aa3e: 4619 mov r1, r3 800aa40: 6878 ldr r0, [r7, #4] 800aa42: f7fe ff80 bl 8009946 pdev->dev_config = cfgidx; 800aa46: 4b1d ldr r3, [pc, #116] @ (800aabc ) 800aa48: 781b ldrb r3, [r3, #0] 800aa4a: 461a mov r2, r3 800aa4c: 687b ldr r3, [r7, #4] 800aa4e: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 800aa50: 4b1a ldr r3, [pc, #104] @ (800aabc ) 800aa52: 781b ldrb r3, [r3, #0] 800aa54: 4619 mov r1, r3 800aa56: 6878 ldr r0, [r7, #4] 800aa58: f7fe ff59 bl 800990e 800aa5c: 4603 mov r3, r0 800aa5e: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 800aa60: 7bfb ldrb r3, [r7, #15] 800aa62: 2b00 cmp r3, #0 800aa64: d00f beq.n 800aa86 USBD_CtlError(pdev, req); 800aa66: 6839 ldr r1, [r7, #0] 800aa68: 6878 ldr r0, [r7, #4] 800aa6a: f000 f918 bl 800ac9e (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 800aa6e: 687b ldr r3, [r7, #4] 800aa70: 685b ldr r3, [r3, #4] 800aa72: b2db uxtb r3, r3 800aa74: 4619 mov r1, r3 800aa76: 6878 ldr r0, [r7, #4] 800aa78: f7fe ff65 bl 8009946 pdev->dev_state = USBD_STATE_ADDRESSED; 800aa7c: 687b ldr r3, [r7, #4] 800aa7e: 2202 movs r2, #2 800aa80: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 800aa84: e014 b.n 800aab0 (void)USBD_CtlSendStatus(pdev); 800aa86: 6878 ldr r0, [r7, #4] 800aa88: f000 f9c6 bl 800ae18 break; 800aa8c: e010 b.n 800aab0 (void)USBD_CtlSendStatus(pdev); 800aa8e: 6878 ldr r0, [r7, #4] 800aa90: f000 f9c2 bl 800ae18 break; 800aa94: e00c b.n 800aab0 default: USBD_CtlError(pdev, req); 800aa96: 6839 ldr r1, [r7, #0] 800aa98: 6878 ldr r0, [r7, #4] 800aa9a: f000 f900 bl 800ac9e (void)USBD_ClrClassConfig(pdev, cfgidx); 800aa9e: 4b07 ldr r3, [pc, #28] @ (800aabc ) 800aaa0: 781b ldrb r3, [r3, #0] 800aaa2: 4619 mov r1, r3 800aaa4: 6878 ldr r0, [r7, #4] 800aaa6: f7fe ff4e bl 8009946 ret = USBD_FAIL; 800aaaa: 2303 movs r3, #3 800aaac: 73fb strb r3, [r7, #15] break; 800aaae: bf00 nop } return ret; 800aab0: 7bfb ldrb r3, [r7, #15] } 800aab2: 4618 mov r0, r3 800aab4: 3710 adds r7, #16 800aab6: 46bd mov sp, r7 800aab8: bd80 pop {r7, pc} 800aaba: bf00 nop 800aabc: 20000f04 .word 0x20000f04 0800aac0 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800aac0: b580 push {r7, lr} 800aac2: b082 sub sp, #8 800aac4: af00 add r7, sp, #0 800aac6: 6078 str r0, [r7, #4] 800aac8: 6039 str r1, [r7, #0] if (req->wLength != 1U) 800aaca: 683b ldr r3, [r7, #0] 800aacc: 88db ldrh r3, [r3, #6] 800aace: 2b01 cmp r3, #1 800aad0: d004 beq.n 800aadc { USBD_CtlError(pdev, req); 800aad2: 6839 ldr r1, [r7, #0] 800aad4: 6878 ldr r0, [r7, #4] 800aad6: f000 f8e2 bl 800ac9e default: USBD_CtlError(pdev, req); break; } } } 800aada: e023 b.n 800ab24 switch (pdev->dev_state) 800aadc: 687b ldr r3, [r7, #4] 800aade: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800aae2: b2db uxtb r3, r3 800aae4: 2b02 cmp r3, #2 800aae6: dc02 bgt.n 800aaee 800aae8: 2b00 cmp r3, #0 800aaea: dc03 bgt.n 800aaf4 800aaec: e015 b.n 800ab1a 800aaee: 2b03 cmp r3, #3 800aaf0: d00b beq.n 800ab0a 800aaf2: e012 b.n 800ab1a pdev->dev_default_config = 0U; 800aaf4: 687b ldr r3, [r7, #4] 800aaf6: 2200 movs r2, #0 800aaf8: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 800aafa: 687b ldr r3, [r7, #4] 800aafc: 3308 adds r3, #8 800aafe: 2201 movs r2, #1 800ab00: 4619 mov r1, r3 800ab02: 6878 ldr r0, [r7, #4] 800ab04: f000 f948 bl 800ad98 break; 800ab08: e00c b.n 800ab24 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 800ab0a: 687b ldr r3, [r7, #4] 800ab0c: 3304 adds r3, #4 800ab0e: 2201 movs r2, #1 800ab10: 4619 mov r1, r3 800ab12: 6878 ldr r0, [r7, #4] 800ab14: f000 f940 bl 800ad98 break; 800ab18: e004 b.n 800ab24 USBD_CtlError(pdev, req); 800ab1a: 6839 ldr r1, [r7, #0] 800ab1c: 6878 ldr r0, [r7, #4] 800ab1e: f000 f8be bl 800ac9e break; 800ab22: bf00 nop } 800ab24: bf00 nop 800ab26: 3708 adds r7, #8 800ab28: 46bd mov sp, r7 800ab2a: bd80 pop {r7, pc} 0800ab2c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800ab2c: b580 push {r7, lr} 800ab2e: b082 sub sp, #8 800ab30: af00 add r7, sp, #0 800ab32: 6078 str r0, [r7, #4] 800ab34: 6039 str r1, [r7, #0] switch (pdev->dev_state) 800ab36: 687b ldr r3, [r7, #4] 800ab38: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800ab3c: b2db uxtb r3, r3 800ab3e: 3b01 subs r3, #1 800ab40: 2b02 cmp r3, #2 800ab42: d81e bhi.n 800ab82 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 800ab44: 683b ldr r3, [r7, #0] 800ab46: 88db ldrh r3, [r3, #6] 800ab48: 2b02 cmp r3, #2 800ab4a: d004 beq.n 800ab56 { USBD_CtlError(pdev, req); 800ab4c: 6839 ldr r1, [r7, #0] 800ab4e: 6878 ldr r0, [r7, #4] 800ab50: f000 f8a5 bl 800ac9e break; 800ab54: e01a b.n 800ab8c } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 800ab56: 687b ldr r3, [r7, #4] 800ab58: 2201 movs r2, #1 800ab5a: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 800ab5c: 687b ldr r3, [r7, #4] 800ab5e: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 800ab62: 2b00 cmp r3, #0 800ab64: d005 beq.n 800ab72 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 800ab66: 687b ldr r3, [r7, #4] 800ab68: 68db ldr r3, [r3, #12] 800ab6a: f043 0202 orr.w r2, r3, #2 800ab6e: 687b ldr r3, [r7, #4] 800ab70: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 800ab72: 687b ldr r3, [r7, #4] 800ab74: 330c adds r3, #12 800ab76: 2202 movs r2, #2 800ab78: 4619 mov r1, r3 800ab7a: 6878 ldr r0, [r7, #4] 800ab7c: f000 f90c bl 800ad98 break; 800ab80: e004 b.n 800ab8c default: USBD_CtlError(pdev, req); 800ab82: 6839 ldr r1, [r7, #0] 800ab84: 6878 ldr r0, [r7, #4] 800ab86: f000 f88a bl 800ac9e break; 800ab8a: bf00 nop } } 800ab8c: bf00 nop 800ab8e: 3708 adds r7, #8 800ab90: 46bd mov sp, r7 800ab92: bd80 pop {r7, pc} 0800ab94 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800ab94: b580 push {r7, lr} 800ab96: b082 sub sp, #8 800ab98: af00 add r7, sp, #0 800ab9a: 6078 str r0, [r7, #4] 800ab9c: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 800ab9e: 683b ldr r3, [r7, #0] 800aba0: 885b ldrh r3, [r3, #2] 800aba2: 2b01 cmp r3, #1 800aba4: d107 bne.n 800abb6 { pdev->dev_remote_wakeup = 1U; 800aba6: 687b ldr r3, [r7, #4] 800aba8: 2201 movs r2, #1 800abaa: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 800abae: 6878 ldr r0, [r7, #4] 800abb0: f000 f932 bl 800ae18 } else { USBD_CtlError(pdev, req); } } 800abb4: e013 b.n 800abde else if (req->wValue == USB_FEATURE_TEST_MODE) 800abb6: 683b ldr r3, [r7, #0] 800abb8: 885b ldrh r3, [r3, #2] 800abba: 2b02 cmp r3, #2 800abbc: d10b bne.n 800abd6 pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 800abbe: 683b ldr r3, [r7, #0] 800abc0: 889b ldrh r3, [r3, #4] 800abc2: 0a1b lsrs r3, r3, #8 800abc4: b29b uxth r3, r3 800abc6: b2da uxtb r2, r3 800abc8: 687b ldr r3, [r7, #4] 800abca: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 800abce: 6878 ldr r0, [r7, #4] 800abd0: f000 f922 bl 800ae18 } 800abd4: e003 b.n 800abde USBD_CtlError(pdev, req); 800abd6: 6839 ldr r1, [r7, #0] 800abd8: 6878 ldr r0, [r7, #4] 800abda: f000 f860 bl 800ac9e } 800abde: bf00 nop 800abe0: 3708 adds r7, #8 800abe2: 46bd mov sp, r7 800abe4: bd80 pop {r7, pc} 0800abe6 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800abe6: b580 push {r7, lr} 800abe8: b082 sub sp, #8 800abea: af00 add r7, sp, #0 800abec: 6078 str r0, [r7, #4] 800abee: 6039 str r1, [r7, #0] switch (pdev->dev_state) 800abf0: 687b ldr r3, [r7, #4] 800abf2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800abf6: b2db uxtb r3, r3 800abf8: 3b01 subs r3, #1 800abfa: 2b02 cmp r3, #2 800abfc: d80b bhi.n 800ac16 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 800abfe: 683b ldr r3, [r7, #0] 800ac00: 885b ldrh r3, [r3, #2] 800ac02: 2b01 cmp r3, #1 800ac04: d10c bne.n 800ac20 { pdev->dev_remote_wakeup = 0U; 800ac06: 687b ldr r3, [r7, #4] 800ac08: 2200 movs r2, #0 800ac0a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 800ac0e: 6878 ldr r0, [r7, #4] 800ac10: f000 f902 bl 800ae18 } break; 800ac14: e004 b.n 800ac20 default: USBD_CtlError(pdev, req); 800ac16: 6839 ldr r1, [r7, #0] 800ac18: 6878 ldr r0, [r7, #4] 800ac1a: f000 f840 bl 800ac9e break; 800ac1e: e000 b.n 800ac22 break; 800ac20: bf00 nop } } 800ac22: bf00 nop 800ac24: 3708 adds r7, #8 800ac26: 46bd mov sp, r7 800ac28: bd80 pop {r7, pc} 0800ac2a : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 800ac2a: b580 push {r7, lr} 800ac2c: b084 sub sp, #16 800ac2e: af00 add r7, sp, #0 800ac30: 6078 str r0, [r7, #4] 800ac32: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 800ac34: 683b ldr r3, [r7, #0] 800ac36: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 800ac38: 68fb ldr r3, [r7, #12] 800ac3a: 781a ldrb r2, [r3, #0] 800ac3c: 687b ldr r3, [r7, #4] 800ac3e: 701a strb r2, [r3, #0] pbuff++; 800ac40: 68fb ldr r3, [r7, #12] 800ac42: 3301 adds r3, #1 800ac44: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 800ac46: 68fb ldr r3, [r7, #12] 800ac48: 781a ldrb r2, [r3, #0] 800ac4a: 687b ldr r3, [r7, #4] 800ac4c: 705a strb r2, [r3, #1] pbuff++; 800ac4e: 68fb ldr r3, [r7, #12] 800ac50: 3301 adds r3, #1 800ac52: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 800ac54: 68f8 ldr r0, [r7, #12] 800ac56: f7ff fa13 bl 800a080 800ac5a: 4603 mov r3, r0 800ac5c: 461a mov r2, r3 800ac5e: 687b ldr r3, [r7, #4] 800ac60: 805a strh r2, [r3, #2] pbuff++; 800ac62: 68fb ldr r3, [r7, #12] 800ac64: 3301 adds r3, #1 800ac66: 60fb str r3, [r7, #12] pbuff++; 800ac68: 68fb ldr r3, [r7, #12] 800ac6a: 3301 adds r3, #1 800ac6c: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 800ac6e: 68f8 ldr r0, [r7, #12] 800ac70: f7ff fa06 bl 800a080 800ac74: 4603 mov r3, r0 800ac76: 461a mov r2, r3 800ac78: 687b ldr r3, [r7, #4] 800ac7a: 809a strh r2, [r3, #4] pbuff++; 800ac7c: 68fb ldr r3, [r7, #12] 800ac7e: 3301 adds r3, #1 800ac80: 60fb str r3, [r7, #12] pbuff++; 800ac82: 68fb ldr r3, [r7, #12] 800ac84: 3301 adds r3, #1 800ac86: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 800ac88: 68f8 ldr r0, [r7, #12] 800ac8a: f7ff f9f9 bl 800a080 800ac8e: 4603 mov r3, r0 800ac90: 461a mov r2, r3 800ac92: 687b ldr r3, [r7, #4] 800ac94: 80da strh r2, [r3, #6] } 800ac96: bf00 nop 800ac98: 3710 adds r7, #16 800ac9a: 46bd mov sp, r7 800ac9c: bd80 pop {r7, pc} 0800ac9e : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800ac9e: b580 push {r7, lr} 800aca0: b082 sub sp, #8 800aca2: af00 add r7, sp, #0 800aca4: 6078 str r0, [r7, #4] 800aca6: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 800aca8: 2180 movs r1, #128 @ 0x80 800acaa: 6878 ldr r0, [r7, #4] 800acac: f000 fc2a bl 800b504 (void)USBD_LL_StallEP(pdev, 0U); 800acb0: 2100 movs r1, #0 800acb2: 6878 ldr r0, [r7, #4] 800acb4: f000 fc26 bl 800b504 } 800acb8: bf00 nop 800acba: 3708 adds r7, #8 800acbc: 46bd mov sp, r7 800acbe: bd80 pop {r7, pc} 0800acc0 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 800acc0: b580 push {r7, lr} 800acc2: b086 sub sp, #24 800acc4: af00 add r7, sp, #0 800acc6: 60f8 str r0, [r7, #12] 800acc8: 60b9 str r1, [r7, #8] 800acca: 607a str r2, [r7, #4] uint8_t idx = 0U; 800accc: 2300 movs r3, #0 800acce: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 800acd0: 68fb ldr r3, [r7, #12] 800acd2: 2b00 cmp r3, #0 800acd4: d042 beq.n 800ad5c { return; } pdesc = desc; 800acd6: 68fb ldr r3, [r7, #12] 800acd8: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 800acda: 6938 ldr r0, [r7, #16] 800acdc: f000 f842 bl 800ad64 800ace0: 4603 mov r3, r0 800ace2: 3301 adds r3, #1 800ace4: 005b lsls r3, r3, #1 800ace6: f5b3 7f00 cmp.w r3, #512 @ 0x200 800acea: d808 bhi.n 800acfe 800acec: 6938 ldr r0, [r7, #16] 800acee: f000 f839 bl 800ad64 800acf2: 4603 mov r3, r0 800acf4: 3301 adds r3, #1 800acf6: b29b uxth r3, r3 800acf8: 005b lsls r3, r3, #1 800acfa: b29a uxth r2, r3 800acfc: e001 b.n 800ad02 800acfe: f44f 7200 mov.w r2, #512 @ 0x200 800ad02: 687b ldr r3, [r7, #4] 800ad04: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 800ad06: 7dfb ldrb r3, [r7, #23] 800ad08: 68ba ldr r2, [r7, #8] 800ad0a: 4413 add r3, r2 800ad0c: 687a ldr r2, [r7, #4] 800ad0e: 7812 ldrb r2, [r2, #0] 800ad10: 701a strb r2, [r3, #0] idx++; 800ad12: 7dfb ldrb r3, [r7, #23] 800ad14: 3301 adds r3, #1 800ad16: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 800ad18: 7dfb ldrb r3, [r7, #23] 800ad1a: 68ba ldr r2, [r7, #8] 800ad1c: 4413 add r3, r2 800ad1e: 2203 movs r2, #3 800ad20: 701a strb r2, [r3, #0] idx++; 800ad22: 7dfb ldrb r3, [r7, #23] 800ad24: 3301 adds r3, #1 800ad26: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800ad28: e013 b.n 800ad52 { unicode[idx] = *pdesc; 800ad2a: 7dfb ldrb r3, [r7, #23] 800ad2c: 68ba ldr r2, [r7, #8] 800ad2e: 4413 add r3, r2 800ad30: 693a ldr r2, [r7, #16] 800ad32: 7812 ldrb r2, [r2, #0] 800ad34: 701a strb r2, [r3, #0] pdesc++; 800ad36: 693b ldr r3, [r7, #16] 800ad38: 3301 adds r3, #1 800ad3a: 613b str r3, [r7, #16] idx++; 800ad3c: 7dfb ldrb r3, [r7, #23] 800ad3e: 3301 adds r3, #1 800ad40: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 800ad42: 7dfb ldrb r3, [r7, #23] 800ad44: 68ba ldr r2, [r7, #8] 800ad46: 4413 add r3, r2 800ad48: 2200 movs r2, #0 800ad4a: 701a strb r2, [r3, #0] idx++; 800ad4c: 7dfb ldrb r3, [r7, #23] 800ad4e: 3301 adds r3, #1 800ad50: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800ad52: 693b ldr r3, [r7, #16] 800ad54: 781b ldrb r3, [r3, #0] 800ad56: 2b00 cmp r3, #0 800ad58: d1e7 bne.n 800ad2a 800ad5a: e000 b.n 800ad5e return; 800ad5c: bf00 nop } } 800ad5e: 3718 adds r7, #24 800ad60: 46bd mov sp, r7 800ad62: bd80 pop {r7, pc} 0800ad64 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 800ad64: b480 push {r7} 800ad66: b085 sub sp, #20 800ad68: af00 add r7, sp, #0 800ad6a: 6078 str r0, [r7, #4] uint8_t len = 0U; 800ad6c: 2300 movs r3, #0 800ad6e: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 800ad70: 687b ldr r3, [r7, #4] 800ad72: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800ad74: e005 b.n 800ad82 { len++; 800ad76: 7bfb ldrb r3, [r7, #15] 800ad78: 3301 adds r3, #1 800ad7a: 73fb strb r3, [r7, #15] pbuff++; 800ad7c: 68bb ldr r3, [r7, #8] 800ad7e: 3301 adds r3, #1 800ad80: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800ad82: 68bb ldr r3, [r7, #8] 800ad84: 781b ldrb r3, [r3, #0] 800ad86: 2b00 cmp r3, #0 800ad88: d1f5 bne.n 800ad76 } return len; 800ad8a: 7bfb ldrb r3, [r7, #15] } 800ad8c: 4618 mov r0, r3 800ad8e: 3714 adds r7, #20 800ad90: 46bd mov sp, r7 800ad92: f85d 7b04 ldr.w r7, [sp], #4 800ad96: 4770 bx lr 0800ad98 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800ad98: b580 push {r7, lr} 800ad9a: b084 sub sp, #16 800ad9c: af00 add r7, sp, #0 800ad9e: 60f8 str r0, [r7, #12] 800ada0: 60b9 str r1, [r7, #8] 800ada2: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 800ada4: 68fb ldr r3, [r7, #12] 800ada6: 2202 movs r2, #2 800ada8: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 800adac: 68fb ldr r3, [r7, #12] 800adae: 687a ldr r2, [r7, #4] 800adb0: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 800adb2: 68fb ldr r3, [r7, #12] 800adb4: 68ba ldr r2, [r7, #8] 800adb6: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 800adb8: 68fb ldr r3, [r7, #12] 800adba: 687a ldr r2, [r7, #4] 800adbc: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800adbe: 687b ldr r3, [r7, #4] 800adc0: 68ba ldr r2, [r7, #8] 800adc2: 2100 movs r1, #0 800adc4: 68f8 ldr r0, [r7, #12] 800adc6: f000 fc26 bl 800b616 return USBD_OK; 800adca: 2300 movs r3, #0 } 800adcc: 4618 mov r0, r3 800adce: 3710 adds r7, #16 800add0: 46bd mov sp, r7 800add2: bd80 pop {r7, pc} 0800add4 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800add4: b580 push {r7, lr} 800add6: b084 sub sp, #16 800add8: af00 add r7, sp, #0 800adda: 60f8 str r0, [r7, #12] 800addc: 60b9 str r1, [r7, #8] 800adde: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800ade0: 687b ldr r3, [r7, #4] 800ade2: 68ba ldr r2, [r7, #8] 800ade4: 2100 movs r1, #0 800ade6: 68f8 ldr r0, [r7, #12] 800ade8: f000 fc15 bl 800b616 return USBD_OK; 800adec: 2300 movs r3, #0 } 800adee: 4618 mov r0, r3 800adf0: 3710 adds r7, #16 800adf2: 46bd mov sp, r7 800adf4: bd80 pop {r7, pc} 0800adf6 : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800adf6: b580 push {r7, lr} 800adf8: b084 sub sp, #16 800adfa: af00 add r7, sp, #0 800adfc: 60f8 str r0, [r7, #12] 800adfe: 60b9 str r1, [r7, #8] 800ae00: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800ae02: 687b ldr r3, [r7, #4] 800ae04: 68ba ldr r2, [r7, #8] 800ae06: 2100 movs r1, #0 800ae08: 68f8 ldr r0, [r7, #12] 800ae0a: f000 fc25 bl 800b658 return USBD_OK; 800ae0e: 2300 movs r3, #0 } 800ae10: 4618 mov r0, r3 800ae12: 3710 adds r7, #16 800ae14: 46bd mov sp, r7 800ae16: bd80 pop {r7, pc} 0800ae18 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 800ae18: b580 push {r7, lr} 800ae1a: b082 sub sp, #8 800ae1c: af00 add r7, sp, #0 800ae1e: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 800ae20: 687b ldr r3, [r7, #4] 800ae22: 2204 movs r2, #4 800ae24: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 800ae28: 2300 movs r3, #0 800ae2a: 2200 movs r2, #0 800ae2c: 2100 movs r1, #0 800ae2e: 6878 ldr r0, [r7, #4] 800ae30: f000 fbf1 bl 800b616 return USBD_OK; 800ae34: 2300 movs r3, #0 } 800ae36: 4618 mov r0, r3 800ae38: 3708 adds r7, #8 800ae3a: 46bd mov sp, r7 800ae3c: bd80 pop {r7, pc} 0800ae3e : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 800ae3e: b580 push {r7, lr} 800ae40: b082 sub sp, #8 800ae42: af00 add r7, sp, #0 800ae44: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 800ae46: 687b ldr r3, [r7, #4] 800ae48: 2205 movs r2, #5 800ae4a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800ae4e: 2300 movs r3, #0 800ae50: 2200 movs r2, #0 800ae52: 2100 movs r1, #0 800ae54: 6878 ldr r0, [r7, #4] 800ae56: f000 fbff bl 800b658 return USBD_OK; 800ae5a: 2300 movs r3, #0 } 800ae5c: 4618 mov r0, r3 800ae5e: 3708 adds r7, #8 800ae60: 46bd mov sp, r7 800ae62: bd80 pop {r7, pc} 0800ae64 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 800ae64: b580 push {r7, lr} 800ae66: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 800ae68: 2200 movs r2, #0 800ae6a: 490e ldr r1, [pc, #56] @ (800aea4 ) 800ae6c: 480e ldr r0, [pc, #56] @ (800aea8 ) 800ae6e: f7fe fcd1 bl 8009814 800ae72: 4603 mov r3, r0 800ae74: 2b00 cmp r3, #0 800ae76: d001 beq.n 800ae7c { Error_Handler(); 800ae78: f7f6 fa68 bl 800134c } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) 800ae7c: 490b ldr r1, [pc, #44] @ (800aeac ) 800ae7e: 480a ldr r0, [pc, #40] @ (800aea8 ) 800ae80: f7fe fcf8 bl 8009874 800ae84: 4603 mov r3, r0 800ae86: 2b00 cmp r3, #0 800ae88: d001 beq.n 800ae8e { Error_Handler(); 800ae8a: f7f6 fa5f bl 800134c } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 800ae8e: 4806 ldr r0, [pc, #24] @ (800aea8 ) 800ae90: f7fe fd26 bl 80098e0 800ae94: 4603 mov r3, r0 800ae96: 2b00 cmp r3, #0 800ae98: d001 beq.n 800ae9e { Error_Handler(); 800ae9a: f7f6 fa57 bl 800134c } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 800ae9e: bf00 nop 800aea0: bd80 pop {r7, pc} 800aea2: bf00 nop 800aea4: 20000140 .word 0x20000140 800aea8: 20000f08 .word 0x20000f08 800aeac: 2000009c .word 0x2000009c 0800aeb0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aeb0: b480 push {r7} 800aeb2: b083 sub sp, #12 800aeb4: af00 add r7, sp, #0 800aeb6: 4603 mov r3, r0 800aeb8: 6039 str r1, [r7, #0] 800aeba: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 800aebc: 683b ldr r3, [r7, #0] 800aebe: 2212 movs r2, #18 800aec0: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 800aec2: 4b03 ldr r3, [pc, #12] @ (800aed0 ) } 800aec4: 4618 mov r0, r3 800aec6: 370c adds r7, #12 800aec8: 46bd mov sp, r7 800aeca: f85d 7b04 ldr.w r7, [sp], #4 800aece: 4770 bx lr 800aed0: 20000160 .word 0x20000160 0800aed4 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aed4: b480 push {r7} 800aed6: b083 sub sp, #12 800aed8: af00 add r7, sp, #0 800aeda: 4603 mov r3, r0 800aedc: 6039 str r1, [r7, #0] 800aede: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 800aee0: 683b ldr r3, [r7, #0] 800aee2: 2204 movs r2, #4 800aee4: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800aee6: 4b03 ldr r3, [pc, #12] @ (800aef4 ) } 800aee8: 4618 mov r0, r3 800aeea: 370c adds r7, #12 800aeec: 46bd mov sp, r7 800aeee: f85d 7b04 ldr.w r7, [sp], #4 800aef2: 4770 bx lr 800aef4: 20000180 .word 0x20000180 0800aef8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aef8: b580 push {r7, lr} 800aefa: b082 sub sp, #8 800aefc: af00 add r7, sp, #0 800aefe: 4603 mov r3, r0 800af00: 6039 str r1, [r7, #0] 800af02: 71fb strb r3, [r7, #7] if(speed == 0) 800af04: 79fb ldrb r3, [r7, #7] 800af06: 2b00 cmp r3, #0 800af08: d105 bne.n 800af16 { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800af0a: 683a ldr r2, [r7, #0] 800af0c: 4907 ldr r1, [pc, #28] @ (800af2c ) 800af0e: 4808 ldr r0, [pc, #32] @ (800af30 ) 800af10: f7ff fed6 bl 800acc0 800af14: e004 b.n 800af20 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800af16: 683a ldr r2, [r7, #0] 800af18: 4904 ldr r1, [pc, #16] @ (800af2c ) 800af1a: 4805 ldr r0, [pc, #20] @ (800af30 ) 800af1c: f7ff fed0 bl 800acc0 } return USBD_StrDesc; 800af20: 4b02 ldr r3, [pc, #8] @ (800af2c ) } 800af22: 4618 mov r0, r3 800af24: 3708 adds r7, #8 800af26: 46bd mov sp, r7 800af28: bd80 pop {r7, pc} 800af2a: bf00 nop 800af2c: 200011e4 .word 0x200011e4 800af30: 0800b84c .word 0x0800b84c 0800af34 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800af34: b580 push {r7, lr} 800af36: b082 sub sp, #8 800af38: af00 add r7, sp, #0 800af3a: 4603 mov r3, r0 800af3c: 6039 str r1, [r7, #0] 800af3e: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800af40: 683a ldr r2, [r7, #0] 800af42: 4904 ldr r1, [pc, #16] @ (800af54 ) 800af44: 4804 ldr r0, [pc, #16] @ (800af58 ) 800af46: f7ff febb bl 800acc0 return USBD_StrDesc; 800af4a: 4b02 ldr r3, [pc, #8] @ (800af54 ) } 800af4c: 4618 mov r0, r3 800af4e: 3708 adds r7, #8 800af50: 46bd mov sp, r7 800af52: bd80 pop {r7, pc} 800af54: 200011e4 .word 0x200011e4 800af58: 0800b860 .word 0x0800b860 0800af5c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800af5c: b580 push {r7, lr} 800af5e: b082 sub sp, #8 800af60: af00 add r7, sp, #0 800af62: 4603 mov r3, r0 800af64: 6039 str r1, [r7, #0] 800af66: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800af68: 683b ldr r3, [r7, #0] 800af6a: 221a movs r2, #26 800af6c: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800af6e: f000 f855 bl 800b01c /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800af72: 4b02 ldr r3, [pc, #8] @ (800af7c ) } 800af74: 4618 mov r0, r3 800af76: 3708 adds r7, #8 800af78: 46bd mov sp, r7 800af7a: bd80 pop {r7, pc} 800af7c: 20000184 .word 0x20000184 0800af80 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800af80: b580 push {r7, lr} 800af82: b082 sub sp, #8 800af84: af00 add r7, sp, #0 800af86: 4603 mov r3, r0 800af88: 6039 str r1, [r7, #0] 800af8a: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 800af8c: 79fb ldrb r3, [r7, #7] 800af8e: 2b00 cmp r3, #0 800af90: d105 bne.n 800af9e { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800af92: 683a ldr r2, [r7, #0] 800af94: 4907 ldr r1, [pc, #28] @ (800afb4 ) 800af96: 4808 ldr r0, [pc, #32] @ (800afb8 ) 800af98: f7ff fe92 bl 800acc0 800af9c: e004 b.n 800afa8 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800af9e: 683a ldr r2, [r7, #0] 800afa0: 4904 ldr r1, [pc, #16] @ (800afb4 ) 800afa2: 4805 ldr r0, [pc, #20] @ (800afb8 ) 800afa4: f7ff fe8c bl 800acc0 } return USBD_StrDesc; 800afa8: 4b02 ldr r3, [pc, #8] @ (800afb4 ) } 800afaa: 4618 mov r0, r3 800afac: 3708 adds r7, #8 800afae: 46bd mov sp, r7 800afb0: bd80 pop {r7, pc} 800afb2: bf00 nop 800afb4: 200011e4 .word 0x200011e4 800afb8: 0800b86c .word 0x0800b86c 0800afbc : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800afbc: b580 push {r7, lr} 800afbe: b082 sub sp, #8 800afc0: af00 add r7, sp, #0 800afc2: 4603 mov r3, r0 800afc4: 6039 str r1, [r7, #0] 800afc6: 71fb strb r3, [r7, #7] if(speed == 0) 800afc8: 79fb ldrb r3, [r7, #7] 800afca: 2b00 cmp r3, #0 800afcc: d105 bne.n 800afda { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800afce: 683a ldr r2, [r7, #0] 800afd0: 4907 ldr r1, [pc, #28] @ (800aff0 ) 800afd2: 4808 ldr r0, [pc, #32] @ (800aff4 ) 800afd4: f7ff fe74 bl 800acc0 800afd8: e004 b.n 800afe4 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800afda: 683a ldr r2, [r7, #0] 800afdc: 4904 ldr r1, [pc, #16] @ (800aff0 ) 800afde: 4805 ldr r0, [pc, #20] @ (800aff4 ) 800afe0: f7ff fe6e bl 800acc0 } return USBD_StrDesc; 800afe4: 4b02 ldr r3, [pc, #8] @ (800aff0 ) } 800afe6: 4618 mov r0, r3 800afe8: 3708 adds r7, #8 800afea: 46bd mov sp, r7 800afec: bd80 pop {r7, pc} 800afee: bf00 nop 800aff0: 200011e4 .word 0x200011e4 800aff4: 0800b878 .word 0x0800b878 0800aff8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aff8: b480 push {r7} 800affa: b083 sub sp, #12 800affc: af00 add r7, sp, #0 800affe: 4603 mov r3, r0 800b000: 6039 str r1, [r7, #0] 800b002: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 800b004: 683b ldr r3, [r7, #0] 800b006: 220c movs r2, #12 800b008: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 800b00a: 4b03 ldr r3, [pc, #12] @ (800b018 ) } 800b00c: 4618 mov r0, r3 800b00e: 370c adds r7, #12 800b010: 46bd mov sp, r7 800b012: f85d 7b04 ldr.w r7, [sp], #4 800b016: 4770 bx lr 800b018: 20000174 .word 0x20000174 0800b01c : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800b01c: b580 push {r7, lr} 800b01e: b084 sub sp, #16 800b020: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 800b022: 4b0f ldr r3, [pc, #60] @ (800b060 ) 800b024: 681b ldr r3, [r3, #0] 800b026: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800b028: 4b0e ldr r3, [pc, #56] @ (800b064 ) 800b02a: 681b ldr r3, [r3, #0] 800b02c: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800b02e: 4b0e ldr r3, [pc, #56] @ (800b068 ) 800b030: 681b ldr r3, [r3, #0] 800b032: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 800b034: 68fa ldr r2, [r7, #12] 800b036: 687b ldr r3, [r7, #4] 800b038: 4413 add r3, r2 800b03a: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 800b03c: 68fb ldr r3, [r7, #12] 800b03e: 2b00 cmp r3, #0 800b040: d009 beq.n 800b056 { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 800b042: 2208 movs r2, #8 800b044: 4909 ldr r1, [pc, #36] @ (800b06c ) 800b046: 68f8 ldr r0, [r7, #12] 800b048: f000 f814 bl 800b074 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 800b04c: 2204 movs r2, #4 800b04e: 4908 ldr r1, [pc, #32] @ (800b070 ) 800b050: 68b8 ldr r0, [r7, #8] 800b052: f000 f80f bl 800b074 } } 800b056: bf00 nop 800b058: 3710 adds r7, #16 800b05a: 46bd mov sp, r7 800b05c: bd80 pop {r7, pc} 800b05e: bf00 nop 800b060: 1fff7a10 .word 0x1fff7a10 800b064: 1fff7a14 .word 0x1fff7a14 800b068: 1fff7a18 .word 0x1fff7a18 800b06c: 20000186 .word 0x20000186 800b070: 20000196 .word 0x20000196 0800b074 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800b074: b480 push {r7} 800b076: b087 sub sp, #28 800b078: af00 add r7, sp, #0 800b07a: 60f8 str r0, [r7, #12] 800b07c: 60b9 str r1, [r7, #8] 800b07e: 4613 mov r3, r2 800b080: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800b082: 2300 movs r3, #0 800b084: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800b086: 2300 movs r3, #0 800b088: 75fb strb r3, [r7, #23] 800b08a: e027 b.n 800b0dc { if (((value >> 28)) < 0xA) 800b08c: 68fb ldr r3, [r7, #12] 800b08e: 0f1b lsrs r3, r3, #28 800b090: 2b09 cmp r3, #9 800b092: d80b bhi.n 800b0ac { pbuf[2 * idx] = (value >> 28) + '0'; 800b094: 68fb ldr r3, [r7, #12] 800b096: 0f1b lsrs r3, r3, #28 800b098: b2da uxtb r2, r3 800b09a: 7dfb ldrb r3, [r7, #23] 800b09c: 005b lsls r3, r3, #1 800b09e: 4619 mov r1, r3 800b0a0: 68bb ldr r3, [r7, #8] 800b0a2: 440b add r3, r1 800b0a4: 3230 adds r2, #48 @ 0x30 800b0a6: b2d2 uxtb r2, r2 800b0a8: 701a strb r2, [r3, #0] 800b0aa: e00a b.n 800b0c2 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800b0ac: 68fb ldr r3, [r7, #12] 800b0ae: 0f1b lsrs r3, r3, #28 800b0b0: b2da uxtb r2, r3 800b0b2: 7dfb ldrb r3, [r7, #23] 800b0b4: 005b lsls r3, r3, #1 800b0b6: 4619 mov r1, r3 800b0b8: 68bb ldr r3, [r7, #8] 800b0ba: 440b add r3, r1 800b0bc: 3237 adds r2, #55 @ 0x37 800b0be: b2d2 uxtb r2, r2 800b0c0: 701a strb r2, [r3, #0] } value = value << 4; 800b0c2: 68fb ldr r3, [r7, #12] 800b0c4: 011b lsls r3, r3, #4 800b0c6: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 800b0c8: 7dfb ldrb r3, [r7, #23] 800b0ca: 005b lsls r3, r3, #1 800b0cc: 3301 adds r3, #1 800b0ce: 68ba ldr r2, [r7, #8] 800b0d0: 4413 add r3, r2 800b0d2: 2200 movs r2, #0 800b0d4: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800b0d6: 7dfb ldrb r3, [r7, #23] 800b0d8: 3301 adds r3, #1 800b0da: 75fb strb r3, [r7, #23] 800b0dc: 7dfa ldrb r2, [r7, #23] 800b0de: 79fb ldrb r3, [r7, #7] 800b0e0: 429a cmp r2, r3 800b0e2: d3d3 bcc.n 800b08c } } 800b0e4: bf00 nop 800b0e6: bf00 nop 800b0e8: 371c adds r7, #28 800b0ea: 46bd mov sp, r7 800b0ec: f85d 7b04 ldr.w r7, [sp], #4 800b0f0: 4770 bx lr ... 0800b0f4 : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 800b0f4: b580 push {r7, lr} 800b0f6: b0a0 sub sp, #128 @ 0x80 800b0f8: af00 add r7, sp, #0 800b0fa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800b0fc: f107 036c add.w r3, r7, #108 @ 0x6c 800b100: 2200 movs r2, #0 800b102: 601a str r2, [r3, #0] 800b104: 605a str r2, [r3, #4] 800b106: 609a str r2, [r3, #8] 800b108: 60da str r2, [r3, #12] 800b10a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800b10c: f107 0310 add.w r3, r7, #16 800b110: 225c movs r2, #92 @ 0x5c 800b112: 2100 movs r1, #0 800b114: 4618 mov r0, r3 800b116: f000 fb53 bl 800b7c0 if(pcdHandle->Instance==USB_OTG_FS) 800b11a: 687b ldr r3, [r7, #4] 800b11c: 681b ldr r3, [r3, #0] 800b11e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800b122: d149 bne.n 800b1b8 /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 800b124: f44f 7380 mov.w r3, #256 @ 0x100 800b128: 613b str r3, [r7, #16] PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; 800b12a: 2300 movs r3, #0 800b12c: 667b str r3, [r7, #100] @ 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800b12e: f107 0310 add.w r3, r7, #16 800b132: 4618 mov r0, r3 800b134: f7f9 fb10 bl 8004758 800b138: 4603 mov r3, r0 800b13a: 2b00 cmp r3, #0 800b13c: d001 beq.n 800b142 { Error_Handler(); 800b13e: f7f6 f905 bl 800134c } __HAL_RCC_GPIOA_CLK_ENABLE(); 800b142: 2300 movs r3, #0 800b144: 60fb str r3, [r7, #12] 800b146: 4b1e ldr r3, [pc, #120] @ (800b1c0 ) 800b148: 6b1b ldr r3, [r3, #48] @ 0x30 800b14a: 4a1d ldr r2, [pc, #116] @ (800b1c0 ) 800b14c: f043 0301 orr.w r3, r3, #1 800b150: 6313 str r3, [r2, #48] @ 0x30 800b152: 4b1b ldr r3, [pc, #108] @ (800b1c0 ) 800b154: 6b1b ldr r3, [r3, #48] @ 0x30 800b156: f003 0301 and.w r3, r3, #1 800b15a: 60fb str r3, [r7, #12] 800b15c: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 800b15e: f44f 53c0 mov.w r3, #6144 @ 0x1800 800b162: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800b164: 2302 movs r3, #2 800b166: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 800b168: 2300 movs r3, #0 800b16a: 677b str r3, [r7, #116] @ 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800b16c: 2303 movs r3, #3 800b16e: 67bb str r3, [r7, #120] @ 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 800b170: 230a movs r3, #10 800b172: 67fb str r3, [r7, #124] @ 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800b174: f107 036c add.w r3, r7, #108 @ 0x6c 800b178: 4619 mov r1, r3 800b17a: 4812 ldr r0, [pc, #72] @ (800b1c4 ) 800b17c: f7f7 fc42 bl 8002a04 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800b180: 4b0f ldr r3, [pc, #60] @ (800b1c0 ) 800b182: 6b5b ldr r3, [r3, #52] @ 0x34 800b184: 4a0e ldr r2, [pc, #56] @ (800b1c0 ) 800b186: f043 0380 orr.w r3, r3, #128 @ 0x80 800b18a: 6353 str r3, [r2, #52] @ 0x34 800b18c: 2300 movs r3, #0 800b18e: 60bb str r3, [r7, #8] 800b190: 4b0b ldr r3, [pc, #44] @ (800b1c0 ) 800b192: 6c5b ldr r3, [r3, #68] @ 0x44 800b194: 4a0a ldr r2, [pc, #40] @ (800b1c0 ) 800b196: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800b19a: 6453 str r3, [r2, #68] @ 0x44 800b19c: 4b08 ldr r3, [pc, #32] @ (800b1c0 ) 800b19e: 6c5b ldr r3, [r3, #68] @ 0x44 800b1a0: f403 4380 and.w r3, r3, #16384 @ 0x4000 800b1a4: 60bb str r3, [r7, #8] 800b1a6: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 800b1a8: 2200 movs r2, #0 800b1aa: 2100 movs r1, #0 800b1ac: 2043 movs r0, #67 @ 0x43 800b1ae: f7f6 fff0 bl 8002192 HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 800b1b2: 2043 movs r0, #67 @ 0x43 800b1b4: f7f7 f809 bl 80021ca /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 800b1b8: bf00 nop 800b1ba: 3780 adds r7, #128 @ 0x80 800b1bc: 46bd mov sp, r7 800b1be: bd80 pop {r7, pc} 800b1c0: 40023800 .word 0x40023800 800b1c4: 40020000 .word 0x40020000 0800b1c8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b1c8: b580 push {r7, lr} 800b1ca: b082 sub sp, #8 800b1cc: af00 add r7, sp, #0 800b1ce: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 800b1d0: 687b ldr r3, [r7, #4] 800b1d2: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 800b1d6: 687b ldr r3, [r7, #4] 800b1d8: f203 439c addw r3, r3, #1180 @ 0x49c 800b1dc: 4619 mov r1, r3 800b1de: 4610 mov r0, r2 800b1e0: f7fe fbcb bl 800997a } 800b1e4: bf00 nop 800b1e6: 3708 adds r7, #8 800b1e8: 46bd mov sp, r7 800b1ea: bd80 pop {r7, pc} 0800b1ec : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b1ec: b580 push {r7, lr} 800b1ee: b082 sub sp, #8 800b1f0: af00 add r7, sp, #0 800b1f2: 6078 str r0, [r7, #4] 800b1f4: 460b mov r3, r1 800b1f6: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 800b1f8: 687b ldr r3, [r7, #4] 800b1fa: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800b1fe: 78fa ldrb r2, [r7, #3] 800b200: 6879 ldr r1, [r7, #4] 800b202: 4613 mov r3, r2 800b204: 00db lsls r3, r3, #3 800b206: 4413 add r3, r2 800b208: 009b lsls r3, r3, #2 800b20a: 440b add r3, r1 800b20c: f503 7318 add.w r3, r3, #608 @ 0x260 800b210: 681a ldr r2, [r3, #0] 800b212: 78fb ldrb r3, [r7, #3] 800b214: 4619 mov r1, r3 800b216: f7fe fc05 bl 8009a24 } 800b21a: bf00 nop 800b21c: 3708 adds r7, #8 800b21e: 46bd mov sp, r7 800b220: bd80 pop {r7, pc} 0800b222 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b222: b580 push {r7, lr} 800b224: b082 sub sp, #8 800b226: af00 add r7, sp, #0 800b228: 6078 str r0, [r7, #4] 800b22a: 460b mov r3, r1 800b22c: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800b22e: 687b ldr r3, [r7, #4] 800b230: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800b234: 78fa ldrb r2, [r7, #3] 800b236: 6879 ldr r1, [r7, #4] 800b238: 4613 mov r3, r2 800b23a: 00db lsls r3, r3, #3 800b23c: 4413 add r3, r2 800b23e: 009b lsls r3, r3, #2 800b240: 440b add r3, r1 800b242: 3320 adds r3, #32 800b244: 681a ldr r2, [r3, #0] 800b246: 78fb ldrb r3, [r7, #3] 800b248: 4619 mov r1, r3 800b24a: f7fe fca7 bl 8009b9c } 800b24e: bf00 nop 800b250: 3708 adds r7, #8 800b252: 46bd mov sp, r7 800b254: bd80 pop {r7, pc} 0800b256 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b256: b580 push {r7, lr} 800b258: b082 sub sp, #8 800b25a: af00 add r7, sp, #0 800b25c: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800b25e: 687b ldr r3, [r7, #4] 800b260: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b264: 4618 mov r0, r3 800b266: f7fe fdeb bl 8009e40 } 800b26a: bf00 nop 800b26c: 3708 adds r7, #8 800b26e: 46bd mov sp, r7 800b270: bd80 pop {r7, pc} 0800b272 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b272: b580 push {r7, lr} 800b274: b084 sub sp, #16 800b276: af00 add r7, sp, #0 800b278: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 800b27a: 2301 movs r3, #1 800b27c: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 800b27e: 687b ldr r3, [r7, #4] 800b280: 79db ldrb r3, [r3, #7] 800b282: 2b00 cmp r3, #0 800b284: d102 bne.n 800b28c { speed = USBD_SPEED_HIGH; 800b286: 2300 movs r3, #0 800b288: 73fb strb r3, [r7, #15] 800b28a: e008 b.n 800b29e } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 800b28c: 687b ldr r3, [r7, #4] 800b28e: 79db ldrb r3, [r3, #7] 800b290: 2b02 cmp r3, #2 800b292: d102 bne.n 800b29a { speed = USBD_SPEED_FULL; 800b294: 2301 movs r3, #1 800b296: 73fb strb r3, [r7, #15] 800b298: e001 b.n 800b29e } else { Error_Handler(); 800b29a: f7f6 f857 bl 800134c } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800b29e: 687b ldr r3, [r7, #4] 800b2a0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b2a4: 7bfa ldrb r2, [r7, #15] 800b2a6: 4611 mov r1, r2 800b2a8: 4618 mov r0, r3 800b2aa: f7fe fd85 bl 8009db8 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800b2ae: 687b ldr r3, [r7, #4] 800b2b0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b2b4: 4618 mov r0, r3 800b2b6: f7fe fd2c bl 8009d12 } 800b2ba: bf00 nop 800b2bc: 3710 adds r7, #16 800b2be: 46bd mov sp, r7 800b2c0: bd80 pop {r7, pc} ... 0800b2c4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b2c4: b580 push {r7, lr} 800b2c6: b082 sub sp, #8 800b2c8: af00 add r7, sp, #0 800b2ca: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800b2cc: 687b ldr r3, [r7, #4] 800b2ce: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b2d2: 4618 mov r0, r3 800b2d4: f7fe fd80 bl 8009dd8 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800b2d8: 687b ldr r3, [r7, #4] 800b2da: 681b ldr r3, [r3, #0] 800b2dc: f503 6360 add.w r3, r3, #3584 @ 0xe00 800b2e0: 681b ldr r3, [r3, #0] 800b2e2: 687a ldr r2, [r7, #4] 800b2e4: 6812 ldr r2, [r2, #0] 800b2e6: f502 6260 add.w r2, r2, #3584 @ 0xe00 800b2ea: f043 0301 orr.w r3, r3, #1 800b2ee: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 800b2f0: 687b ldr r3, [r7, #4] 800b2f2: 7adb ldrb r3, [r3, #11] 800b2f4: 2b00 cmp r3, #0 800b2f6: d005 beq.n 800b304 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800b2f8: 4b04 ldr r3, [pc, #16] @ (800b30c ) 800b2fa: 691b ldr r3, [r3, #16] 800b2fc: 4a03 ldr r2, [pc, #12] @ (800b30c ) 800b2fe: f043 0306 orr.w r3, r3, #6 800b302: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 800b304: bf00 nop 800b306: 3708 adds r7, #8 800b308: 46bd mov sp, r7 800b30a: bd80 pop {r7, pc} 800b30c: e000ed00 .word 0xe000ed00 0800b310 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b310: b580 push {r7, lr} 800b312: b082 sub sp, #8 800b314: af00 add r7, sp, #0 800b316: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 800b318: 687b ldr r3, [r7, #4] 800b31a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b31e: 4618 mov r0, r3 800b320: f7fe fd76 bl 8009e10 } 800b324: bf00 nop 800b326: 3708 adds r7, #8 800b328: 46bd mov sp, r7 800b32a: bd80 pop {r7, pc} 0800b32c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b32c: b580 push {r7, lr} 800b32e: b082 sub sp, #8 800b330: af00 add r7, sp, #0 800b332: 6078 str r0, [r7, #4] 800b334: 460b mov r3, r1 800b336: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800b338: 687b ldr r3, [r7, #4] 800b33a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b33e: 78fa ldrb r2, [r7, #3] 800b340: 4611 mov r1, r2 800b342: 4618 mov r0, r3 800b344: f7fe fdce bl 8009ee4 } 800b348: bf00 nop 800b34a: 3708 adds r7, #8 800b34c: 46bd mov sp, r7 800b34e: bd80 pop {r7, pc} 0800b350 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b350: b580 push {r7, lr} 800b352: b082 sub sp, #8 800b354: af00 add r7, sp, #0 800b356: 6078 str r0, [r7, #4] 800b358: 460b mov r3, r1 800b35a: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800b35c: 687b ldr r3, [r7, #4] 800b35e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b362: 78fa ldrb r2, [r7, #3] 800b364: 4611 mov r1, r2 800b366: 4618 mov r0, r3 800b368: f7fe fd8a bl 8009e80 } 800b36c: bf00 nop 800b36e: 3708 adds r7, #8 800b370: 46bd mov sp, r7 800b372: bd80 pop {r7, pc} 0800b374 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b374: b580 push {r7, lr} 800b376: b082 sub sp, #8 800b378: af00 add r7, sp, #0 800b37a: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 800b37c: 687b ldr r3, [r7, #4] 800b37e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b382: 4618 mov r0, r3 800b384: f7fe fde0 bl 8009f48 } 800b388: bf00 nop 800b38a: 3708 adds r7, #8 800b38c: 46bd mov sp, r7 800b38e: bd80 pop {r7, pc} 0800b390 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b390: b580 push {r7, lr} 800b392: b082 sub sp, #8 800b394: af00 add r7, sp, #0 800b396: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 800b398: 687b ldr r3, [r7, #4] 800b39a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b39e: 4618 mov r0, r3 800b3a0: f7fe fddd bl 8009f5e } 800b3a4: bf00 nop 800b3a6: 3708 adds r7, #8 800b3a8: 46bd mov sp, r7 800b3aa: bd80 pop {r7, pc} 0800b3ac : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800b3ac: b580 push {r7, lr} 800b3ae: b082 sub sp, #8 800b3b0: af00 add r7, sp, #0 800b3b2: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 800b3b4: 687b ldr r3, [r7, #4] 800b3b6: 781b ldrb r3, [r3, #0] 800b3b8: 2b00 cmp r3, #0 800b3ba: d13c bne.n 800b436 /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 800b3bc: 4a20 ldr r2, [pc, #128] @ (800b440 ) 800b3be: 687b ldr r3, [r7, #4] 800b3c0: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 pdev->pData = &hpcd_USB_OTG_FS; 800b3c4: 687b ldr r3, [r7, #4] 800b3c6: 4a1e ldr r2, [pc, #120] @ (800b440 ) 800b3c8: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800b3cc: 4b1c ldr r3, [pc, #112] @ (800b440 ) 800b3ce: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 800b3d2: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 800b3d4: 4b1a ldr r3, [pc, #104] @ (800b440 ) 800b3d6: 2206 movs r2, #6 800b3d8: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800b3da: 4b19 ldr r3, [pc, #100] @ (800b440 ) 800b3dc: 2202 movs r2, #2 800b3de: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 800b3e0: 4b17 ldr r3, [pc, #92] @ (800b440 ) 800b3e2: 2200 movs r2, #0 800b3e4: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 800b3e6: 4b16 ldr r3, [pc, #88] @ (800b440 ) 800b3e8: 2202 movs r2, #2 800b3ea: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 800b3ec: 4b14 ldr r3, [pc, #80] @ (800b440 ) 800b3ee: 2200 movs r2, #0 800b3f0: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800b3f2: 4b13 ldr r3, [pc, #76] @ (800b440 ) 800b3f4: 2200 movs r2, #0 800b3f6: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 800b3f8: 4b11 ldr r3, [pc, #68] @ (800b440 ) 800b3fa: 2200 movs r2, #0 800b3fc: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 800b3fe: 4b10 ldr r3, [pc, #64] @ (800b440 ) 800b400: 2200 movs r2, #0 800b402: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 800b404: 4b0e ldr r3, [pc, #56] @ (800b440 ) 800b406: 2200 movs r2, #0 800b408: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 800b40a: 480d ldr r0, [pc, #52] @ (800b440 ) 800b40c: f7f7 fe04 bl 8003018 800b410: 4603 mov r3, r0 800b412: 2b00 cmp r3, #0 800b414: d001 beq.n 800b41a { Error_Handler( ); 800b416: f7f5 ff99 bl 800134c HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 800b41a: 2180 movs r1, #128 @ 0x80 800b41c: 4808 ldr r0, [pc, #32] @ (800b440 ) 800b41e: f7f9 f84c bl 80044ba HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 800b422: 2240 movs r2, #64 @ 0x40 800b424: 2100 movs r1, #0 800b426: 4806 ldr r0, [pc, #24] @ (800b440 ) 800b428: f7f9 f800 bl 800442c HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 800b42c: 2280 movs r2, #128 @ 0x80 800b42e: 2101 movs r1, #1 800b430: 4803 ldr r0, [pc, #12] @ (800b440 ) 800b432: f7f8 fffb bl 800442c } return USBD_OK; 800b436: 2300 movs r3, #0 } 800b438: 4618 mov r0, r3 800b43a: 3708 adds r7, #8 800b43c: 46bd mov sp, r7 800b43e: bd80 pop {r7, pc} 800b440: 200013e4 .word 0x200013e4 0800b444 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800b444: b580 push {r7, lr} 800b446: b084 sub sp, #16 800b448: af00 add r7, sp, #0 800b44a: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800b44c: 2300 movs r3, #0 800b44e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b450: 2300 movs r3, #0 800b452: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800b454: 687b ldr r3, [r7, #4] 800b456: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b45a: 4618 mov r0, r3 800b45c: f7f7 fef2 bl 8003244 800b460: 4603 mov r3, r0 800b462: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b464: 7bfb ldrb r3, [r7, #15] 800b466: 4618 mov r0, r3 800b468: f000 f97e bl 800b768 800b46c: 4603 mov r3, r0 800b46e: 73bb strb r3, [r7, #14] return usb_status; 800b470: 7bbb ldrb r3, [r7, #14] } 800b472: 4618 mov r0, r3 800b474: 3710 adds r7, #16 800b476: 46bd mov sp, r7 800b478: bd80 pop {r7, pc} 0800b47a : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800b47a: b580 push {r7, lr} 800b47c: b084 sub sp, #16 800b47e: af00 add r7, sp, #0 800b480: 6078 str r0, [r7, #4] 800b482: 4608 mov r0, r1 800b484: 4611 mov r1, r2 800b486: 461a mov r2, r3 800b488: 4603 mov r3, r0 800b48a: 70fb strb r3, [r7, #3] 800b48c: 460b mov r3, r1 800b48e: 70bb strb r3, [r7, #2] 800b490: 4613 mov r3, r2 800b492: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800b494: 2300 movs r3, #0 800b496: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b498: 2300 movs r3, #0 800b49a: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800b49c: 687b ldr r3, [r7, #4] 800b49e: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800b4a2: 78bb ldrb r3, [r7, #2] 800b4a4: 883a ldrh r2, [r7, #0] 800b4a6: 78f9 ldrb r1, [r7, #3] 800b4a8: f7f8 fbf3 bl 8003c92 800b4ac: 4603 mov r3, r0 800b4ae: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b4b0: 7bfb ldrb r3, [r7, #15] 800b4b2: 4618 mov r0, r3 800b4b4: f000 f958 bl 800b768 800b4b8: 4603 mov r3, r0 800b4ba: 73bb strb r3, [r7, #14] return usb_status; 800b4bc: 7bbb ldrb r3, [r7, #14] } 800b4be: 4618 mov r0, r3 800b4c0: 3710 adds r7, #16 800b4c2: 46bd mov sp, r7 800b4c4: bd80 pop {r7, pc} 0800b4c6 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b4c6: b580 push {r7, lr} 800b4c8: b084 sub sp, #16 800b4ca: af00 add r7, sp, #0 800b4cc: 6078 str r0, [r7, #4] 800b4ce: 460b mov r3, r1 800b4d0: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b4d2: 2300 movs r3, #0 800b4d4: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b4d6: 2300 movs r3, #0 800b4d8: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800b4da: 687b ldr r3, [r7, #4] 800b4dc: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b4e0: 78fa ldrb r2, [r7, #3] 800b4e2: 4611 mov r1, r2 800b4e4: 4618 mov r0, r3 800b4e6: f7f8 fc3e bl 8003d66 800b4ea: 4603 mov r3, r0 800b4ec: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b4ee: 7bfb ldrb r3, [r7, #15] 800b4f0: 4618 mov r0, r3 800b4f2: f000 f939 bl 800b768 800b4f6: 4603 mov r3, r0 800b4f8: 73bb strb r3, [r7, #14] return usb_status; 800b4fa: 7bbb ldrb r3, [r7, #14] } 800b4fc: 4618 mov r0, r3 800b4fe: 3710 adds r7, #16 800b500: 46bd mov sp, r7 800b502: bd80 pop {r7, pc} 0800b504 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b504: b580 push {r7, lr} 800b506: b084 sub sp, #16 800b508: af00 add r7, sp, #0 800b50a: 6078 str r0, [r7, #4] 800b50c: 460b mov r3, r1 800b50e: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b510: 2300 movs r3, #0 800b512: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b514: 2300 movs r3, #0 800b516: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800b518: 687b ldr r3, [r7, #4] 800b51a: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b51e: 78fa ldrb r2, [r7, #3] 800b520: 4611 mov r1, r2 800b522: 4618 mov r0, r3 800b524: f7f8 fcde bl 8003ee4 800b528: 4603 mov r3, r0 800b52a: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b52c: 7bfb ldrb r3, [r7, #15] 800b52e: 4618 mov r0, r3 800b530: f000 f91a bl 800b768 800b534: 4603 mov r3, r0 800b536: 73bb strb r3, [r7, #14] return usb_status; 800b538: 7bbb ldrb r3, [r7, #14] } 800b53a: 4618 mov r0, r3 800b53c: 3710 adds r7, #16 800b53e: 46bd mov sp, r7 800b540: bd80 pop {r7, pc} 0800b542 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b542: b580 push {r7, lr} 800b544: b084 sub sp, #16 800b546: af00 add r7, sp, #0 800b548: 6078 str r0, [r7, #4] 800b54a: 460b mov r3, r1 800b54c: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b54e: 2300 movs r3, #0 800b550: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b552: 2300 movs r3, #0 800b554: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800b556: 687b ldr r3, [r7, #4] 800b558: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b55c: 78fa ldrb r2, [r7, #3] 800b55e: 4611 mov r1, r2 800b560: 4618 mov r0, r3 800b562: f7f8 fd22 bl 8003faa 800b566: 4603 mov r3, r0 800b568: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b56a: 7bfb ldrb r3, [r7, #15] 800b56c: 4618 mov r0, r3 800b56e: f000 f8fb bl 800b768 800b572: 4603 mov r3, r0 800b574: 73bb strb r3, [r7, #14] return usb_status; 800b576: 7bbb ldrb r3, [r7, #14] } 800b578: 4618 mov r0, r3 800b57a: 3710 adds r7, #16 800b57c: 46bd mov sp, r7 800b57e: bd80 pop {r7, pc} 0800b580 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b580: b480 push {r7} 800b582: b085 sub sp, #20 800b584: af00 add r7, sp, #0 800b586: 6078 str r0, [r7, #4] 800b588: 460b mov r3, r1 800b58a: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800b58c: 687b ldr r3, [r7, #4] 800b58e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b592: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800b594: f997 3003 ldrsb.w r3, [r7, #3] 800b598: 2b00 cmp r3, #0 800b59a: da0b bge.n 800b5b4 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800b59c: 78fb ldrb r3, [r7, #3] 800b59e: f003 027f and.w r2, r3, #127 @ 0x7f 800b5a2: 68f9 ldr r1, [r7, #12] 800b5a4: 4613 mov r3, r2 800b5a6: 00db lsls r3, r3, #3 800b5a8: 4413 add r3, r2 800b5aa: 009b lsls r3, r3, #2 800b5ac: 440b add r3, r1 800b5ae: 3316 adds r3, #22 800b5b0: 781b ldrb r3, [r3, #0] 800b5b2: e00b b.n 800b5cc } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800b5b4: 78fb ldrb r3, [r7, #3] 800b5b6: f003 027f and.w r2, r3, #127 @ 0x7f 800b5ba: 68f9 ldr r1, [r7, #12] 800b5bc: 4613 mov r3, r2 800b5be: 00db lsls r3, r3, #3 800b5c0: 4413 add r3, r2 800b5c2: 009b lsls r3, r3, #2 800b5c4: 440b add r3, r1 800b5c6: f203 2356 addw r3, r3, #598 @ 0x256 800b5ca: 781b ldrb r3, [r3, #0] } } 800b5cc: 4618 mov r0, r3 800b5ce: 3714 adds r7, #20 800b5d0: 46bd mov sp, r7 800b5d2: f85d 7b04 ldr.w r7, [sp], #4 800b5d6: 4770 bx lr 0800b5d8 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800b5d8: b580 push {r7, lr} 800b5da: b084 sub sp, #16 800b5dc: af00 add r7, sp, #0 800b5de: 6078 str r0, [r7, #4] 800b5e0: 460b mov r3, r1 800b5e2: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b5e4: 2300 movs r3, #0 800b5e6: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b5e8: 2300 movs r3, #0 800b5ea: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800b5ec: 687b ldr r3, [r7, #4] 800b5ee: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b5f2: 78fa ldrb r2, [r7, #3] 800b5f4: 4611 mov r1, r2 800b5f6: 4618 mov r0, r3 800b5f8: f7f8 fb27 bl 8003c4a 800b5fc: 4603 mov r3, r0 800b5fe: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b600: 7bfb ldrb r3, [r7, #15] 800b602: 4618 mov r0, r3 800b604: f000 f8b0 bl 800b768 800b608: 4603 mov r3, r0 800b60a: 73bb strb r3, [r7, #14] return usb_status; 800b60c: 7bbb ldrb r3, [r7, #14] } 800b60e: 4618 mov r0, r3 800b610: 3710 adds r7, #16 800b612: 46bd mov sp, r7 800b614: bd80 pop {r7, pc} 0800b616 : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800b616: b580 push {r7, lr} 800b618: b086 sub sp, #24 800b61a: af00 add r7, sp, #0 800b61c: 60f8 str r0, [r7, #12] 800b61e: 607a str r2, [r7, #4] 800b620: 603b str r3, [r7, #0] 800b622: 460b mov r3, r1 800b624: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800b626: 2300 movs r3, #0 800b628: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800b62a: 2300 movs r3, #0 800b62c: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800b62e: 68fb ldr r3, [r7, #12] 800b630: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800b634: 7af9 ldrb r1, [r7, #11] 800b636: 683b ldr r3, [r7, #0] 800b638: 687a ldr r2, [r7, #4] 800b63a: f7f8 fc19 bl 8003e70 800b63e: 4603 mov r3, r0 800b640: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800b642: 7dfb ldrb r3, [r7, #23] 800b644: 4618 mov r0, r3 800b646: f000 f88f bl 800b768 800b64a: 4603 mov r3, r0 800b64c: 75bb strb r3, [r7, #22] return usb_status; 800b64e: 7dbb ldrb r3, [r7, #22] } 800b650: 4618 mov r0, r3 800b652: 3718 adds r7, #24 800b654: 46bd mov sp, r7 800b656: bd80 pop {r7, pc} 0800b658 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800b658: b580 push {r7, lr} 800b65a: b086 sub sp, #24 800b65c: af00 add r7, sp, #0 800b65e: 60f8 str r0, [r7, #12] 800b660: 607a str r2, [r7, #4] 800b662: 603b str r3, [r7, #0] 800b664: 460b mov r3, r1 800b666: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800b668: 2300 movs r3, #0 800b66a: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800b66c: 2300 movs r3, #0 800b66e: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800b670: 68fb ldr r3, [r7, #12] 800b672: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800b676: 7af9 ldrb r1, [r7, #11] 800b678: 683b ldr r3, [r7, #0] 800b67a: 687a ldr r2, [r7, #4] 800b67c: f7f8 fbbd bl 8003dfa 800b680: 4603 mov r3, r0 800b682: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800b684: 7dfb ldrb r3, [r7, #23] 800b686: 4618 mov r0, r3 800b688: f000 f86e bl 800b768 800b68c: 4603 mov r3, r0 800b68e: 75bb strb r3, [r7, #22] return usb_status; 800b690: 7dbb ldrb r3, [r7, #22] } 800b692: 4618 mov r0, r3 800b694: 3718 adds r7, #24 800b696: 46bd mov sp, r7 800b698: bd80 pop {r7, pc} ... 0800b69c : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 800b69c: b580 push {r7, lr} 800b69e: b082 sub sp, #8 800b6a0: af00 add r7, sp, #0 800b6a2: 6078 str r0, [r7, #4] 800b6a4: 460b mov r3, r1 800b6a6: 70fb strb r3, [r7, #3] switch (msg) 800b6a8: 78fb ldrb r3, [r7, #3] 800b6aa: 2b00 cmp r3, #0 800b6ac: d002 beq.n 800b6b4 800b6ae: 2b01 cmp r3, #1 800b6b0: d01f beq.n 800b6f2 /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 800b6b2: e03b b.n 800b72c if (hpcd->Init.low_power_enable) 800b6b4: 687b ldr r3, [r7, #4] 800b6b6: 7adb ldrb r3, [r3, #11] 800b6b8: 2b00 cmp r3, #0 800b6ba: d007 beq.n 800b6cc SystemClock_Config(); 800b6bc: f7f5 fb3e bl 8000d3c SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800b6c0: 4b1c ldr r3, [pc, #112] @ (800b734 ) 800b6c2: 691b ldr r3, [r3, #16] 800b6c4: 4a1b ldr r2, [pc, #108] @ (800b734 ) 800b6c6: f023 0306 bic.w r3, r3, #6 800b6ca: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 800b6cc: 687b ldr r3, [r7, #4] 800b6ce: 681b ldr r3, [r3, #0] 800b6d0: f503 6360 add.w r3, r3, #3584 @ 0xe00 800b6d4: 681b ldr r3, [r3, #0] 800b6d6: 687a ldr r2, [r7, #4] 800b6d8: 6812 ldr r2, [r2, #0] 800b6da: f502 6260 add.w r2, r2, #3584 @ 0xe00 800b6de: f023 0301 bic.w r3, r3, #1 800b6e2: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 800b6e4: 687b ldr r3, [r7, #4] 800b6e6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b6ea: 4618 mov r0, r3 800b6ec: f7fe fb90 bl 8009e10 break; 800b6f0: e01c b.n 800b72c __HAL_PCD_GATE_PHYCLOCK(hpcd); 800b6f2: 687b ldr r3, [r7, #4] 800b6f4: 681b ldr r3, [r3, #0] 800b6f6: f503 6360 add.w r3, r3, #3584 @ 0xe00 800b6fa: 681b ldr r3, [r3, #0] 800b6fc: 687a ldr r2, [r7, #4] 800b6fe: 6812 ldr r2, [r2, #0] 800b700: f502 6260 add.w r2, r2, #3584 @ 0xe00 800b704: f043 0301 orr.w r3, r3, #1 800b708: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 800b70a: 687b ldr r3, [r7, #4] 800b70c: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b710: 4618 mov r0, r3 800b712: f7fe fb61 bl 8009dd8 if (hpcd->Init.low_power_enable) 800b716: 687b ldr r3, [r7, #4] 800b718: 7adb ldrb r3, [r3, #11] 800b71a: 2b00 cmp r3, #0 800b71c: d005 beq.n 800b72a SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800b71e: 4b05 ldr r3, [pc, #20] @ (800b734 ) 800b720: 691b ldr r3, [r3, #16] 800b722: 4a04 ldr r2, [pc, #16] @ (800b734 ) 800b724: f043 0306 orr.w r3, r3, #6 800b728: 6113 str r3, [r2, #16] break; 800b72a: bf00 nop } 800b72c: bf00 nop 800b72e: 3708 adds r7, #8 800b730: 46bd mov sp, r7 800b732: bd80 pop {r7, pc} 800b734: e000ed00 .word 0xe000ed00 0800b738 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800b738: b480 push {r7} 800b73a: b083 sub sp, #12 800b73c: af00 add r7, sp, #0 800b73e: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800b740: 4b03 ldr r3, [pc, #12] @ (800b750 ) } 800b742: 4618 mov r0, r3 800b744: 370c adds r7, #12 800b746: 46bd mov sp, r7 800b748: f85d 7b04 ldr.w r7, [sp], #4 800b74c: 4770 bx lr 800b74e: bf00 nop 800b750: 200018c8 .word 0x200018c8 0800b754 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800b754: b480 push {r7} 800b756: b083 sub sp, #12 800b758: af00 add r7, sp, #0 800b75a: 6078 str r0, [r7, #4] } 800b75c: bf00 nop 800b75e: 370c adds r7, #12 800b760: 46bd mov sp, r7 800b762: f85d 7b04 ldr.w r7, [sp], #4 800b766: 4770 bx lr 0800b768 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800b768: b480 push {r7} 800b76a: b085 sub sp, #20 800b76c: af00 add r7, sp, #0 800b76e: 4603 mov r3, r0 800b770: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800b772: 2300 movs r3, #0 800b774: 73fb strb r3, [r7, #15] switch (hal_status) 800b776: 79fb ldrb r3, [r7, #7] 800b778: 2b03 cmp r3, #3 800b77a: d817 bhi.n 800b7ac 800b77c: a201 add r2, pc, #4 @ (adr r2, 800b784 ) 800b77e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b782: bf00 nop 800b784: 0800b795 .word 0x0800b795 800b788: 0800b79b .word 0x0800b79b 800b78c: 0800b7a1 .word 0x0800b7a1 800b790: 0800b7a7 .word 0x0800b7a7 { case HAL_OK : usb_status = USBD_OK; 800b794: 2300 movs r3, #0 800b796: 73fb strb r3, [r7, #15] break; 800b798: e00b b.n 800b7b2 case HAL_ERROR : usb_status = USBD_FAIL; 800b79a: 2303 movs r3, #3 800b79c: 73fb strb r3, [r7, #15] break; 800b79e: e008 b.n 800b7b2 case HAL_BUSY : usb_status = USBD_BUSY; 800b7a0: 2301 movs r3, #1 800b7a2: 73fb strb r3, [r7, #15] break; 800b7a4: e005 b.n 800b7b2 case HAL_TIMEOUT : usb_status = USBD_FAIL; 800b7a6: 2303 movs r3, #3 800b7a8: 73fb strb r3, [r7, #15] break; 800b7aa: e002 b.n 800b7b2 default : usb_status = USBD_FAIL; 800b7ac: 2303 movs r3, #3 800b7ae: 73fb strb r3, [r7, #15] break; 800b7b0: bf00 nop } return usb_status; 800b7b2: 7bfb ldrb r3, [r7, #15] } 800b7b4: 4618 mov r0, r3 800b7b6: 3714 adds r7, #20 800b7b8: 46bd mov sp, r7 800b7ba: f85d 7b04 ldr.w r7, [sp], #4 800b7be: 4770 bx lr 0800b7c0 : 800b7c0: 4402 add r2, r0 800b7c2: 4603 mov r3, r0 800b7c4: 4293 cmp r3, r2 800b7c6: d100 bne.n 800b7ca 800b7c8: 4770 bx lr 800b7ca: f803 1b01 strb.w r1, [r3], #1 800b7ce: e7f9 b.n 800b7c4 0800b7d0 <__libc_init_array>: 800b7d0: b570 push {r4, r5, r6, lr} 800b7d2: 4d0d ldr r5, [pc, #52] @ (800b808 <__libc_init_array+0x38>) 800b7d4: 4c0d ldr r4, [pc, #52] @ (800b80c <__libc_init_array+0x3c>) 800b7d6: 1b64 subs r4, r4, r5 800b7d8: 10a4 asrs r4, r4, #2 800b7da: 2600 movs r6, #0 800b7dc: 42a6 cmp r6, r4 800b7de: d109 bne.n 800b7f4 <__libc_init_array+0x24> 800b7e0: 4d0b ldr r5, [pc, #44] @ (800b810 <__libc_init_array+0x40>) 800b7e2: 4c0c ldr r4, [pc, #48] @ (800b814 <__libc_init_array+0x44>) 800b7e4: f000 f826 bl 800b834 <_init> 800b7e8: 1b64 subs r4, r4, r5 800b7ea: 10a4 asrs r4, r4, #2 800b7ec: 2600 movs r6, #0 800b7ee: 42a6 cmp r6, r4 800b7f0: d105 bne.n 800b7fe <__libc_init_array+0x2e> 800b7f2: bd70 pop {r4, r5, r6, pc} 800b7f4: f855 3b04 ldr.w r3, [r5], #4 800b7f8: 4798 blx r3 800b7fa: 3601 adds r6, #1 800b7fc: e7ee b.n 800b7dc <__libc_init_array+0xc> 800b7fe: f855 3b04 ldr.w r3, [r5], #4 800b802: 4798 blx r3 800b804: 3601 adds r6, #1 800b806: e7f2 b.n 800b7ee <__libc_init_array+0x1e> 800b808: 0800b8b0 .word 0x0800b8b0 800b80c: 0800b8b0 .word 0x0800b8b0 800b810: 0800b8b0 .word 0x0800b8b0 800b814: 0800b8b4 .word 0x0800b8b4 0800b818 : 800b818: 440a add r2, r1 800b81a: 4291 cmp r1, r2 800b81c: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800b820: d100 bne.n 800b824 800b822: 4770 bx lr 800b824: b510 push {r4, lr} 800b826: f811 4b01 ldrb.w r4, [r1], #1 800b82a: f803 4f01 strb.w r4, [r3, #1]! 800b82e: 4291 cmp r1, r2 800b830: d1f9 bne.n 800b826 800b832: bd10 pop {r4, pc} 0800b834 <_init>: 800b834: b5f8 push {r3, r4, r5, r6, r7, lr} 800b836: bf00 nop 800b838: bcf8 pop {r3, r4, r5, r6, r7} 800b83a: bc08 pop {r3} 800b83c: 469e mov lr, r3 800b83e: 4770 bx lr 0800b840 <_fini>: 800b840: b5f8 push {r3, r4, r5, r6, r7, lr} 800b842: bf00 nop 800b844: bcf8 pop {r3, r4, r5, r6, r7} 800b846: bc08 pop {r3} 800b848: 469e mov lr, r3 800b84a: 4770 bx lr