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Oliver "Kim" Avecilla Cabral
2025-09-22 14:39:59 -07:00
parent 72c174bfc1
commit fc28b98ea7
60 changed files with 121628 additions and 2 deletions
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hardware/68percent/68percent-backups/68percent-2025-09-22_143308.zip Normal file
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hardware/68percent/68percent-backups/68percent-2025-09-22_143923.zip Normal file
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hardware/68percent/68percent.csv Normal file
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2"Reference","Qty","Value","DNP","Exclude from BOM","Exclude from Board","Footprint","Datasheet"
"C1,C2","2","20pF","","","","PCM_Capacitor_SMD_AKL:C_0805_2012Metric","~"
"C3,C4,C5,C6","4","100nF","","","","PCM_Capacitor_SMD_AKL:C_0805_2012Metric","~"
"C7,C10","2","1uF","","","","PCM_Capacitor_SMD_AKL:C_0805_2012Metric","~"
"C8","1","10uF","","","","PCM_Capacitor_SMD_AKL:C_0805_2012Metric","~"
"C9","1","4.7uF","","","","PCM_Capacitor_SMD_AKL:C_0805_2012Metric","~"
"C11","1","0.1uF","","","","PCM_Capacitor_SMD_AKL:C_0805_2012Metric","~"
"D1","1","PRTR5V0U2X","","","","PCM_Package_TO_SOT_SMD_AKL:SOT-143_Handsoldering","https://www.tme.eu/Document/4eac14af69261014af6cc93b35742953/PRTR5V0U2X-DTE.pdf"
"D2","1","BAT60JFILM","","","","PCM_Diode_SMD_AKL:D_SOD-323",""
"D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15,D16,D17,D18,D19,D20,D21,D22,D23,D24,D25,D26,D27,D28,D29","27","1N4148W","","","","PCM_Diode_SMD_AKL:D_SOD-123","https://datasheet.octopart.com/1N4148W-HE3-18-Vishay-datasheet-17291302.pdf"
"East1,North1,South1,West1","4","Conn_01x04","","","","Connector_PinSocket_2.54mm:PinSocket_1x04_P2.54mm_Vertical",""
"FB1","1","Ferrite_Bead","","","","PCM_Fuse_AKL:Fuse_0805_2012Metric_Pad1.15x1.40mm_BigPads","~"
"IC1","1","LD1117-3.3V-SOT223","","","","PCM_4ms_Package_SOT:SOT223","https://www.mouser.com/datasheet/2/389/cd00000544-1795431.pdf"
"J1","1","Conn_01x06","","","","Connector_PinSocket_2.54mm:PinSocket_1x06_P2.54mm_Horizontal",""
"LED1,LED2,LED3,LED4,LED5,LED6,LED7,LED8,LED9,LED10,LED11,LED12,LED13,LED14,LED15,LED16,LED17,LED18,LED19,LED20,LED21,LED22,LED23,LED24,LED25,LED26,LED27","27","MX_SK6812MINI-E","","","","PCM_marbastlib-mx:LED_MX_6028R",""
"MACRO_A1,MACRO_B1,MACRO_C1,MACRO_D1,MACRO_E1,MACRO_F1,MACRO_G1,MACRO_H1,MACRO_I1,NUM_0,NUM_1,NUM_2,NUM_3,NUM_4,NUM_5,NUM_6,NUM_7,NUM_8,NUM_10,NUM_ADD1,NUM_DIV1,NUM_ENTER1,NUM_LOCK1,NUM_MULT1,NUM_PERIOD1,NUM_SUB1","26","MX_SW_HS","","","","PCM_marbastlib-mx:SW_MX_HS_CPG151101S11_1u","~"
"R1,R2","2","5.1k","","","","PCM_Resistor_SMD_AKL:R_0805_2012Metric","~"
"R3,R4,R6,R7,R8,R9","6","22","","","","PCM_Resistor_SMD_AKL:R_0805_2012Metric","~"
"R5","1","10k","","","","PCM_Resistor_SMD_AKL:R_0805_2012Metric","~"
"R10,R13","2","DNP","","","","PCM_Resistor_SMD_AKL:R_0805_2012Metric","~"
"S1,S2,S3","3","MX_stab","","","","PCM_marbastlib-mx:STAB_MX_P_2u",""
"SW1","1","ROT_SKYLOONG_HS","","Excluded from BOM","","PCM_marbastlib-various:ROT_SKYLOONG_HS-Switch","https://skyloong.vip/products/abs-hot-swappable-knobs-madule"
"SW2","1","Push_Button","","","","PCM_marbastlib-various:SW_SPST_SKQG_WithStem",""
"U1","1","~","","","","footprints:LQFP64-10x10mm",""
"USB1","1","HRO-TYPE-C-31-M-12","","","","Type-C.pretty-master:HRO-TYPE-C-31-M-12-HandSoldering",""
"Y1","1","8MHz","","","","PCM_Crystal_AKL:Crystal_HC52-U_Vertical",""
Can't render this file because it contains an unexpected character in line 1 and column 2.

169
hardware/68percent/68percent.kicad_dru Normal file
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(version 1)
#PCBWay Custom DRC for Kicad 7
# ----------------------------------- Minimum trace width and spacing (PICK ONE) --------------------
# 2oz copper
#(rule "Minimum Trace Width and Spacing (outer layer)"
#(constraint track_width (min 0.1524mm))
#(constraint clearance (min 0.1778mm))
#(layer outer)
#(condition "A.Type == 'track'"))
#(rule "Minimum Trace Width and Spacing (innner layer)"
#(constraint track_width (min 0.1524mm))
#(constraint clearance (min 0.1778mm))
#(layer inner)
#(condition "A.Type == 'track'"))
# 2-layer, 1oz copper
(rule "Minimum Trace Width and Spacing (outer layer)"
(constraint track_width (min 0.127mm))
(constraint clearance (min 0.127mm))
(layer outer)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Width and Spacing (inner layer)"
(constraint track_width (min 0.1mm))
(constraint clearance (min 0.1mm))
(layer inner)
(condition "A.Type == 'track'"))
# 4-layer , 1oz and 0.5oz copper
#(rule "Minimum Trace Width and Spacing (outer layer)"
#(constraint track_width (min 0.09mm))
#(constraint clearance (min 0.09mm))
#(layer outer)
#(condition "A.Type == 'track'"))
#(rule "Minimum Trace Width and Spacing (inner layer)"
#(constraint track_width (min 0.1mm))
#(constraint clearance (min 0.09mm))
#(layer inner)
#(condition "A.Type == 'track'"))
# ------------------------------------------------------------------------------------------------------
# Drill/hole size - listed here to maintain order of rule application. Must not override rule set in Via hole/diameter size below.
(rule "drill hole size (mechanical)"
(constraint hole_size (min 0.15mm) (max 6.3mm)))
# ----------------------------------- Via hole/diameter size (PICK ONE) ------------------------------------
# 2-layer standard
(rule "Minimum Via Diameter and Hole Size"
(constraint hole_size (min 0.3mm))
(constraint via_diameter (min 0.5mm))
(condition "A.Type == 'via'"))
# 4-layer standard
#(rule "Minimum Via Diameter and Hole Size"
#(constraint hole_size (min 0.3mm))
#(constraint via_diameter (min 0.45mm))
#(condition "A.Type == 'via'"))
# 4-layer advanced
#(rule "Minimum Via Diameter and Hole Size"
#(constraint hole_size (min 0.25mm))
#(constraint via_diameter (min 0.4mm))
#(constraint disallow buried_via)
#(condition "A.Type == 'via'"))
# 4-layer advanced
#(rule "Minimum Via Diameter and Hole Size"
#(constraint hole_size (min 0.2mm))
#(constraint via_diameter (min 0.35mm))
#(condition "A.Type == 'via'"))
# 4-layer advanced
#(rule "Minimum Via Diameter and Hole Size"
#(constraint hole_size (min 0.15mm))
#(constraint via_diameter (min 0.3mm))
#(condition "A.Type == 'via'"))
# ----------------------------------- Drill/hole size ------------------------------------
(rule "PTH Hole Size"
(constraint hole_size (min 0.2mm) (max 6.35mm))
(condition "A.Type != 'Via' && A.isPlated()"))
(rule "Minimum Non-plated Hole Size"
(constraint hole_size (min 0.5mm))
(condition "A.Type == 'pad' && !A.isPlated()"))
(rule "Pad Size"
(constraint hole_size (min 0.5mm))
(constraint annular_width (min 0.25mm))
(condition "A.Type == 'Pad' && A.isPlated()"))
(rule "Minimum Castellated Hole Size"
(constraint hole_size (min 0.6mm))
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
(rule "Min. Plated Slot Width"
(constraint hole_size (min 0.5mm))
(condition "(A.Hole_Size_X != A.Hole_Size_Y) && A.isPlated()"))
(rule "Min. Non-Plated Slot Width"
(constraint hole_size (min 0.8mm))
(condition "(A.Hole_Size_X != A.Hole_Size_Y) && !A.isPlated()"))
# ----------------------------------- Minimum clearance ----------------------------------
(rule "hole to hole clearance (different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Net != B.Net"))
(rule "via to track clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'via' && B.Type == 'track'"))
(rule "via to via clearance (same nets)"
(constraint hole_to_hole (min 0.254mm))
(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
(rule "pad to pad clearance (with hole, different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "pad to pad clearance (without hole, different nets)"
(constraint clearance (min 0.127mm))
(condition "A.Type == 'Pad' && B.Type == 'Pad'"))
(rule "NPTH to Track clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
(rule "NPTH with copper around"
(constraint hole_clearance (min 0.20mm))
(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type != 'track'"))
(rule "PTH to Track clearance"
(constraint hole_clearance (min 0.33mm))
(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'"))
(rule "Pad to Track clearance"
(constraint clearance (min 0.2mm))
(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'"))
# ----------------------------------- Board Outlines (PICK ONE) -------------------------------------
#Default Routed Edge Clearance
(rule "Trace to Outline"
(constraint edge_clearance (min 0.3mm))
(condition "A.Type == 'track'"))
#Special Clearance for V-Score Edges
#(rule "Trace to V-Cut"
#(constraint edge_clearance (min 0.4mm))
#(condition "A.Type == 'track'"))
# ----------------------------------- silkscreen --------------------------
(rule "Minimum Text"
(constraint text_thickness (min 0.15mm))
(constraint text_height (min 0.8mm))
(layer "?.Silkscreen"))
(rule "Pad to Silkscreen"
(constraint silk_clearance (min 0.15mm))
(layer outer)
(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))

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hardware/68percent/68percent.kicad_pcb Normal file
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hardware/68percent/68percent.kicad_prl Normal file
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{
"board": {
"active_layer": 5,
"active_layer_preset": "",
"auto_track_width": false,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"shapes": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.3700000047683716
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
"vias",
"footprint_text",
"footprint_anchors",
"ratsnest",
"grid",
"footprints_front",
"footprints_back",
"footprint_values",
"footprint_references",
"tracks",
"drc_errors",
"drawing_sheet",
"bitmaps",
"pads",
"zones",
"drc_warnings",
"drc_exclusions",
"locked_item_shadows",
"conflict_shadows",
"shapes"
],
"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
"zone_display_mode": 0
},
"git": {
"repo_type": "",
"repo_username": "",
"ssh_key": ""
},
"meta": {
"filename": "68percent.kicad_prl",
"version": 5
},
"net_inspector_panel": {
"col_hidden": [
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false
],
"col_order": [
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"col_widths": [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
],
"custom_group_rules": [],
"expanded_rows": [],
"filter_by_net_name": true,
"filter_by_netclass": true,
"filter_text": "",
"group_by_constraint": false,
"group_by_netclass": false,
"show_unconnected_nets": false,
"show_zero_pad_nets": false,
"sort_ascending": true,
"sorting_column": 0
},
"open_jobsets": [],
"project": {
"files": []
},
"schematic": {
"selection_filter": {
"graphics": true,
"images": true,
"labels": true,
"lockedItems": false,
"otherItems": true,
"pins": true,
"symbols": true,
"text": true,
"wires": true
}
}
}

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hardware/68percent/68percent.kicad_pro Normal file
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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": true,
"text_position": 0,
"units_format": 0
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.8,
"height": 1.27,
"width": 2.54
},
"silk_line_width": 0.1,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
},
{
"gap": 0.4,
"via_gap": 0.4,
"width": 0.8
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"creepage": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_filters_mismatch": "ignore",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_to_hole": "warning",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"mirrored_text_on_front_layer": "warning",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"nonmirrored_text_on_back_layer": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_angle": "error",
"track_dangling": "warning",
"track_segment_length": "error",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_groove_width": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.16,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpthpad": true,
"td_onroundshapesonly": false,
"td_onsmdpad": true,
"td_ontrackend": false,
"td_onvia": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.2,
0.6
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_pairs": [],
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
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],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
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(kicad_sch
(version 20250114)
(generator "eeschema")
(generator_version "9.0")
(uuid "6f2c82b5-c9ad-40d0-84fe-43041274abb2")
(paper "A4")
(lib_symbols)
)

3597
hardware/68percent/untitled.kicad_sc.kicad_sch-bak Normal file
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hardware/68percent/untitled.kicad_sch Normal file
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(kicad_sch
(version 20250114)
(generator "eeschema")
(generator_version "9.0")
(uuid "40b1bbce-d916-44f1-8247-5f0a1c45385b")
(paper "A4")
(lib_symbols)
)

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hardware/68percent/usbpow.kicad_sch Normal file
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(kicad_sch
(version 20250114)
(generator "eeschema")
(generator_version "9.0")
(uuid "3cb9f3e3-5e6a-4c23-8d8d-52b5ae63fbaf")
(paper "A4")
(lib_symbols)
(text "USB Receptacle. Needs to be a USB C connector.\nESD Protection would be nice\nAdd a diode to prevent backflow from other 5v sources (i.e. modules)\nMake sure D+/D- are differential lines"
(exclude_from_sim no)
(at 101.346 90.932 0)
(effects
(font
(size 1.27 1.27)
)
(justify left)
)
(uuid "b8671ba6-87fa-4960-bcc3-fbddf17f4d76")
)
(hierarchical_label "D-"
(shape input)
(at 177.8 72.39 0)
(effects
(font
(size 1.27 1.27)
)
(justify left)
)
(uuid "5cbd4a5a-ac39-4a2d-a0ad-0c3ce3f9d635")
)
(hierarchical_label "D+"
(shape input)
(at 177.8 67.31 0)
(effects
(font
(size 1.27 1.27)
)
(justify left)
)
(uuid "80d42395-23c2-4264-878d-42f2e81a4374")
)
(hierarchical_label "5v"
(shape input)
(at 177.8 78.74 0)
(effects
(font
(size 1.27 1.27)
)
(justify left)
)
(uuid "b70746ac-3765-45c4-a69a-b93b10cc6628")
)
)

1
hardware/68percent/~68percent.kicad_sch.lck Normal file
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{"hostname":"framework16","username":"ukim"}