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Oliver "Kim" Avecilla Cabral
2025-09-02 20:35:02 -07:00
parent 41fc26ad4a
commit f2adbc1a75
41 changed files with 45481 additions and 41345 deletions
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# if defined(__INTEL_COMPILER_BUILD_DATE)
/* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */
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*/
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# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 100)
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# define SIMULATE_VERSION_MAJOR DEC(__GNUG__)
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/* _MSC_VER = VVRR */
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# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
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# if defined(__GNUC_MINOR__)
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/* _MSC_VER = VVRR */
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# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100)
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# define COMPILER_VERSION_MINOR DEC(__VERSION_MINOR_NUMBER__)
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/* These compilers are either not known or too old to define an
identification macro. Try to identify the platform and guess that
it is the native compiler. */
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getting matched. Store it in a pointer rather than an array
because some compilers will just produce instructions to fill the
array rather than assigning a pointer to a static array. */
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char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]";
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char const* qnxnto = "INFO" ":" "qnxnto[]";
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#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]";
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#define STRINGIFY_HELPER(X) #X
#define STRINGIFY(X) STRINGIFY_HELPER(X)
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# define PLATFORM_ID "Linux"
#elif defined(__MSYS__)
# define PLATFORM_ID "MSYS"
#elif defined(__CYGWIN__)
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#elif defined(__MINGW32__)
# define PLATFORM_ID "MinGW"
#elif defined(__APPLE__)
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# define PLATFORM_ID "Windows"
#elif defined(__FreeBSD__) || defined(__FreeBSD)
# define PLATFORM_ID "FreeBSD"
#elif defined(__NetBSD__) || defined(__NetBSD)
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#elif defined(__OpenBSD__) || defined(__OPENBSD)
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#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__)
# define PLATFORM_ID "AIX"
#elif defined(__hpux) || defined(__hpux__)
# define PLATFORM_ID "HP-UX"
#elif defined(__HAIKU__)
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# define PLATFORM_ID "BeOS"
#elif defined(__QNX__) || defined(__QNXNTO__)
# define PLATFORM_ID "QNX"
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# define PLATFORM_ID "RISCos"
#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__)
# define PLATFORM_ID "SINIX"
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# define PLATFORM_ID "UNIX_SV"
#elif defined(__bsdos__)
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#elif defined(__osf) || defined(__osf__)
# define PLATFORM_ID "OSF1"
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#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX)
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#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX)
# define PLATFORM_ID "Xenix"
#elif defined(__WATCOMC__)
# if defined(__LINUX__)
# define PLATFORM_ID "Linux"
# elif defined(__DOS__)
# define PLATFORM_ID "DOS"
# elif defined(__OS2__)
# define PLATFORM_ID "OS2"
# elif defined(__WINDOWS__)
# define PLATFORM_ID "Windows3x"
# elif defined(__VXWORKS__)
# define PLATFORM_ID "VxWorks"
# else /* unknown platform */
# define PLATFORM_ID
# endif
#elif defined(__INTEGRITY)
# if defined(INT_178B)
# define PLATFORM_ID "Integrity178"
# else /* regular Integrity */
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# elif defined(_ADI_COMPILER)
# define PLATFORM_ID "ADSP"
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# define PLATFORM_ID
#endif
/* For windows compilers MSVC and Intel we can determine
the architecture of the compiler being used. This is because
the compilers do not have flags that can change the architecture,
but rather depend on which compiler is being used
*/
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# if defined(_M_IA64)
# define ARCHITECTURE_ID "IA64"
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# define ARCHITECTURE_ID "X86"
# elif defined(_M_ARM64)
# define ARCHITECTURE_ID "ARM64"
# elif defined(_M_ARM)
# if _M_ARM == 4
# define ARCHITECTURE_ID "ARMV4I"
# elif _M_ARM == 5
# define ARCHITECTURE_ID "ARMV5I"
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# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM)
# endif
# elif defined(_M_MIPS)
# define ARCHITECTURE_ID "MIPS"
# elif defined(_M_SH)
# define ARCHITECTURE_ID "SHx"
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# define ARCHITECTURE_ID ""
# endif
#elif defined(__WATCOMC__)
# if defined(_M_I86)
# define ARCHITECTURE_ID "I86"
# elif defined(_M_IX86)
# define ARCHITECTURE_ID "X86"
# else /* unknown architecture */
# define ARCHITECTURE_ID ""
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#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
# if defined(__ICCARM__)
# define ARCHITECTURE_ID "ARM"
# elif defined(__ICCRX__)
# define ARCHITECTURE_ID "RX"
# elif defined(__ICCRH850__)
# define ARCHITECTURE_ID "RH850"
# elif defined(__ICCRL78__)
# define ARCHITECTURE_ID "RL78"
# elif defined(__ICCRISCV__)
# define ARCHITECTURE_ID "RISCV"
# elif defined(__ICCAVR__)
# define ARCHITECTURE_ID "AVR"
# elif defined(__ICC430__)
# define ARCHITECTURE_ID "MSP430"
# elif defined(__ICCV850__)
# define ARCHITECTURE_ID "V850"
# elif defined(__ICC8051__)
# define ARCHITECTURE_ID "8051"
# elif defined(__ICCSTM8__)
# define ARCHITECTURE_ID "STM8"
# else /* unknown architecture */
# define ARCHITECTURE_ID ""
# endif
#elif defined(__ghs__)
# if defined(__PPC64__)
# define ARCHITECTURE_ID "PPC64"
# elif defined(__ppc__)
# define ARCHITECTURE_ID "PPC"
# elif defined(__ARM__)
# define ARCHITECTURE_ID "ARM"
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(version 1)
# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
#
# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
#
# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
#
# Inspiration
# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
# TODO new rule: NPTH pads.
# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
# TODO: new rule for plated slots: min diameter/width 0.5mm
# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
# TODO new rule: non-plated slots: min diameter/width 1.0mm
# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
(rule "Track width, outer layer (1oz copper)"
(layer outer)
(condition "A.Type == 'track'")
(constraint track_width (min 0.127mm))
)
(rule "Track spacing, outer layer (1oz copper)"
(layer outer)
(condition "A.Type == 'track' && B.Type == A.Type")
(constraint clearance (min 0.127mm))
)
(rule "Track width, inner layer"
(layer inner)
(condition "A.Type == 'track'")
(constraint track_width (min 0.09mm))
)
(rule "Track spacing, inner layer"
(layer inner)
(condition "A.Type == 'track' && B.Type == A.Type")
(constraint clearance (min 0.09mm))
)
(rule "Silkscreen text"
(layer "?.Silkscreen")
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
(constraint text_thickness (min 0.15mm))
(constraint text_height (min 1mm))
)
(rule "Pad to Silkscreen"
(layer outer)
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
(constraint silk_clearance (min 0.15mm))
)
(rule "Edge (routed) to track clearance"
(condition "A.Type == 'track'")
(constraint edge_clearance (min 0.3mm))
)
#(rule "Edge (v-cut) to track clearance"
# (condition "A.Type == 'track'")
# (constraint edge_clearance (min 0.4mm))
#)
# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
(rule "Hole diameter"
(constraint hole_size (min 0.2mm) (max 6.3mm))
)
(rule "Hole (NPTH) diameter"
(layer outer)
(condition "!A.isPlated()")
(constraint hole_size (min 0.5mm))
)
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Hole (castellated) diameter"
(layer outer)
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
(constraint hole_size (min 0.6mm))
)
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Annular ring width (via and PTH)"
(layer outer)
(condition "A.isPlated()")
(constraint annular_width (min 0.075mm))
)
(rule "Clearance: hole to hole (perimeter), different nets"
(layer outer)
(condition "A.Net != B.Net")
(constraint hole_to_hole (min 0.5mm))
)
(rule "Clearance: hole to hole (perimeter), same net"
(layer outer)
(condition "A.Net == B.Net")
(constraint hole_to_hole (min 0.254mm))
)
(rule "Clearance: track to NPTH hole (perimeter)"
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
(constraint hole_clearance (min 0.254mm))
)
(rule "Clearance: track to PTH hole perimeter"
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
(constraint hole_clearance (min 0.33mm))
)
# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Clearance: track to pad"
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
(constraint clearance (min 0.2mm))
)
(rule "Clearance: pad/via to pad/via"
(layer outer)
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
(constraint clearance (min 0.127mm))
)

69612
hardware/numpad/numpad/numpad.kicad_pcb
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30
hardware/numpad/numpad/numpad.kicad_prl
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@@ -13,7 +13,7 @@
"shapes": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
"zones": 0.4099999964237213
},
"selection_filter": {
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@@ -73,6 +73,8 @@
false,
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26
hardware/numpad/numpad/numpad.kicad_pro
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@@ -51,7 +51,13 @@
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
@@ -130,7 +136,7 @@
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_track_width": 0.16,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
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"td_width_to_size_filter_ratio": 0.9
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"track_widths": [],
"track_widths": [
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"via_dimensions": [
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[
"1d905906-6e74-4741-8b2e-53dc470a7c79",
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[
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2469
hardware/numpad/numpad/numpad.kicad_sch
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1
hardware/numpad/numpad/sym-lib-table
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@@ -2,4 +2,5 @@
(version 7)
(lib (name "stm32f446ret6")(type "KiCad")(uri "/home/kymkim/Projects/modular-kbd/hardware/symbols/stm32f446ret6/stm32f446ret6.kicad_sym")(options "")(descr ""))
(lib (name "Type-C")(type "Legacy")(uri "/home/kymkim/Projects/modular-kbd/hardware/Type-C.pretty-master/Type-C.lib")(options "")(descr ""))
(lib (name "T36K3BGR-05D000121U1930")(type "KiCad")(uri "/home/ukim/Projects/modular-kbd/hardware/symbols/T36K3BGR-05D000121U1930/T36K3BGR-05D000121U1930.kicad_sym")(options "")(descr ""))
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3581
hardware/numpad/numpad/untitled.kicad_sc.kicad_sch Normal file
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3597
hardware/numpad/numpad/untitled.kicad_sc.kicad_sch-bak Normal file
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1
hardware/numpad/numpad/~_autosave-numpad.kicad_pcb.lck Normal file
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{"hostname":"framework16","username":"ukim"}

32
hardware/symbols/T36K3BGR-05D000121U1930/LED_T36K3BGR-05D000121U1930.kicad_mod Normal file
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(footprint LED_T36K3BGR-05D000121U1930 (layer F.Cu) (tedit 68B7726D)
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(effects (font (size 1.0 1.0) (thickness 0.15)))
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(pad 3 smd rect (at 2.75 -0.725) (size 2.0 0.75) (layers F.Cu F.Mask F.Paste) (solder_mask_margin 0.102))
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228
hardware/symbols/T36K3BGR-05D000121U1930/T36K3BGR-05D000121U1930.kicad_sym Normal file
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2006
hardware/symbols/T36K3BGR-05D000121U1930/T36K3BGR-05D000121U1930.step Normal file
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1
hardware/symbols/T36K3BGR-05D000121U1930/how-to-import.htm Normal file
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@@ -0,0 +1 @@
<!DOCTYPE HTML><html lang="en-US"> <head> <meta charset="UTF-8"> <meta http-equiv="refresh" content="0; url=https://www.snapeda.com/about/import/#"> <script type="text/javascript">window.location.href="https://www.snapeda.com/about/import/#" </script> <title>Page Redirection</title> </head> <body> If you are not redirected automatically, follow this <a href="https://www.snapeda.com/about/import/#">link to the import guide</a>. </body></html>