rgb matrix and drc rules
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133
hardware/numpad/numpad/numpad.kicad_dru
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133
hardware/numpad/numpad/numpad.kicad_dru
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@@ -0,0 +1,133 @@
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||||
(version 1)
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||||
# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
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#
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# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
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#
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# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
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#
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# Inspiration
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# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
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# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
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# TODO new rule: NPTH pads.
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# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
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# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
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# TODO: new rule for plated slots: min diameter/width 0.5mm
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# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
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# TODO new rule: non-plated slots: min diameter/width 1.0mm
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# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
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(rule "Track width, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.127mm))
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)
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(rule "Track spacing, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.127mm))
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)
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(rule "Track width, inner layer"
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(layer inner)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.09mm))
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)
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(rule "Track spacing, inner layer"
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(layer inner)
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(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.09mm))
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)
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(rule "Silkscreen text"
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(layer "?.Silkscreen")
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(condition "A.Type == 'Text' || A.Type == 'Text Box'")
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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)
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(rule "Pad to Silkscreen"
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(layer outer)
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(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
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(constraint silk_clearance (min 0.15mm))
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)
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(rule "Edge (routed) to track clearance"
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(condition "A.Type == 'track'")
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(constraint edge_clearance (min 0.3mm))
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)
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#(rule "Edge (v-cut) to track clearance"
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# (condition "A.Type == 'track'")
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# (constraint edge_clearance (min 0.4mm))
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#)
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# JLCPCB restrictions ambiguous:
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# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
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# This rule handles diameter minimum and maximum for ALL holes.
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# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
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(rule "Hole diameter"
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(constraint hole_size (min 0.2mm) (max 6.3mm))
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)
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(rule "Hole (NPTH) diameter"
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(layer outer)
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(condition "!A.isPlated()")
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(constraint hole_size (min 0.5mm))
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)
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# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
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(rule "Hole (castellated) diameter"
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(layer outer)
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
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(constraint hole_size (min 0.6mm))
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)
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# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
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# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
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(rule "Annular ring width (via and PTH)"
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(layer outer)
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(condition "A.isPlated()")
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(constraint annular_width (min 0.075mm))
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)
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(rule "Clearance: hole to hole (perimeter), different nets"
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(layer outer)
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(condition "A.Net != B.Net")
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(constraint hole_to_hole (min 0.5mm))
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)
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(rule "Clearance: hole to hole (perimeter), same net"
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(layer outer)
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(condition "A.Net == B.Net")
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(constraint hole_to_hole (min 0.254mm))
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)
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(rule "Clearance: track to NPTH hole (perimeter)"
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# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
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(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.254mm))
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)
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(rule "Clearance: track to PTH hole perimeter"
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(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.33mm))
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)
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# TODO: try combining with rule "Clearance: PTH to track, different nets"
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(rule "Clearance: track to pad"
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(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
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(constraint clearance (min 0.2mm))
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)
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(rule "Clearance: pad/via to pad/via"
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(layer outer)
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# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
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(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
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(constraint clearance (min 0.127mm))
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)
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File diff suppressed because it is too large
Load Diff
@@ -13,7 +13,7 @@
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"shapes": 1.0,
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"tracks": 1.0,
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"vias": 1.0,
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"zones": 0.6
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"zones": 0.4099999964237213
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},
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"selection_filter": {
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"dimensions": true,
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@@ -73,6 +73,8 @@
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false,
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false,
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false,
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false,
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false,
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false
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],
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"col_order": [
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@@ -85,19 +87,23 @@
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6,
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7,
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8,
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9
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9,
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10,
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11
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],
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"col_widths": [
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10,
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10,
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10,
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10,
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10,
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10,
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10,
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10,
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10,
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185
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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||||
0
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],
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"custom_group_rules": [],
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"expanded_rows": [],
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@@ -51,7 +51,13 @@
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"min_clearance": 0.5
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}
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},
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"diff_pair_dimensions": [],
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"diff_pair_dimensions": [
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{
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"gap": 0.0,
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"via_gap": 0.0,
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"width": 0.0
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}
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],
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"drc_exclusions": [],
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"meta": {
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"version": 2
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@@ -130,7 +136,7 @@
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"min_text_height": 0.8,
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"min_text_thickness": 0.08,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.0,
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"min_track_width": 0.16,
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"min_via_annular_width": 0.1,
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"min_via_diameter": 0.5,
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"solder_mask_to_copper_clearance": 0.0,
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@@ -180,7 +186,10 @@
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"td_width_to_size_filter_ratio": 0.9
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}
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],
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"track_widths": [],
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"track_widths": [
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0.0,
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0.2
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],
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"tuning_pattern_settings": {
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"diff_pair_defaults": {
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"corner_radius_percentage": 80,
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@@ -207,7 +216,12 @@
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"spacing": 0.6
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}
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},
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"via_dimensions": [],
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"via_dimensions": [
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{
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"diameter": 0.0,
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"drill": 0.0
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}
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],
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"zones_allow_external_fillets": false
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},
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"ipc2581": {
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||||
@@ -617,6 +631,10 @@
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[
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||||
"1d905906-6e74-4741-8b2e-53dc470a7c79",
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"Numpad Matrix + Rotary Encoder"
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],
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||||
[
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||||
"ead3be26-7f43-4289-81f3-aae72a11e5f1",
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||||
"RGB Matrix"
|
||||
]
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||||
],
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||||
"text_variables": {}
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File diff suppressed because it is too large
Load Diff
@@ -2,4 +2,5 @@
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(version 7)
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(lib (name "stm32f446ret6")(type "KiCad")(uri "/home/kymkim/Projects/modular-kbd/hardware/symbols/stm32f446ret6/stm32f446ret6.kicad_sym")(options "")(descr ""))
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||||
(lib (name "Type-C")(type "Legacy")(uri "/home/kymkim/Projects/modular-kbd/hardware/Type-C.pretty-master/Type-C.lib")(options "")(descr ""))
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||||
(lib (name "T36K3BGR-05D000121U1930")(type "KiCad")(uri "/home/ukim/Projects/modular-kbd/hardware/symbols/T36K3BGR-05D000121U1930/T36K3BGR-05D000121U1930.kicad_sym")(options "")(descr ""))
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||||
)
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||||
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||||
3581
hardware/numpad/numpad/untitled.kicad_sc.kicad_sch
Normal file
3581
hardware/numpad/numpad/untitled.kicad_sc.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
3597
hardware/numpad/numpad/untitled.kicad_sc.kicad_sch-bak
Normal file
3597
hardware/numpad/numpad/untitled.kicad_sc.kicad_sch-bak
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File diff suppressed because it is too large
Load Diff
1
hardware/numpad/numpad/~_autosave-numpad.kicad_pcb.lck
Normal file
1
hardware/numpad/numpad/~_autosave-numpad.kicad_pcb.lck
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@@ -0,0 +1 @@
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{"hostname":"framework16","username":"ukim"}
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@@ -0,0 +1,32 @@
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(footprint LED_T36K3BGR-05D000121U1930 (layer F.Cu) (tedit 68B7726D)
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(descr "")
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(attr smd)
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(fp_text reference REF** (at -0.825 -2.635 0) (layer F.SilkS)
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(effects (font (size 1.0 1.0) (thickness 0.15)))
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||||
)
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(fp_text value LED_T36K3BGR-05D000121U1930 (at 13.145 2.615 0) (layer F.Fab)
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||||
(effects (font (size 1.0 1.0) (thickness 0.15)))
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||||
)
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(pad 3 smd rect (at 2.75 -0.725) (size 2.0 0.75) (layers F.Cu F.Mask F.Paste) (solder_mask_margin 0.102))
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(pad 2 smd rect (at 2.75 0.725) (size 2.0 0.75) (layers F.Cu F.Mask F.Paste) (solder_mask_margin 0.102))
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(pad 1 smd rect (at -2.75 0.725) (size 2.0 0.75) (layers F.Cu F.Mask F.Paste) (solder_mask_margin 0.102))
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||||
(pad 4 smd rect (at -2.75 -0.725) (size 2.0 0.75) (layers F.Cu F.Mask F.Paste) (solder_mask_margin 0.102))
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||||
(fp_line (start -1.6 -1.4) (end 1.6 -1.4) (layer F.Fab) (width 0.127))
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||||
(fp_line (start 1.6 -1.4) (end 1.6 1.4) (layer F.Fab) (width 0.127))
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||||
(fp_line (start 1.6 1.4) (end -1.6 1.4) (layer F.Fab) (width 0.127))
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||||
(fp_line (start -1.6 1.4) (end -1.6 -1.4) (layer F.Fab) (width 0.127))
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||||
(fp_line (start -4.0 -1.75) (end 4.0 -1.75) (layer F.CrtYd) (width 0.05))
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||||
(fp_line (start 4.0 -1.75) (end 4.0 1.75) (layer F.CrtYd) (width 0.05))
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||||
(fp_line (start 4.0 1.75) (end -4.0 1.75) (layer F.CrtYd) (width 0.05))
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||||
(fp_line (start -4.0 1.75) (end -4.0 -1.75) (layer F.CrtYd) (width 0.05))
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||||
(fp_circle (center -4.5 0.703) (end -4.4 0.703) (layer F.Fab) (width 0.2))
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||||
(fp_circle (center -4.5 0.703) (end -4.4 0.703) (layer F.SilkS) (width 0.2))
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||||
(fp_line (start -1.7 -1.5) (end -1.7 1.5) (layer Edge.Cuts) (width 0.01))
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||||
(fp_line (start -1.7 1.5) (end 1.7 1.5) (layer Edge.Cuts) (width 0.01))
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||||
(fp_line (start 1.7 1.5) (end 1.7 -1.5) (layer Edge.Cuts) (width 0.01))
|
||||
(fp_line (start 1.7 -1.5) (end -1.7 -1.5) (layer Edge.Cuts) (width 0.01))
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||||
(fp_text user "The pins are mirrored assuming the LED is facing down on the PCB" (at -3.81 5.08) (layer F.Fab)
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||||
(effects (font (size 0.64 0.64) (thickness 0.15)))
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||||
)
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||||
)
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||||
@@ -0,0 +1,228 @@
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||||
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||||
(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor)
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||||
(symbol "T36K3BGR-05D000121U1930" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
|
||||
(property "Reference" "D" (id 0) (at -10.16 12.7 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom left))
|
||||
)
|
||||
(property "Value" "T36K3BGR-05D000121U1930" (id 1) (at -10.16 10.16 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom left))
|
||||
)
|
||||
(property "Footprint" "T36K3BGR-05D000121U1930:LED_T36K3BGR-05D000121U1930" (id 2) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "MF" "Harvatek Corporation" (id 4) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "MAXIMUM_PACKAGE_HEIGHT" "1.0mm" (id 5) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "Package" "SMD-4 Harvatek" (id 6) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "Price" "None" (id 7) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "Check_prices" "https://www.snapeda.com/parts/T36K3BGR-05D000121U1930/Harvatek/view-part/?ref=eda" (id 8) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "STANDARD" "Manufacturer Recommendations" (id 9) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "PARTREV" "1.1" (id 10) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "SnapEDA_Link" "https://www.snapeda.com/parts/T36K3BGR-05D000121U1930/Harvatek/view-part/?ref=snap" (id 11) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "MP" "T36K3BGR-05D000121U1930" (id 12) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "Description" "\n \n Red, Green, Blue (RGB) - LED Indication - Discrete 2V Red, 2.6V Green, 2.6V Blue 4-SMD, Flat Leads\n \n" (id 13) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "Availability" "In Stock" (id 14) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(property "MANUFACTURER" "Harvatek" (id 15) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom) hide)
|
||||
)
|
||||
(symbol "T36K3BGR-05D000121U1930_0_0"
|
||||
(polyline
|
||||
(pts (xy 0.0 9.144) (xy 0.0 7.62)) (stroke (width 0.254))
|
||||
)
|
||||
(polyline
|
||||
(pts (xy 0.0 7.62) (xy 0.0 6.096)) (stroke (width 0.254))
|
||||
)
|
||||
(polyline
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||||
(pts (xy 0.0 6.096) (xy 2.54 7.62)) (stroke (width 0.254))
|
||||
)
|
||||
(polyline
|
||||
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|
||||
)
|
||||
(polyline
|
||||
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|
||||
)
|
||||
(polyline
|
||||
(pts (xy 0.0 1.524) (xy 0.0 0.0)) (stroke (width 0.254))
|
||||
)
|
||||
(polyline
|
||||
(pts (xy 0.0 0.0) (xy 0.0 -1.524)) (stroke (width 0.254))
|
||||
)
|
||||
(polyline
|
||||
(pts (xy 0.0 -1.524) (xy 2.54 0.0)) (stroke (width 0.254))
|
||||
)
|
||||
(polyline
|
||||
(pts (xy 2.54 0.0) (xy 0.0 1.524)) (stroke (width 0.254))
|
||||
)
|
||||
(polyline
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1 @@
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<!DOCTYPE HTML><html lang="en-US"> <head> <meta charset="UTF-8"> <meta http-equiv="refresh" content="0; url=https://www.snapeda.com/about/import/#"> <script type="text/javascript">window.location.href="https://www.snapeda.com/about/import/#" </script> <title>Page Redirection</title> </head> <body> If you are not redirected automatically, follow this <a href="https://www.snapeda.com/about/import/#">link to the import guide</a>. </body></html>
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Reference in New Issue
Block a user